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1/* SPDX-License-Identifier: GPL-2.0 */
2/* $Id: sungem.h,v 1.10.2.4 2002/03/11 08:54:48 davem Exp $
3 * sungem.h: Definitions for Sun GEM ethernet driver.
4 *
5 * Copyright (C) 2000 David S. Miller (davem@redhat.com)
6 */
7
8#ifndef _SUNGEM_H
9#define _SUNGEM_H
10
11/* Global Registers */
12#define GREG_SEBSTATE 0x0000UL /* SEB State Register */
13#define GREG_CFG 0x0004UL /* Configuration Register */
14#define GREG_STAT 0x000CUL /* Status Register */
15#define GREG_IMASK 0x0010UL /* Interrupt Mask Register */
16#define GREG_IACK 0x0014UL /* Interrupt ACK Register */
17#define GREG_STAT2 0x001CUL /* Alias of GREG_STAT */
18#define GREG_PCIESTAT 0x1000UL /* PCI Error Status Register */
19#define GREG_PCIEMASK 0x1004UL /* PCI Error Mask Register */
20#define GREG_BIFCFG 0x1008UL /* BIF Configuration Register */
21#define GREG_BIFDIAG 0x100CUL /* BIF Diagnostics Register */
22#define GREG_SWRST 0x1010UL /* Software Reset Register */
23
24/* Global SEB State Register */
25#define GREG_SEBSTATE_ARB 0x00000003 /* State of Arbiter */
26#define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */
27
28/* Global Configuration Register */
29#define GREG_CFG_IBURST 0x00000001 /* Infinite Burst */
30#define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */
31#define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */
32#define GREG_CFG_RONPAULBIT 0x00000800 /* Use mem read multiple for PCI read
33 * after infinite burst (Apple) */
34#define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */
35
36/* Global Interrupt Status Register.
37 *
38 * Reading this register automatically clears bits 0 through 6.
39 * This auto-clearing does not occur when the alias at GREG_STAT2
40 * is read instead. The rest of the interrupt bits only clear when
41 * the secondary interrupt status register corresponding to that
42 * bit is read (ie. if GREG_STAT_PCS is set, it will be cleared by
43 * reading PCS_ISTAT).
44 */
45#define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */
46#define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */
47#define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */
48#define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */
49#define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */
50#define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */
51#define GREG_STAT_PCS 0x00002000 /* PCS signalled interrupt */
52#define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */
53#define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */
54#define GREG_STAT_MAC 0x00010000 /* MAC Control signalled irq */
55#define GREG_STAT_MIF 0x00020000 /* MIF signalled interrupt */
56#define GREG_STAT_PCIERR 0x00040000 /* PCI Error interrupt */
57#define GREG_STAT_TXNR 0xfff80000 /* == TXDMA_TXDONE reg val */
58#define GREG_STAT_TXNR_SHIFT 19
59
60#define GREG_STAT_ABNORMAL (GREG_STAT_RXNOBUF | GREG_STAT_RXTAGERR | \
61 GREG_STAT_PCS | GREG_STAT_TXMAC | GREG_STAT_RXMAC | \
62 GREG_STAT_MAC | GREG_STAT_MIF | GREG_STAT_PCIERR)
63
64#define GREG_STAT_NAPI (GREG_STAT_TXALL | GREG_STAT_TXINTME | \
65 GREG_STAT_RXDONE | GREG_STAT_ABNORMAL)
66
67/* The layout of GREG_IMASK and GREG_IACK is identical to GREG_STAT.
68 * Bits set in GREG_IMASK will prevent that interrupt type from being
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
70 * interrupt conditions in GREG_STAT, ie. it only works for bits 0 through 6.
71 * Setting the bit will clear that interrupt, clear bits will have no effect
72 * on GREG_STAT.
73 */
74
75/* Global PCI Error Status Register */
76#define GREG_PCIESTAT_BADACK 0x00000001 /* No ACK64# during ABS64 cycle */
77#define GREG_PCIESTAT_DTRTO 0x00000002 /* Delayed transaction timeout */
78#define GREG_PCIESTAT_OTHER 0x00000004 /* Other PCI error, check cfg space */
79
80/* The layout of the GREG_PCIEMASK is identical to that of GREG_PCIESTAT.
81 * Bits set in GREG_PCIEMASK will prevent that interrupt type from being
82 * signalled to the cpu.
83 */
84
85/* Global BIF Configuration Register */
86#define GREG_BIFCFG_SLOWCLK 0x00000001 /* Set if PCI runs < 25Mhz */
87#define GREG_BIFCFG_B64DIS 0x00000002 /* Disable 64bit wide data cycle*/
88#define GREG_BIFCFG_M66EN 0x00000004 /* Set if on 66Mhz PCI segment */
89
90/* Global BIF Diagnostics Register */
91#define GREG_BIFDIAG_BURSTSM 0x007f0000 /* PCI Burst state machine */
92#define GREG_BIFDIAG_BIFSM 0xff000000 /* BIF state machine */
93
94/* Global Software Reset Register.
95 *
96 * This register is used to perform a global reset of the RX and TX portions
97 * of the GEM asic. Setting the RX or TX reset bit will start the reset.
98 * The driver _MUST_ poll these bits until they clear. One may not attempt
99 * to program any other part of GEM until the bits clear.
100 */
101#define GREG_SWRST_TXRST 0x00000001 /* TX Software Reset */
102#define GREG_SWRST_RXRST 0x00000002 /* RX Software Reset */
103#define GREG_SWRST_RSTOUT 0x00000004 /* Force RST# pin active */
104#define GREG_SWRST_CACHESIZE 0x00ff0000 /* RIO only: cache line size */
105#define GREG_SWRST_CACHE_SHIFT 16
106
107/* TX DMA Registers */
108#define TXDMA_KICK 0x2000UL /* TX Kick Register */
109#define TXDMA_CFG 0x2004UL /* TX Configuration Register */
110#define TXDMA_DBLOW 0x2008UL /* TX Desc. Base Low */
111#define TXDMA_DBHI 0x200CUL /* TX Desc. Base High */
112#define TXDMA_FWPTR 0x2014UL /* TX FIFO Write Pointer */
113#define TXDMA_FSWPTR 0x2018UL /* TX FIFO Shadow Write Pointer */
114#define TXDMA_FRPTR 0x201CUL /* TX FIFO Read Pointer */
115#define TXDMA_FSRPTR 0x2020UL /* TX FIFO Shadow Read Pointer */
116#define TXDMA_PCNT 0x2024UL /* TX FIFO Packet Counter */
117#define TXDMA_SMACHINE 0x2028UL /* TX State Machine Register */
118#define TXDMA_DPLOW 0x2030UL /* TX Data Pointer Low */
119#define TXDMA_DPHI 0x2034UL /* TX Data Pointer High */
120#define TXDMA_TXDONE 0x2100UL /* TX Completion Register */
121#define TXDMA_FADDR 0x2104UL /* TX FIFO Address */
122#define TXDMA_FTAG 0x2108UL /* TX FIFO Tag */
123#define TXDMA_DLOW 0x210CUL /* TX FIFO Data Low */
124#define TXDMA_DHIT1 0x2110UL /* TX FIFO Data HighT1 */
125#define TXDMA_DHIT0 0x2114UL /* TX FIFO Data HighT0 */
126#define TXDMA_FSZ 0x2118UL /* TX FIFO Size */
127
128/* TX Kick Register.
129 *
130 * This 13-bit register is programmed by the driver to hold the descriptor
131 * entry index which follows the last valid transmit descriptor.
132 */
133
134/* TX Completion Register.
135 *
136 * This 13-bit register is updated by GEM to hold to descriptor entry index
137 * which follows the last descriptor already processed by GEM. Note that
138 * this value is mirrored in GREG_STAT which eliminates the need to even
139 * access this register in the driver during interrupt processing.
140 */
141
142/* TX Configuration Register.
143 *
144 * Note that TXDMA_CFG_FTHRESH, the TX FIFO Threshold, is an obsolete feature
145 * that was meant to be used with jumbo packets. It should be set to the
146 * maximum value of 0x4ff, else one risks getting TX MAC Underrun errors.
147 */
148#define TXDMA_CFG_ENABLE 0x00000001 /* Enable TX DMA channel */
149#define TXDMA_CFG_RINGSZ 0x0000001e /* TX descriptor ring size */
150#define TXDMA_CFG_RINGSZ_32 0x00000000 /* 32 TX descriptors */
151#define TXDMA_CFG_RINGSZ_64 0x00000002 /* 64 TX descriptors */
152#define TXDMA_CFG_RINGSZ_128 0x00000004 /* 128 TX descriptors */
153#define TXDMA_CFG_RINGSZ_256 0x00000006 /* 256 TX descriptors */
154#define TXDMA_CFG_RINGSZ_512 0x00000008 /* 512 TX descriptors */
155#define TXDMA_CFG_RINGSZ_1K 0x0000000a /* 1024 TX descriptors */
156#define TXDMA_CFG_RINGSZ_2K 0x0000000c /* 2048 TX descriptors */
157#define TXDMA_CFG_RINGSZ_4K 0x0000000e /* 4096 TX descriptors */
158#define TXDMA_CFG_RINGSZ_8K 0x00000010 /* 8192 TX descriptors */
159#define TXDMA_CFG_PIOSEL 0x00000020 /* Enable TX FIFO PIO from cpu */
160#define TXDMA_CFG_FTHRESH 0x001ffc00 /* TX FIFO Threshold, obsolete */
161#define TXDMA_CFG_PMODE 0x00200000 /* TXALL irq means TX FIFO empty*/
162
163/* TX Descriptor Base Low/High.
164 *
165 * These two registers store the 53 most significant bits of the base address
166 * of the TX descriptor table. The 11 least significant bits are always
167 * zero. As a result, the TX descriptor table must be 2K aligned.
168 */
169
170/* The rest of the TXDMA_* registers are for diagnostics and debug, I will document
171 * them later. -DaveM
172 */
173
174/* WakeOnLan Registers */
175#define WOL_MATCH0 0x3000UL
176#define WOL_MATCH1 0x3004UL
177#define WOL_MATCH2 0x3008UL
178#define WOL_MCOUNT 0x300CUL
179#define WOL_WAKECSR 0x3010UL
180
181/* WOL Match count register
182 */
183#define WOL_MCOUNT_N 0x00000010
184#define WOL_MCOUNT_M 0x00000000 /* 0 << 8 */
185
186#define WOL_WAKECSR_ENABLE 0x00000001
187#define WOL_WAKECSR_MII 0x00000002
188#define WOL_WAKECSR_SEEN 0x00000004
189#define WOL_WAKECSR_FILT_UCAST 0x00000008
190#define WOL_WAKECSR_FILT_MCAST 0x00000010
191#define WOL_WAKECSR_FILT_BCAST 0x00000020
192#define WOL_WAKECSR_FILT_SEEN 0x00000040
193
194
195/* Receive DMA Registers */
196#define RXDMA_CFG 0x4000UL /* RX Configuration Register */
197#define RXDMA_DBLOW 0x4004UL /* RX Descriptor Base Low */
198#define RXDMA_DBHI 0x4008UL /* RX Descriptor Base High */
199#define RXDMA_FWPTR 0x400CUL /* RX FIFO Write Pointer */
200#define RXDMA_FSWPTR 0x4010UL /* RX FIFO Shadow Write Pointer */
201#define RXDMA_FRPTR 0x4014UL /* RX FIFO Read Pointer */
202#define RXDMA_PCNT 0x4018UL /* RX FIFO Packet Counter */
203#define RXDMA_SMACHINE 0x401CUL /* RX State Machine Register */
204#define RXDMA_PTHRESH 0x4020UL /* Pause Thresholds */
205#define RXDMA_DPLOW 0x4024UL /* RX Data Pointer Low */
206#define RXDMA_DPHI 0x4028UL /* RX Data Pointer High */
207#define RXDMA_KICK 0x4100UL /* RX Kick Register */
208#define RXDMA_DONE 0x4104UL /* RX Completion Register */
209#define RXDMA_BLANK 0x4108UL /* RX Blanking Register */
210#define RXDMA_FADDR 0x410CUL /* RX FIFO Address */
211#define RXDMA_FTAG 0x4110UL /* RX FIFO Tag */
212#define RXDMA_DLOW 0x4114UL /* RX FIFO Data Low */
213#define RXDMA_DHIT1 0x4118UL /* RX FIFO Data HighT0 */
214#define RXDMA_DHIT0 0x411CUL /* RX FIFO Data HighT1 */
215#define RXDMA_FSZ 0x4120UL /* RX FIFO Size */
216
217/* RX Configuration Register. */
218#define RXDMA_CFG_ENABLE 0x00000001 /* Enable RX DMA channel */
219#define RXDMA_CFG_RINGSZ 0x0000001e /* RX descriptor ring size */
220#define RXDMA_CFG_RINGSZ_32 0x00000000 /* - 32 entries */
221#define RXDMA_CFG_RINGSZ_64 0x00000002 /* - 64 entries */
222#define RXDMA_CFG_RINGSZ_128 0x00000004 /* - 128 entries */
223#define RXDMA_CFG_RINGSZ_256 0x00000006 /* - 256 entries */
224#define RXDMA_CFG_RINGSZ_512 0x00000008 /* - 512 entries */
225#define RXDMA_CFG_RINGSZ_1K 0x0000000a /* - 1024 entries */
226#define RXDMA_CFG_RINGSZ_2K 0x0000000c /* - 2048 entries */
227#define RXDMA_CFG_RINGSZ_4K 0x0000000e /* - 4096 entries */
228#define RXDMA_CFG_RINGSZ_8K 0x00000010 /* - 8192 entries */
229#define RXDMA_CFG_RINGSZ_BDISAB 0x00000020 /* Disable RX desc batching */
230#define RXDMA_CFG_FBOFF 0x00001c00 /* Offset of first data byte */
231#define RXDMA_CFG_CSUMOFF 0x000fe000 /* Skip bytes before csum calc */
232#define RXDMA_CFG_FTHRESH 0x07000000 /* RX FIFO dma start threshold */
233#define RXDMA_CFG_FTHRESH_64 0x00000000 /* - 64 bytes */
234#define RXDMA_CFG_FTHRESH_128 0x01000000 /* - 128 bytes */
235#define RXDMA_CFG_FTHRESH_256 0x02000000 /* - 256 bytes */
236#define RXDMA_CFG_FTHRESH_512 0x03000000 /* - 512 bytes */
237#define RXDMA_CFG_FTHRESH_1K 0x04000000 /* - 1024 bytes */
238#define RXDMA_CFG_FTHRESH_2K 0x05000000 /* - 2048 bytes */
239
240/* RX Descriptor Base Low/High.
241 *
242 * These two registers store the 53 most significant bits of the base address
243 * of the RX descriptor table. The 11 least significant bits are always
244 * zero. As a result, the RX descriptor table must be 2K aligned.
245 */
246
247/* RX PAUSE Thresholds.
248 *
249 * These values determine when XOFF and XON PAUSE frames are emitted by
250 * GEM. The thresholds measure RX FIFO occupancy in units of 64 bytes.
251 */
252#define RXDMA_PTHRESH_OFF 0x000001ff /* XOFF emitted w/FIFO > this */
253#define RXDMA_PTHRESH_ON 0x001ff000 /* XON emitted w/FIFO < this */
254
255/* RX Kick Register.
256 *
257 * This 13-bit register is written by the host CPU and holds the last
258 * valid RX descriptor number plus one. This is, if 'N' is written to
259 * this register, it means that all RX descriptors up to but excluding
260 * 'N' are valid.
261 *
262 * The hardware requires that RX descriptors are posted in increments
263 * of 4. This means 'N' must be a multiple of four. For the best
264 * performance, the first new descriptor being posted should be (PCI)
265 * cache line aligned.
266 */
267
268/* RX Completion Register.
269 *
270 * This 13-bit register is updated by GEM to indicate which RX descriptors
271 * have already been used for receive frames. All descriptors up to but
272 * excluding the value in this register are ready to be processed. GEM
273 * updates this register value after the RX FIFO empties completely into
274 * the RX descriptor's buffer, but before the RX_DONE bit is set in the
275 * interrupt status register.
276 */
277
278/* RX Blanking Register. */
279#define RXDMA_BLANK_IPKTS 0x000001ff /* RX_DONE asserted after this
280 * many packets received since
281 * previous RX_DONE.
282 */
283#define RXDMA_BLANK_ITIME 0x000ff000 /* RX_DONE asserted after this
284 * many clocks (measured in 2048
285 * PCI clocks) were counted since
286 * the previous RX_DONE.
287 */
288
289/* RX FIFO Size.
290 *
291 * This 11-bit read-only register indicates how large, in units of 64-bytes,
292 * the RX FIFO is. The driver uses this to properly configure the RX PAUSE
293 * thresholds.
294 */
295
296/* The rest of the RXDMA_* registers are for diagnostics and debug, I will document
297 * them later. -DaveM
298 */
299
300/* MAC Registers */
301#define MAC_TXRST 0x6000UL /* TX MAC Software Reset Command*/
302#define MAC_RXRST 0x6004UL /* RX MAC Software Reset Command*/
303#define MAC_SNDPAUSE 0x6008UL /* Send Pause Command Register */
304#define MAC_TXSTAT 0x6010UL /* TX MAC Status Register */
305#define MAC_RXSTAT 0x6014UL /* RX MAC Status Register */
306#define MAC_CSTAT 0x6018UL /* MAC Control Status Register */
307#define MAC_TXMASK 0x6020UL /* TX MAC Mask Register */
308#define MAC_RXMASK 0x6024UL /* RX MAC Mask Register */
309#define MAC_MCMASK 0x6028UL /* MAC Control Mask Register */
310#define MAC_TXCFG 0x6030UL /* TX MAC Configuration Register*/
311#define MAC_RXCFG 0x6034UL /* RX MAC Configuration Register*/
312#define MAC_MCCFG 0x6038UL /* MAC Control Config Register */
313#define MAC_XIFCFG 0x603CUL /* XIF Configuration Register */
314#define MAC_IPG0 0x6040UL /* InterPacketGap0 Register */
315#define MAC_IPG1 0x6044UL /* InterPacketGap1 Register */
316#define MAC_IPG2 0x6048UL /* InterPacketGap2 Register */
317#define MAC_STIME 0x604CUL /* SlotTime Register */
318#define MAC_MINFSZ 0x6050UL /* MinFrameSize Register */
319#define MAC_MAXFSZ 0x6054UL /* MaxFrameSize Register */
320#define MAC_PASIZE 0x6058UL /* PA Size Register */
321#define MAC_JAMSIZE 0x605CUL /* JamSize Register */
322#define MAC_ATTLIM 0x6060UL /* Attempt Limit Register */
323#define MAC_MCTYPE 0x6064UL /* MAC Control Type Register */
324#define MAC_ADDR0 0x6080UL /* MAC Address 0 Register */
325#define MAC_ADDR1 0x6084UL /* MAC Address 1 Register */
326#define MAC_ADDR2 0x6088UL /* MAC Address 2 Register */
327#define MAC_ADDR3 0x608CUL /* MAC Address 3 Register */
328#define MAC_ADDR4 0x6090UL /* MAC Address 4 Register */
329#define MAC_ADDR5 0x6094UL /* MAC Address 5 Register */
330#define MAC_ADDR6 0x6098UL /* MAC Address 6 Register */
331#define MAC_ADDR7 0x609CUL /* MAC Address 7 Register */
332#define MAC_ADDR8 0x60A0UL /* MAC Address 8 Register */
333#define MAC_AFILT0 0x60A4UL /* Address Filter 0 Register */
334#define MAC_AFILT1 0x60A8UL /* Address Filter 1 Register */
335#define MAC_AFILT2 0x60ACUL /* Address Filter 2 Register */
336#define MAC_AF21MSK 0x60B0UL /* Address Filter 2&1 Mask Reg */
337#define MAC_AF0MSK 0x60B4UL /* Address Filter 0 Mask Reg */
338#define MAC_HASH0 0x60C0UL /* Hash Table 0 Register */
339#define MAC_HASH1 0x60C4UL /* Hash Table 1 Register */
340#define MAC_HASH2 0x60C8UL /* Hash Table 2 Register */
341#define MAC_HASH3 0x60CCUL /* Hash Table 3 Register */
342#define MAC_HASH4 0x60D0UL /* Hash Table 4 Register */
343#define MAC_HASH5 0x60D4UL /* Hash Table 5 Register */
344#define MAC_HASH6 0x60D8UL /* Hash Table 6 Register */
345#define MAC_HASH7 0x60DCUL /* Hash Table 7 Register */
346#define MAC_HASH8 0x60E0UL /* Hash Table 8 Register */
347#define MAC_HASH9 0x60E4UL /* Hash Table 9 Register */
348#define MAC_HASH10 0x60E8UL /* Hash Table 10 Register */
349#define MAC_HASH11 0x60ECUL /* Hash Table 11 Register */
350#define MAC_HASH12 0x60F0UL /* Hash Table 12 Register */
351#define MAC_HASH13 0x60F4UL /* Hash Table 13 Register */
352#define MAC_HASH14 0x60F8UL /* Hash Table 14 Register */
353#define MAC_HASH15 0x60FCUL /* Hash Table 15 Register */
354#define MAC_NCOLL 0x6100UL /* Normal Collision Counter */
355#define MAC_FASUCC 0x6104UL /* First Attmpt. Succ Coll Ctr. */
356#define MAC_ECOLL 0x6108UL /* Excessive Collision Counter */
357#define MAC_LCOLL 0x610CUL /* Late Collision Counter */
358#define MAC_DTIMER 0x6110UL /* Defer Timer */
359#define MAC_PATMPS 0x6114UL /* Peak Attempts Register */
360#define MAC_RFCTR 0x6118UL /* Receive Frame Counter */
361#define MAC_LERR 0x611CUL /* Length Error Counter */
362#define MAC_AERR 0x6120UL /* Alignment Error Counter */
363#define MAC_FCSERR 0x6124UL /* FCS Error Counter */
364#define MAC_RXCVERR 0x6128UL /* RX code Violation Error Ctr */
365#define MAC_RANDSEED 0x6130UL /* Random Number Seed Register */
366#define MAC_SMACHINE 0x6134UL /* State Machine Register */
367
368/* TX MAC Software Reset Command. */
369#define MAC_TXRST_CMD 0x00000001 /* Start sw reset, self-clears */
370
371/* RX MAC Software Reset Command. */
372#define MAC_RXRST_CMD 0x00000001 /* Start sw reset, self-clears */
373
374/* Send Pause Command. */
375#define MAC_SNDPAUSE_TS 0x0000ffff /* The pause_time operand used in
376 * Send_Pause and flow-control
377 * handshakes.
378 */
379#define MAC_SNDPAUSE_SP 0x00010000 /* Setting this bit instructs the MAC
380 * to send a Pause Flow Control
381 * frame onto the network.
382 */
383
384/* TX MAC Status Register. */
385#define MAC_TXSTAT_XMIT 0x00000001 /* Frame Transmitted */
386#define MAC_TXSTAT_URUN 0x00000002 /* TX Underrun */
387#define MAC_TXSTAT_MPE 0x00000004 /* Max Packet Size Error */
388#define MAC_TXSTAT_NCE 0x00000008 /* Normal Collision Cntr Expire */
389#define MAC_TXSTAT_ECE 0x00000010 /* Excess Collision Cntr Expire */
390#define MAC_TXSTAT_LCE 0x00000020 /* Late Collision Cntr Expire */
391#define MAC_TXSTAT_FCE 0x00000040 /* First Collision Cntr Expire */
392#define MAC_TXSTAT_DTE 0x00000080 /* Defer Timer Expire */
393#define MAC_TXSTAT_PCE 0x00000100 /* Peak Attempts Cntr Expire */
394
395/* RX MAC Status Register. */
396#define MAC_RXSTAT_RCV 0x00000001 /* Frame Received */
397#define MAC_RXSTAT_OFLW 0x00000002 /* Receive Overflow */
398#define MAC_RXSTAT_FCE 0x00000004 /* Frame Cntr Expire */
399#define MAC_RXSTAT_ACE 0x00000008 /* Align Error Cntr Expire */
400#define MAC_RXSTAT_CCE 0x00000010 /* CRC Error Cntr Expire */
401#define MAC_RXSTAT_LCE 0x00000020 /* Length Error Cntr Expire */
402#define MAC_RXSTAT_VCE 0x00000040 /* Code Violation Cntr Expire */
403
404/* MAC Control Status Register. */
405#define MAC_CSTAT_PRCV 0x00000001 /* Pause Received */
406#define MAC_CSTAT_PS 0x00000002 /* Paused State */
407#define MAC_CSTAT_NPS 0x00000004 /* Not Paused State */
408#define MAC_CSTAT_PTR 0xffff0000 /* Pause Time Received */
409
410/* The layout of the MAC_{TX,RX,C}MASK registers is identical to that
411 * of MAC_{TX,RX,C}STAT. Bits set in MAC_{TX,RX,C}MASK will prevent
412 * that interrupt type from being signalled to front end of GEM. For
413 * the interrupt to actually get sent to the cpu, it is necessary to
414 * properly set the appropriate GREG_IMASK_{TX,RX,}MAC bits as well.
415 */
416
417/* TX MAC Configuration Register.
418 *
419 * NOTE: The TX MAC Enable bit must be cleared and polled until
420 * zero before any other bits in this register are changed.
421 *
422 * Also, enabling the Carrier Extension feature of GEM is
423 * a 3 step process 1) Set TX Carrier Extension 2) Set
424 * RX Carrier Extension 3) Set Slot Time to 0x200. This
425 * mode must be enabled when in half-duplex at 1Gbps, else
426 * it must be disabled.
427 */
428#define MAC_TXCFG_ENAB 0x00000001 /* TX MAC Enable */
429#define MAC_TXCFG_ICS 0x00000002 /* Ignore Carrier Sense */
430#define MAC_TXCFG_ICOLL 0x00000004 /* Ignore Collisions */
431#define MAC_TXCFG_EIPG0 0x00000008 /* Enable IPG0 */
432#define MAC_TXCFG_NGU 0x00000010 /* Never Give Up */
433#define MAC_TXCFG_NGUL 0x00000020 /* Never Give Up Limit */
434#define MAC_TXCFG_NBO 0x00000040 /* No Backoff */
435#define MAC_TXCFG_SD 0x00000080 /* Slow Down */
436#define MAC_TXCFG_NFCS 0x00000100 /* No FCS */
437#define MAC_TXCFG_TCE 0x00000200 /* TX Carrier Extension */
438
439/* RX MAC Configuration Register.
440 *
441 * NOTE: The RX MAC Enable bit must be cleared and polled until
442 * zero before any other bits in this register are changed.
443 *
444 * Similar rules apply to the Hash Filter Enable bit when
445 * programming the hash table registers, and the Address Filter
446 * Enable bit when programming the address filter registers.
447 */
448#define MAC_RXCFG_ENAB 0x00000001 /* RX MAC Enable */
449#define MAC_RXCFG_SPAD 0x00000002 /* Strip Pad */
450#define MAC_RXCFG_SFCS 0x00000004 /* Strip FCS */
451#define MAC_RXCFG_PROM 0x00000008 /* Promiscuous Mode */
452#define MAC_RXCFG_PGRP 0x00000010 /* Promiscuous Group */
453#define MAC_RXCFG_HFE 0x00000020 /* Hash Filter Enable */
454#define MAC_RXCFG_AFE 0x00000040 /* Address Filter Enable */
455#define MAC_RXCFG_DDE 0x00000080 /* Disable Discard on Error */
456#define MAC_RXCFG_RCE 0x00000100 /* RX Carrier Extension */
457
458/* MAC Control Config Register. */
459#define MAC_MCCFG_SPE 0x00000001 /* Send Pause Enable */
460#define MAC_MCCFG_RPE 0x00000002 /* Receive Pause Enable */
461#define MAC_MCCFG_PMC 0x00000004 /* Pass MAC Control */
462
463/* XIF Configuration Register.
464 *
465 * NOTE: When leaving or entering loopback mode, a global hardware
466 * init of GEM should be performed.
467 */
468#define MAC_XIFCFG_OE 0x00000001 /* MII TX Output Driver Enable */
469#define MAC_XIFCFG_LBCK 0x00000002 /* Loopback TX to RX */
470#define MAC_XIFCFG_DISE 0x00000004 /* Disable RX path during TX */
471#define MAC_XIFCFG_GMII 0x00000008 /* Use GMII clocks + datapath */
472#define MAC_XIFCFG_MBOE 0x00000010 /* Controls MII_BUF_EN pin */
473#define MAC_XIFCFG_LLED 0x00000020 /* Force LINKLED# active (low) */
474#define MAC_XIFCFG_FLED 0x00000040 /* Force FDPLXLED# active (low) */
475
476/* InterPacketGap0 Register. This 8-bit value is used as an extension
477 * to the InterPacketGap1 Register. Specifically it contributes to the
478 * timing of the RX-to-TX IPG. This value is ignored and presumed to
479 * be zero for TX-to-TX IPG calculations and/or when the Enable IPG0 bit
480 * is cleared in the TX MAC Configuration Register.
481 *
482 * This value in this register in terms of media byte time.
483 *
484 * Recommended value: 0x00
485 */
486
487/* InterPacketGap1 Register. This 8-bit value defines the first 2/3
488 * portion of the Inter Packet Gap.
489 *
490 * This value in this register in terms of media byte time.
491 *
492 * Recommended value: 0x08
493 */
494
495/* InterPacketGap2 Register. This 8-bit value defines the second 1/3
496 * portion of the Inter Packet Gap.
497 *
498 * This value in this register in terms of media byte time.
499 *
500 * Recommended value: 0x04
501 */
502
503/* Slot Time Register. This 10-bit value specifies the slot time
504 * parameter in units of media byte time. It determines the physical
505 * span of the network.
506 *
507 * Recommended value: 0x40
508 */
509
510/* Minimum Frame Size Register. This 10-bit register specifies the
511 * smallest sized frame the TXMAC will send onto the medium, and the
512 * RXMAC will receive from the medium.
513 *
514 * Recommended value: 0x40
515 */
516
517/* Maximum Frame and Burst Size Register.
518 *
519 * This register specifies two things. First it specifies the maximum
520 * sized frame the TXMAC will send and the RXMAC will recognize as
521 * valid. Second, it specifies the maximum run length of a burst of
522 * packets sent in half-duplex gigabit modes.
523 *
524 * Recommended value: 0x200005ee
525 */
526#define MAC_MAXFSZ_MFS 0x00007fff /* Max Frame Size */
527#define MAC_MAXFSZ_MBS 0x7fff0000 /* Max Burst Size */
528
529/* PA Size Register. This 10-bit register specifies the number of preamble
530 * bytes which will be transmitted at the beginning of each frame. A
531 * value of two or greater should be programmed here.
532 *
533 * Recommended value: 0x07
534 */
535
536/* Jam Size Register. This 4-bit register specifies the duration of
537 * the jam in units of media byte time.
538 *
539 * Recommended value: 0x04
540 */
541
542/* Attempts Limit Register. This 8-bit register specifies the number
543 * of attempts that the TXMAC will make to transmit a frame, before it
544 * resets its Attempts Counter. After reaching the Attempts Limit the
545 * TXMAC may or may not drop the frame, as determined by the NGU
546 * (Never Give Up) and NGUL (Never Give Up Limit) bits in the TXMAC
547 * Configuration Register.
548 *
549 * Recommended value: 0x10
550 */
551
552/* MAX Control Type Register. This 16-bit register specifies the
553 * "type" field of a MAC Control frame. The TXMAC uses this field to
554 * encapsulate the MAC Control frame for transmission, and the RXMAC
555 * uses it for decoding valid MAC Control frames received from the
556 * network.
557 *
558 * Recommended value: 0x8808
559 */
560
561/* MAC Address Registers. Each of these registers specify the
562 * ethernet MAC of the interface, 16-bits at a time. Register
563 * 0 specifies bits [47:32], register 1 bits [31:16], and register
564 * 2 bits [15:0].
565 *
566 * Registers 3 through and including 5 specify an alternate
567 * MAC address for the interface.
568 *
569 * Registers 6 through and including 8 specify the MAC Control
570 * Address, which must be the reserved multicast address for MAC
571 * Control frames.
572 *
573 * Example: To program primary station address a:b:c:d:e:f into
574 * the chip.
575 * MAC_Address_2 = (a << 8) | b
576 * MAC_Address_1 = (c << 8) | d
577 * MAC_Address_0 = (e << 8) | f
578 */
579
580/* Address Filter Registers. Registers 0 through 2 specify bit
581 * fields [47:32] through [15:0], respectively, of the address
582 * filter. The Address Filter 2&1 Mask Register denotes the 8-bit
583 * nibble mask for Address Filter Registers 2 and 1. The Address
584 * Filter 0 Mask Register denotes the 16-bit mask for the Address
585 * Filter Register 0.
586 */
587
588/* Hash Table Registers. Registers 0 through 15 specify bit fields
589 * [255:240] through [15:0], respectively, of the hash table.
590 */
591
592/* Statistics Registers. All of these registers are 16-bits and
593 * track occurrences of a specific event. GEM can be configured
594 * to interrupt the host cpu when any of these counters overflow.
595 * They should all be explicitly initialized to zero when the interface
596 * is brought up.
597 */
598
599/* Random Number Seed Register. This 10-bit value is used as the
600 * RNG seed inside GEM for the CSMA/CD backoff algorithm. It is
601 * recommended to program this register to the 10 LSB of the
602 * interfaces MAC address.
603 */
604
605/* Pause Timer, read-only. This 16-bit timer is used to time the pause
606 * interval as indicated by a received pause flow control frame.
607 * A non-zero value in this timer indicates that the MAC is currently in
608 * the paused state.
609 */
610
611/* MIF Registers */
612#define MIF_BBCLK 0x6200UL /* MIF Bit-Bang Clock */
613#define MIF_BBDATA 0x6204UL /* MIF Bit-Band Data */
614#define MIF_BBOENAB 0x6208UL /* MIF Bit-Bang Output Enable */
615#define MIF_FRAME 0x620CUL /* MIF Frame/Output Register */
616#define MIF_CFG 0x6210UL /* MIF Configuration Register */
617#define MIF_MASK 0x6214UL /* MIF Mask Register */
618#define MIF_STATUS 0x6218UL /* MIF Status Register */
619#define MIF_SMACHINE 0x621CUL /* MIF State Machine Register */
620
621/* MIF Bit-Bang Clock. This 1-bit register is used to generate the
622 * MDC clock waveform on the MII Management Interface when the MIF is
623 * programmed in the "Bit-Bang" mode. Writing a '1' after a '0' into
624 * this register will create a rising edge on the MDC, while writing
625 * a '0' after a '1' will create a falling edge. For every bit that
626 * is transferred on the management interface, both edges have to be
627 * generated.
628 */
629
630/* MIF Bit-Bang Data. This 1-bit register is used to generate the
631 * outgoing data (MDO) on the MII Management Interface when the MIF
632 * is programmed in the "Bit-Bang" mode. The daa will be steered to the
633 * appropriate MDIO based on the state of the PHY_Select bit in the MIF
634 * Configuration Register.
635 */
636
637/* MIF Big-Band Output Enable. THis 1-bit register is used to enable
638 * ('1') or disable ('0') the I-directional driver on the MII when the
639 * MIF is programmed in the "Bit-Bang" mode. The MDIO should be enabled
640 * when data bits are transferred from the MIF to the transceiver, and it
641 * should be disabled when the interface is idle or when data bits are
642 * transferred from the transceiver to the MIF (data portion of a read
643 * instruction). Only one MDIO will be enabled at a given time, depending
644 * on the state of the PHY_Select bit in the MIF Configuration Register.
645 */
646
647/* MIF Configuration Register. This 15-bit register controls the operation
648 * of the MIF.
649 */
650#define MIF_CFG_PSELECT 0x00000001 /* Xcvr slct: 0=mdio0 1=mdio1 */
651#define MIF_CFG_POLL 0x00000002 /* Enable polling mechanism */
652#define MIF_CFG_BBMODE 0x00000004 /* 1=bit-bang 0=frame mode */
653#define MIF_CFG_PRADDR 0x000000f8 /* Xcvr poll register address */
654#define MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */
655#define MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */
656#define MIF_CFG_PPADDR 0x00007c00 /* Xcvr poll PHY address */
657
658/* MIF Frame/Output Register. This 32-bit register allows the host to
659 * communicate with a transceiver in frame mode (as opposed to big-bang
660 * mode). Writes by the host specify an instrution. After being issued
661 * the host must poll this register for completion. Also, after
662 * completion this register holds the data returned by the transceiver
663 * if applicable.
664 */
665#define MIF_FRAME_ST 0xc0000000 /* STart of frame */
666#define MIF_FRAME_OP 0x30000000 /* OPcode */
667#define MIF_FRAME_PHYAD 0x0f800000 /* PHY ADdress */
668#define MIF_FRAME_REGAD 0x007c0000 /* REGister ADdress */
669#define MIF_FRAME_TAMSB 0x00020000 /* Turn Around MSB */
670#define MIF_FRAME_TALSB 0x00010000 /* Turn Around LSB */
671#define MIF_FRAME_DATA 0x0000ffff /* Instruction Payload */
672
673/* MIF Status Register. This register reports status when the MIF is
674 * operating in the poll mode. The poll status field is auto-clearing
675 * on read.
676 */
677#define MIF_STATUS_DATA 0xffff0000 /* Live image of XCVR reg */
678#define MIF_STATUS_STAT 0x0000ffff /* Which bits have changed */
679
680/* MIF Mask Register. This 16-bit register is used when in poll mode
681 * to say which bits of the polled register will cause an interrupt
682 * when changed.
683 */
684
685/* PCS/Serialink Registers */
686#define PCS_MIICTRL 0x9000UL /* PCS MII Control Register */
687#define PCS_MIISTAT 0x9004UL /* PCS MII Status Register */
688#define PCS_MIIADV 0x9008UL /* PCS MII Advertisement Reg */
689#define PCS_MIILP 0x900CUL /* PCS MII Link Partner Ability */
690#define PCS_CFG 0x9010UL /* PCS Configuration Register */
691#define PCS_SMACHINE 0x9014UL /* PCS State Machine Register */
692#define PCS_ISTAT 0x9018UL /* PCS Interrupt Status Reg */
693#define PCS_DMODE 0x9050UL /* Datapath Mode Register */
694#define PCS_SCTRL 0x9054UL /* Serialink Control Register */
695#define PCS_SOS 0x9058UL /* Shared Output Select Reg */
696#define PCS_SSTATE 0x905CUL /* Serialink State Register */
697
698/* PCD MII Control Register. */
699#define PCS_MIICTRL_SPD 0x00000040 /* Read as one, writes ignored */
700#define PCS_MIICTRL_CT 0x00000080 /* Force COL signal active */
701#define PCS_MIICTRL_DM 0x00000100 /* Duplex mode, forced low */
702#define PCS_MIICTRL_RAN 0x00000200 /* Restart auto-neg, self clear */
703#define PCS_MIICTRL_ISO 0x00000400 /* Read as zero, writes ignored */
704#define PCS_MIICTRL_PD 0x00000800 /* Read as zero, writes ignored */
705#define PCS_MIICTRL_ANE 0x00001000 /* Auto-neg enable */
706#define PCS_MIICTRL_SS 0x00002000 /* Read as zero, writes ignored */
707#define PCS_MIICTRL_WB 0x00004000 /* Wrapback, loopback at 10-bit
708 * input side of Serialink
709 */
710#define PCS_MIICTRL_RST 0x00008000 /* Resets PCS, self clearing */
711
712/* PCS MII Status Register. */
713#define PCS_MIISTAT_EC 0x00000001 /* Ext Capability: Read as zero */
714#define PCS_MIISTAT_JD 0x00000002 /* Jabber Detect: Read as zero */
715#define PCS_MIISTAT_LS 0x00000004 /* Link Status: 1=up 0=down */
716#define PCS_MIISTAT_ANA 0x00000008 /* Auto-neg Ability, always 1 */
717#define PCS_MIISTAT_RF 0x00000010 /* Remote Fault */
718#define PCS_MIISTAT_ANC 0x00000020 /* Auto-neg complete */
719#define PCS_MIISTAT_ES 0x00000100 /* Extended Status, always 1 */
720
721/* PCS MII Advertisement Register. */
722#define PCS_MIIADV_FD 0x00000020 /* Advertise Full Duplex */
723#define PCS_MIIADV_HD 0x00000040 /* Advertise Half Duplex */
724#define PCS_MIIADV_SP 0x00000080 /* Advertise Symmetric Pause */
725#define PCS_MIIADV_AP 0x00000100 /* Advertise Asymmetric Pause */
726#define PCS_MIIADV_RF 0x00003000 /* Remote Fault */
727#define PCS_MIIADV_ACK 0x00004000 /* Read-only */
728#define PCS_MIIADV_NP 0x00008000 /* Next-page, forced low */
729
730/* PCS MII Link Partner Ability Register. This register is equivalent
731 * to the Link Partnet Ability Register of the standard MII register set.
732 * It's layout corresponds to the PCS MII Advertisement Register.
733 */
734
735/* PCS Configuration Register. */
736#define PCS_CFG_ENABLE 0x00000001 /* Must be zero while changing
737 * PCS MII advertisement reg.
738 */
739#define PCS_CFG_SDO 0x00000002 /* Signal detect override */
740#define PCS_CFG_SDL 0x00000004 /* Signal detect active low */
741#define PCS_CFG_JS 0x00000018 /* Jitter-study:
742 * 0 = normal operation
743 * 1 = high-frequency test pattern
744 * 2 = low-frequency test pattern
745 * 3 = reserved
746 */
747#define PCS_CFG_TO 0x00000020 /* 10ms auto-neg timer override */
748
749/* PCS Interrupt Status Register. This register is self-clearing
750 * when read.
751 */
752#define PCS_ISTAT_LSC 0x00000004 /* Link Status Change */
753
754/* Datapath Mode Register. */
755#define PCS_DMODE_SM 0x00000001 /* 1 = use internal Serialink */
756#define PCS_DMODE_ESM 0x00000002 /* External SERDES mode */
757#define PCS_DMODE_MGM 0x00000004 /* MII/GMII mode */
758#define PCS_DMODE_GMOE 0x00000008 /* GMII Output Enable */
759
760/* Serialink Control Register.
761 *
762 * NOTE: When in SERDES mode, the loopback bit has inverse logic.
763 */
764#define PCS_SCTRL_LOOP 0x00000001 /* Loopback enable */
765#define PCS_SCTRL_ESCD 0x00000002 /* Enable sync char detection */
766#define PCS_SCTRL_LOCK 0x00000004 /* Lock to reference clock */
767#define PCS_SCTRL_EMP 0x00000018 /* Output driver emphasis */
768#define PCS_SCTRL_STEST 0x000001c0 /* Self test patterns */
769#define PCS_SCTRL_PDWN 0x00000200 /* Software power-down */
770#define PCS_SCTRL_RXZ 0x00000c00 /* PLL input to Serialink */
771#define PCS_SCTRL_RXP 0x00003000 /* PLL input to Serialink */
772#define PCS_SCTRL_TXZ 0x0000c000 /* PLL input to Serialink */
773#define PCS_SCTRL_TXP 0x00030000 /* PLL input to Serialink */
774
775/* Shared Output Select Register. For test and debug, allows multiplexing
776 * test outputs into the PROM address pins. Set to zero for normal
777 * operation.
778 */
779#define PCS_SOS_PADDR 0x00000003 /* PROM Address */
780
781/* PROM Image Space */
782#define PROM_START 0x100000UL /* Expansion ROM run time access*/
783#define PROM_SIZE 0x0fffffUL /* Size of ROM */
784#define PROM_END 0x200000UL /* End of ROM */
785
786/* MII definitions missing from mii.h */
787
788#define BMCR_SPD2 0x0040 /* Gigabit enable? (bcm5411) */
789#define LPA_PAUSE 0x0400
790
791/* More PHY registers (specific to Broadcom models) */
792
793/* MII BCM5201 MULTIPHY interrupt register */
794#define MII_BCM5201_INTERRUPT 0x1A
795#define MII_BCM5201_INTERRUPT_INTENABLE 0x4000
796
797#define MII_BCM5201_AUXMODE2 0x1B
798#define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008
799
800#define MII_BCM5201_MULTIPHY 0x1E
801
802/* MII BCM5201 MULTIPHY register bits */
803#define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002
804#define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008
805
806/* MII BCM5400 1000-BASET Control register */
807#define MII_BCM5400_GB_CONTROL 0x09
808#define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200
809
810/* MII BCM5400 AUXCONTROL register */
811#define MII_BCM5400_AUXCONTROL 0x18
812#define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004
813
814/* MII BCM5400 AUXSTATUS register */
815#define MII_BCM5400_AUXSTATUS 0x19
816#define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700
817#define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8
818
819/* When it can, GEM internally caches 4 aligned TX descriptors
820 * at a time, so that it can use full cacheline DMA reads.
821 *
822 * Note that unlike HME, there is no ownership bit in the descriptor
823 * control word. The same functionality is obtained via the TX-Kick
824 * and TX-Complete registers. As a result, GEM need not write back
825 * updated values to the TX descriptor ring, it only performs reads.
826 *
827 * Since TX descriptors are never modified by GEM, the driver can
828 * use the buffer DMA address as a place to keep track of allocated
829 * DMA mappings for a transmitted packet.
830 */
831struct gem_txd {
832 __le64 control_word;
833 __le64 buffer;
834};
835
836#define TXDCTRL_BUFSZ 0x0000000000007fffULL /* Buffer Size */
837#define TXDCTRL_CSTART 0x00000000001f8000ULL /* CSUM Start Offset */
838#define TXDCTRL_COFF 0x000000001fe00000ULL /* CSUM Stuff Offset */
839#define TXDCTRL_CENAB 0x0000000020000000ULL /* CSUM Enable */
840#define TXDCTRL_EOF 0x0000000040000000ULL /* End of Frame */
841#define TXDCTRL_SOF 0x0000000080000000ULL /* Start of Frame */
842#define TXDCTRL_INTME 0x0000000100000000ULL /* "Interrupt Me" */
843#define TXDCTRL_NOCRC 0x0000000200000000ULL /* No CRC Present */
844
845/* GEM requires that RX descriptors are provided four at a time,
846 * aligned. Also, the RX ring may not wrap around. This means that
847 * there will be at least 4 unused descriptor entries in the middle
848 * of the RX ring at all times.
849 *
850 * Similar to HME, GEM assumes that it can write garbage bytes before
851 * the beginning of the buffer and right after the end in order to DMA
852 * whole cachelines.
853 *
854 * Unlike for TX, GEM does update the status word in the RX descriptors
855 * when packets arrive. Therefore an ownership bit does exist in the
856 * RX descriptors. It is advisory, GEM clears it but does not check
857 * it in any way. So when buffers are posted to the RX ring (via the
858 * RX Kick register) by the driver it must make sure the buffers are
859 * truly ready and that the ownership bits are set properly.
860 *
861 * Even though GEM modifies the RX descriptors, it guarantees that the
862 * buffer DMA address field will stay the same when it performs these
863 * updates. Therefore it can be used to keep track of DMA mappings
864 * by the host driver just as in the TX descriptor case above.
865 */
866struct gem_rxd {
867 __le64 status_word;
868 __le64 buffer;
869};
870
871#define RXDCTRL_TCPCSUM 0x000000000000ffffULL /* TCP Pseudo-CSUM */
872#define RXDCTRL_BUFSZ 0x000000007fff0000ULL /* Buffer Size */
873#define RXDCTRL_OWN 0x0000000080000000ULL /* GEM owns this entry */
874#define RXDCTRL_HASHVAL 0x0ffff00000000000ULL /* Hash Value */
875#define RXDCTRL_HPASS 0x1000000000000000ULL /* Passed Hash Filter */
876#define RXDCTRL_ALTMAC 0x2000000000000000ULL /* Matched ALT MAC */
877#define RXDCTRL_BAD 0x4000000000000000ULL /* Frame has bad CRC */
878
879#define RXDCTRL_FRESH(gp) \
880 ((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) | \
881 RXDCTRL_OWN)
882
883#define TX_RING_SIZE 128
884#define RX_RING_SIZE 128
885
886#if TX_RING_SIZE == 32
887#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_32
888#elif TX_RING_SIZE == 64
889#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_64
890#elif TX_RING_SIZE == 128
891#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_128
892#elif TX_RING_SIZE == 256
893#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_256
894#elif TX_RING_SIZE == 512
895#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_512
896#elif TX_RING_SIZE == 1024
897#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_1K
898#elif TX_RING_SIZE == 2048
899#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_2K
900#elif TX_RING_SIZE == 4096
901#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_4K
902#elif TX_RING_SIZE == 8192
903#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_8K
904#else
905#error TX_RING_SIZE value is illegal...
906#endif
907
908#if RX_RING_SIZE == 32
909#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_32
910#elif RX_RING_SIZE == 64
911#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_64
912#elif RX_RING_SIZE == 128
913#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_128
914#elif RX_RING_SIZE == 256
915#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_256
916#elif RX_RING_SIZE == 512
917#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_512
918#elif RX_RING_SIZE == 1024
919#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_1K
920#elif RX_RING_SIZE == 2048
921#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_2K
922#elif RX_RING_SIZE == 4096
923#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_4K
924#elif RX_RING_SIZE == 8192
925#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_8K
926#else
927#error RX_RING_SIZE is illegal...
928#endif
929
930#define NEXT_TX(N) (((N) + 1) & (TX_RING_SIZE - 1))
931#define NEXT_RX(N) (((N) + 1) & (RX_RING_SIZE - 1))
932
933#define TX_BUFFS_AVAIL(GP) \
934 (((GP)->tx_old <= (GP)->tx_new) ? \
935 (GP)->tx_old + (TX_RING_SIZE - 1) - (GP)->tx_new : \
936 (GP)->tx_old - (GP)->tx_new - 1)
937
938#define RX_OFFSET 2
939#define RX_BUF_ALLOC_SIZE(gp) ((gp)->rx_buf_sz + 28 + RX_OFFSET + 64)
940
941#define RX_COPY_THRESHOLD 256
942
943#if TX_RING_SIZE < 128
944#define INIT_BLOCK_TX_RING_SIZE 128
945#else
946#define INIT_BLOCK_TX_RING_SIZE TX_RING_SIZE
947#endif
948
949#if RX_RING_SIZE < 128
950#define INIT_BLOCK_RX_RING_SIZE 128
951#else
952#define INIT_BLOCK_RX_RING_SIZE RX_RING_SIZE
953#endif
954
955struct gem_init_block {
956 struct gem_txd txd[INIT_BLOCK_TX_RING_SIZE];
957 struct gem_rxd rxd[INIT_BLOCK_RX_RING_SIZE];
958};
959
960enum gem_phy_type {
961 phy_mii_mdio0,
962 phy_mii_mdio1,
963 phy_serialink,
964 phy_serdes,
965};
966
967enum link_state {
968 link_down = 0, /* No link, will retry */
969 link_aneg, /* Autoneg in progress */
970 link_force_try, /* Try Forced link speed */
971 link_force_ret, /* Forced mode worked, retrying autoneg */
972 link_force_ok, /* Stay in forced mode */
973 link_up /* Link is up */
974};
975
976struct gem {
977 void __iomem *regs;
978 int rx_new, rx_old;
979 int tx_new, tx_old;
980
981 unsigned int has_wol : 1; /* chip supports wake-on-lan */
982 unsigned int asleep_wol : 1; /* was asleep with WOL enabled */
983
984 int cell_enabled;
985 u32 msg_enable;
986 u32 status;
987
988 struct napi_struct napi;
989
990 int tx_fifo_sz;
991 int rx_fifo_sz;
992 int rx_pause_off;
993 int rx_pause_on;
994 int rx_buf_sz;
995 u64 pause_entered;
996 u16 pause_last_time_recvd;
997 u32 mac_rx_cfg;
998 u32 swrst_base;
999
1000 int want_autoneg;
1001 int last_forced_speed;
1002 enum link_state lstate;
1003 struct timer_list link_timer;
1004 int timer_ticks;
1005 int wake_on_lan;
1006 struct work_struct reset_task;
1007 volatile int reset_task_pending;
1008
1009 enum gem_phy_type phy_type;
1010 struct mii_phy phy_mii;
1011 int mii_phy_addr;
1012
1013 struct gem_init_block *init_block;
1014 struct sk_buff *rx_skbs[RX_RING_SIZE];
1015 struct sk_buff *tx_skbs[TX_RING_SIZE];
1016 dma_addr_t gblock_dvma;
1017
1018 struct pci_dev *pdev;
1019 struct net_device *dev;
1020#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
1021 struct device_node *of_node;
1022#endif
1023};
1024
1025#define found_mii_phy(gp) ((gp->phy_type == phy_mii_mdio0 || gp->phy_type == phy_mii_mdio1) && \
1026 gp->phy_mii.def && gp->phy_mii.def->ops)
1027
1028#endif /* _SUNGEM_H */