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1/* SPDX-License-Identifier: GPL-2.0-only */
2/****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
6 */
7
8#ifndef EFX_IO_H
9#define EFX_IO_H
10
11#include <linux/io.h>
12#include <linux/spinlock.h>
13
14/**************************************************************************
15 *
16 * NIC register I/O
17 *
18 **************************************************************************
19 *
20 * The EF10 architecture exposes very few registers to the host and
21 * most of them are only 32 bits wide. The only exceptions are the MC
22 * doorbell register pair, which has its own latching, and
23 * TX_DESC_UPD.
24 *
25 * The TX_DESC_UPD DMA descriptor pointer is 128-bits but is a special
26 * case in the BIU to avoid the need for locking in the host:
27 *
28 * - It is write-only.
29 * - The semantics of writing to this register is such that
30 * replacing the low 96 bits with zero does not affect functionality.
31 * - If the host writes to the last dword address of the register
32 * (i.e. the high 32 bits) the underlying register will always be
33 * written. If the collector and the current write together do not
34 * provide values for all 128 bits of the register, the low 96 bits
35 * will be written as zero.
36 */
37
38#if BITS_PER_LONG == 64
39#define EFX_USE_QWORD_IO 1
40#endif
41
42/* Hardware issue requires that only 64-bit naturally aligned writes
43 * are seen by hardware. Its not strictly necessary to restrict to
44 * x86_64 arch, but done for safety since unusual write combining behaviour
45 * can break PIO.
46 */
47#ifdef CONFIG_X86_64
48/* PIO is a win only if write-combining is possible */
49#ifdef ioremap_wc
50#define EFX_USE_PIO 1
51#endif
52#endif
53
54static inline u32 efx_reg(struct efx_nic *efx, unsigned int reg)
55{
56 return efx->reg_base + reg;
57}
58
59#ifdef EFX_USE_QWORD_IO
60static inline void _efx_writeq(struct efx_nic *efx, __le64 value,
61 unsigned int reg)
62{
63 __raw_writeq((__force u64)value, efx->membase + reg);
64}
65static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg)
66{
67 return (__force __le64)__raw_readq(efx->membase + reg);
68}
69#endif
70
71static inline void _efx_writed(struct efx_nic *efx, __le32 value,
72 unsigned int reg)
73{
74 __raw_writel((__force u32)value, efx->membase + reg);
75}
76static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg)
77{
78 return (__force __le32)__raw_readl(efx->membase + reg);
79}
80
81/* Write a normal 128-bit CSR, locking as appropriate. */
82static inline void efx_writeo(struct efx_nic *efx, const efx_oword_t *value,
83 unsigned int reg)
84{
85 unsigned long flags __attribute__ ((unused));
86
87 netif_vdbg(efx, hw, efx->net_dev,
88 "writing register %x with " EFX_OWORD_FMT "\n", reg,
89 EFX_OWORD_VAL(*value));
90
91 spin_lock_irqsave(&efx->biu_lock, flags);
92#ifdef EFX_USE_QWORD_IO
93 _efx_writeq(efx, value->u64[0], reg + 0);
94 _efx_writeq(efx, value->u64[1], reg + 8);
95#else
96 _efx_writed(efx, value->u32[0], reg + 0);
97 _efx_writed(efx, value->u32[1], reg + 4);
98 _efx_writed(efx, value->u32[2], reg + 8);
99 _efx_writed(efx, value->u32[3], reg + 12);
100#endif
101 spin_unlock_irqrestore(&efx->biu_lock, flags);
102}
103
104/* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
105static inline void efx_writed(struct efx_nic *efx, const efx_dword_t *value,
106 unsigned int reg)
107{
108 netif_vdbg(efx, hw, efx->net_dev,
109 "writing register %x with "EFX_DWORD_FMT"\n",
110 reg, EFX_DWORD_VAL(*value));
111
112 /* No lock required */
113 _efx_writed(efx, value->u32[0], reg);
114}
115
116/* Read a 128-bit CSR, locking as appropriate. */
117static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
118 unsigned int reg)
119{
120 unsigned long flags __attribute__ ((unused));
121
122 spin_lock_irqsave(&efx->biu_lock, flags);
123 value->u32[0] = _efx_readd(efx, reg + 0);
124 value->u32[1] = _efx_readd(efx, reg + 4);
125 value->u32[2] = _efx_readd(efx, reg + 8);
126 value->u32[3] = _efx_readd(efx, reg + 12);
127 spin_unlock_irqrestore(&efx->biu_lock, flags);
128
129 netif_vdbg(efx, hw, efx->net_dev,
130 "read from register %x, got " EFX_OWORD_FMT "\n", reg,
131 EFX_OWORD_VAL(*value));
132}
133
134/* Read a 32-bit CSR or SRAM */
135static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,
136 unsigned int reg)
137{
138 value->u32[0] = _efx_readd(efx, reg);
139 netif_vdbg(efx, hw, efx->net_dev,
140 "read from register %x, got "EFX_DWORD_FMT"\n",
141 reg, EFX_DWORD_VAL(*value));
142}
143
144/* Write a 128-bit CSR forming part of a table */
145static inline void
146efx_writeo_table(struct efx_nic *efx, const efx_oword_t *value,
147 unsigned int reg, unsigned int index)
148{
149 efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));
150}
151
152/* Read a 128-bit CSR forming part of a table */
153static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value,
154 unsigned int reg, unsigned int index)
155{
156 efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
157}
158
159/* default VI stride (step between per-VI registers) is 8K on EF10 and
160 * 64K on EF100
161 */
162#define EFX_DEFAULT_VI_STRIDE 0x2000
163#define EF100_DEFAULT_VI_STRIDE 0x10000
164
165/* Calculate offset to page-mapped register */
166static inline unsigned int efx_paged_reg(struct efx_nic *efx, unsigned int page,
167 unsigned int reg)
168{
169 return page * efx->vi_stride + reg;
170}
171
172/* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
173static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,
174 unsigned int reg, unsigned int page)
175{
176 reg = efx_paged_reg(efx, page, reg);
177
178 netif_vdbg(efx, hw, efx->net_dev,
179 "writing register %x with " EFX_OWORD_FMT "\n", reg,
180 EFX_OWORD_VAL(*value));
181
182#ifdef EFX_USE_QWORD_IO
183 _efx_writeq(efx, value->u64[0], reg + 0);
184 _efx_writeq(efx, value->u64[1], reg + 8);
185#else
186 _efx_writed(efx, value->u32[0], reg + 0);
187 _efx_writed(efx, value->u32[1], reg + 4);
188 _efx_writed(efx, value->u32[2], reg + 8);
189 _efx_writed(efx, value->u32[3], reg + 12);
190#endif
191}
192#define efx_writeo_page(efx, value, reg, page) \
193 _efx_writeo_page(efx, value, \
194 reg + \
195 BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
196 page)
197
198/* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the
199 * high bits of RX_DESC_UPD or TX_DESC_UPD)
200 */
201static inline void
202_efx_writed_page(struct efx_nic *efx, const efx_dword_t *value,
203 unsigned int reg, unsigned int page)
204{
205 efx_writed(efx, value, efx_paged_reg(efx, page, reg));
206}
207#define efx_writed_page(efx, value, reg, page) \
208 _efx_writed_page(efx, value, \
209 reg + \
210 BUILD_BUG_ON_ZERO((reg) != 0x180 && \
211 (reg) != 0x200 && \
212 (reg) != 0x400 && \
213 (reg) != 0x420 && \
214 (reg) != 0x830 && \
215 (reg) != 0x83c && \
216 (reg) != 0xa18 && \
217 (reg) != 0xa1c), \
218 page)
219
220/* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug
221 * in the BIU means that writes to TIMER_COMMAND[0] invalidate the
222 * collector register.
223 */
224static inline void _efx_writed_page_locked(struct efx_nic *efx,
225 const efx_dword_t *value,
226 unsigned int reg,
227 unsigned int page)
228{
229 unsigned long flags __attribute__ ((unused));
230
231 if (page == 0) {
232 spin_lock_irqsave(&efx->biu_lock, flags);
233 efx_writed(efx, value, efx_paged_reg(efx, page, reg));
234 spin_unlock_irqrestore(&efx->biu_lock, flags);
235 } else {
236 efx_writed(efx, value, efx_paged_reg(efx, page, reg));
237 }
238}
239#define efx_writed_page_locked(efx, value, reg, page) \
240 _efx_writed_page_locked(efx, value, \
241 reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
242 page)
243
244#endif /* EFX_IO_H */