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1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
30 * 82571EB Gigabit Ethernet Controller
31 * 82571EB Gigabit Ethernet Controller (Copper)
32 * 82571EB Gigabit Ethernet Controller (Fiber)
33 * 82571EB Dual Port Gigabit Mezzanine Adapter
34 * 82571EB Quad Port Gigabit Mezzanine Adapter
35 * 82571PT Gigabit PT Quad Port Server ExpressModule
36 * 82572EI Gigabit Ethernet Controller (Copper)
37 * 82572EI Gigabit Ethernet Controller (Fiber)
38 * 82572EI Gigabit Ethernet Controller
39 * 82573V Gigabit Ethernet Controller (Copper)
40 * 82573E Gigabit Ethernet Controller (Copper)
41 * 82573L Gigabit Ethernet Controller
42 * 82574L Gigabit Network Connection
43 * 82583V Gigabit Network Connection
44 */
45
46#include "e1000.h"
47
48#define ID_LED_RESERVED_F746 0xF746
49#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
50 (ID_LED_OFF1_ON2 << 8) | \
51 (ID_LED_DEF1_DEF2 << 4) | \
52 (ID_LED_DEF1_DEF2))
53
54#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
55#define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */
56#define E1000_BASE1000T_STATUS 10
57#define E1000_IDLE_ERROR_COUNT_MASK 0xFF
58#define E1000_RECEIVE_ERROR_COUNTER 21
59#define E1000_RECEIVE_ERROR_MAX 0xFFFF
60
61#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
62
63static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
64static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
65static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
66static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
67static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
68 u16 words, u16 *data);
69static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
70static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
71static s32 e1000_setup_link_82571(struct e1000_hw *hw);
72static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
73static void e1000_clear_vfta_82571(struct e1000_hw *hw);
74static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
75static s32 e1000_led_on_82574(struct e1000_hw *hw);
76static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
77static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
78static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
79static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
80static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
81static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
82static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
83
84/**
85 * e1000_init_phy_params_82571 - Init PHY func ptrs.
86 * @hw: pointer to the HW structure
87 **/
88static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
89{
90 struct e1000_phy_info *phy = &hw->phy;
91 s32 ret_val;
92
93 if (hw->phy.media_type != e1000_media_type_copper) {
94 phy->type = e1000_phy_none;
95 return 0;
96 }
97
98 phy->addr = 1;
99 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
100 phy->reset_delay_us = 100;
101
102 phy->ops.power_up = e1000_power_up_phy_copper;
103 phy->ops.power_down = e1000_power_down_phy_copper_82571;
104
105 switch (hw->mac.type) {
106 case e1000_82571:
107 case e1000_82572:
108 phy->type = e1000_phy_igp_2;
109 break;
110 case e1000_82573:
111 phy->type = e1000_phy_m88;
112 break;
113 case e1000_82574:
114 case e1000_82583:
115 phy->type = e1000_phy_bm;
116 phy->ops.acquire = e1000_get_hw_semaphore_82574;
117 phy->ops.release = e1000_put_hw_semaphore_82574;
118 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
119 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
120 break;
121 default:
122 return -E1000_ERR_PHY;
123 break;
124 }
125
126 /* This can only be done after all function pointers are setup. */
127 ret_val = e1000_get_phy_id_82571(hw);
128 if (ret_val) {
129 e_dbg("Error getting PHY ID\n");
130 return ret_val;
131 }
132
133 /* Verify phy id */
134 switch (hw->mac.type) {
135 case e1000_82571:
136 case e1000_82572:
137 if (phy->id != IGP01E1000_I_PHY_ID)
138 ret_val = -E1000_ERR_PHY;
139 break;
140 case e1000_82573:
141 if (phy->id != M88E1111_I_PHY_ID)
142 ret_val = -E1000_ERR_PHY;
143 break;
144 case e1000_82574:
145 case e1000_82583:
146 if (phy->id != BME1000_E_PHY_ID_R2)
147 ret_val = -E1000_ERR_PHY;
148 break;
149 default:
150 ret_val = -E1000_ERR_PHY;
151 break;
152 }
153
154 if (ret_val)
155 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
156
157 return ret_val;
158}
159
160/**
161 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
162 * @hw: pointer to the HW structure
163 **/
164static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
165{
166 struct e1000_nvm_info *nvm = &hw->nvm;
167 u32 eecd = er32(EECD);
168 u16 size;
169
170 nvm->opcode_bits = 8;
171 nvm->delay_usec = 1;
172 switch (nvm->override) {
173 case e1000_nvm_override_spi_large:
174 nvm->page_size = 32;
175 nvm->address_bits = 16;
176 break;
177 case e1000_nvm_override_spi_small:
178 nvm->page_size = 8;
179 nvm->address_bits = 8;
180 break;
181 default:
182 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
183 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
184 break;
185 }
186
187 switch (hw->mac.type) {
188 case e1000_82573:
189 case e1000_82574:
190 case e1000_82583:
191 if (((eecd >> 15) & 0x3) == 0x3) {
192 nvm->type = e1000_nvm_flash_hw;
193 nvm->word_size = 2048;
194 /*
195 * Autonomous Flash update bit must be cleared due
196 * to Flash update issue.
197 */
198 eecd &= ~E1000_EECD_AUPDEN;
199 ew32(EECD, eecd);
200 break;
201 }
202 /* Fall Through */
203 default:
204 nvm->type = e1000_nvm_eeprom_spi;
205 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
206 E1000_EECD_SIZE_EX_SHIFT);
207 /*
208 * Added to a constant, "size" becomes the left-shift value
209 * for setting word_size.
210 */
211 size += NVM_WORD_SIZE_BASE_SHIFT;
212
213 /* EEPROM access above 16k is unsupported */
214 if (size > 14)
215 size = 14;
216 nvm->word_size = 1 << size;
217 break;
218 }
219
220 /* Function Pointers */
221 switch (hw->mac.type) {
222 case e1000_82574:
223 case e1000_82583:
224 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
225 nvm->ops.release = e1000_put_hw_semaphore_82574;
226 break;
227 default:
228 break;
229 }
230
231 return 0;
232}
233
234/**
235 * e1000_init_mac_params_82571 - Init MAC func ptrs.
236 * @hw: pointer to the HW structure
237 **/
238static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
239{
240 struct e1000_hw *hw = &adapter->hw;
241 struct e1000_mac_info *mac = &hw->mac;
242 struct e1000_mac_operations *func = &mac->ops;
243 u32 swsm = 0;
244 u32 swsm2 = 0;
245 bool force_clear_smbi = false;
246
247 /* Set media type */
248 switch (adapter->pdev->device) {
249 case E1000_DEV_ID_82571EB_FIBER:
250 case E1000_DEV_ID_82572EI_FIBER:
251 case E1000_DEV_ID_82571EB_QUAD_FIBER:
252 hw->phy.media_type = e1000_media_type_fiber;
253 break;
254 case E1000_DEV_ID_82571EB_SERDES:
255 case E1000_DEV_ID_82572EI_SERDES:
256 case E1000_DEV_ID_82571EB_SERDES_DUAL:
257 case E1000_DEV_ID_82571EB_SERDES_QUAD:
258 hw->phy.media_type = e1000_media_type_internal_serdes;
259 break;
260 default:
261 hw->phy.media_type = e1000_media_type_copper;
262 break;
263 }
264
265 /* Set mta register count */
266 mac->mta_reg_count = 128;
267 /* Set rar entry count */
268 mac->rar_entry_count = E1000_RAR_ENTRIES;
269 /* Adaptive IFS supported */
270 mac->adaptive_ifs = true;
271
272 /* check for link */
273 switch (hw->phy.media_type) {
274 case e1000_media_type_copper:
275 func->setup_physical_interface = e1000_setup_copper_link_82571;
276 func->check_for_link = e1000e_check_for_copper_link;
277 func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
278 break;
279 case e1000_media_type_fiber:
280 func->setup_physical_interface =
281 e1000_setup_fiber_serdes_link_82571;
282 func->check_for_link = e1000e_check_for_fiber_link;
283 func->get_link_up_info =
284 e1000e_get_speed_and_duplex_fiber_serdes;
285 break;
286 case e1000_media_type_internal_serdes:
287 func->setup_physical_interface =
288 e1000_setup_fiber_serdes_link_82571;
289 func->check_for_link = e1000_check_for_serdes_link_82571;
290 func->get_link_up_info =
291 e1000e_get_speed_and_duplex_fiber_serdes;
292 break;
293 default:
294 return -E1000_ERR_CONFIG;
295 break;
296 }
297
298 switch (hw->mac.type) {
299 case e1000_82573:
300 func->set_lan_id = e1000_set_lan_id_single_port;
301 func->check_mng_mode = e1000e_check_mng_mode_generic;
302 func->led_on = e1000e_led_on_generic;
303 func->blink_led = e1000e_blink_led_generic;
304
305 /* FWSM register */
306 mac->has_fwsm = true;
307 /*
308 * ARC supported; valid only if manageability features are
309 * enabled.
310 */
311 mac->arc_subsystem_valid =
312 (er32(FWSM) & E1000_FWSM_MODE_MASK)
313 ? true : false;
314 break;
315 case e1000_82574:
316 case e1000_82583:
317 func->set_lan_id = e1000_set_lan_id_single_port;
318 func->check_mng_mode = e1000_check_mng_mode_82574;
319 func->led_on = e1000_led_on_82574;
320 break;
321 default:
322 func->check_mng_mode = e1000e_check_mng_mode_generic;
323 func->led_on = e1000e_led_on_generic;
324 func->blink_led = e1000e_blink_led_generic;
325
326 /* FWSM register */
327 mac->has_fwsm = true;
328 break;
329 }
330
331 /*
332 * Ensure that the inter-port SWSM.SMBI lock bit is clear before
333 * first NVM or PHY access. This should be done for single-port
334 * devices, and for one port only on dual-port devices so that
335 * for those devices we can still use the SMBI lock to synchronize
336 * inter-port accesses to the PHY & NVM.
337 */
338 switch (hw->mac.type) {
339 case e1000_82571:
340 case e1000_82572:
341 swsm2 = er32(SWSM2);
342
343 if (!(swsm2 & E1000_SWSM2_LOCK)) {
344 /* Only do this for the first interface on this card */
345 ew32(SWSM2,
346 swsm2 | E1000_SWSM2_LOCK);
347 force_clear_smbi = true;
348 } else
349 force_clear_smbi = false;
350 break;
351 default:
352 force_clear_smbi = true;
353 break;
354 }
355
356 if (force_clear_smbi) {
357 /* Make sure SWSM.SMBI is clear */
358 swsm = er32(SWSM);
359 if (swsm & E1000_SWSM_SMBI) {
360 /* This bit should not be set on a first interface, and
361 * indicates that the bootagent or EFI code has
362 * improperly left this bit enabled
363 */
364 e_dbg("Please update your 82571 Bootagent\n");
365 }
366 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
367 }
368
369 /*
370 * Initialize device specific counter of SMBI acquisition
371 * timeouts.
372 */
373 hw->dev_spec.e82571.smb_counter = 0;
374
375 return 0;
376}
377
378static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
379{
380 struct e1000_hw *hw = &adapter->hw;
381 static int global_quad_port_a; /* global port a indication */
382 struct pci_dev *pdev = adapter->pdev;
383 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
384 s32 rc;
385
386 rc = e1000_init_mac_params_82571(adapter);
387 if (rc)
388 return rc;
389
390 rc = e1000_init_nvm_params_82571(hw);
391 if (rc)
392 return rc;
393
394 rc = e1000_init_phy_params_82571(hw);
395 if (rc)
396 return rc;
397
398 /* tag quad port adapters first, it's used below */
399 switch (pdev->device) {
400 case E1000_DEV_ID_82571EB_QUAD_COPPER:
401 case E1000_DEV_ID_82571EB_QUAD_FIBER:
402 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
403 case E1000_DEV_ID_82571PT_QUAD_COPPER:
404 adapter->flags |= FLAG_IS_QUAD_PORT;
405 /* mark the first port */
406 if (global_quad_port_a == 0)
407 adapter->flags |= FLAG_IS_QUAD_PORT_A;
408 /* Reset for multiple quad port adapters */
409 global_quad_port_a++;
410 if (global_quad_port_a == 4)
411 global_quad_port_a = 0;
412 break;
413 default:
414 break;
415 }
416
417 switch (adapter->hw.mac.type) {
418 case e1000_82571:
419 /* these dual ports don't have WoL on port B at all */
420 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
421 (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
422 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
423 (is_port_b))
424 adapter->flags &= ~FLAG_HAS_WOL;
425 /* quad ports only support WoL on port A */
426 if (adapter->flags & FLAG_IS_QUAD_PORT &&
427 (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
428 adapter->flags &= ~FLAG_HAS_WOL;
429 /* Does not support WoL on any port */
430 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
431 adapter->flags &= ~FLAG_HAS_WOL;
432 break;
433 case e1000_82573:
434 if (pdev->device == E1000_DEV_ID_82573L) {
435 adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
436 adapter->max_hw_frame_size = DEFAULT_JUMBO;
437 }
438 break;
439 default:
440 break;
441 }
442
443 return 0;
444}
445
446/**
447 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
448 * @hw: pointer to the HW structure
449 *
450 * Reads the PHY registers and stores the PHY ID and possibly the PHY
451 * revision in the hardware structure.
452 **/
453static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
454{
455 struct e1000_phy_info *phy = &hw->phy;
456 s32 ret_val;
457 u16 phy_id = 0;
458
459 switch (hw->mac.type) {
460 case e1000_82571:
461 case e1000_82572:
462 /*
463 * The 82571 firmware may still be configuring the PHY.
464 * In this case, we cannot access the PHY until the
465 * configuration is done. So we explicitly set the
466 * PHY ID.
467 */
468 phy->id = IGP01E1000_I_PHY_ID;
469 break;
470 case e1000_82573:
471 return e1000e_get_phy_id(hw);
472 break;
473 case e1000_82574:
474 case e1000_82583:
475 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
476 if (ret_val)
477 return ret_val;
478
479 phy->id = (u32)(phy_id << 16);
480 udelay(20);
481 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
482 if (ret_val)
483 return ret_val;
484
485 phy->id |= (u32)(phy_id);
486 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
487 break;
488 default:
489 return -E1000_ERR_PHY;
490 break;
491 }
492
493 return 0;
494}
495
496/**
497 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
498 * @hw: pointer to the HW structure
499 *
500 * Acquire the HW semaphore to access the PHY or NVM
501 **/
502static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
503{
504 u32 swsm;
505 s32 sw_timeout = hw->nvm.word_size + 1;
506 s32 fw_timeout = hw->nvm.word_size + 1;
507 s32 i = 0;
508
509 /*
510 * If we have timedout 3 times on trying to acquire
511 * the inter-port SMBI semaphore, there is old code
512 * operating on the other port, and it is not
513 * releasing SMBI. Modify the number of times that
514 * we try for the semaphore to interwork with this
515 * older code.
516 */
517 if (hw->dev_spec.e82571.smb_counter > 2)
518 sw_timeout = 1;
519
520 /* Get the SW semaphore */
521 while (i < sw_timeout) {
522 swsm = er32(SWSM);
523 if (!(swsm & E1000_SWSM_SMBI))
524 break;
525
526 udelay(50);
527 i++;
528 }
529
530 if (i == sw_timeout) {
531 e_dbg("Driver can't access device - SMBI bit is set.\n");
532 hw->dev_spec.e82571.smb_counter++;
533 }
534 /* Get the FW semaphore. */
535 for (i = 0; i < fw_timeout; i++) {
536 swsm = er32(SWSM);
537 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
538
539 /* Semaphore acquired if bit latched */
540 if (er32(SWSM) & E1000_SWSM_SWESMBI)
541 break;
542
543 udelay(50);
544 }
545
546 if (i == fw_timeout) {
547 /* Release semaphores */
548 e1000_put_hw_semaphore_82571(hw);
549 e_dbg("Driver can't access the NVM\n");
550 return -E1000_ERR_NVM;
551 }
552
553 return 0;
554}
555
556/**
557 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
558 * @hw: pointer to the HW structure
559 *
560 * Release hardware semaphore used to access the PHY or NVM
561 **/
562static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
563{
564 u32 swsm;
565
566 swsm = er32(SWSM);
567 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
568 ew32(SWSM, swsm);
569}
570/**
571 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
572 * @hw: pointer to the HW structure
573 *
574 * Acquire the HW semaphore during reset.
575 *
576 **/
577static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
578{
579 u32 extcnf_ctrl;
580 s32 ret_val = 0;
581 s32 i = 0;
582
583 extcnf_ctrl = er32(EXTCNF_CTRL);
584 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
585 do {
586 ew32(EXTCNF_CTRL, extcnf_ctrl);
587 extcnf_ctrl = er32(EXTCNF_CTRL);
588
589 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
590 break;
591
592 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
593
594 usleep_range(2000, 4000);
595 i++;
596 } while (i < MDIO_OWNERSHIP_TIMEOUT);
597
598 if (i == MDIO_OWNERSHIP_TIMEOUT) {
599 /* Release semaphores */
600 e1000_put_hw_semaphore_82573(hw);
601 e_dbg("Driver can't access the PHY\n");
602 ret_val = -E1000_ERR_PHY;
603 goto out;
604 }
605
606out:
607 return ret_val;
608}
609
610/**
611 * e1000_put_hw_semaphore_82573 - Release hardware semaphore
612 * @hw: pointer to the HW structure
613 *
614 * Release hardware semaphore used during reset.
615 *
616 **/
617static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
618{
619 u32 extcnf_ctrl;
620
621 extcnf_ctrl = er32(EXTCNF_CTRL);
622 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
623 ew32(EXTCNF_CTRL, extcnf_ctrl);
624}
625
626static DEFINE_MUTEX(swflag_mutex);
627
628/**
629 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
630 * @hw: pointer to the HW structure
631 *
632 * Acquire the HW semaphore to access the PHY or NVM.
633 *
634 **/
635static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
636{
637 s32 ret_val;
638
639 mutex_lock(&swflag_mutex);
640 ret_val = e1000_get_hw_semaphore_82573(hw);
641 if (ret_val)
642 mutex_unlock(&swflag_mutex);
643 return ret_val;
644}
645
646/**
647 * e1000_put_hw_semaphore_82574 - Release hardware semaphore
648 * @hw: pointer to the HW structure
649 *
650 * Release hardware semaphore used to access the PHY or NVM
651 *
652 **/
653static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
654{
655 e1000_put_hw_semaphore_82573(hw);
656 mutex_unlock(&swflag_mutex);
657}
658
659/**
660 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
661 * @hw: pointer to the HW structure
662 * @active: true to enable LPLU, false to disable
663 *
664 * Sets the LPLU D0 state according to the active flag.
665 * LPLU will not be activated unless the
666 * device autonegotiation advertisement meets standards of
667 * either 10 or 10/100 or 10/100/1000 at all duplexes.
668 * This is a function pointer entry point only called by
669 * PHY setup routines.
670 **/
671static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
672{
673 u16 data = er32(POEMB);
674
675 if (active)
676 data |= E1000_PHY_CTRL_D0A_LPLU;
677 else
678 data &= ~E1000_PHY_CTRL_D0A_LPLU;
679
680 ew32(POEMB, data);
681 return 0;
682}
683
684/**
685 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
686 * @hw: pointer to the HW structure
687 * @active: boolean used to enable/disable lplu
688 *
689 * The low power link up (lplu) state is set to the power management level D3
690 * when active is true, else clear lplu for D3. LPLU
691 * is used during Dx states where the power conservation is most important.
692 * During driver activity, SmartSpeed should be enabled so performance is
693 * maintained.
694 **/
695static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
696{
697 u16 data = er32(POEMB);
698
699 if (!active) {
700 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
701 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
702 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
703 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
704 data |= E1000_PHY_CTRL_NOND0A_LPLU;
705 }
706
707 ew32(POEMB, data);
708 return 0;
709}
710
711/**
712 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
713 * @hw: pointer to the HW structure
714 *
715 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
716 * Then for non-82573 hardware, set the EEPROM access request bit and wait
717 * for EEPROM access grant bit. If the access grant bit is not set, release
718 * hardware semaphore.
719 **/
720static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
721{
722 s32 ret_val;
723
724 ret_val = e1000_get_hw_semaphore_82571(hw);
725 if (ret_val)
726 return ret_val;
727
728 switch (hw->mac.type) {
729 case e1000_82573:
730 break;
731 default:
732 ret_val = e1000e_acquire_nvm(hw);
733 break;
734 }
735
736 if (ret_val)
737 e1000_put_hw_semaphore_82571(hw);
738
739 return ret_val;
740}
741
742/**
743 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
744 * @hw: pointer to the HW structure
745 *
746 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
747 **/
748static void e1000_release_nvm_82571(struct e1000_hw *hw)
749{
750 e1000e_release_nvm(hw);
751 e1000_put_hw_semaphore_82571(hw);
752}
753
754/**
755 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
756 * @hw: pointer to the HW structure
757 * @offset: offset within the EEPROM to be written to
758 * @words: number of words to write
759 * @data: 16 bit word(s) to be written to the EEPROM
760 *
761 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
762 *
763 * If e1000e_update_nvm_checksum is not called after this function, the
764 * EEPROM will most likely contain an invalid checksum.
765 **/
766static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
767 u16 *data)
768{
769 s32 ret_val;
770
771 switch (hw->mac.type) {
772 case e1000_82573:
773 case e1000_82574:
774 case e1000_82583:
775 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
776 break;
777 case e1000_82571:
778 case e1000_82572:
779 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
780 break;
781 default:
782 ret_val = -E1000_ERR_NVM;
783 break;
784 }
785
786 return ret_val;
787}
788
789/**
790 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
791 * @hw: pointer to the HW structure
792 *
793 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
794 * up to the checksum. Then calculates the EEPROM checksum and writes the
795 * value to the EEPROM.
796 **/
797static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
798{
799 u32 eecd;
800 s32 ret_val;
801 u16 i;
802
803 ret_val = e1000e_update_nvm_checksum_generic(hw);
804 if (ret_val)
805 return ret_val;
806
807 /*
808 * If our nvm is an EEPROM, then we're done
809 * otherwise, commit the checksum to the flash NVM.
810 */
811 if (hw->nvm.type != e1000_nvm_flash_hw)
812 return ret_val;
813
814 /* Check for pending operations. */
815 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
816 usleep_range(1000, 2000);
817 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
818 break;
819 }
820
821 if (i == E1000_FLASH_UPDATES)
822 return -E1000_ERR_NVM;
823
824 /* Reset the firmware if using STM opcode. */
825 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
826 /*
827 * The enabling of and the actual reset must be done
828 * in two write cycles.
829 */
830 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
831 e1e_flush();
832 ew32(HICR, E1000_HICR_FW_RESET);
833 }
834
835 /* Commit the write to flash */
836 eecd = er32(EECD) | E1000_EECD_FLUPD;
837 ew32(EECD, eecd);
838
839 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
840 usleep_range(1000, 2000);
841 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
842 break;
843 }
844
845 if (i == E1000_FLASH_UPDATES)
846 return -E1000_ERR_NVM;
847
848 return 0;
849}
850
851/**
852 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
853 * @hw: pointer to the HW structure
854 *
855 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
856 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
857 **/
858static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
859{
860 if (hw->nvm.type == e1000_nvm_flash_hw)
861 e1000_fix_nvm_checksum_82571(hw);
862
863 return e1000e_validate_nvm_checksum_generic(hw);
864}
865
866/**
867 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
868 * @hw: pointer to the HW structure
869 * @offset: offset within the EEPROM to be written to
870 * @words: number of words to write
871 * @data: 16 bit word(s) to be written to the EEPROM
872 *
873 * After checking for invalid values, poll the EEPROM to ensure the previous
874 * command has completed before trying to write the next word. After write
875 * poll for completion.
876 *
877 * If e1000e_update_nvm_checksum is not called after this function, the
878 * EEPROM will most likely contain an invalid checksum.
879 **/
880static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
881 u16 words, u16 *data)
882{
883 struct e1000_nvm_info *nvm = &hw->nvm;
884 u32 i, eewr = 0;
885 s32 ret_val = 0;
886
887 /*
888 * A check for invalid values: offset too large, too many words,
889 * and not enough words.
890 */
891 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
892 (words == 0)) {
893 e_dbg("nvm parameter(s) out of bounds\n");
894 return -E1000_ERR_NVM;
895 }
896
897 for (i = 0; i < words; i++) {
898 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
899 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
900 E1000_NVM_RW_REG_START;
901
902 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
903 if (ret_val)
904 break;
905
906 ew32(EEWR, eewr);
907
908 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
909 if (ret_val)
910 break;
911 }
912
913 return ret_val;
914}
915
916/**
917 * e1000_get_cfg_done_82571 - Poll for configuration done
918 * @hw: pointer to the HW structure
919 *
920 * Reads the management control register for the config done bit to be set.
921 **/
922static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
923{
924 s32 timeout = PHY_CFG_TIMEOUT;
925
926 while (timeout) {
927 if (er32(EEMNGCTL) &
928 E1000_NVM_CFG_DONE_PORT_0)
929 break;
930 usleep_range(1000, 2000);
931 timeout--;
932 }
933 if (!timeout) {
934 e_dbg("MNG configuration cycle has not completed.\n");
935 return -E1000_ERR_RESET;
936 }
937
938 return 0;
939}
940
941/**
942 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
943 * @hw: pointer to the HW structure
944 * @active: true to enable LPLU, false to disable
945 *
946 * Sets the LPLU D0 state according to the active flag. When activating LPLU
947 * this function also disables smart speed and vice versa. LPLU will not be
948 * activated unless the device autonegotiation advertisement meets standards
949 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
950 * pointer entry point only called by PHY setup routines.
951 **/
952static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
953{
954 struct e1000_phy_info *phy = &hw->phy;
955 s32 ret_val;
956 u16 data;
957
958 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
959 if (ret_val)
960 return ret_val;
961
962 if (active) {
963 data |= IGP02E1000_PM_D0_LPLU;
964 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
965 if (ret_val)
966 return ret_val;
967
968 /* When LPLU is enabled, we should disable SmartSpeed */
969 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
970 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
971 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
972 if (ret_val)
973 return ret_val;
974 } else {
975 data &= ~IGP02E1000_PM_D0_LPLU;
976 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
977 /*
978 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
979 * during Dx states where the power conservation is most
980 * important. During driver activity we should enable
981 * SmartSpeed, so performance is maintained.
982 */
983 if (phy->smart_speed == e1000_smart_speed_on) {
984 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
985 &data);
986 if (ret_val)
987 return ret_val;
988
989 data |= IGP01E1000_PSCFR_SMART_SPEED;
990 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
991 data);
992 if (ret_val)
993 return ret_val;
994 } else if (phy->smart_speed == e1000_smart_speed_off) {
995 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
996 &data);
997 if (ret_val)
998 return ret_val;
999
1000 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1001 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1002 data);
1003 if (ret_val)
1004 return ret_val;
1005 }
1006 }
1007
1008 return 0;
1009}
1010
1011/**
1012 * e1000_reset_hw_82571 - Reset hardware
1013 * @hw: pointer to the HW structure
1014 *
1015 * This resets the hardware into a known state.
1016 **/
1017static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1018{
1019 u32 ctrl, ctrl_ext;
1020 s32 ret_val;
1021
1022 /*
1023 * Prevent the PCI-E bus from sticking if there is no TLP connection
1024 * on the last TLP read/write transaction when MAC is reset.
1025 */
1026 ret_val = e1000e_disable_pcie_master(hw);
1027 if (ret_val)
1028 e_dbg("PCI-E Master disable polling has failed.\n");
1029
1030 e_dbg("Masking off all interrupts\n");
1031 ew32(IMC, 0xffffffff);
1032
1033 ew32(RCTL, 0);
1034 ew32(TCTL, E1000_TCTL_PSP);
1035 e1e_flush();
1036
1037 usleep_range(10000, 20000);
1038
1039 /*
1040 * Must acquire the MDIO ownership before MAC reset.
1041 * Ownership defaults to firmware after a reset.
1042 */
1043 switch (hw->mac.type) {
1044 case e1000_82573:
1045 ret_val = e1000_get_hw_semaphore_82573(hw);
1046 break;
1047 case e1000_82574:
1048 case e1000_82583:
1049 ret_val = e1000_get_hw_semaphore_82574(hw);
1050 break;
1051 default:
1052 break;
1053 }
1054 if (ret_val)
1055 e_dbg("Cannot acquire MDIO ownership\n");
1056
1057 ctrl = er32(CTRL);
1058
1059 e_dbg("Issuing a global reset to MAC\n");
1060 ew32(CTRL, ctrl | E1000_CTRL_RST);
1061
1062 /* Must release MDIO ownership and mutex after MAC reset. */
1063 switch (hw->mac.type) {
1064 case e1000_82574:
1065 case e1000_82583:
1066 e1000_put_hw_semaphore_82574(hw);
1067 break;
1068 default:
1069 break;
1070 }
1071
1072 if (hw->nvm.type == e1000_nvm_flash_hw) {
1073 udelay(10);
1074 ctrl_ext = er32(CTRL_EXT);
1075 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1076 ew32(CTRL_EXT, ctrl_ext);
1077 e1e_flush();
1078 }
1079
1080 ret_val = e1000e_get_auto_rd_done(hw);
1081 if (ret_val)
1082 /* We don't want to continue accessing MAC registers. */
1083 return ret_val;
1084
1085 /*
1086 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1087 * Need to wait for Phy configuration completion before accessing
1088 * NVM and Phy.
1089 */
1090
1091 switch (hw->mac.type) {
1092 case e1000_82573:
1093 case e1000_82574:
1094 case e1000_82583:
1095 msleep(25);
1096 break;
1097 default:
1098 break;
1099 }
1100
1101 /* Clear any pending interrupt events. */
1102 ew32(IMC, 0xffffffff);
1103 er32(ICR);
1104
1105 if (hw->mac.type == e1000_82571) {
1106 /* Install any alternate MAC address into RAR0 */
1107 ret_val = e1000_check_alt_mac_addr_generic(hw);
1108 if (ret_val)
1109 return ret_val;
1110
1111 e1000e_set_laa_state_82571(hw, true);
1112 }
1113
1114 /* Reinitialize the 82571 serdes link state machine */
1115 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1116 hw->mac.serdes_link_state = e1000_serdes_link_down;
1117
1118 return 0;
1119}
1120
1121/**
1122 * e1000_init_hw_82571 - Initialize hardware
1123 * @hw: pointer to the HW structure
1124 *
1125 * This inits the hardware readying it for operation.
1126 **/
1127static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1128{
1129 struct e1000_mac_info *mac = &hw->mac;
1130 u32 reg_data;
1131 s32 ret_val;
1132 u16 i, rar_count = mac->rar_entry_count;
1133
1134 e1000_initialize_hw_bits_82571(hw);
1135
1136 /* Initialize identification LED */
1137 ret_val = e1000e_id_led_init(hw);
1138 if (ret_val)
1139 e_dbg("Error initializing identification LED\n");
1140 /* This is not fatal and we should not stop init due to this */
1141
1142 /* Disabling VLAN filtering */
1143 e_dbg("Initializing the IEEE VLAN\n");
1144 mac->ops.clear_vfta(hw);
1145
1146 /* Setup the receive address. */
1147 /*
1148 * If, however, a locally administered address was assigned to the
1149 * 82571, we must reserve a RAR for it to work around an issue where
1150 * resetting one port will reload the MAC on the other port.
1151 */
1152 if (e1000e_get_laa_state_82571(hw))
1153 rar_count--;
1154 e1000e_init_rx_addrs(hw, rar_count);
1155
1156 /* Zero out the Multicast HASH table */
1157 e_dbg("Zeroing the MTA\n");
1158 for (i = 0; i < mac->mta_reg_count; i++)
1159 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1160
1161 /* Setup link and flow control */
1162 ret_val = e1000_setup_link_82571(hw);
1163
1164 /* Set the transmit descriptor write-back policy */
1165 reg_data = er32(TXDCTL(0));
1166 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1167 E1000_TXDCTL_FULL_TX_DESC_WB |
1168 E1000_TXDCTL_COUNT_DESC;
1169 ew32(TXDCTL(0), reg_data);
1170
1171 /* ...for both queues. */
1172 switch (mac->type) {
1173 case e1000_82573:
1174 e1000e_enable_tx_pkt_filtering(hw);
1175 /* fall through */
1176 case e1000_82574:
1177 case e1000_82583:
1178 reg_data = er32(GCR);
1179 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1180 ew32(GCR, reg_data);
1181 break;
1182 default:
1183 reg_data = er32(TXDCTL(1));
1184 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1185 E1000_TXDCTL_FULL_TX_DESC_WB |
1186 E1000_TXDCTL_COUNT_DESC;
1187 ew32(TXDCTL(1), reg_data);
1188 break;
1189 }
1190
1191 /*
1192 * Clear all of the statistics registers (clear on read). It is
1193 * important that we do this after we have tried to establish link
1194 * because the symbol error count will increment wildly if there
1195 * is no link.
1196 */
1197 e1000_clear_hw_cntrs_82571(hw);
1198
1199 return ret_val;
1200}
1201
1202/**
1203 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1204 * @hw: pointer to the HW structure
1205 *
1206 * Initializes required hardware-dependent bits needed for normal operation.
1207 **/
1208static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1209{
1210 u32 reg;
1211
1212 /* Transmit Descriptor Control 0 */
1213 reg = er32(TXDCTL(0));
1214 reg |= (1 << 22);
1215 ew32(TXDCTL(0), reg);
1216
1217 /* Transmit Descriptor Control 1 */
1218 reg = er32(TXDCTL(1));
1219 reg |= (1 << 22);
1220 ew32(TXDCTL(1), reg);
1221
1222 /* Transmit Arbitration Control 0 */
1223 reg = er32(TARC(0));
1224 reg &= ~(0xF << 27); /* 30:27 */
1225 switch (hw->mac.type) {
1226 case e1000_82571:
1227 case e1000_82572:
1228 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1229 break;
1230 default:
1231 break;
1232 }
1233 ew32(TARC(0), reg);
1234
1235 /* Transmit Arbitration Control 1 */
1236 reg = er32(TARC(1));
1237 switch (hw->mac.type) {
1238 case e1000_82571:
1239 case e1000_82572:
1240 reg &= ~((1 << 29) | (1 << 30));
1241 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1242 if (er32(TCTL) & E1000_TCTL_MULR)
1243 reg &= ~(1 << 28);
1244 else
1245 reg |= (1 << 28);
1246 ew32(TARC(1), reg);
1247 break;
1248 default:
1249 break;
1250 }
1251
1252 /* Device Control */
1253 switch (hw->mac.type) {
1254 case e1000_82573:
1255 case e1000_82574:
1256 case e1000_82583:
1257 reg = er32(CTRL);
1258 reg &= ~(1 << 29);
1259 ew32(CTRL, reg);
1260 break;
1261 default:
1262 break;
1263 }
1264
1265 /* Extended Device Control */
1266 switch (hw->mac.type) {
1267 case e1000_82573:
1268 case e1000_82574:
1269 case e1000_82583:
1270 reg = er32(CTRL_EXT);
1271 reg &= ~(1 << 23);
1272 reg |= (1 << 22);
1273 ew32(CTRL_EXT, reg);
1274 break;
1275 default:
1276 break;
1277 }
1278
1279 if (hw->mac.type == e1000_82571) {
1280 reg = er32(PBA_ECC);
1281 reg |= E1000_PBA_ECC_CORR_EN;
1282 ew32(PBA_ECC, reg);
1283 }
1284 /*
1285 * Workaround for hardware errata.
1286 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1287 */
1288
1289 if ((hw->mac.type == e1000_82571) ||
1290 (hw->mac.type == e1000_82572)) {
1291 reg = er32(CTRL_EXT);
1292 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1293 ew32(CTRL_EXT, reg);
1294 }
1295
1296
1297 /* PCI-Ex Control Registers */
1298 switch (hw->mac.type) {
1299 case e1000_82574:
1300 case e1000_82583:
1301 reg = er32(GCR);
1302 reg |= (1 << 22);
1303 ew32(GCR, reg);
1304
1305 /*
1306 * Workaround for hardware errata.
1307 * apply workaround for hardware errata documented in errata
1308 * docs Fixes issue where some error prone or unreliable PCIe
1309 * completions are occurring, particularly with ASPM enabled.
1310 * Without fix, issue can cause Tx timeouts.
1311 */
1312 reg = er32(GCR2);
1313 reg |= 1;
1314 ew32(GCR2, reg);
1315 break;
1316 default:
1317 break;
1318 }
1319}
1320
1321/**
1322 * e1000_clear_vfta_82571 - Clear VLAN filter table
1323 * @hw: pointer to the HW structure
1324 *
1325 * Clears the register array which contains the VLAN filter table by
1326 * setting all the values to 0.
1327 **/
1328static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1329{
1330 u32 offset;
1331 u32 vfta_value = 0;
1332 u32 vfta_offset = 0;
1333 u32 vfta_bit_in_reg = 0;
1334
1335 switch (hw->mac.type) {
1336 case e1000_82573:
1337 case e1000_82574:
1338 case e1000_82583:
1339 if (hw->mng_cookie.vlan_id != 0) {
1340 /*
1341 * The VFTA is a 4096b bit-field, each identifying
1342 * a single VLAN ID. The following operations
1343 * determine which 32b entry (i.e. offset) into the
1344 * array we want to set the VLAN ID (i.e. bit) of
1345 * the manageability unit.
1346 */
1347 vfta_offset = (hw->mng_cookie.vlan_id >>
1348 E1000_VFTA_ENTRY_SHIFT) &
1349 E1000_VFTA_ENTRY_MASK;
1350 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1351 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1352 }
1353 break;
1354 default:
1355 break;
1356 }
1357 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1358 /*
1359 * If the offset we want to clear is the same offset of the
1360 * manageability VLAN ID, then clear all bits except that of
1361 * the manageability unit.
1362 */
1363 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1364 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1365 e1e_flush();
1366 }
1367}
1368
1369/**
1370 * e1000_check_mng_mode_82574 - Check manageability is enabled
1371 * @hw: pointer to the HW structure
1372 *
1373 * Reads the NVM Initialization Control Word 2 and returns true
1374 * (>0) if any manageability is enabled, else false (0).
1375 **/
1376static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1377{
1378 u16 data;
1379
1380 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1381 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1382}
1383
1384/**
1385 * e1000_led_on_82574 - Turn LED on
1386 * @hw: pointer to the HW structure
1387 *
1388 * Turn LED on.
1389 **/
1390static s32 e1000_led_on_82574(struct e1000_hw *hw)
1391{
1392 u32 ctrl;
1393 u32 i;
1394
1395 ctrl = hw->mac.ledctl_mode2;
1396 if (!(E1000_STATUS_LU & er32(STATUS))) {
1397 /*
1398 * If no link, then turn LED on by setting the invert bit
1399 * for each LED that's "on" (0x0E) in ledctl_mode2.
1400 */
1401 for (i = 0; i < 4; i++)
1402 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1403 E1000_LEDCTL_MODE_LED_ON)
1404 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1405 }
1406 ew32(LEDCTL, ctrl);
1407
1408 return 0;
1409}
1410
1411/**
1412 * e1000_check_phy_82574 - check 82574 phy hung state
1413 * @hw: pointer to the HW structure
1414 *
1415 * Returns whether phy is hung or not
1416 **/
1417bool e1000_check_phy_82574(struct e1000_hw *hw)
1418{
1419 u16 status_1kbt = 0;
1420 u16 receive_errors = 0;
1421 bool phy_hung = false;
1422 s32 ret_val = 0;
1423
1424 /*
1425 * Read PHY Receive Error counter first, if its is max - all F's then
1426 * read the Base1000T status register If both are max then PHY is hung.
1427 */
1428 ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
1429
1430 if (ret_val)
1431 goto out;
1432 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1433 ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
1434 if (ret_val)
1435 goto out;
1436 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1437 E1000_IDLE_ERROR_COUNT_MASK)
1438 phy_hung = true;
1439 }
1440out:
1441 return phy_hung;
1442}
1443
1444/**
1445 * e1000_setup_link_82571 - Setup flow control and link settings
1446 * @hw: pointer to the HW structure
1447 *
1448 * Determines which flow control settings to use, then configures flow
1449 * control. Calls the appropriate media-specific link configuration
1450 * function. Assuming the adapter has a valid link partner, a valid link
1451 * should be established. Assumes the hardware has previously been reset
1452 * and the transmitter and receiver are not enabled.
1453 **/
1454static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1455{
1456 /*
1457 * 82573 does not have a word in the NVM to determine
1458 * the default flow control setting, so we explicitly
1459 * set it to full.
1460 */
1461 switch (hw->mac.type) {
1462 case e1000_82573:
1463 case e1000_82574:
1464 case e1000_82583:
1465 if (hw->fc.requested_mode == e1000_fc_default)
1466 hw->fc.requested_mode = e1000_fc_full;
1467 break;
1468 default:
1469 break;
1470 }
1471
1472 return e1000e_setup_link(hw);
1473}
1474
1475/**
1476 * e1000_setup_copper_link_82571 - Configure copper link settings
1477 * @hw: pointer to the HW structure
1478 *
1479 * Configures the link for auto-neg or forced speed and duplex. Then we check
1480 * for link, once link is established calls to configure collision distance
1481 * and flow control are called.
1482 **/
1483static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1484{
1485 u32 ctrl;
1486 s32 ret_val;
1487
1488 ctrl = er32(CTRL);
1489 ctrl |= E1000_CTRL_SLU;
1490 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1491 ew32(CTRL, ctrl);
1492
1493 switch (hw->phy.type) {
1494 case e1000_phy_m88:
1495 case e1000_phy_bm:
1496 ret_val = e1000e_copper_link_setup_m88(hw);
1497 break;
1498 case e1000_phy_igp_2:
1499 ret_val = e1000e_copper_link_setup_igp(hw);
1500 break;
1501 default:
1502 return -E1000_ERR_PHY;
1503 break;
1504 }
1505
1506 if (ret_val)
1507 return ret_val;
1508
1509 ret_val = e1000e_setup_copper_link(hw);
1510
1511 return ret_val;
1512}
1513
1514/**
1515 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1516 * @hw: pointer to the HW structure
1517 *
1518 * Configures collision distance and flow control for fiber and serdes links.
1519 * Upon successful setup, poll for link.
1520 **/
1521static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1522{
1523 switch (hw->mac.type) {
1524 case e1000_82571:
1525 case e1000_82572:
1526 /*
1527 * If SerDes loopback mode is entered, there is no form
1528 * of reset to take the adapter out of that mode. So we
1529 * have to explicitly take the adapter out of loopback
1530 * mode. This prevents drivers from twiddling their thumbs
1531 * if another tool failed to take it out of loopback mode.
1532 */
1533 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1534 break;
1535 default:
1536 break;
1537 }
1538
1539 return e1000e_setup_fiber_serdes_link(hw);
1540}
1541
1542/**
1543 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1544 * @hw: pointer to the HW structure
1545 *
1546 * Reports the link state as up or down.
1547 *
1548 * If autonegotiation is supported by the link partner, the link state is
1549 * determined by the result of autonegotiation. This is the most likely case.
1550 * If autonegotiation is not supported by the link partner, and the link
1551 * has a valid signal, force the link up.
1552 *
1553 * The link state is represented internally here by 4 states:
1554 *
1555 * 1) down
1556 * 2) autoneg_progress
1557 * 3) autoneg_complete (the link successfully autonegotiated)
1558 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1559 *
1560 **/
1561static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1562{
1563 struct e1000_mac_info *mac = &hw->mac;
1564 u32 rxcw;
1565 u32 ctrl;
1566 u32 status;
1567 u32 txcw;
1568 u32 i;
1569 s32 ret_val = 0;
1570
1571 ctrl = er32(CTRL);
1572 status = er32(STATUS);
1573 rxcw = er32(RXCW);
1574
1575 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1576
1577 /* Receiver is synchronized with no invalid bits. */
1578 switch (mac->serdes_link_state) {
1579 case e1000_serdes_link_autoneg_complete:
1580 if (!(status & E1000_STATUS_LU)) {
1581 /*
1582 * We have lost link, retry autoneg before
1583 * reporting link failure
1584 */
1585 mac->serdes_link_state =
1586 e1000_serdes_link_autoneg_progress;
1587 mac->serdes_has_link = false;
1588 e_dbg("AN_UP -> AN_PROG\n");
1589 } else {
1590 mac->serdes_has_link = true;
1591 }
1592 break;
1593
1594 case e1000_serdes_link_forced_up:
1595 /*
1596 * If we are receiving /C/ ordered sets, re-enable
1597 * auto-negotiation in the TXCW register and disable
1598 * forced link in the Device Control register in an
1599 * attempt to auto-negotiate with our link partner.
1600 * If the partner code word is null, stop forcing
1601 * and restart auto negotiation.
1602 */
1603 if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW)) {
1604 /* Enable autoneg, and unforce link up */
1605 ew32(TXCW, mac->txcw);
1606 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1607 mac->serdes_link_state =
1608 e1000_serdes_link_autoneg_progress;
1609 mac->serdes_has_link = false;
1610 e_dbg("FORCED_UP -> AN_PROG\n");
1611 } else {
1612 mac->serdes_has_link = true;
1613 }
1614 break;
1615
1616 case e1000_serdes_link_autoneg_progress:
1617 if (rxcw & E1000_RXCW_C) {
1618 /*
1619 * We received /C/ ordered sets, meaning the
1620 * link partner has autonegotiated, and we can
1621 * trust the Link Up (LU) status bit.
1622 */
1623 if (status & E1000_STATUS_LU) {
1624 mac->serdes_link_state =
1625 e1000_serdes_link_autoneg_complete;
1626 e_dbg("AN_PROG -> AN_UP\n");
1627 mac->serdes_has_link = true;
1628 } else {
1629 /* Autoneg completed, but failed. */
1630 mac->serdes_link_state =
1631 e1000_serdes_link_down;
1632 e_dbg("AN_PROG -> DOWN\n");
1633 }
1634 } else {
1635 /*
1636 * The link partner did not autoneg.
1637 * Force link up and full duplex, and change
1638 * state to forced.
1639 */
1640 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1641 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1642 ew32(CTRL, ctrl);
1643
1644 /* Configure Flow Control after link up. */
1645 ret_val = e1000e_config_fc_after_link_up(hw);
1646 if (ret_val) {
1647 e_dbg("Error config flow control\n");
1648 break;
1649 }
1650 mac->serdes_link_state =
1651 e1000_serdes_link_forced_up;
1652 mac->serdes_has_link = true;
1653 e_dbg("AN_PROG -> FORCED_UP\n");
1654 }
1655 break;
1656
1657 case e1000_serdes_link_down:
1658 default:
1659 /*
1660 * The link was down but the receiver has now gained
1661 * valid sync, so lets see if we can bring the link
1662 * up.
1663 */
1664 ew32(TXCW, mac->txcw);
1665 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1666 mac->serdes_link_state =
1667 e1000_serdes_link_autoneg_progress;
1668 mac->serdes_has_link = false;
1669 e_dbg("DOWN -> AN_PROG\n");
1670 break;
1671 }
1672 } else {
1673 if (!(rxcw & E1000_RXCW_SYNCH)) {
1674 mac->serdes_has_link = false;
1675 mac->serdes_link_state = e1000_serdes_link_down;
1676 e_dbg("ANYSTATE -> DOWN\n");
1677 } else {
1678 /*
1679 * Check several times, if Sync and Config
1680 * both are consistently 1 then simply ignore
1681 * the Invalid bit and restart Autoneg
1682 */
1683 for (i = 0; i < AN_RETRY_COUNT; i++) {
1684 udelay(10);
1685 rxcw = er32(RXCW);
1686 if ((rxcw & E1000_RXCW_IV) &&
1687 !((rxcw & E1000_RXCW_SYNCH) &&
1688 (rxcw & E1000_RXCW_C))) {
1689 mac->serdes_has_link = false;
1690 mac->serdes_link_state =
1691 e1000_serdes_link_down;
1692 e_dbg("ANYSTATE -> DOWN\n");
1693 break;
1694 }
1695 }
1696
1697 if (i == AN_RETRY_COUNT) {
1698 txcw = er32(TXCW);
1699 txcw |= E1000_TXCW_ANE;
1700 ew32(TXCW, txcw);
1701 mac->serdes_link_state =
1702 e1000_serdes_link_autoneg_progress;
1703 mac->serdes_has_link = false;
1704 e_dbg("ANYSTATE -> AN_PROG\n");
1705 }
1706 }
1707 }
1708
1709 return ret_val;
1710}
1711
1712/**
1713 * e1000_valid_led_default_82571 - Verify a valid default LED config
1714 * @hw: pointer to the HW structure
1715 * @data: pointer to the NVM (EEPROM)
1716 *
1717 * Read the EEPROM for the current default LED configuration. If the
1718 * LED configuration is not valid, set to a valid LED configuration.
1719 **/
1720static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1721{
1722 s32 ret_val;
1723
1724 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1725 if (ret_val) {
1726 e_dbg("NVM Read Error\n");
1727 return ret_val;
1728 }
1729
1730 switch (hw->mac.type) {
1731 case e1000_82573:
1732 case e1000_82574:
1733 case e1000_82583:
1734 if (*data == ID_LED_RESERVED_F746)
1735 *data = ID_LED_DEFAULT_82573;
1736 break;
1737 default:
1738 if (*data == ID_LED_RESERVED_0000 ||
1739 *data == ID_LED_RESERVED_FFFF)
1740 *data = ID_LED_DEFAULT;
1741 break;
1742 }
1743
1744 return 0;
1745}
1746
1747/**
1748 * e1000e_get_laa_state_82571 - Get locally administered address state
1749 * @hw: pointer to the HW structure
1750 *
1751 * Retrieve and return the current locally administered address state.
1752 **/
1753bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1754{
1755 if (hw->mac.type != e1000_82571)
1756 return false;
1757
1758 return hw->dev_spec.e82571.laa_is_present;
1759}
1760
1761/**
1762 * e1000e_set_laa_state_82571 - Set locally administered address state
1763 * @hw: pointer to the HW structure
1764 * @state: enable/disable locally administered address
1765 *
1766 * Enable/Disable the current locally administered address state.
1767 **/
1768void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1769{
1770 if (hw->mac.type != e1000_82571)
1771 return;
1772
1773 hw->dev_spec.e82571.laa_is_present = state;
1774
1775 /* If workaround is activated... */
1776 if (state)
1777 /*
1778 * Hold a copy of the LAA in RAR[14] This is done so that
1779 * between the time RAR[0] gets clobbered and the time it
1780 * gets fixed, the actual LAA is in one of the RARs and no
1781 * incoming packets directed to this port are dropped.
1782 * Eventually the LAA will be in RAR[0] and RAR[14].
1783 */
1784 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1785}
1786
1787/**
1788 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1789 * @hw: pointer to the HW structure
1790 *
1791 * Verifies that the EEPROM has completed the update. After updating the
1792 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1793 * the checksum fix is not implemented, we need to set the bit and update
1794 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1795 * we need to return bad checksum.
1796 **/
1797static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1798{
1799 struct e1000_nvm_info *nvm = &hw->nvm;
1800 s32 ret_val;
1801 u16 data;
1802
1803 if (nvm->type != e1000_nvm_flash_hw)
1804 return 0;
1805
1806 /*
1807 * Check bit 4 of word 10h. If it is 0, firmware is done updating
1808 * 10h-12h. Checksum may need to be fixed.
1809 */
1810 ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1811 if (ret_val)
1812 return ret_val;
1813
1814 if (!(data & 0x10)) {
1815 /*
1816 * Read 0x23 and check bit 15. This bit is a 1
1817 * when the checksum has already been fixed. If
1818 * the checksum is still wrong and this bit is a
1819 * 1, we need to return bad checksum. Otherwise,
1820 * we need to set this bit to a 1 and update the
1821 * checksum.
1822 */
1823 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1824 if (ret_val)
1825 return ret_val;
1826
1827 if (!(data & 0x8000)) {
1828 data |= 0x8000;
1829 ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1830 if (ret_val)
1831 return ret_val;
1832 ret_val = e1000e_update_nvm_checksum(hw);
1833 }
1834 }
1835
1836 return 0;
1837}
1838
1839/**
1840 * e1000_read_mac_addr_82571 - Read device MAC address
1841 * @hw: pointer to the HW structure
1842 **/
1843static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1844{
1845 s32 ret_val = 0;
1846
1847 if (hw->mac.type == e1000_82571) {
1848 /*
1849 * If there's an alternate MAC address place it in RAR0
1850 * so that it will override the Si installed default perm
1851 * address.
1852 */
1853 ret_val = e1000_check_alt_mac_addr_generic(hw);
1854 if (ret_val)
1855 goto out;
1856 }
1857
1858 ret_val = e1000_read_mac_addr_generic(hw);
1859
1860out:
1861 return ret_val;
1862}
1863
1864/**
1865 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1866 * @hw: pointer to the HW structure
1867 *
1868 * In the case of a PHY power down to save power, or to turn off link during a
1869 * driver unload, or wake on lan is not enabled, remove the link.
1870 **/
1871static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1872{
1873 struct e1000_phy_info *phy = &hw->phy;
1874 struct e1000_mac_info *mac = &hw->mac;
1875
1876 if (!(phy->ops.check_reset_block))
1877 return;
1878
1879 /* If the management interface is not enabled, then power down */
1880 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1881 e1000_power_down_phy_copper(hw);
1882}
1883
1884/**
1885 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1886 * @hw: pointer to the HW structure
1887 *
1888 * Clears the hardware counters by reading the counter registers.
1889 **/
1890static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1891{
1892 e1000e_clear_hw_cntrs_base(hw);
1893
1894 er32(PRC64);
1895 er32(PRC127);
1896 er32(PRC255);
1897 er32(PRC511);
1898 er32(PRC1023);
1899 er32(PRC1522);
1900 er32(PTC64);
1901 er32(PTC127);
1902 er32(PTC255);
1903 er32(PTC511);
1904 er32(PTC1023);
1905 er32(PTC1522);
1906
1907 er32(ALGNERRC);
1908 er32(RXERRC);
1909 er32(TNCRS);
1910 er32(CEXTERR);
1911 er32(TSCTC);
1912 er32(TSCTFC);
1913
1914 er32(MGTPRC);
1915 er32(MGTPDC);
1916 er32(MGTPTC);
1917
1918 er32(IAC);
1919 er32(ICRXOC);
1920
1921 er32(ICRXPTC);
1922 er32(ICRXATC);
1923 er32(ICTXPTC);
1924 er32(ICTXATC);
1925 er32(ICTXQEC);
1926 er32(ICTXQMTC);
1927 er32(ICRXDMTC);
1928}
1929
1930static struct e1000_mac_operations e82571_mac_ops = {
1931 /* .check_mng_mode: mac type dependent */
1932 /* .check_for_link: media type dependent */
1933 .id_led_init = e1000e_id_led_init,
1934 .cleanup_led = e1000e_cleanup_led_generic,
1935 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571,
1936 .get_bus_info = e1000e_get_bus_info_pcie,
1937 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1938 /* .get_link_up_info: media type dependent */
1939 /* .led_on: mac type dependent */
1940 .led_off = e1000e_led_off_generic,
1941 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1942 .write_vfta = e1000_write_vfta_generic,
1943 .clear_vfta = e1000_clear_vfta_82571,
1944 .reset_hw = e1000_reset_hw_82571,
1945 .init_hw = e1000_init_hw_82571,
1946 .setup_link = e1000_setup_link_82571,
1947 /* .setup_physical_interface: media type dependent */
1948 .setup_led = e1000e_setup_led_generic,
1949 .read_mac_addr = e1000_read_mac_addr_82571,
1950};
1951
1952static struct e1000_phy_operations e82_phy_ops_igp = {
1953 .acquire = e1000_get_hw_semaphore_82571,
1954 .check_polarity = e1000_check_polarity_igp,
1955 .check_reset_block = e1000e_check_reset_block_generic,
1956 .commit = NULL,
1957 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1958 .get_cfg_done = e1000_get_cfg_done_82571,
1959 .get_cable_length = e1000e_get_cable_length_igp_2,
1960 .get_info = e1000e_get_phy_info_igp,
1961 .read_reg = e1000e_read_phy_reg_igp,
1962 .release = e1000_put_hw_semaphore_82571,
1963 .reset = e1000e_phy_hw_reset_generic,
1964 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1965 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1966 .write_reg = e1000e_write_phy_reg_igp,
1967 .cfg_on_link_up = NULL,
1968};
1969
1970static struct e1000_phy_operations e82_phy_ops_m88 = {
1971 .acquire = e1000_get_hw_semaphore_82571,
1972 .check_polarity = e1000_check_polarity_m88,
1973 .check_reset_block = e1000e_check_reset_block_generic,
1974 .commit = e1000e_phy_sw_reset,
1975 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1976 .get_cfg_done = e1000e_get_cfg_done,
1977 .get_cable_length = e1000e_get_cable_length_m88,
1978 .get_info = e1000e_get_phy_info_m88,
1979 .read_reg = e1000e_read_phy_reg_m88,
1980 .release = e1000_put_hw_semaphore_82571,
1981 .reset = e1000e_phy_hw_reset_generic,
1982 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1983 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1984 .write_reg = e1000e_write_phy_reg_m88,
1985 .cfg_on_link_up = NULL,
1986};
1987
1988static struct e1000_phy_operations e82_phy_ops_bm = {
1989 .acquire = e1000_get_hw_semaphore_82571,
1990 .check_polarity = e1000_check_polarity_m88,
1991 .check_reset_block = e1000e_check_reset_block_generic,
1992 .commit = e1000e_phy_sw_reset,
1993 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1994 .get_cfg_done = e1000e_get_cfg_done,
1995 .get_cable_length = e1000e_get_cable_length_m88,
1996 .get_info = e1000e_get_phy_info_m88,
1997 .read_reg = e1000e_read_phy_reg_bm2,
1998 .release = e1000_put_hw_semaphore_82571,
1999 .reset = e1000e_phy_hw_reset_generic,
2000 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
2001 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
2002 .write_reg = e1000e_write_phy_reg_bm2,
2003 .cfg_on_link_up = NULL,
2004};
2005
2006static struct e1000_nvm_operations e82571_nvm_ops = {
2007 .acquire = e1000_acquire_nvm_82571,
2008 .read = e1000e_read_nvm_eerd,
2009 .release = e1000_release_nvm_82571,
2010 .update = e1000_update_nvm_checksum_82571,
2011 .valid_led_default = e1000_valid_led_default_82571,
2012 .validate = e1000_validate_nvm_checksum_82571,
2013 .write = e1000_write_nvm_82571,
2014};
2015
2016struct e1000_info e1000_82571_info = {
2017 .mac = e1000_82571,
2018 .flags = FLAG_HAS_HW_VLAN_FILTER
2019 | FLAG_HAS_JUMBO_FRAMES
2020 | FLAG_HAS_WOL
2021 | FLAG_APME_IN_CTRL3
2022 | FLAG_RX_CSUM_ENABLED
2023 | FLAG_HAS_CTRLEXT_ON_LOAD
2024 | FLAG_HAS_SMART_POWER_DOWN
2025 | FLAG_RESET_OVERWRITES_LAA /* errata */
2026 | FLAG_TARC_SPEED_MODE_BIT /* errata */
2027 | FLAG_APME_CHECK_PORT_B,
2028 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
2029 | FLAG2_DMA_BURST,
2030 .pba = 38,
2031 .max_hw_frame_size = DEFAULT_JUMBO,
2032 .get_variants = e1000_get_variants_82571,
2033 .mac_ops = &e82571_mac_ops,
2034 .phy_ops = &e82_phy_ops_igp,
2035 .nvm_ops = &e82571_nvm_ops,
2036};
2037
2038struct e1000_info e1000_82572_info = {
2039 .mac = e1000_82572,
2040 .flags = FLAG_HAS_HW_VLAN_FILTER
2041 | FLAG_HAS_JUMBO_FRAMES
2042 | FLAG_HAS_WOL
2043 | FLAG_APME_IN_CTRL3
2044 | FLAG_RX_CSUM_ENABLED
2045 | FLAG_HAS_CTRLEXT_ON_LOAD
2046 | FLAG_TARC_SPEED_MODE_BIT, /* errata */
2047 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
2048 | FLAG2_DMA_BURST,
2049 .pba = 38,
2050 .max_hw_frame_size = DEFAULT_JUMBO,
2051 .get_variants = e1000_get_variants_82571,
2052 .mac_ops = &e82571_mac_ops,
2053 .phy_ops = &e82_phy_ops_igp,
2054 .nvm_ops = &e82571_nvm_ops,
2055};
2056
2057struct e1000_info e1000_82573_info = {
2058 .mac = e1000_82573,
2059 .flags = FLAG_HAS_HW_VLAN_FILTER
2060 | FLAG_HAS_WOL
2061 | FLAG_APME_IN_CTRL3
2062 | FLAG_RX_CSUM_ENABLED
2063 | FLAG_HAS_SMART_POWER_DOWN
2064 | FLAG_HAS_AMT
2065 | FLAG_HAS_SWSM_ON_LOAD,
2066 .flags2 = FLAG2_DISABLE_ASPM_L1
2067 | FLAG2_DISABLE_ASPM_L0S,
2068 .pba = 20,
2069 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
2070 .get_variants = e1000_get_variants_82571,
2071 .mac_ops = &e82571_mac_ops,
2072 .phy_ops = &e82_phy_ops_m88,
2073 .nvm_ops = &e82571_nvm_ops,
2074};
2075
2076struct e1000_info e1000_82574_info = {
2077 .mac = e1000_82574,
2078 .flags = FLAG_HAS_HW_VLAN_FILTER
2079 | FLAG_HAS_MSIX
2080 | FLAG_HAS_JUMBO_FRAMES
2081 | FLAG_HAS_WOL
2082 | FLAG_APME_IN_CTRL3
2083 | FLAG_RX_CSUM_ENABLED
2084 | FLAG_HAS_SMART_POWER_DOWN
2085 | FLAG_HAS_AMT
2086 | FLAG_HAS_CTRLEXT_ON_LOAD,
2087 .flags2 = FLAG2_CHECK_PHY_HANG
2088 | FLAG2_DISABLE_ASPM_L0S
2089 | FLAG2_NO_DISABLE_RX,
2090 .pba = 32,
2091 .max_hw_frame_size = DEFAULT_JUMBO,
2092 .get_variants = e1000_get_variants_82571,
2093 .mac_ops = &e82571_mac_ops,
2094 .phy_ops = &e82_phy_ops_bm,
2095 .nvm_ops = &e82571_nvm_ops,
2096};
2097
2098struct e1000_info e1000_82583_info = {
2099 .mac = e1000_82583,
2100 .flags = FLAG_HAS_HW_VLAN_FILTER
2101 | FLAG_HAS_WOL
2102 | FLAG_APME_IN_CTRL3
2103 | FLAG_RX_CSUM_ENABLED
2104 | FLAG_HAS_SMART_POWER_DOWN
2105 | FLAG_HAS_AMT
2106 | FLAG_HAS_JUMBO_FRAMES
2107 | FLAG_HAS_CTRLEXT_ON_LOAD,
2108 .flags2 = FLAG2_DISABLE_ASPM_L0S
2109 | FLAG2_NO_DISABLE_RX,
2110 .pba = 32,
2111 .max_hw_frame_size = DEFAULT_JUMBO,
2112 .get_variants = e1000_get_variants_82571,
2113 .mac_ops = &e82571_mac_ops,
2114 .phy_ops = &e82_phy_ops_bm,
2115 .nvm_ops = &e82571_nvm_ops,
2116};
2117