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1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
80#include <linux/interrupt.h>
81#include <linux/pci.h>
82#include <linux/mii.h>
83#include <linux/init.h>
84#include <linux/netdevice.h>
85#include <linux/etherdevice.h>
86#include <linux/skbuff.h>
87#include <linux/ethtool.h>
88#include <linux/highmem.h>
89#include <linux/eisa.h>
90#include <linux/bitops.h>
91#include <linux/jiffies.h>
92#include <linux/gfp.h>
93#include <asm/irq.h> /* For nr_irqs only. */
94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
105static const char version[] __devinitconst =
106 DRV_NAME ": Donald Becker and others.\n";
107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
110MODULE_LICENSE("GPL");
111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
211 PCI_USES_MASTER=4,
212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
238 CH_3C905B_TX,
239 CH_3C905B_1,
240
241 CH_3C905B_2,
242 CH_3C905B_FX,
243 CH_3C905C,
244 CH_3C9202,
245 CH_3C980,
246 CH_3C9805,
247
248 CH_3CSOHO100_TX,
249 CH_3C555,
250 CH_3C556,
251 CH_3C556B,
252 CH_3C575,
253
254 CH_3C575_1,
255 CH_3CCFE575,
256 CH_3CCFE575CT,
257 CH_3CCFE656,
258 CH_3CCFEM656,
259
260 CH_3CCFEM656_1,
261 CH_3C450,
262 CH_3C920,
263 CH_3C982A,
264 CH_3C982B,
265
266 CH_905BT4,
267 CH_920B_EMB_WNM,
268};
269
270
271/* note: this array directly indexed by above enums, and MUST
272 * be kept in sync with both the enums above, and the PCI device
273 * table below
274 */
275static struct vortex_chip_info {
276 const char *name;
277 int flags;
278 int drv_flags;
279 int io_size;
280} vortex_info_tbl[] __devinitdata = {
281 {"3c590 Vortex 10Mbps",
282 PCI_USES_MASTER, IS_VORTEX, 32, },
283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
284 PCI_USES_MASTER, IS_VORTEX, 32, },
285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
286 PCI_USES_MASTER, IS_VORTEX, 32, },
287 {"3c595 Vortex 100baseTx",
288 PCI_USES_MASTER, IS_VORTEX, 32, },
289 {"3c595 Vortex 100baseT4",
290 PCI_USES_MASTER, IS_VORTEX, 32, },
291
292 {"3c595 Vortex 100base-MII",
293 PCI_USES_MASTER, IS_VORTEX, 32, },
294 {"3c900 Boomerang 10baseT",
295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
296 {"3c900 Boomerang 10Mbps Combo",
297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
300 {"3c900 Cyclone 10Mbps Combo",
301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
302
303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
305 {"3c900B-FL Cyclone 10base-FL",
306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
307 {"3c905 Boomerang 100baseTx",
308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
309 {"3c905 Boomerang 100baseT4",
310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
313 {"3c905B Cyclone 100baseTx",
314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
315
316 {"3c905B Cyclone 10/100/BNC",
317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
318 {"3c905B-FX Cyclone 100baseFx",
319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
320 {"3c905C Tornado",
321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
324 {"3c980 Cyclone",
325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
326
327 {"3c980C Python-T",
328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
329 {"3cSOHO100-TX Hurricane",
330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
331 {"3c555 Laptop Hurricane",
332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
333 {"3c556 Laptop Tornado",
334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
335 HAS_HWCKSM, 128, },
336 {"3c556B Laptop Hurricane",
337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
339
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
342 {"3c575 Boomerang CardBus",
343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
344 {"3CCFE575BT Cyclone CardBus",
345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
353
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
362 {"3c920 Tornado",
363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
364 {"3c982 Hydra Dual Port A",
365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
366
367 {"3c982 Hydra Dual Port B",
368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
369 {"3c905B-T4",
370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
371 {"3c920B-EMB-WNM Tornado",
372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
373
374 {NULL,}, /* NULL terminated list. */
375};
376
377
378static DEFINE_PCI_DEVICE_TABLE(vortex_pci_tbl) = {
379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
384
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
390
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
397
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
404
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
410
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
416
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
422
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
425
426 {0,} /* 0 terminated list. */
427};
428MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
429
430
431/* Operational definitions.
432 These are not used by other compilation units and thus are not
433 exported in a ".h" file.
434
435 First the windows. There are eight register windows, with the command
436 and status registers available in each.
437 */
438#define EL3_CMD 0x0e
439#define EL3_STATUS 0x0e
440
441/* The top five bits written to EL3_CMD are a command, the lower
442 11 bits are the parameter, if applicable.
443 Note that 11 parameters bits was fine for ethernet, but the new chip
444 can handle FDDI length frames (~4500 octets) and now parameters count
445 32-bit 'Dwords' rather than octets. */
446
447enum vortex_cmd {
448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
449 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
450 UpStall = 6<<11, UpUnstall = (6<<11)+1,
451 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
452 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
453 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
454 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
455 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
456 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
457 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
458
459/* The SetRxFilter command accepts the following classes: */
460enum RxFilter {
461 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
462
463/* Bits in the general status register. */
464enum vortex_status {
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
467 IntReq = 0x0040, StatsFull = 0x0080,
468 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
469 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
471};
472
473/* Register window 1 offsets, the window used in normal operation.
474 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
475enum Window1 {
476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
478 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
479};
480enum Window0 {
481 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
482 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
483 IntrStatus=0x0E, /* Valid in all windows. */
484};
485enum Win0_EEPROM_bits {
486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
487 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
488 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
489};
490/* EEPROM locations. */
491enum eeprom_offset {
492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
493 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
494 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
495 DriverTune=13, Checksum=15};
496
497enum Window2 { /* Window 2. */
498 Wn2_ResetOptions=12,
499};
500enum Window3 { /* Window 3: MAC/config bits. */
501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
502};
503
504#define BFEXT(value, offset, bitcount) \
505 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
506
507#define BFINS(lhs, rhs, offset, bitcount) \
508 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
509 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
510
511#define RAM_SIZE(v) BFEXT(v, 0, 3)
512#define RAM_WIDTH(v) BFEXT(v, 3, 1)
513#define RAM_SPEED(v) BFEXT(v, 4, 2)
514#define ROM_SIZE(v) BFEXT(v, 6, 2)
515#define RAM_SPLIT(v) BFEXT(v, 16, 2)
516#define XCVR(v) BFEXT(v, 20, 4)
517#define AUTOSELECT(v) BFEXT(v, 24, 1)
518
519enum Window4 { /* Window 4: Xcvr/media bits. */
520 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
521};
522enum Win4_Media_bits {
523 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
524 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
525 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
526 Media_LnkBeat = 0x0800,
527};
528enum Window7 { /* Window 7: Bus Master control. */
529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
530 Wn7_MasterStatus = 12,
531};
532/* Boomerang bus master control registers. */
533enum MasterCtrl {
534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
536};
537
538/* The Rx and Tx descriptor lists.
539 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
540 alignment contraint on tx_ring[] and rx_ring[]. */
541#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
542#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
543struct boom_rx_desc {
544 __le32 next; /* Last entry points to 0. */
545 __le32 status;
546 __le32 addr; /* Up to 63 addr/len pairs possible. */
547 __le32 length; /* Set LAST_FRAG to indicate last pair. */
548};
549/* Values for the Rx status entry. */
550enum rx_desc_status {
551 RxDComplete=0x00008000, RxDError=0x4000,
552 /* See boomerang_rx() for actual error bits */
553 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
554 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
555};
556
557#ifdef MAX_SKB_FRAGS
558#define DO_ZEROCOPY 1
559#else
560#define DO_ZEROCOPY 0
561#endif
562
563struct boom_tx_desc {
564 __le32 next; /* Last entry points to 0. */
565 __le32 status; /* bits 0:12 length, others see below. */
566#if DO_ZEROCOPY
567 struct {
568 __le32 addr;
569 __le32 length;
570 } frag[1+MAX_SKB_FRAGS];
571#else
572 __le32 addr;
573 __le32 length;
574#endif
575};
576
577/* Values for the Tx status entry. */
578enum tx_desc_status {
579 CRCDisable=0x2000, TxDComplete=0x8000,
580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
581 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
582};
583
584/* Chip features we care about in vp->capabilities, read from the EEPROM. */
585enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
586
587struct vortex_extra_stats {
588 unsigned long tx_deferred;
589 unsigned long tx_max_collisions;
590 unsigned long tx_multiple_collisions;
591 unsigned long tx_single_collisions;
592 unsigned long rx_bad_ssd;
593};
594
595struct vortex_private {
596 /* The Rx and Tx rings should be quad-word-aligned. */
597 struct boom_rx_desc* rx_ring;
598 struct boom_tx_desc* tx_ring;
599 dma_addr_t rx_ring_dma;
600 dma_addr_t tx_ring_dma;
601 /* The addresses of transmit- and receive-in-place skbuffs. */
602 struct sk_buff* rx_skbuff[RX_RING_SIZE];
603 struct sk_buff* tx_skbuff[TX_RING_SIZE];
604 unsigned int cur_rx, cur_tx; /* The next free ring entry */
605 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
606 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
607 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
608 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
609
610 /* PCI configuration space information. */
611 struct device *gendev;
612 void __iomem *ioaddr; /* IO address space */
613 void __iomem *cb_fn_base; /* CardBus function status addr space. */
614
615 /* Some values here only for performance evaluation and path-coverage */
616 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
617 int card_idx;
618
619 /* The remainder are related to chip state, mostly media selection. */
620 struct timer_list timer; /* Media selection timer. */
621 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
622 int options; /* User-settable misc. driver options. */
623 unsigned int media_override:4, /* Passed-in media type. */
624 default_media:4, /* Read from the EEPROM/Wn3_Config. */
625 full_duplex:1, autoselect:1,
626 bus_master:1, /* Vortex can only do a fragment bus-m. */
627 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
628 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
629 partner_flow_ctrl:1, /* Partner supports flow control */
630 has_nway:1,
631 enable_wol:1, /* Wake-on-LAN is enabled */
632 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
633 open:1,
634 medialock:1,
635 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
636 large_frames:1, /* accept large frames */
637 handling_irq:1; /* private in_irq indicator */
638 /* {get|set}_wol operations are already serialized by rtnl.
639 * no additional locking is required for the enable_wol and acpi_set_WOL()
640 */
641 int drv_flags;
642 u16 status_enable;
643 u16 intr_enable;
644 u16 available_media; /* From Wn3_Options. */
645 u16 capabilities, info1, info2; /* Various, from EEPROM. */
646 u16 advertising; /* NWay media advertisement */
647 unsigned char phys[2]; /* MII device addresses. */
648 u16 deferred; /* Resend these interrupts when we
649 * bale from the ISR */
650 u16 io_size; /* Size of PCI region (for release_region) */
651
652 /* Serialises access to hardware other than MII and variables below.
653 * The lock hierarchy is rtnl_lock > {lock, mii_lock} > window_lock. */
654 spinlock_t lock;
655
656 spinlock_t mii_lock; /* Serialises access to MII */
657 struct mii_if_info mii; /* MII lib hooks/info */
658 spinlock_t window_lock; /* Serialises access to windowed regs */
659 int window; /* Register window */
660};
661
662static void window_set(struct vortex_private *vp, int window)
663{
664 if (window != vp->window) {
665 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
666 vp->window = window;
667 }
668}
669
670#define DEFINE_WINDOW_IO(size) \
671static u ## size \
672window_read ## size(struct vortex_private *vp, int window, int addr) \
673{ \
674 unsigned long flags; \
675 u ## size ret; \
676 spin_lock_irqsave(&vp->window_lock, flags); \
677 window_set(vp, window); \
678 ret = ioread ## size(vp->ioaddr + addr); \
679 spin_unlock_irqrestore(&vp->window_lock, flags); \
680 return ret; \
681} \
682static void \
683window_write ## size(struct vortex_private *vp, u ## size value, \
684 int window, int addr) \
685{ \
686 unsigned long flags; \
687 spin_lock_irqsave(&vp->window_lock, flags); \
688 window_set(vp, window); \
689 iowrite ## size(value, vp->ioaddr + addr); \
690 spin_unlock_irqrestore(&vp->window_lock, flags); \
691}
692DEFINE_WINDOW_IO(8)
693DEFINE_WINDOW_IO(16)
694DEFINE_WINDOW_IO(32)
695
696#ifdef CONFIG_PCI
697#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
698#else
699#define DEVICE_PCI(dev) NULL
700#endif
701
702#define VORTEX_PCI(vp) \
703 ((struct pci_dev *) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL))
704
705#ifdef CONFIG_EISA
706#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
707#else
708#define DEVICE_EISA(dev) NULL
709#endif
710
711#define VORTEX_EISA(vp) \
712 ((struct eisa_device *) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL))
713
714/* The action to take with a media selection timer tick.
715 Note that we deviate from the 3Com order by checking 10base2 before AUI.
716 */
717enum xcvr_types {
718 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
719 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
720};
721
722static const struct media_table {
723 char *name;
724 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
725 mask:8, /* The transceiver-present bit in Wn3_Config.*/
726 next:8; /* The media type to try next. */
727 int wait; /* Time before we check media status. */
728} media_tbl[] = {
729 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
730 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
731 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
732 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
733 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
734 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
735 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
736 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
737 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
738 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
739 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
740};
741
742static struct {
743 const char str[ETH_GSTRING_LEN];
744} ethtool_stats_keys[] = {
745 { "tx_deferred" },
746 { "tx_max_collisions" },
747 { "tx_multiple_collisions" },
748 { "tx_single_collisions" },
749 { "rx_bad_ssd" },
750};
751
752/* number of ETHTOOL_GSTATS u64's */
753#define VORTEX_NUM_STATS 5
754
755static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
756 int chip_idx, int card_idx);
757static int vortex_up(struct net_device *dev);
758static void vortex_down(struct net_device *dev, int final);
759static int vortex_open(struct net_device *dev);
760static void mdio_sync(struct vortex_private *vp, int bits);
761static int mdio_read(struct net_device *dev, int phy_id, int location);
762static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
763static void vortex_timer(unsigned long arg);
764static void rx_oom_timer(unsigned long arg);
765static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
766 struct net_device *dev);
767static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
768 struct net_device *dev);
769static int vortex_rx(struct net_device *dev);
770static int boomerang_rx(struct net_device *dev);
771static irqreturn_t vortex_interrupt(int irq, void *dev_id);
772static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
773static int vortex_close(struct net_device *dev);
774static void dump_tx_ring(struct net_device *dev);
775static void update_stats(void __iomem *ioaddr, struct net_device *dev);
776static struct net_device_stats *vortex_get_stats(struct net_device *dev);
777static void set_rx_mode(struct net_device *dev);
778#ifdef CONFIG_PCI
779static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
780#endif
781static void vortex_tx_timeout(struct net_device *dev);
782static void acpi_set_WOL(struct net_device *dev);
783static const struct ethtool_ops vortex_ethtool_ops;
784static void set_8021q_mode(struct net_device *dev, int enable);
785
786/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
787/* Option count limit only -- unlimited interfaces are supported. */
788#define MAX_UNITS 8
789static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
790static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
791static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
792static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
793static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
794static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
795static int global_options = -1;
796static int global_full_duplex = -1;
797static int global_enable_wol = -1;
798static int global_use_mmio = -1;
799
800/* Variables to work-around the Compaq PCI BIOS32 problem. */
801static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
802static struct net_device *compaq_net_device;
803
804static int vortex_cards_found;
805
806module_param(debug, int, 0);
807module_param(global_options, int, 0);
808module_param_array(options, int, NULL, 0);
809module_param(global_full_duplex, int, 0);
810module_param_array(full_duplex, int, NULL, 0);
811module_param_array(hw_checksums, int, NULL, 0);
812module_param_array(flow_ctrl, int, NULL, 0);
813module_param(global_enable_wol, int, 0);
814module_param_array(enable_wol, int, NULL, 0);
815module_param(rx_copybreak, int, 0);
816module_param(max_interrupt_work, int, 0);
817module_param(compaq_ioaddr, int, 0);
818module_param(compaq_irq, int, 0);
819module_param(compaq_device_id, int, 0);
820module_param(watchdog, int, 0);
821module_param(global_use_mmio, int, 0);
822module_param_array(use_mmio, int, NULL, 0);
823MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
824MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
825MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
826MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
827MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
828MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
829MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
830MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
831MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
832MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
833MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
834MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
835MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
836MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
837MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
838MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
839MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
840
841#ifdef CONFIG_NET_POLL_CONTROLLER
842static void poll_vortex(struct net_device *dev)
843{
844 struct vortex_private *vp = netdev_priv(dev);
845 unsigned long flags;
846 local_irq_save(flags);
847 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
848 local_irq_restore(flags);
849}
850#endif
851
852#ifdef CONFIG_PM
853
854static int vortex_suspend(struct device *dev)
855{
856 struct pci_dev *pdev = to_pci_dev(dev);
857 struct net_device *ndev = pci_get_drvdata(pdev);
858
859 if (!ndev || !netif_running(ndev))
860 return 0;
861
862 netif_device_detach(ndev);
863 vortex_down(ndev, 1);
864
865 return 0;
866}
867
868static int vortex_resume(struct device *dev)
869{
870 struct pci_dev *pdev = to_pci_dev(dev);
871 struct net_device *ndev = pci_get_drvdata(pdev);
872 int err;
873
874 if (!ndev || !netif_running(ndev))
875 return 0;
876
877 err = vortex_up(ndev);
878 if (err)
879 return err;
880
881 netif_device_attach(ndev);
882
883 return 0;
884}
885
886static const struct dev_pm_ops vortex_pm_ops = {
887 .suspend = vortex_suspend,
888 .resume = vortex_resume,
889 .freeze = vortex_suspend,
890 .thaw = vortex_resume,
891 .poweroff = vortex_suspend,
892 .restore = vortex_resume,
893};
894
895#define VORTEX_PM_OPS (&vortex_pm_ops)
896
897#else /* !CONFIG_PM */
898
899#define VORTEX_PM_OPS NULL
900
901#endif /* !CONFIG_PM */
902
903#ifdef CONFIG_EISA
904static struct eisa_device_id vortex_eisa_ids[] = {
905 { "TCM5920", CH_3C592 },
906 { "TCM5970", CH_3C597 },
907 { "" }
908};
909MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
910
911static int __init vortex_eisa_probe(struct device *device)
912{
913 void __iomem *ioaddr;
914 struct eisa_device *edev;
915
916 edev = to_eisa_device(device);
917
918 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
919 return -EBUSY;
920
921 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
922
923 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
924 edev->id.driver_data, vortex_cards_found)) {
925 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
926 return -ENODEV;
927 }
928
929 vortex_cards_found++;
930
931 return 0;
932}
933
934static int __devexit vortex_eisa_remove(struct device *device)
935{
936 struct eisa_device *edev;
937 struct net_device *dev;
938 struct vortex_private *vp;
939 void __iomem *ioaddr;
940
941 edev = to_eisa_device(device);
942 dev = eisa_get_drvdata(edev);
943
944 if (!dev) {
945 pr_err("vortex_eisa_remove called for Compaq device!\n");
946 BUG();
947 }
948
949 vp = netdev_priv(dev);
950 ioaddr = vp->ioaddr;
951
952 unregister_netdev(dev);
953 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
954 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
955
956 free_netdev(dev);
957 return 0;
958}
959
960static struct eisa_driver vortex_eisa_driver = {
961 .id_table = vortex_eisa_ids,
962 .driver = {
963 .name = "3c59x",
964 .probe = vortex_eisa_probe,
965 .remove = __devexit_p(vortex_eisa_remove)
966 }
967};
968
969#endif /* CONFIG_EISA */
970
971/* returns count found (>= 0), or negative on error */
972static int __init vortex_eisa_init(void)
973{
974 int eisa_found = 0;
975 int orig_cards_found = vortex_cards_found;
976
977#ifdef CONFIG_EISA
978 int err;
979
980 err = eisa_driver_register (&vortex_eisa_driver);
981 if (!err) {
982 /*
983 * Because of the way EISA bus is probed, we cannot assume
984 * any device have been found when we exit from
985 * eisa_driver_register (the bus root driver may not be
986 * initialized yet). So we blindly assume something was
987 * found, and let the sysfs magic happened...
988 */
989 eisa_found = 1;
990 }
991#endif
992
993 /* Special code to work-around the Compaq PCI BIOS32 problem. */
994 if (compaq_ioaddr) {
995 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
996 compaq_irq, compaq_device_id, vortex_cards_found++);
997 }
998
999 return vortex_cards_found - orig_cards_found + eisa_found;
1000}
1001
1002/* returns count (>= 0), or negative on error */
1003static int __devinit vortex_init_one(struct pci_dev *pdev,
1004 const struct pci_device_id *ent)
1005{
1006 int rc, unit, pci_bar;
1007 struct vortex_chip_info *vci;
1008 void __iomem *ioaddr;
1009
1010 /* wake up and enable device */
1011 rc = pci_enable_device(pdev);
1012 if (rc < 0)
1013 goto out;
1014
1015 unit = vortex_cards_found;
1016
1017 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1018 /* Determine the default if the user didn't override us */
1019 vci = &vortex_info_tbl[ent->driver_data];
1020 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1021 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1022 pci_bar = use_mmio[unit] ? 1 : 0;
1023 else
1024 pci_bar = global_use_mmio ? 1 : 0;
1025
1026 ioaddr = pci_iomap(pdev, pci_bar, 0);
1027 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1028 ioaddr = pci_iomap(pdev, 0, 0);
1029 if (!ioaddr) {
1030 pci_disable_device(pdev);
1031 rc = -ENOMEM;
1032 goto out;
1033 }
1034
1035 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1036 ent->driver_data, unit);
1037 if (rc < 0) {
1038 pci_iounmap(pdev, ioaddr);
1039 pci_disable_device(pdev);
1040 goto out;
1041 }
1042
1043 vortex_cards_found++;
1044
1045out:
1046 return rc;
1047}
1048
1049static const struct net_device_ops boomrang_netdev_ops = {
1050 .ndo_open = vortex_open,
1051 .ndo_stop = vortex_close,
1052 .ndo_start_xmit = boomerang_start_xmit,
1053 .ndo_tx_timeout = vortex_tx_timeout,
1054 .ndo_get_stats = vortex_get_stats,
1055#ifdef CONFIG_PCI
1056 .ndo_do_ioctl = vortex_ioctl,
1057#endif
1058 .ndo_set_multicast_list = set_rx_mode,
1059 .ndo_change_mtu = eth_change_mtu,
1060 .ndo_set_mac_address = eth_mac_addr,
1061 .ndo_validate_addr = eth_validate_addr,
1062#ifdef CONFIG_NET_POLL_CONTROLLER
1063 .ndo_poll_controller = poll_vortex,
1064#endif
1065};
1066
1067static const struct net_device_ops vortex_netdev_ops = {
1068 .ndo_open = vortex_open,
1069 .ndo_stop = vortex_close,
1070 .ndo_start_xmit = vortex_start_xmit,
1071 .ndo_tx_timeout = vortex_tx_timeout,
1072 .ndo_get_stats = vortex_get_stats,
1073#ifdef CONFIG_PCI
1074 .ndo_do_ioctl = vortex_ioctl,
1075#endif
1076 .ndo_set_multicast_list = set_rx_mode,
1077 .ndo_change_mtu = eth_change_mtu,
1078 .ndo_set_mac_address = eth_mac_addr,
1079 .ndo_validate_addr = eth_validate_addr,
1080#ifdef CONFIG_NET_POLL_CONTROLLER
1081 .ndo_poll_controller = poll_vortex,
1082#endif
1083};
1084
1085/*
1086 * Start up the PCI/EISA device which is described by *gendev.
1087 * Return 0 on success.
1088 *
1089 * NOTE: pdev can be NULL, for the case of a Compaq device
1090 */
1091static int __devinit vortex_probe1(struct device *gendev,
1092 void __iomem *ioaddr, int irq,
1093 int chip_idx, int card_idx)
1094{
1095 struct vortex_private *vp;
1096 int option;
1097 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1098 int i, step;
1099 struct net_device *dev;
1100 static int printed_version;
1101 int retval, print_info;
1102 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1103 const char *print_name = "3c59x";
1104 struct pci_dev *pdev = NULL;
1105 struct eisa_device *edev = NULL;
1106
1107 if (!printed_version) {
1108 pr_info("%s", version);
1109 printed_version = 1;
1110 }
1111
1112 if (gendev) {
1113 if ((pdev = DEVICE_PCI(gendev))) {
1114 print_name = pci_name(pdev);
1115 }
1116
1117 if ((edev = DEVICE_EISA(gendev))) {
1118 print_name = dev_name(&edev->dev);
1119 }
1120 }
1121
1122 dev = alloc_etherdev(sizeof(*vp));
1123 retval = -ENOMEM;
1124 if (!dev) {
1125 pr_err(PFX "unable to allocate etherdev, aborting\n");
1126 goto out;
1127 }
1128 SET_NETDEV_DEV(dev, gendev);
1129 vp = netdev_priv(dev);
1130
1131 option = global_options;
1132
1133 /* The lower four bits are the media type. */
1134 if (dev->mem_start) {
1135 /*
1136 * The 'options' param is passed in as the third arg to the
1137 * LILO 'ether=' argument for non-modular use
1138 */
1139 option = dev->mem_start;
1140 }
1141 else if (card_idx < MAX_UNITS) {
1142 if (options[card_idx] >= 0)
1143 option = options[card_idx];
1144 }
1145
1146 if (option > 0) {
1147 if (option & 0x8000)
1148 vortex_debug = 7;
1149 if (option & 0x4000)
1150 vortex_debug = 2;
1151 if (option & 0x0400)
1152 vp->enable_wol = 1;
1153 }
1154
1155 print_info = (vortex_debug > 1);
1156 if (print_info)
1157 pr_info("See Documentation/networking/vortex.txt\n");
1158
1159 pr_info("%s: 3Com %s %s at %p.\n",
1160 print_name,
1161 pdev ? "PCI" : "EISA",
1162 vci->name,
1163 ioaddr);
1164
1165 dev->base_addr = (unsigned long)ioaddr;
1166 dev->irq = irq;
1167 dev->mtu = mtu;
1168 vp->ioaddr = ioaddr;
1169 vp->large_frames = mtu > 1500;
1170 vp->drv_flags = vci->drv_flags;
1171 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1172 vp->io_size = vci->io_size;
1173 vp->card_idx = card_idx;
1174 vp->window = -1;
1175
1176 /* module list only for Compaq device */
1177 if (gendev == NULL) {
1178 compaq_net_device = dev;
1179 }
1180
1181 /* PCI-only startup logic */
1182 if (pdev) {
1183 /* EISA resources already marked, so only PCI needs to do this here */
1184 /* Ignore return value, because Cardbus drivers already allocate for us */
1185 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1186 vp->must_free_region = 1;
1187
1188 /* enable bus-mastering if necessary */
1189 if (vci->flags & PCI_USES_MASTER)
1190 pci_set_master(pdev);
1191
1192 if (vci->drv_flags & IS_VORTEX) {
1193 u8 pci_latency;
1194 u8 new_latency = 248;
1195
1196 /* Check the PCI latency value. On the 3c590 series the latency timer
1197 must be set to the maximum value to avoid data corruption that occurs
1198 when the timer expires during a transfer. This bug exists the Vortex
1199 chip only. */
1200 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1201 if (pci_latency < new_latency) {
1202 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1203 print_name, pci_latency, new_latency);
1204 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1205 }
1206 }
1207 }
1208
1209 spin_lock_init(&vp->lock);
1210 spin_lock_init(&vp->mii_lock);
1211 spin_lock_init(&vp->window_lock);
1212 vp->gendev = gendev;
1213 vp->mii.dev = dev;
1214 vp->mii.mdio_read = mdio_read;
1215 vp->mii.mdio_write = mdio_write;
1216 vp->mii.phy_id_mask = 0x1f;
1217 vp->mii.reg_num_mask = 0x1f;
1218
1219 /* Makes sure rings are at least 16 byte aligned. */
1220 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1221 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1222 &vp->rx_ring_dma);
1223 retval = -ENOMEM;
1224 if (!vp->rx_ring)
1225 goto free_region;
1226
1227 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1228 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1229
1230 /* if we are a PCI driver, we store info in pdev->driver_data
1231 * instead of a module list */
1232 if (pdev)
1233 pci_set_drvdata(pdev, dev);
1234 if (edev)
1235 eisa_set_drvdata(edev, dev);
1236
1237 vp->media_override = 7;
1238 if (option >= 0) {
1239 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1240 if (vp->media_override != 7)
1241 vp->medialock = 1;
1242 vp->full_duplex = (option & 0x200) ? 1 : 0;
1243 vp->bus_master = (option & 16) ? 1 : 0;
1244 }
1245
1246 if (global_full_duplex > 0)
1247 vp->full_duplex = 1;
1248 if (global_enable_wol > 0)
1249 vp->enable_wol = 1;
1250
1251 if (card_idx < MAX_UNITS) {
1252 if (full_duplex[card_idx] > 0)
1253 vp->full_duplex = 1;
1254 if (flow_ctrl[card_idx] > 0)
1255 vp->flow_ctrl = 1;
1256 if (enable_wol[card_idx] > 0)
1257 vp->enable_wol = 1;
1258 }
1259
1260 vp->mii.force_media = vp->full_duplex;
1261 vp->options = option;
1262 /* Read the station address from the EEPROM. */
1263 {
1264 int base;
1265
1266 if (vci->drv_flags & EEPROM_8BIT)
1267 base = 0x230;
1268 else if (vci->drv_flags & EEPROM_OFFSET)
1269 base = EEPROM_Read + 0x30;
1270 else
1271 base = EEPROM_Read;
1272
1273 for (i = 0; i < 0x40; i++) {
1274 int timer;
1275 window_write16(vp, base + i, 0, Wn0EepromCmd);
1276 /* Pause for at least 162 us. for the read to take place. */
1277 for (timer = 10; timer >= 0; timer--) {
1278 udelay(162);
1279 if ((window_read16(vp, 0, Wn0EepromCmd) &
1280 0x8000) == 0)
1281 break;
1282 }
1283 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1284 }
1285 }
1286 for (i = 0; i < 0x18; i++)
1287 checksum ^= eeprom[i];
1288 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1289 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1290 while (i < 0x21)
1291 checksum ^= eeprom[i++];
1292 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1293 }
1294 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1295 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1296 for (i = 0; i < 3; i++)
1297 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1298 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1299 if (print_info)
1300 pr_cont(" %pM", dev->dev_addr);
1301 /* Unfortunately an all zero eeprom passes the checksum and this
1302 gets found in the wild in failure cases. Crypto is hard 8) */
1303 if (!is_valid_ether_addr(dev->dev_addr)) {
1304 retval = -EINVAL;
1305 pr_err("*** EEPROM MAC address is invalid.\n");
1306 goto free_ring; /* With every pack */
1307 }
1308 for (i = 0; i < 6; i++)
1309 window_write8(vp, dev->dev_addr[i], 2, i);
1310
1311 if (print_info)
1312 pr_cont(", IRQ %d\n", dev->irq);
1313 /* Tell them about an invalid IRQ. */
1314 if (dev->irq <= 0 || dev->irq >= nr_irqs)
1315 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n",
1316 dev->irq);
1317
1318 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1319 if (print_info) {
1320 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1321 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1322 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1323 }
1324
1325
1326 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1327 unsigned short n;
1328
1329 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1330 if (!vp->cb_fn_base) {
1331 retval = -ENOMEM;
1332 goto free_ring;
1333 }
1334
1335 if (print_info) {
1336 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
1337 print_name,
1338 (unsigned long long)pci_resource_start(pdev, 2),
1339 vp->cb_fn_base);
1340 }
1341
1342 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1343 if (vp->drv_flags & INVERT_LED_PWR)
1344 n |= 0x10;
1345 if (vp->drv_flags & INVERT_MII_PWR)
1346 n |= 0x4000;
1347 window_write16(vp, n, 2, Wn2_ResetOptions);
1348 if (vp->drv_flags & WNO_XCVR_PWR) {
1349 window_write16(vp, 0x0800, 0, 0);
1350 }
1351 }
1352
1353 /* Extract our information from the EEPROM data. */
1354 vp->info1 = eeprom[13];
1355 vp->info2 = eeprom[15];
1356 vp->capabilities = eeprom[16];
1357
1358 if (vp->info1 & 0x8000) {
1359 vp->full_duplex = 1;
1360 if (print_info)
1361 pr_info("Full duplex capable\n");
1362 }
1363
1364 {
1365 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1366 unsigned int config;
1367 vp->available_media = window_read16(vp, 3, Wn3_Options);
1368 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1369 vp->available_media = 0x40;
1370 config = window_read32(vp, 3, Wn3_Config);
1371 if (print_info) {
1372 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
1373 config, window_read16(vp, 3, Wn3_Options));
1374 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1375 8 << RAM_SIZE(config),
1376 RAM_WIDTH(config) ? "word" : "byte",
1377 ram_split[RAM_SPLIT(config)],
1378 AUTOSELECT(config) ? "autoselect/" : "",
1379 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1380 media_tbl[XCVR(config)].name);
1381 }
1382 vp->default_media = XCVR(config);
1383 if (vp->default_media == XCVR_NWAY)
1384 vp->has_nway = 1;
1385 vp->autoselect = AUTOSELECT(config);
1386 }
1387
1388 if (vp->media_override != 7) {
1389 pr_info("%s: Media override to transceiver type %d (%s).\n",
1390 print_name, vp->media_override,
1391 media_tbl[vp->media_override].name);
1392 dev->if_port = vp->media_override;
1393 } else
1394 dev->if_port = vp->default_media;
1395
1396 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1397 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1398 int phy, phy_idx = 0;
1399 mii_preamble_required++;
1400 if (vp->drv_flags & EXTRA_PREAMBLE)
1401 mii_preamble_required++;
1402 mdio_sync(vp, 32);
1403 mdio_read(dev, 24, MII_BMSR);
1404 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1405 int mii_status, phyx;
1406
1407 /*
1408 * For the 3c905CX we look at index 24 first, because it bogusly
1409 * reports an external PHY at all indices
1410 */
1411 if (phy == 0)
1412 phyx = 24;
1413 else if (phy <= 24)
1414 phyx = phy - 1;
1415 else
1416 phyx = phy;
1417 mii_status = mdio_read(dev, phyx, MII_BMSR);
1418 if (mii_status && mii_status != 0xffff) {
1419 vp->phys[phy_idx++] = phyx;
1420 if (print_info) {
1421 pr_info(" MII transceiver found at address %d, status %4x.\n",
1422 phyx, mii_status);
1423 }
1424 if ((mii_status & 0x0040) == 0)
1425 mii_preamble_required++;
1426 }
1427 }
1428 mii_preamble_required--;
1429 if (phy_idx == 0) {
1430 pr_warning(" ***WARNING*** No MII transceivers found!\n");
1431 vp->phys[0] = 24;
1432 } else {
1433 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1434 if (vp->full_duplex) {
1435 /* Only advertise the FD media types. */
1436 vp->advertising &= ~0x02A0;
1437 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1438 }
1439 }
1440 vp->mii.phy_id = vp->phys[0];
1441 }
1442
1443 if (vp->capabilities & CapBusMaster) {
1444 vp->full_bus_master_tx = 1;
1445 if (print_info) {
1446 pr_info(" Enabling bus-master transmits and %s receives.\n",
1447 (vp->info2 & 1) ? "early" : "whole-frame" );
1448 }
1449 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1450 vp->bus_master = 0; /* AKPM: vortex only */
1451 }
1452
1453 /* The 3c59x-specific entries in the device structure. */
1454 if (vp->full_bus_master_tx) {
1455 dev->netdev_ops = &boomrang_netdev_ops;
1456 /* Actually, it still should work with iommu. */
1457 if (card_idx < MAX_UNITS &&
1458 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1459 hw_checksums[card_idx] == 1)) {
1460 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1461 }
1462 } else
1463 dev->netdev_ops = &vortex_netdev_ops;
1464
1465 if (print_info) {
1466 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1467 print_name,
1468 (dev->features & NETIF_F_SG) ? "en":"dis",
1469 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1470 }
1471
1472 dev->ethtool_ops = &vortex_ethtool_ops;
1473 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1474
1475 if (pdev) {
1476 vp->pm_state_valid = 1;
1477 pci_save_state(VORTEX_PCI(vp));
1478 acpi_set_WOL(dev);
1479 }
1480 retval = register_netdev(dev);
1481 if (retval == 0)
1482 return 0;
1483
1484free_ring:
1485 pci_free_consistent(pdev,
1486 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1487 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1488 vp->rx_ring,
1489 vp->rx_ring_dma);
1490free_region:
1491 if (vp->must_free_region)
1492 release_region(dev->base_addr, vci->io_size);
1493 free_netdev(dev);
1494 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1495out:
1496 return retval;
1497}
1498
1499static void
1500issue_and_wait(struct net_device *dev, int cmd)
1501{
1502 struct vortex_private *vp = netdev_priv(dev);
1503 void __iomem *ioaddr = vp->ioaddr;
1504 int i;
1505
1506 iowrite16(cmd, ioaddr + EL3_CMD);
1507 for (i = 0; i < 2000; i++) {
1508 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1509 return;
1510 }
1511
1512 /* OK, that didn't work. Do it the slow way. One second */
1513 for (i = 0; i < 100000; i++) {
1514 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1515 if (vortex_debug > 1)
1516 pr_info("%s: command 0x%04x took %d usecs\n",
1517 dev->name, cmd, i * 10);
1518 return;
1519 }
1520 udelay(10);
1521 }
1522 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
1523 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1524}
1525
1526static void
1527vortex_set_duplex(struct net_device *dev)
1528{
1529 struct vortex_private *vp = netdev_priv(dev);
1530
1531 pr_info("%s: setting %s-duplex.\n",
1532 dev->name, (vp->full_duplex) ? "full" : "half");
1533
1534 /* Set the full-duplex bit. */
1535 window_write16(vp,
1536 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1537 (vp->large_frames ? 0x40 : 0) |
1538 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1539 0x100 : 0),
1540 3, Wn3_MAC_Ctrl);
1541}
1542
1543static void vortex_check_media(struct net_device *dev, unsigned int init)
1544{
1545 struct vortex_private *vp = netdev_priv(dev);
1546 unsigned int ok_to_print = 0;
1547
1548 if (vortex_debug > 3)
1549 ok_to_print = 1;
1550
1551 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1552 vp->full_duplex = vp->mii.full_duplex;
1553 vortex_set_duplex(dev);
1554 } else if (init) {
1555 vortex_set_duplex(dev);
1556 }
1557}
1558
1559static int
1560vortex_up(struct net_device *dev)
1561{
1562 struct vortex_private *vp = netdev_priv(dev);
1563 void __iomem *ioaddr = vp->ioaddr;
1564 unsigned int config;
1565 int i, mii_reg1, mii_reg5, err = 0;
1566
1567 if (VORTEX_PCI(vp)) {
1568 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
1569 if (vp->pm_state_valid)
1570 pci_restore_state(VORTEX_PCI(vp));
1571 err = pci_enable_device(VORTEX_PCI(vp));
1572 if (err) {
1573 pr_warning("%s: Could not enable device\n",
1574 dev->name);
1575 goto err_out;
1576 }
1577 }
1578
1579 /* Before initializing select the active media port. */
1580 config = window_read32(vp, 3, Wn3_Config);
1581
1582 if (vp->media_override != 7) {
1583 pr_info("%s: Media override to transceiver %d (%s).\n",
1584 dev->name, vp->media_override,
1585 media_tbl[vp->media_override].name);
1586 dev->if_port = vp->media_override;
1587 } else if (vp->autoselect) {
1588 if (vp->has_nway) {
1589 if (vortex_debug > 1)
1590 pr_info("%s: using NWAY device table, not %d\n",
1591 dev->name, dev->if_port);
1592 dev->if_port = XCVR_NWAY;
1593 } else {
1594 /* Find first available media type, starting with 100baseTx. */
1595 dev->if_port = XCVR_100baseTx;
1596 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1597 dev->if_port = media_tbl[dev->if_port].next;
1598 if (vortex_debug > 1)
1599 pr_info("%s: first available media type: %s\n",
1600 dev->name, media_tbl[dev->if_port].name);
1601 }
1602 } else {
1603 dev->if_port = vp->default_media;
1604 if (vortex_debug > 1)
1605 pr_info("%s: using default media %s\n",
1606 dev->name, media_tbl[dev->if_port].name);
1607 }
1608
1609 init_timer(&vp->timer);
1610 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1611 vp->timer.data = (unsigned long)dev;
1612 vp->timer.function = vortex_timer; /* timer handler */
1613 add_timer(&vp->timer);
1614
1615 init_timer(&vp->rx_oom_timer);
1616 vp->rx_oom_timer.data = (unsigned long)dev;
1617 vp->rx_oom_timer.function = rx_oom_timer;
1618
1619 if (vortex_debug > 1)
1620 pr_debug("%s: Initial media type %s.\n",
1621 dev->name, media_tbl[dev->if_port].name);
1622
1623 vp->full_duplex = vp->mii.force_media;
1624 config = BFINS(config, dev->if_port, 20, 4);
1625 if (vortex_debug > 6)
1626 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
1627 window_write32(vp, config, 3, Wn3_Config);
1628
1629 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1630 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1631 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1632 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1633 vp->mii.full_duplex = vp->full_duplex;
1634
1635 vortex_check_media(dev, 1);
1636 }
1637 else
1638 vortex_set_duplex(dev);
1639
1640 issue_and_wait(dev, TxReset);
1641 /*
1642 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1643 */
1644 issue_and_wait(dev, RxReset|0x04);
1645
1646
1647 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1648
1649 if (vortex_debug > 1) {
1650 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
1651 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1652 }
1653
1654 /* Set the station address and mask in window 2 each time opened. */
1655 for (i = 0; i < 6; i++)
1656 window_write8(vp, dev->dev_addr[i], 2, i);
1657 for (; i < 12; i+=2)
1658 window_write16(vp, 0, 2, i);
1659
1660 if (vp->cb_fn_base) {
1661 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1662 if (vp->drv_flags & INVERT_LED_PWR)
1663 n |= 0x10;
1664 if (vp->drv_flags & INVERT_MII_PWR)
1665 n |= 0x4000;
1666 window_write16(vp, n, 2, Wn2_ResetOptions);
1667 }
1668
1669 if (dev->if_port == XCVR_10base2)
1670 /* Start the thinnet transceiver. We should really wait 50ms...*/
1671 iowrite16(StartCoax, ioaddr + EL3_CMD);
1672 if (dev->if_port != XCVR_NWAY) {
1673 window_write16(vp,
1674 (window_read16(vp, 4, Wn4_Media) &
1675 ~(Media_10TP|Media_SQE)) |
1676 media_tbl[dev->if_port].media_bits,
1677 4, Wn4_Media);
1678 }
1679
1680 /* Switch to the stats window, and clear all stats by reading. */
1681 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1682 for (i = 0; i < 10; i++)
1683 window_read8(vp, 6, i);
1684 window_read16(vp, 6, 10);
1685 window_read16(vp, 6, 12);
1686 /* New: On the Vortex we must also clear the BadSSD counter. */
1687 window_read8(vp, 4, 12);
1688 /* ..and on the Boomerang we enable the extra statistics bits. */
1689 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1690
1691 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1692 vp->cur_rx = vp->dirty_rx = 0;
1693 /* Initialize the RxEarly register as recommended. */
1694 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1695 iowrite32(0x0020, ioaddr + PktStatus);
1696 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1697 }
1698 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1699 vp->cur_tx = vp->dirty_tx = 0;
1700 if (vp->drv_flags & IS_BOOMERANG)
1701 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1702 /* Clear the Rx, Tx rings. */
1703 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1704 vp->rx_ring[i].status = 0;
1705 for (i = 0; i < TX_RING_SIZE; i++)
1706 vp->tx_skbuff[i] = NULL;
1707 iowrite32(0, ioaddr + DownListPtr);
1708 }
1709 /* Set receiver mode: presumably accept b-case and phys addr only. */
1710 set_rx_mode(dev);
1711 /* enable 802.1q tagged frames */
1712 set_8021q_mode(dev, 1);
1713 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1714
1715 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1716 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1717 /* Allow status bits to be seen. */
1718 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1719 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1720 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1721 (vp->bus_master ? DMADone : 0);
1722 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1723 (vp->full_bus_master_rx ? 0 : RxComplete) |
1724 StatsFull | HostError | TxComplete | IntReq
1725 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1726 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1727 /* Ack all pending events, and set active indicator mask. */
1728 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1729 ioaddr + EL3_CMD);
1730 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1731 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1732 iowrite32(0x8000, vp->cb_fn_base + 4);
1733 netif_start_queue (dev);
1734err_out:
1735 return err;
1736}
1737
1738static int
1739vortex_open(struct net_device *dev)
1740{
1741 struct vortex_private *vp = netdev_priv(dev);
1742 int i;
1743 int retval;
1744
1745 /* Use the now-standard shared IRQ implementation. */
1746 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1747 boomerang_interrupt : vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1748 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1749 goto err;
1750 }
1751
1752 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1753 if (vortex_debug > 2)
1754 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1755 for (i = 0; i < RX_RING_SIZE; i++) {
1756 struct sk_buff *skb;
1757 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1758 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1759 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1760
1761 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1762 GFP_KERNEL);
1763 vp->rx_skbuff[i] = skb;
1764 if (skb == NULL)
1765 break; /* Bad news! */
1766
1767 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
1768 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1769 }
1770 if (i != RX_RING_SIZE) {
1771 int j;
1772 pr_emerg("%s: no memory for rx ring\n", dev->name);
1773 for (j = 0; j < i; j++) {
1774 if (vp->rx_skbuff[j]) {
1775 dev_kfree_skb(vp->rx_skbuff[j]);
1776 vp->rx_skbuff[j] = NULL;
1777 }
1778 }
1779 retval = -ENOMEM;
1780 goto err_free_irq;
1781 }
1782 /* Wrap the ring. */
1783 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1784 }
1785
1786 retval = vortex_up(dev);
1787 if (!retval)
1788 goto out;
1789
1790err_free_irq:
1791 free_irq(dev->irq, dev);
1792err:
1793 if (vortex_debug > 1)
1794 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
1795out:
1796 return retval;
1797}
1798
1799static void
1800vortex_timer(unsigned long data)
1801{
1802 struct net_device *dev = (struct net_device *)data;
1803 struct vortex_private *vp = netdev_priv(dev);
1804 void __iomem *ioaddr = vp->ioaddr;
1805 int next_tick = 60*HZ;
1806 int ok = 0;
1807 int media_status;
1808
1809 if (vortex_debug > 2) {
1810 pr_debug("%s: Media selection timer tick happened, %s.\n",
1811 dev->name, media_tbl[dev->if_port].name);
1812 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1813 }
1814
1815 media_status = window_read16(vp, 4, Wn4_Media);
1816 switch (dev->if_port) {
1817 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1818 if (media_status & Media_LnkBeat) {
1819 netif_carrier_on(dev);
1820 ok = 1;
1821 if (vortex_debug > 1)
1822 pr_debug("%s: Media %s has link beat, %x.\n",
1823 dev->name, media_tbl[dev->if_port].name, media_status);
1824 } else {
1825 netif_carrier_off(dev);
1826 if (vortex_debug > 1) {
1827 pr_debug("%s: Media %s has no link beat, %x.\n",
1828 dev->name, media_tbl[dev->if_port].name, media_status);
1829 }
1830 }
1831 break;
1832 case XCVR_MII: case XCVR_NWAY:
1833 {
1834 ok = 1;
1835 vortex_check_media(dev, 0);
1836 }
1837 break;
1838 default: /* Other media types handled by Tx timeouts. */
1839 if (vortex_debug > 1)
1840 pr_debug("%s: Media %s has no indication, %x.\n",
1841 dev->name, media_tbl[dev->if_port].name, media_status);
1842 ok = 1;
1843 }
1844
1845 if (!netif_carrier_ok(dev))
1846 next_tick = 5*HZ;
1847
1848 if (vp->medialock)
1849 goto leave_media_alone;
1850
1851 if (!ok) {
1852 unsigned int config;
1853
1854 spin_lock_irq(&vp->lock);
1855
1856 do {
1857 dev->if_port = media_tbl[dev->if_port].next;
1858 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1859 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1860 dev->if_port = vp->default_media;
1861 if (vortex_debug > 1)
1862 pr_debug("%s: Media selection failing, using default %s port.\n",
1863 dev->name, media_tbl[dev->if_port].name);
1864 } else {
1865 if (vortex_debug > 1)
1866 pr_debug("%s: Media selection failed, now trying %s port.\n",
1867 dev->name, media_tbl[dev->if_port].name);
1868 next_tick = media_tbl[dev->if_port].wait;
1869 }
1870 window_write16(vp,
1871 (media_status & ~(Media_10TP|Media_SQE)) |
1872 media_tbl[dev->if_port].media_bits,
1873 4, Wn4_Media);
1874
1875 config = window_read32(vp, 3, Wn3_Config);
1876 config = BFINS(config, dev->if_port, 20, 4);
1877 window_write32(vp, config, 3, Wn3_Config);
1878
1879 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1880 ioaddr + EL3_CMD);
1881 if (vortex_debug > 1)
1882 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1883 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1884
1885 spin_unlock_irq(&vp->lock);
1886 }
1887
1888leave_media_alone:
1889 if (vortex_debug > 2)
1890 pr_debug("%s: Media selection timer finished, %s.\n",
1891 dev->name, media_tbl[dev->if_port].name);
1892
1893 mod_timer(&vp->timer, RUN_AT(next_tick));
1894 if (vp->deferred)
1895 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1896}
1897
1898static void vortex_tx_timeout(struct net_device *dev)
1899{
1900 struct vortex_private *vp = netdev_priv(dev);
1901 void __iomem *ioaddr = vp->ioaddr;
1902
1903 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1904 dev->name, ioread8(ioaddr + TxStatus),
1905 ioread16(ioaddr + EL3_STATUS));
1906 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1907 window_read16(vp, 4, Wn4_NetDiag),
1908 window_read16(vp, 4, Wn4_Media),
1909 ioread32(ioaddr + PktStatus),
1910 window_read16(vp, 4, Wn4_FIFODiag));
1911 /* Slight code bloat to be user friendly. */
1912 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1913 pr_err("%s: Transmitter encountered 16 collisions --"
1914 " network cable problem?\n", dev->name);
1915 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1916 pr_err("%s: Interrupt posted but not delivered --"
1917 " IRQ blocked by another device?\n", dev->name);
1918 /* Bad idea here.. but we might as well handle a few events. */
1919 {
1920 /*
1921 * Block interrupts because vortex_interrupt does a bare spin_lock()
1922 */
1923 unsigned long flags;
1924 local_irq_save(flags);
1925 if (vp->full_bus_master_tx)
1926 boomerang_interrupt(dev->irq, dev);
1927 else
1928 vortex_interrupt(dev->irq, dev);
1929 local_irq_restore(flags);
1930 }
1931 }
1932
1933 if (vortex_debug > 0)
1934 dump_tx_ring(dev);
1935
1936 issue_and_wait(dev, TxReset);
1937
1938 dev->stats.tx_errors++;
1939 if (vp->full_bus_master_tx) {
1940 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
1941 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1942 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1943 ioaddr + DownListPtr);
1944 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1945 netif_wake_queue (dev);
1946 if (vp->drv_flags & IS_BOOMERANG)
1947 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1948 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1949 } else {
1950 dev->stats.tx_dropped++;
1951 netif_wake_queue(dev);
1952 }
1953
1954 /* Issue Tx Enable */
1955 iowrite16(TxEnable, ioaddr + EL3_CMD);
1956 dev->trans_start = jiffies; /* prevent tx timeout */
1957}
1958
1959/*
1960 * Handle uncommon interrupt sources. This is a separate routine to minimize
1961 * the cache impact.
1962 */
1963static void
1964vortex_error(struct net_device *dev, int status)
1965{
1966 struct vortex_private *vp = netdev_priv(dev);
1967 void __iomem *ioaddr = vp->ioaddr;
1968 int do_tx_reset = 0, reset_mask = 0;
1969 unsigned char tx_status = 0;
1970
1971 if (vortex_debug > 2) {
1972 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1973 }
1974
1975 if (status & TxComplete) { /* Really "TxError" for us. */
1976 tx_status = ioread8(ioaddr + TxStatus);
1977 /* Presumably a tx-timeout. We must merely re-enable. */
1978 if (vortex_debug > 2 ||
1979 (tx_status != 0x88 && vortex_debug > 0)) {
1980 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1981 dev->name, tx_status);
1982 if (tx_status == 0x82) {
1983 pr_err("Probably a duplex mismatch. See "
1984 "Documentation/networking/vortex.txt\n");
1985 }
1986 dump_tx_ring(dev);
1987 }
1988 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1989 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1990 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
1991 iowrite8(0, ioaddr + TxStatus);
1992 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1993 do_tx_reset = 1;
1994 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1995 do_tx_reset = 1;
1996 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1997 } else { /* Merely re-enable the transmitter. */
1998 iowrite16(TxEnable, ioaddr + EL3_CMD);
1999 }
2000 }
2001
2002 if (status & RxEarly) /* Rx early is unused. */
2003 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
2004
2005 if (status & StatsFull) { /* Empty statistics. */
2006 static int DoneDidThat;
2007 if (vortex_debug > 4)
2008 pr_debug("%s: Updating stats.\n", dev->name);
2009 update_stats(ioaddr, dev);
2010 /* HACK: Disable statistics as an interrupt source. */
2011 /* This occurs when we have the wrong media type! */
2012 if (DoneDidThat == 0 &&
2013 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
2014 pr_warning("%s: Updating statistics failed, disabling "
2015 "stats as an interrupt source.\n", dev->name);
2016 iowrite16(SetIntrEnb |
2017 (window_read16(vp, 5, 10) & ~StatsFull),
2018 ioaddr + EL3_CMD);
2019 vp->intr_enable &= ~StatsFull;
2020 DoneDidThat++;
2021 }
2022 }
2023 if (status & IntReq) { /* Restore all interrupt sources. */
2024 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2025 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2026 }
2027 if (status & HostError) {
2028 u16 fifo_diag;
2029 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
2030 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
2031 dev->name, fifo_diag);
2032 /* Adapter failure requires Tx/Rx reset and reinit. */
2033 if (vp->full_bus_master_tx) {
2034 int bus_status = ioread32(ioaddr + PktStatus);
2035 /* 0x80000000 PCI master abort. */
2036 /* 0x40000000 PCI target abort. */
2037 if (vortex_debug)
2038 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2039
2040 /* In this case, blow the card away */
2041 /* Must not enter D3 or we can't legally issue the reset! */
2042 vortex_down(dev, 0);
2043 issue_and_wait(dev, TotalReset | 0xff);
2044 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2045 } else if (fifo_diag & 0x0400)
2046 do_tx_reset = 1;
2047 if (fifo_diag & 0x3000) {
2048 /* Reset Rx fifo and upload logic */
2049 issue_and_wait(dev, RxReset|0x07);
2050 /* Set the Rx filter to the current state. */
2051 set_rx_mode(dev);
2052 /* enable 802.1q VLAN tagged frames */
2053 set_8021q_mode(dev, 1);
2054 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2055 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2056 }
2057 }
2058
2059 if (do_tx_reset) {
2060 issue_and_wait(dev, TxReset|reset_mask);
2061 iowrite16(TxEnable, ioaddr + EL3_CMD);
2062 if (!vp->full_bus_master_tx)
2063 netif_wake_queue(dev);
2064 }
2065}
2066
2067static netdev_tx_t
2068vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2069{
2070 struct vortex_private *vp = netdev_priv(dev);
2071 void __iomem *ioaddr = vp->ioaddr;
2072
2073 /* Put out the doubleword header... */
2074 iowrite32(skb->len, ioaddr + TX_FIFO);
2075 if (vp->bus_master) {
2076 /* Set the bus-master controller to transfer the packet. */
2077 int len = (skb->len + 3) & ~3;
2078 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len,
2079 PCI_DMA_TODEVICE);
2080 spin_lock_irq(&vp->window_lock);
2081 window_set(vp, 7);
2082 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
2083 iowrite16(len, ioaddr + Wn7_MasterLen);
2084 spin_unlock_irq(&vp->window_lock);
2085 vp->tx_skb = skb;
2086 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2087 /* netif_wake_queue() will be called at the DMADone interrupt. */
2088 } else {
2089 /* ... and the packet rounded to a doubleword. */
2090 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2091 dev_kfree_skb (skb);
2092 if (ioread16(ioaddr + TxFree) > 1536) {
2093 netif_start_queue (dev); /* AKPM: redundant? */
2094 } else {
2095 /* Interrupt us when the FIFO has room for max-sized packet. */
2096 netif_stop_queue(dev);
2097 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2098 }
2099 }
2100
2101
2102 /* Clear the Tx status stack. */
2103 {
2104 int tx_status;
2105 int i = 32;
2106
2107 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2108 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2109 if (vortex_debug > 2)
2110 pr_debug("%s: Tx error, status %2.2x.\n",
2111 dev->name, tx_status);
2112 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2113 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
2114 if (tx_status & 0x30) {
2115 issue_and_wait(dev, TxReset);
2116 }
2117 iowrite16(TxEnable, ioaddr + EL3_CMD);
2118 }
2119 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2120 }
2121 }
2122 return NETDEV_TX_OK;
2123}
2124
2125static netdev_tx_t
2126boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2127{
2128 struct vortex_private *vp = netdev_priv(dev);
2129 void __iomem *ioaddr = vp->ioaddr;
2130 /* Calculate the next Tx descriptor entry. */
2131 int entry = vp->cur_tx % TX_RING_SIZE;
2132 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2133 unsigned long flags;
2134
2135 if (vortex_debug > 6) {
2136 pr_debug("boomerang_start_xmit()\n");
2137 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
2138 dev->name, vp->cur_tx);
2139 }
2140
2141 /*
2142 * We can't allow a recursion from our interrupt handler back into the
2143 * tx routine, as they take the same spin lock, and that causes
2144 * deadlock. Just return NETDEV_TX_BUSY and let the stack try again in
2145 * a bit
2146 */
2147 if (vp->handling_irq)
2148 return NETDEV_TX_BUSY;
2149
2150 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2151 if (vortex_debug > 0)
2152 pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n",
2153 dev->name);
2154 netif_stop_queue(dev);
2155 return NETDEV_TX_BUSY;
2156 }
2157
2158 vp->tx_skbuff[entry] = skb;
2159
2160 vp->tx_ring[entry].next = 0;
2161#if DO_ZEROCOPY
2162 if (skb->ip_summed != CHECKSUM_PARTIAL)
2163 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2164 else
2165 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2166
2167 if (!skb_shinfo(skb)->nr_frags) {
2168 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2169 skb->len, PCI_DMA_TODEVICE));
2170 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2171 } else {
2172 int i;
2173
2174 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2175 skb_headlen(skb), PCI_DMA_TODEVICE));
2176 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
2177
2178 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2179 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2180
2181 vp->tx_ring[entry].frag[i+1].addr =
2182 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2183 (void*)page_address(frag->page) + frag->page_offset,
2184 frag->size, PCI_DMA_TODEVICE));
2185
2186 if (i == skb_shinfo(skb)->nr_frags-1)
2187 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2188 else
2189 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2190 }
2191 }
2192#else
2193 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2194 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2195 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2196#endif
2197
2198 spin_lock_irqsave(&vp->lock, flags);
2199 /* Wait for the stall to complete. */
2200 issue_and_wait(dev, DownStall);
2201 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2202 if (ioread32(ioaddr + DownListPtr) == 0) {
2203 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2204 vp->queued_packet++;
2205 }
2206
2207 vp->cur_tx++;
2208 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2209 netif_stop_queue (dev);
2210 } else { /* Clear previous interrupt enable. */
2211#if defined(tx_interrupt_mitigation)
2212 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2213 * were selected, this would corrupt DN_COMPLETE. No?
2214 */
2215 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2216#endif
2217 }
2218 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2219 spin_unlock_irqrestore(&vp->lock, flags);
2220 return NETDEV_TX_OK;
2221}
2222
2223/* The interrupt handler does all of the Rx thread work and cleans up
2224 after the Tx thread. */
2225
2226/*
2227 * This is the ISR for the vortex series chips.
2228 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2229 */
2230
2231static irqreturn_t
2232vortex_interrupt(int irq, void *dev_id)
2233{
2234 struct net_device *dev = dev_id;
2235 struct vortex_private *vp = netdev_priv(dev);
2236 void __iomem *ioaddr;
2237 int status;
2238 int work_done = max_interrupt_work;
2239 int handled = 0;
2240
2241 ioaddr = vp->ioaddr;
2242 spin_lock(&vp->lock);
2243
2244 status = ioread16(ioaddr + EL3_STATUS);
2245
2246 if (vortex_debug > 6)
2247 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
2248
2249 if ((status & IntLatch) == 0)
2250 goto handler_exit; /* No interrupt: shared IRQs cause this */
2251 handled = 1;
2252
2253 if (status & IntReq) {
2254 status |= vp->deferred;
2255 vp->deferred = 0;
2256 }
2257
2258 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2259 goto handler_exit;
2260
2261 if (vortex_debug > 4)
2262 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2263 dev->name, status, ioread8(ioaddr + Timer));
2264
2265 spin_lock(&vp->window_lock);
2266 window_set(vp, 7);
2267
2268 do {
2269 if (vortex_debug > 5)
2270 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2271 dev->name, status);
2272 if (status & RxComplete)
2273 vortex_rx(dev);
2274
2275 if (status & TxAvailable) {
2276 if (vortex_debug > 5)
2277 pr_debug(" TX room bit was handled.\n");
2278 /* There's room in the FIFO for a full-sized packet. */
2279 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2280 netif_wake_queue (dev);
2281 }
2282
2283 if (status & DMADone) {
2284 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2285 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2286 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2287 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2288 if (ioread16(ioaddr + TxFree) > 1536) {
2289 /*
2290 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2291 * insufficient FIFO room, the TxAvailable test will succeed and call
2292 * netif_wake_queue()
2293 */
2294 netif_wake_queue(dev);
2295 } else { /* Interrupt when FIFO has room for max-sized packet. */
2296 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2297 netif_stop_queue(dev);
2298 }
2299 }
2300 }
2301 /* Check for all uncommon interrupts at once. */
2302 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2303 if (status == 0xffff)
2304 break;
2305 if (status & RxEarly)
2306 vortex_rx(dev);
2307 spin_unlock(&vp->window_lock);
2308 vortex_error(dev, status);
2309 spin_lock(&vp->window_lock);
2310 window_set(vp, 7);
2311 }
2312
2313 if (--work_done < 0) {
2314 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2315 dev->name, status);
2316 /* Disable all pending interrupts. */
2317 do {
2318 vp->deferred |= status;
2319 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2320 ioaddr + EL3_CMD);
2321 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2322 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2323 /* The timer will reenable interrupts. */
2324 mod_timer(&vp->timer, jiffies + 1*HZ);
2325 break;
2326 }
2327 /* Acknowledge the IRQ. */
2328 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2329 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2330
2331 spin_unlock(&vp->window_lock);
2332
2333 if (vortex_debug > 4)
2334 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2335 dev->name, status);
2336handler_exit:
2337 spin_unlock(&vp->lock);
2338 return IRQ_RETVAL(handled);
2339}
2340
2341/*
2342 * This is the ISR for the boomerang series chips.
2343 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2344 */
2345
2346static irqreturn_t
2347boomerang_interrupt(int irq, void *dev_id)
2348{
2349 struct net_device *dev = dev_id;
2350 struct vortex_private *vp = netdev_priv(dev);
2351 void __iomem *ioaddr;
2352 int status;
2353 int work_done = max_interrupt_work;
2354
2355 ioaddr = vp->ioaddr;
2356
2357
2358 /*
2359 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2360 * and boomerang_start_xmit
2361 */
2362 spin_lock(&vp->lock);
2363 vp->handling_irq = 1;
2364
2365 status = ioread16(ioaddr + EL3_STATUS);
2366
2367 if (vortex_debug > 6)
2368 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
2369
2370 if ((status & IntLatch) == 0)
2371 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2372
2373 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2374 if (vortex_debug > 1)
2375 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
2376 goto handler_exit;
2377 }
2378
2379 if (status & IntReq) {
2380 status |= vp->deferred;
2381 vp->deferred = 0;
2382 }
2383
2384 if (vortex_debug > 4)
2385 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2386 dev->name, status, ioread8(ioaddr + Timer));
2387 do {
2388 if (vortex_debug > 5)
2389 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2390 dev->name, status);
2391 if (status & UpComplete) {
2392 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2393 if (vortex_debug > 5)
2394 pr_debug("boomerang_interrupt->boomerang_rx\n");
2395 boomerang_rx(dev);
2396 }
2397
2398 if (status & DownComplete) {
2399 unsigned int dirty_tx = vp->dirty_tx;
2400
2401 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2402 while (vp->cur_tx - dirty_tx > 0) {
2403 int entry = dirty_tx % TX_RING_SIZE;
2404#if 1 /* AKPM: the latter is faster, but cyclone-only */
2405 if (ioread32(ioaddr + DownListPtr) ==
2406 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2407 break; /* It still hasn't been processed. */
2408#else
2409 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2410 break; /* It still hasn't been processed. */
2411#endif
2412
2413 if (vp->tx_skbuff[entry]) {
2414 struct sk_buff *skb = vp->tx_skbuff[entry];
2415#if DO_ZEROCOPY
2416 int i;
2417 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2418 pci_unmap_single(VORTEX_PCI(vp),
2419 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2420 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2421 PCI_DMA_TODEVICE);
2422#else
2423 pci_unmap_single(VORTEX_PCI(vp),
2424 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2425#endif
2426 dev_kfree_skb_irq(skb);
2427 vp->tx_skbuff[entry] = NULL;
2428 } else {
2429 pr_debug("boomerang_interrupt: no skb!\n");
2430 }
2431 /* dev->stats.tx_packets++; Counted below. */
2432 dirty_tx++;
2433 }
2434 vp->dirty_tx = dirty_tx;
2435 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2436 if (vortex_debug > 6)
2437 pr_debug("boomerang_interrupt: wake queue\n");
2438 netif_wake_queue (dev);
2439 }
2440 }
2441
2442 /* Check for all uncommon interrupts at once. */
2443 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2444 vortex_error(dev, status);
2445
2446 if (--work_done < 0) {
2447 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2448 dev->name, status);
2449 /* Disable all pending interrupts. */
2450 do {
2451 vp->deferred |= status;
2452 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2453 ioaddr + EL3_CMD);
2454 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2455 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2456 /* The timer will reenable interrupts. */
2457 mod_timer(&vp->timer, jiffies + 1*HZ);
2458 break;
2459 }
2460 /* Acknowledge the IRQ. */
2461 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2462 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2463 iowrite32(0x8000, vp->cb_fn_base + 4);
2464
2465 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2466
2467 if (vortex_debug > 4)
2468 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2469 dev->name, status);
2470handler_exit:
2471 vp->handling_irq = 0;
2472 spin_unlock(&vp->lock);
2473 return IRQ_HANDLED;
2474}
2475
2476static int vortex_rx(struct net_device *dev)
2477{
2478 struct vortex_private *vp = netdev_priv(dev);
2479 void __iomem *ioaddr = vp->ioaddr;
2480 int i;
2481 short rx_status;
2482
2483 if (vortex_debug > 5)
2484 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2485 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2486 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2487 if (rx_status & 0x4000) { /* Error, update stats. */
2488 unsigned char rx_error = ioread8(ioaddr + RxErrors);
2489 if (vortex_debug > 2)
2490 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2491 dev->stats.rx_errors++;
2492 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2493 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2494 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2495 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2496 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2497 } else {
2498 /* The packet length: up to 4.5K!. */
2499 int pkt_len = rx_status & 0x1fff;
2500 struct sk_buff *skb;
2501
2502 skb = dev_alloc_skb(pkt_len + 5);
2503 if (vortex_debug > 4)
2504 pr_debug("Receiving packet size %d status %4.4x.\n",
2505 pkt_len, rx_status);
2506 if (skb != NULL) {
2507 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2508 /* 'skb_put()' points to the start of sk_buff data area. */
2509 if (vp->bus_master &&
2510 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2511 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2512 pkt_len, PCI_DMA_FROMDEVICE);
2513 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2514 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2515 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2516 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2517 ;
2518 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2519 } else {
2520 ioread32_rep(ioaddr + RX_FIFO,
2521 skb_put(skb, pkt_len),
2522 (pkt_len + 3) >> 2);
2523 }
2524 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2525 skb->protocol = eth_type_trans(skb, dev);
2526 netif_rx(skb);
2527 dev->stats.rx_packets++;
2528 /* Wait a limited time to go to next packet. */
2529 for (i = 200; i >= 0; i--)
2530 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2531 break;
2532 continue;
2533 } else if (vortex_debug > 0)
2534 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2535 dev->name, pkt_len);
2536 dev->stats.rx_dropped++;
2537 }
2538 issue_and_wait(dev, RxDiscard);
2539 }
2540
2541 return 0;
2542}
2543
2544static int
2545boomerang_rx(struct net_device *dev)
2546{
2547 struct vortex_private *vp = netdev_priv(dev);
2548 int entry = vp->cur_rx % RX_RING_SIZE;
2549 void __iomem *ioaddr = vp->ioaddr;
2550 int rx_status;
2551 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2552
2553 if (vortex_debug > 5)
2554 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2555
2556 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2557 if (--rx_work_limit < 0)
2558 break;
2559 if (rx_status & RxDError) { /* Error, update stats. */
2560 unsigned char rx_error = rx_status >> 16;
2561 if (vortex_debug > 2)
2562 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2563 dev->stats.rx_errors++;
2564 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2565 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2566 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2567 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2568 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2569 } else {
2570 /* The packet length: up to 4.5K!. */
2571 int pkt_len = rx_status & 0x1fff;
2572 struct sk_buff *skb;
2573 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2574
2575 if (vortex_debug > 4)
2576 pr_debug("Receiving packet size %d status %4.4x.\n",
2577 pkt_len, rx_status);
2578
2579 /* Check if the packet is long enough to just accept without
2580 copying to a properly sized skbuff. */
2581 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
2582 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2583 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2584 /* 'skb_put()' points to the start of sk_buff data area. */
2585 memcpy(skb_put(skb, pkt_len),
2586 vp->rx_skbuff[entry]->data,
2587 pkt_len);
2588 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2589 vp->rx_copy++;
2590 } else {
2591 /* Pass up the skbuff already on the Rx ring. */
2592 skb = vp->rx_skbuff[entry];
2593 vp->rx_skbuff[entry] = NULL;
2594 skb_put(skb, pkt_len);
2595 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2596 vp->rx_nocopy++;
2597 }
2598 skb->protocol = eth_type_trans(skb, dev);
2599 { /* Use hardware checksum info. */
2600 int csum_bits = rx_status & 0xee000000;
2601 if (csum_bits &&
2602 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2603 csum_bits == (IPChksumValid | UDPChksumValid))) {
2604 skb->ip_summed = CHECKSUM_UNNECESSARY;
2605 vp->rx_csumhits++;
2606 }
2607 }
2608 netif_rx(skb);
2609 dev->stats.rx_packets++;
2610 }
2611 entry = (++vp->cur_rx) % RX_RING_SIZE;
2612 }
2613 /* Refill the Rx ring buffers. */
2614 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2615 struct sk_buff *skb;
2616 entry = vp->dirty_rx % RX_RING_SIZE;
2617 if (vp->rx_skbuff[entry] == NULL) {
2618 skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
2619 if (skb == NULL) {
2620 static unsigned long last_jif;
2621 if (time_after(jiffies, last_jif + 10 * HZ)) {
2622 pr_warning("%s: memory shortage\n", dev->name);
2623 last_jif = jiffies;
2624 }
2625 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2626 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2627 break; /* Bad news! */
2628 }
2629
2630 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2631 vp->rx_skbuff[entry] = skb;
2632 }
2633 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2634 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2635 }
2636 return 0;
2637}
2638
2639/*
2640 * If we've hit a total OOM refilling the Rx ring we poll once a second
2641 * for some memory. Otherwise there is no way to restart the rx process.
2642 */
2643static void
2644rx_oom_timer(unsigned long arg)
2645{
2646 struct net_device *dev = (struct net_device *)arg;
2647 struct vortex_private *vp = netdev_priv(dev);
2648
2649 spin_lock_irq(&vp->lock);
2650 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2651 boomerang_rx(dev);
2652 if (vortex_debug > 1) {
2653 pr_debug("%s: rx_oom_timer %s\n", dev->name,
2654 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2655 }
2656 spin_unlock_irq(&vp->lock);
2657}
2658
2659static void
2660vortex_down(struct net_device *dev, int final_down)
2661{
2662 struct vortex_private *vp = netdev_priv(dev);
2663 void __iomem *ioaddr = vp->ioaddr;
2664
2665 netif_stop_queue (dev);
2666
2667 del_timer_sync(&vp->rx_oom_timer);
2668 del_timer_sync(&vp->timer);
2669
2670 /* Turn off statistics ASAP. We update dev->stats below. */
2671 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2672
2673 /* Disable the receiver and transmitter. */
2674 iowrite16(RxDisable, ioaddr + EL3_CMD);
2675 iowrite16(TxDisable, ioaddr + EL3_CMD);
2676
2677 /* Disable receiving 802.1q tagged frames */
2678 set_8021q_mode(dev, 0);
2679
2680 if (dev->if_port == XCVR_10base2)
2681 /* Turn off thinnet power. Green! */
2682 iowrite16(StopCoax, ioaddr + EL3_CMD);
2683
2684 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2685
2686 update_stats(ioaddr, dev);
2687 if (vp->full_bus_master_rx)
2688 iowrite32(0, ioaddr + UpListPtr);
2689 if (vp->full_bus_master_tx)
2690 iowrite32(0, ioaddr + DownListPtr);
2691
2692 if (final_down && VORTEX_PCI(vp)) {
2693 vp->pm_state_valid = 1;
2694 pci_save_state(VORTEX_PCI(vp));
2695 acpi_set_WOL(dev);
2696 }
2697}
2698
2699static int
2700vortex_close(struct net_device *dev)
2701{
2702 struct vortex_private *vp = netdev_priv(dev);
2703 void __iomem *ioaddr = vp->ioaddr;
2704 int i;
2705
2706 if (netif_device_present(dev))
2707 vortex_down(dev, 1);
2708
2709 if (vortex_debug > 1) {
2710 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2711 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2712 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
2713 " tx_queued %d Rx pre-checksummed %d.\n",
2714 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2715 }
2716
2717#if DO_ZEROCOPY
2718 if (vp->rx_csumhits &&
2719 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2720 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2721 pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name);
2722 }
2723#endif
2724
2725 free_irq(dev->irq, dev);
2726
2727 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2728 for (i = 0; i < RX_RING_SIZE; i++)
2729 if (vp->rx_skbuff[i]) {
2730 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2731 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2732 dev_kfree_skb(vp->rx_skbuff[i]);
2733 vp->rx_skbuff[i] = NULL;
2734 }
2735 }
2736 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2737 for (i = 0; i < TX_RING_SIZE; i++) {
2738 if (vp->tx_skbuff[i]) {
2739 struct sk_buff *skb = vp->tx_skbuff[i];
2740#if DO_ZEROCOPY
2741 int k;
2742
2743 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2744 pci_unmap_single(VORTEX_PCI(vp),
2745 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2746 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2747 PCI_DMA_TODEVICE);
2748#else
2749 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2750#endif
2751 dev_kfree_skb(skb);
2752 vp->tx_skbuff[i] = NULL;
2753 }
2754 }
2755 }
2756
2757 return 0;
2758}
2759
2760static void
2761dump_tx_ring(struct net_device *dev)
2762{
2763 if (vortex_debug > 0) {
2764 struct vortex_private *vp = netdev_priv(dev);
2765 void __iomem *ioaddr = vp->ioaddr;
2766
2767 if (vp->full_bus_master_tx) {
2768 int i;
2769 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2770
2771 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2772 vp->full_bus_master_tx,
2773 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2774 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2775 pr_err(" Transmit list %8.8x vs. %p.\n",
2776 ioread32(ioaddr + DownListPtr),
2777 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2778 issue_and_wait(dev, DownStall);
2779 for (i = 0; i < TX_RING_SIZE; i++) {
2780 unsigned int length;
2781
2782#if DO_ZEROCOPY
2783 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
2784#else
2785 length = le32_to_cpu(vp->tx_ring[i].length);
2786#endif
2787 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2788 i, &vp->tx_ring[i], length,
2789 le32_to_cpu(vp->tx_ring[i].status));
2790 }
2791 if (!stalled)
2792 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2793 }
2794 }
2795}
2796
2797static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2798{
2799 struct vortex_private *vp = netdev_priv(dev);
2800 void __iomem *ioaddr = vp->ioaddr;
2801 unsigned long flags;
2802
2803 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2804 spin_lock_irqsave (&vp->lock, flags);
2805 update_stats(ioaddr, dev);
2806 spin_unlock_irqrestore (&vp->lock, flags);
2807 }
2808 return &dev->stats;
2809}
2810
2811/* Update statistics.
2812 Unlike with the EL3 we need not worry about interrupts changing
2813 the window setting from underneath us, but we must still guard
2814 against a race condition with a StatsUpdate interrupt updating the
2815 table. This is done by checking that the ASM (!) code generated uses
2816 atomic updates with '+='.
2817 */
2818static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2819{
2820 struct vortex_private *vp = netdev_priv(dev);
2821
2822 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2823 /* Switch to the stats window, and read everything. */
2824 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2825 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2826 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2827 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2828 dev->stats.tx_packets += window_read8(vp, 6, 6);
2829 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2830 0x30) << 4;
2831 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
2832 /* Don't bother with register 9, an extension of registers 6&7.
2833 If we do use the 6&7 values the atomic update assumption above
2834 is invalid. */
2835 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2836 dev->stats.tx_bytes += window_read16(vp, 6, 12);
2837 /* Extra stats for get_ethtool_stats() */
2838 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2839 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2840 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2841 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
2842
2843 dev->stats.collisions = vp->xstats.tx_multiple_collisions
2844 + vp->xstats.tx_single_collisions
2845 + vp->xstats.tx_max_collisions;
2846
2847 {
2848 u8 up = window_read8(vp, 4, 13);
2849 dev->stats.rx_bytes += (up & 0x0f) << 16;
2850 dev->stats.tx_bytes += (up & 0xf0) << 12;
2851 }
2852}
2853
2854static int vortex_nway_reset(struct net_device *dev)
2855{
2856 struct vortex_private *vp = netdev_priv(dev);
2857
2858 return mii_nway_restart(&vp->mii);
2859}
2860
2861static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2862{
2863 struct vortex_private *vp = netdev_priv(dev);
2864
2865 return mii_ethtool_gset(&vp->mii, cmd);
2866}
2867
2868static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2869{
2870 struct vortex_private *vp = netdev_priv(dev);
2871
2872 return mii_ethtool_sset(&vp->mii, cmd);
2873}
2874
2875static u32 vortex_get_msglevel(struct net_device *dev)
2876{
2877 return vortex_debug;
2878}
2879
2880static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2881{
2882 vortex_debug = dbg;
2883}
2884
2885static int vortex_get_sset_count(struct net_device *dev, int sset)
2886{
2887 switch (sset) {
2888 case ETH_SS_STATS:
2889 return VORTEX_NUM_STATS;
2890 default:
2891 return -EOPNOTSUPP;
2892 }
2893}
2894
2895static void vortex_get_ethtool_stats(struct net_device *dev,
2896 struct ethtool_stats *stats, u64 *data)
2897{
2898 struct vortex_private *vp = netdev_priv(dev);
2899 void __iomem *ioaddr = vp->ioaddr;
2900 unsigned long flags;
2901
2902 spin_lock_irqsave(&vp->lock, flags);
2903 update_stats(ioaddr, dev);
2904 spin_unlock_irqrestore(&vp->lock, flags);
2905
2906 data[0] = vp->xstats.tx_deferred;
2907 data[1] = vp->xstats.tx_max_collisions;
2908 data[2] = vp->xstats.tx_multiple_collisions;
2909 data[3] = vp->xstats.tx_single_collisions;
2910 data[4] = vp->xstats.rx_bad_ssd;
2911}
2912
2913
2914static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2915{
2916 switch (stringset) {
2917 case ETH_SS_STATS:
2918 memcpy(data, ðtool_stats_keys, sizeof(ethtool_stats_keys));
2919 break;
2920 default:
2921 WARN_ON(1);
2922 break;
2923 }
2924}
2925
2926static void vortex_get_drvinfo(struct net_device *dev,
2927 struct ethtool_drvinfo *info)
2928{
2929 struct vortex_private *vp = netdev_priv(dev);
2930
2931 strcpy(info->driver, DRV_NAME);
2932 if (VORTEX_PCI(vp)) {
2933 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2934 } else {
2935 if (VORTEX_EISA(vp))
2936 strcpy(info->bus_info, dev_name(vp->gendev));
2937 else
2938 sprintf(info->bus_info, "EISA 0x%lx %d",
2939 dev->base_addr, dev->irq);
2940 }
2941}
2942
2943static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2944{
2945 struct vortex_private *vp = netdev_priv(dev);
2946
2947 if (!VORTEX_PCI(vp))
2948 return;
2949
2950 wol->supported = WAKE_MAGIC;
2951
2952 wol->wolopts = 0;
2953 if (vp->enable_wol)
2954 wol->wolopts |= WAKE_MAGIC;
2955}
2956
2957static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2958{
2959 struct vortex_private *vp = netdev_priv(dev);
2960
2961 if (!VORTEX_PCI(vp))
2962 return -EOPNOTSUPP;
2963
2964 if (wol->wolopts & ~WAKE_MAGIC)
2965 return -EINVAL;
2966
2967 if (wol->wolopts & WAKE_MAGIC)
2968 vp->enable_wol = 1;
2969 else
2970 vp->enable_wol = 0;
2971 acpi_set_WOL(dev);
2972
2973 return 0;
2974}
2975
2976static const struct ethtool_ops vortex_ethtool_ops = {
2977 .get_drvinfo = vortex_get_drvinfo,
2978 .get_strings = vortex_get_strings,
2979 .get_msglevel = vortex_get_msglevel,
2980 .set_msglevel = vortex_set_msglevel,
2981 .get_ethtool_stats = vortex_get_ethtool_stats,
2982 .get_sset_count = vortex_get_sset_count,
2983 .get_settings = vortex_get_settings,
2984 .set_settings = vortex_set_settings,
2985 .get_link = ethtool_op_get_link,
2986 .nway_reset = vortex_nway_reset,
2987 .get_wol = vortex_get_wol,
2988 .set_wol = vortex_set_wol,
2989};
2990
2991#ifdef CONFIG_PCI
2992/*
2993 * Must power the device up to do MDIO operations
2994 */
2995static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2996{
2997 int err;
2998 struct vortex_private *vp = netdev_priv(dev);
2999 pci_power_t state = 0;
3000
3001 if(VORTEX_PCI(vp))
3002 state = VORTEX_PCI(vp)->current_state;
3003
3004 /* The kernel core really should have pci_get_power_state() */
3005
3006 if(state != 0)
3007 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3008 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3009 if(state != 0)
3010 pci_set_power_state(VORTEX_PCI(vp), state);
3011
3012 return err;
3013}
3014#endif
3015
3016
3017/* Pre-Cyclone chips have no documented multicast filter, so the only
3018 multicast setting is to receive all multicast frames. At least
3019 the chip has a very clean way to set the mode, unlike many others. */
3020static void set_rx_mode(struct net_device *dev)
3021{
3022 struct vortex_private *vp = netdev_priv(dev);
3023 void __iomem *ioaddr = vp->ioaddr;
3024 int new_mode;
3025
3026 if (dev->flags & IFF_PROMISC) {
3027 if (vortex_debug > 3)
3028 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
3029 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3030 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
3031 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3032 } else
3033 new_mode = SetRxFilter | RxStation | RxBroadcast;
3034
3035 iowrite16(new_mode, ioaddr + EL3_CMD);
3036}
3037
3038#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3039/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3040 Note that this must be done after each RxReset due to some backwards
3041 compatibility logic in the Cyclone and Tornado ASICs */
3042
3043/* The Ethernet Type used for 802.1q tagged frames */
3044#define VLAN_ETHER_TYPE 0x8100
3045
3046static void set_8021q_mode(struct net_device *dev, int enable)
3047{
3048 struct vortex_private *vp = netdev_priv(dev);
3049 int mac_ctrl;
3050
3051 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3052 /* cyclone and tornado chipsets can recognize 802.1q
3053 * tagged frames and treat them correctly */
3054
3055 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3056 if (enable)
3057 max_pkt_size += 4; /* 802.1Q VLAN tag */
3058
3059 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
3060
3061 /* set VlanEtherType to let the hardware checksumming
3062 treat tagged frames correctly */
3063 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
3064 } else {
3065 /* on older cards we have to enable large frames */
3066
3067 vp->large_frames = dev->mtu > 1500 || enable;
3068
3069 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
3070 if (vp->large_frames)
3071 mac_ctrl |= 0x40;
3072 else
3073 mac_ctrl &= ~0x40;
3074 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
3075 }
3076}
3077#else
3078
3079static void set_8021q_mode(struct net_device *dev, int enable)
3080{
3081}
3082
3083
3084#endif
3085
3086/* MII transceiver control section.
3087 Read and write the MII registers using software-generated serial
3088 MDIO protocol. See the MII specifications or DP83840A data sheet
3089 for details. */
3090
3091/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3092 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3093 "overclocking" issues. */
3094static void mdio_delay(struct vortex_private *vp)
3095{
3096 window_read32(vp, 4, Wn4_PhysicalMgmt);
3097}
3098
3099#define MDIO_SHIFT_CLK 0x01
3100#define MDIO_DIR_WRITE 0x04
3101#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3102#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3103#define MDIO_DATA_READ 0x02
3104#define MDIO_ENB_IN 0x00
3105
3106/* Generate the preamble required for initial synchronization and
3107 a few older transceivers. */
3108static void mdio_sync(struct vortex_private *vp, int bits)
3109{
3110 /* Establish sync by sending at least 32 logic ones. */
3111 while (-- bits >= 0) {
3112 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3113 mdio_delay(vp);
3114 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3115 4, Wn4_PhysicalMgmt);
3116 mdio_delay(vp);
3117 }
3118}
3119
3120static int mdio_read(struct net_device *dev, int phy_id, int location)
3121{
3122 int i;
3123 struct vortex_private *vp = netdev_priv(dev);
3124 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3125 unsigned int retval = 0;
3126
3127 spin_lock_bh(&vp->mii_lock);
3128
3129 if (mii_preamble_required)
3130 mdio_sync(vp, 32);
3131
3132 /* Shift the read command bits out. */
3133 for (i = 14; i >= 0; i--) {
3134 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3135 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3136 mdio_delay(vp);
3137 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3138 4, Wn4_PhysicalMgmt);
3139 mdio_delay(vp);
3140 }
3141 /* Read the two transition, 16 data, and wire-idle bits. */
3142 for (i = 19; i > 0; i--) {
3143 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3144 mdio_delay(vp);
3145 retval = (retval << 1) |
3146 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3147 MDIO_DATA_READ) ? 1 : 0);
3148 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3149 4, Wn4_PhysicalMgmt);
3150 mdio_delay(vp);
3151 }
3152
3153 spin_unlock_bh(&vp->mii_lock);
3154
3155 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3156}
3157
3158static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3159{
3160 struct vortex_private *vp = netdev_priv(dev);
3161 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3162 int i;
3163
3164 spin_lock_bh(&vp->mii_lock);
3165
3166 if (mii_preamble_required)
3167 mdio_sync(vp, 32);
3168
3169 /* Shift the command bits out. */
3170 for (i = 31; i >= 0; i--) {
3171 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3172 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3173 mdio_delay(vp);
3174 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3175 4, Wn4_PhysicalMgmt);
3176 mdio_delay(vp);
3177 }
3178 /* Leave the interface idle. */
3179 for (i = 1; i >= 0; i--) {
3180 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3181 mdio_delay(vp);
3182 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3183 4, Wn4_PhysicalMgmt);
3184 mdio_delay(vp);
3185 }
3186
3187 spin_unlock_bh(&vp->mii_lock);
3188}
3189
3190/* ACPI: Advanced Configuration and Power Interface. */
3191/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3192static void acpi_set_WOL(struct net_device *dev)
3193{
3194 struct vortex_private *vp = netdev_priv(dev);
3195 void __iomem *ioaddr = vp->ioaddr;
3196
3197 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3198
3199 if (vp->enable_wol) {
3200 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3201 window_write16(vp, 2, 7, 0x0c);
3202 /* The RxFilter must accept the WOL frames. */
3203 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3204 iowrite16(RxEnable, ioaddr + EL3_CMD);
3205
3206 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3207 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
3208
3209 vp->enable_wol = 0;
3210 return;
3211 }
3212
3213 if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
3214 return;
3215
3216 /* Change the power state to D3; RxEnable doesn't take effect. */
3217 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3218 }
3219}
3220
3221
3222static void __devexit vortex_remove_one(struct pci_dev *pdev)
3223{
3224 struct net_device *dev = pci_get_drvdata(pdev);
3225 struct vortex_private *vp;
3226
3227 if (!dev) {
3228 pr_err("vortex_remove_one called for Compaq device!\n");
3229 BUG();
3230 }
3231
3232 vp = netdev_priv(dev);
3233
3234 if (vp->cb_fn_base)
3235 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3236
3237 unregister_netdev(dev);
3238
3239 if (VORTEX_PCI(vp)) {
3240 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3241 if (vp->pm_state_valid)
3242 pci_restore_state(VORTEX_PCI(vp));
3243 pci_disable_device(VORTEX_PCI(vp));
3244 }
3245 /* Should really use issue_and_wait() here */
3246 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3247 vp->ioaddr + EL3_CMD);
3248
3249 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
3250
3251 pci_free_consistent(pdev,
3252 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3253 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3254 vp->rx_ring,
3255 vp->rx_ring_dma);
3256 if (vp->must_free_region)
3257 release_region(dev->base_addr, vp->io_size);
3258 free_netdev(dev);
3259}
3260
3261
3262static struct pci_driver vortex_driver = {
3263 .name = "3c59x",
3264 .probe = vortex_init_one,
3265 .remove = __devexit_p(vortex_remove_one),
3266 .id_table = vortex_pci_tbl,
3267 .driver.pm = VORTEX_PM_OPS,
3268};
3269
3270
3271static int vortex_have_pci;
3272static int vortex_have_eisa;
3273
3274
3275static int __init vortex_init(void)
3276{
3277 int pci_rc, eisa_rc;
3278
3279 pci_rc = pci_register_driver(&vortex_driver);
3280 eisa_rc = vortex_eisa_init();
3281
3282 if (pci_rc == 0)
3283 vortex_have_pci = 1;
3284 if (eisa_rc > 0)
3285 vortex_have_eisa = 1;
3286
3287 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3288}
3289
3290
3291static void __exit vortex_eisa_cleanup(void)
3292{
3293 struct vortex_private *vp;
3294 void __iomem *ioaddr;
3295
3296#ifdef CONFIG_EISA
3297 /* Take care of the EISA devices */
3298 eisa_driver_unregister(&vortex_eisa_driver);
3299#endif
3300
3301 if (compaq_net_device) {
3302 vp = netdev_priv(compaq_net_device);
3303 ioaddr = ioport_map(compaq_net_device->base_addr,
3304 VORTEX_TOTAL_SIZE);
3305
3306 unregister_netdev(compaq_net_device);
3307 iowrite16(TotalReset, ioaddr + EL3_CMD);
3308 release_region(compaq_net_device->base_addr,
3309 VORTEX_TOTAL_SIZE);
3310
3311 free_netdev(compaq_net_device);
3312 }
3313}
3314
3315
3316static void __exit vortex_cleanup(void)
3317{
3318 if (vortex_have_pci)
3319 pci_unregister_driver(&vortex_driver);
3320 if (vortex_have_eisa)
3321 vortex_eisa_cleanup();
3322}
3323
3324
3325module_init(vortex_init);
3326module_exit(vortex_cleanup);