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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/drivers/mmc/host/omap.c
4 *
5 * Copyright (C) 2004 Nokia Corporation
6 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
7 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
8 * Other hacks (DMA, SD, etc) by David Brownell
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/platform_device.h>
16#include <linux/interrupt.h>
17#include <linux/dmaengine.h>
18#include <linux/dma-mapping.h>
19#include <linux/delay.h>
20#include <linux/spinlock.h>
21#include <linux/timer.h>
22#include <linux/of.h>
23#include <linux/mmc/host.h>
24#include <linux/mmc/card.h>
25#include <linux/mmc/mmc.h>
26#include <linux/clk.h>
27#include <linux/scatterlist.h>
28#include <linux/slab.h>
29#include <linux/gpio/consumer.h>
30#include <linux/platform_data/mmc-omap.h>
31
32
33#define OMAP_MMC_REG_CMD 0x00
34#define OMAP_MMC_REG_ARGL 0x01
35#define OMAP_MMC_REG_ARGH 0x02
36#define OMAP_MMC_REG_CON 0x03
37#define OMAP_MMC_REG_STAT 0x04
38#define OMAP_MMC_REG_IE 0x05
39#define OMAP_MMC_REG_CTO 0x06
40#define OMAP_MMC_REG_DTO 0x07
41#define OMAP_MMC_REG_DATA 0x08
42#define OMAP_MMC_REG_BLEN 0x09
43#define OMAP_MMC_REG_NBLK 0x0a
44#define OMAP_MMC_REG_BUF 0x0b
45#define OMAP_MMC_REG_SDIO 0x0d
46#define OMAP_MMC_REG_REV 0x0f
47#define OMAP_MMC_REG_RSP0 0x10
48#define OMAP_MMC_REG_RSP1 0x11
49#define OMAP_MMC_REG_RSP2 0x12
50#define OMAP_MMC_REG_RSP3 0x13
51#define OMAP_MMC_REG_RSP4 0x14
52#define OMAP_MMC_REG_RSP5 0x15
53#define OMAP_MMC_REG_RSP6 0x16
54#define OMAP_MMC_REG_RSP7 0x17
55#define OMAP_MMC_REG_IOSR 0x18
56#define OMAP_MMC_REG_SYSC 0x19
57#define OMAP_MMC_REG_SYSS 0x1a
58
59#define OMAP_MMC_STAT_CARD_ERR (1 << 14)
60#define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
61#define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
62#define OMAP_MMC_STAT_A_EMPTY (1 << 11)
63#define OMAP_MMC_STAT_A_FULL (1 << 10)
64#define OMAP_MMC_STAT_CMD_CRC (1 << 8)
65#define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
66#define OMAP_MMC_STAT_DATA_CRC (1 << 6)
67#define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
68#define OMAP_MMC_STAT_END_BUSY (1 << 4)
69#define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
70#define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
71#define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
72
73#define mmc_omap7xx() (host->features & MMC_OMAP7XX)
74#define mmc_omap15xx() (host->features & MMC_OMAP15XX)
75#define mmc_omap16xx() (host->features & MMC_OMAP16XX)
76#define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
77#define mmc_omap1() (host->features & MMC_OMAP1_MASK)
78#define mmc_omap2() (!mmc_omap1())
79
80#define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
81#define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
82#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
83
84/*
85 * Command types
86 */
87#define OMAP_MMC_CMDTYPE_BC 0
88#define OMAP_MMC_CMDTYPE_BCR 1
89#define OMAP_MMC_CMDTYPE_AC 2
90#define OMAP_MMC_CMDTYPE_ADTC 3
91
92#define DRIVER_NAME "mmci-omap"
93
94/* Specifies how often in millisecs to poll for card status changes
95 * when the cover switch is open */
96#define OMAP_MMC_COVER_POLL_DELAY 500
97
98struct mmc_omap_host;
99
100struct mmc_omap_slot {
101 int id;
102 unsigned int vdd;
103 u16 saved_con;
104 u16 bus_mode;
105 u16 power_mode;
106 unsigned int fclk_freq;
107
108 struct tasklet_struct cover_tasklet;
109 struct timer_list cover_timer;
110 unsigned cover_open;
111
112 struct mmc_request *mrq;
113 struct mmc_omap_host *host;
114 struct mmc_host *mmc;
115 struct gpio_desc *vsd;
116 struct gpio_desc *vio;
117 struct gpio_desc *cover;
118 struct omap_mmc_slot_data *pdata;
119};
120
121struct mmc_omap_host {
122 int initialized;
123 struct mmc_request * mrq;
124 struct mmc_command * cmd;
125 struct mmc_data * data;
126 struct mmc_host * mmc;
127 struct device * dev;
128 unsigned char id; /* 16xx chips have 2 MMC blocks */
129 struct clk * iclk;
130 struct clk * fclk;
131 struct dma_chan *dma_rx;
132 u32 dma_rx_burst;
133 struct dma_chan *dma_tx;
134 u32 dma_tx_burst;
135 void __iomem *virt_base;
136 unsigned int phys_base;
137 int irq;
138 unsigned char bus_mode;
139 unsigned int reg_shift;
140 struct gpio_desc *slot_switch;
141
142 struct work_struct cmd_abort_work;
143 unsigned abort:1;
144 struct timer_list cmd_abort_timer;
145
146 struct work_struct slot_release_work;
147 struct mmc_omap_slot *next_slot;
148 struct work_struct send_stop_work;
149 struct mmc_data *stop_data;
150
151 unsigned int sg_len;
152 int sg_idx;
153 u16 * buffer;
154 u32 buffer_bytes_left;
155 u32 total_bytes_left;
156
157 unsigned features;
158 unsigned brs_received:1, dma_done:1;
159 unsigned dma_in_use:1;
160 spinlock_t dma_lock;
161
162 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
163 struct mmc_omap_slot *current_slot;
164 spinlock_t slot_lock;
165 wait_queue_head_t slot_wq;
166 int nr_slots;
167
168 struct timer_list clk_timer;
169 spinlock_t clk_lock; /* for changing enabled state */
170 unsigned int fclk_enabled:1;
171 struct workqueue_struct *mmc_omap_wq;
172
173 struct omap_mmc_platform_data *pdata;
174};
175
176
177static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
178{
179 unsigned long tick_ns;
180
181 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
182 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
183 ndelay(8 * tick_ns);
184 }
185}
186
187static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
188{
189 unsigned long flags;
190
191 spin_lock_irqsave(&host->clk_lock, flags);
192 if (host->fclk_enabled != enable) {
193 host->fclk_enabled = enable;
194 if (enable)
195 clk_enable(host->fclk);
196 else
197 clk_disable(host->fclk);
198 }
199 spin_unlock_irqrestore(&host->clk_lock, flags);
200}
201
202static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
203{
204 struct mmc_omap_host *host = slot->host;
205 unsigned long flags;
206
207 if (claimed)
208 goto no_claim;
209 spin_lock_irqsave(&host->slot_lock, flags);
210 while (host->mmc != NULL) {
211 spin_unlock_irqrestore(&host->slot_lock, flags);
212 wait_event(host->slot_wq, host->mmc == NULL);
213 spin_lock_irqsave(&host->slot_lock, flags);
214 }
215 host->mmc = slot->mmc;
216 spin_unlock_irqrestore(&host->slot_lock, flags);
217no_claim:
218 del_timer(&host->clk_timer);
219 if (host->current_slot != slot || !claimed)
220 mmc_omap_fclk_offdelay(host->current_slot);
221
222 if (host->current_slot != slot) {
223 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
224 if (host->slot_switch)
225 /*
226 * With two slots and a simple GPIO switch, setting
227 * the GPIO to 0 selects slot ID 0, setting it to 1
228 * selects slot ID 1.
229 */
230 gpiod_set_value(host->slot_switch, slot->id);
231 host->current_slot = slot;
232 }
233
234 if (claimed) {
235 mmc_omap_fclk_enable(host, 1);
236
237 /* Doing the dummy read here seems to work around some bug
238 * at least in OMAP24xx silicon where the command would not
239 * start after writing the CMD register. Sigh. */
240 OMAP_MMC_READ(host, CON);
241
242 OMAP_MMC_WRITE(host, CON, slot->saved_con);
243 } else
244 mmc_omap_fclk_enable(host, 0);
245}
246
247static void mmc_omap_start_request(struct mmc_omap_host *host,
248 struct mmc_request *req);
249
250static void mmc_omap_slot_release_work(struct work_struct *work)
251{
252 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
253 slot_release_work);
254 struct mmc_omap_slot *next_slot = host->next_slot;
255 struct mmc_request *rq;
256
257 host->next_slot = NULL;
258 mmc_omap_select_slot(next_slot, 1);
259
260 rq = next_slot->mrq;
261 next_slot->mrq = NULL;
262 mmc_omap_start_request(host, rq);
263}
264
265static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
266{
267 struct mmc_omap_host *host = slot->host;
268 unsigned long flags;
269 int i;
270
271 BUG_ON(slot == NULL || host->mmc == NULL);
272
273 if (clk_enabled)
274 /* Keeps clock running for at least 8 cycles on valid freq */
275 mod_timer(&host->clk_timer, jiffies + HZ/10);
276 else {
277 del_timer(&host->clk_timer);
278 mmc_omap_fclk_offdelay(slot);
279 mmc_omap_fclk_enable(host, 0);
280 }
281
282 spin_lock_irqsave(&host->slot_lock, flags);
283 /* Check for any pending requests */
284 for (i = 0; i < host->nr_slots; i++) {
285 struct mmc_omap_slot *new_slot;
286
287 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
288 continue;
289
290 BUG_ON(host->next_slot != NULL);
291 new_slot = host->slots[i];
292 /* The current slot should not have a request in queue */
293 BUG_ON(new_slot == host->current_slot);
294
295 host->next_slot = new_slot;
296 host->mmc = new_slot->mmc;
297 spin_unlock_irqrestore(&host->slot_lock, flags);
298 queue_work(host->mmc_omap_wq, &host->slot_release_work);
299 return;
300 }
301
302 host->mmc = NULL;
303 wake_up(&host->slot_wq);
304 spin_unlock_irqrestore(&host->slot_lock, flags);
305}
306
307static inline
308int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
309{
310 /* If we have a GPIO then use that */
311 if (slot->cover)
312 return gpiod_get_value(slot->cover);
313 if (slot->pdata->get_cover_state)
314 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
315 slot->id);
316 return 0;
317}
318
319static ssize_t
320mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
321 char *buf)
322{
323 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
324 struct mmc_omap_slot *slot = mmc_priv(mmc);
325
326 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
327 "closed");
328}
329
330static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
331
332static ssize_t
333mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
334 char *buf)
335{
336 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
337 struct mmc_omap_slot *slot = mmc_priv(mmc);
338
339 return sprintf(buf, "%s\n", slot->pdata->name);
340}
341
342static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
343
344static void
345mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
346{
347 u32 cmdreg;
348 u32 resptype;
349 u32 cmdtype;
350 u16 irq_mask;
351
352 host->cmd = cmd;
353
354 resptype = 0;
355 cmdtype = 0;
356
357 /* Our hardware needs to know exact type */
358 switch (mmc_resp_type(cmd)) {
359 case MMC_RSP_NONE:
360 break;
361 case MMC_RSP_R1:
362 case MMC_RSP_R1B:
363 /* resp 1, 1b, 6, 7 */
364 resptype = 1;
365 break;
366 case MMC_RSP_R2:
367 resptype = 2;
368 break;
369 case MMC_RSP_R3:
370 resptype = 3;
371 break;
372 default:
373 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
374 break;
375 }
376
377 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
378 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
379 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
380 cmdtype = OMAP_MMC_CMDTYPE_BC;
381 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
382 cmdtype = OMAP_MMC_CMDTYPE_BCR;
383 } else {
384 cmdtype = OMAP_MMC_CMDTYPE_AC;
385 }
386
387 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
388
389 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
390 cmdreg |= 1 << 6;
391
392 if (cmd->flags & MMC_RSP_BUSY)
393 cmdreg |= 1 << 11;
394
395 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
396 cmdreg |= 1 << 15;
397
398 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
399
400 OMAP_MMC_WRITE(host, CTO, 200);
401 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
402 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
403 irq_mask = OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
404 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
405 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
406 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
407 OMAP_MMC_STAT_END_OF_DATA;
408 if (cmd->opcode == MMC_ERASE)
409 irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT;
410 OMAP_MMC_WRITE(host, IE, irq_mask);
411 OMAP_MMC_WRITE(host, CMD, cmdreg);
412}
413
414static void
415mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
416 int abort)
417{
418 enum dma_data_direction dma_data_dir;
419 struct device *dev = mmc_dev(host->mmc);
420 struct dma_chan *c;
421
422 if (data->flags & MMC_DATA_WRITE) {
423 dma_data_dir = DMA_TO_DEVICE;
424 c = host->dma_tx;
425 } else {
426 dma_data_dir = DMA_FROM_DEVICE;
427 c = host->dma_rx;
428 }
429 if (c) {
430 if (data->error) {
431 dmaengine_terminate_all(c);
432 /* Claim nothing transferred on error... */
433 data->bytes_xfered = 0;
434 }
435 dev = c->device->dev;
436 }
437 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
438}
439
440static void mmc_omap_send_stop_work(struct work_struct *work)
441{
442 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
443 send_stop_work);
444 struct mmc_omap_slot *slot = host->current_slot;
445 struct mmc_data *data = host->stop_data;
446 unsigned long tick_ns;
447
448 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
449 ndelay(8*tick_ns);
450
451 mmc_omap_start_command(host, data->stop);
452}
453
454static void
455mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
456{
457 if (host->dma_in_use)
458 mmc_omap_release_dma(host, data, data->error);
459
460 host->data = NULL;
461 host->sg_len = 0;
462
463 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
464 * dozens of requests until the card finishes writing data.
465 * It'd be cheaper to just wait till an EOFB interrupt arrives...
466 */
467
468 if (!data->stop) {
469 struct mmc_host *mmc;
470
471 host->mrq = NULL;
472 mmc = host->mmc;
473 mmc_omap_release_slot(host->current_slot, 1);
474 mmc_request_done(mmc, data->mrq);
475 return;
476 }
477
478 host->stop_data = data;
479 queue_work(host->mmc_omap_wq, &host->send_stop_work);
480}
481
482static void
483mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
484{
485 struct mmc_omap_slot *slot = host->current_slot;
486 unsigned int restarts, passes, timeout;
487 u16 stat = 0;
488
489 /* Sending abort takes 80 clocks. Have some extra and round up */
490 timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq);
491 restarts = 0;
492 while (restarts < maxloops) {
493 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
494 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
495
496 passes = 0;
497 while (passes < timeout) {
498 stat = OMAP_MMC_READ(host, STAT);
499 if (stat & OMAP_MMC_STAT_END_OF_CMD)
500 goto out;
501 udelay(1);
502 passes++;
503 }
504
505 restarts++;
506 }
507out:
508 OMAP_MMC_WRITE(host, STAT, stat);
509}
510
511static void
512mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
513{
514 if (host->dma_in_use)
515 mmc_omap_release_dma(host, data, 1);
516
517 host->data = NULL;
518 host->sg_len = 0;
519
520 mmc_omap_send_abort(host, 10000);
521}
522
523static void
524mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
525{
526 unsigned long flags;
527 int done;
528
529 if (!host->dma_in_use) {
530 mmc_omap_xfer_done(host, data);
531 return;
532 }
533 done = 0;
534 spin_lock_irqsave(&host->dma_lock, flags);
535 if (host->dma_done)
536 done = 1;
537 else
538 host->brs_received = 1;
539 spin_unlock_irqrestore(&host->dma_lock, flags);
540 if (done)
541 mmc_omap_xfer_done(host, data);
542}
543
544static void
545mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
546{
547 unsigned long flags;
548 int done;
549
550 done = 0;
551 spin_lock_irqsave(&host->dma_lock, flags);
552 if (host->brs_received)
553 done = 1;
554 else
555 host->dma_done = 1;
556 spin_unlock_irqrestore(&host->dma_lock, flags);
557 if (done)
558 mmc_omap_xfer_done(host, data);
559}
560
561static void
562mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
563{
564 host->cmd = NULL;
565
566 del_timer(&host->cmd_abort_timer);
567
568 if (cmd->flags & MMC_RSP_PRESENT) {
569 if (cmd->flags & MMC_RSP_136) {
570 /* response type 2 */
571 cmd->resp[3] =
572 OMAP_MMC_READ(host, RSP0) |
573 (OMAP_MMC_READ(host, RSP1) << 16);
574 cmd->resp[2] =
575 OMAP_MMC_READ(host, RSP2) |
576 (OMAP_MMC_READ(host, RSP3) << 16);
577 cmd->resp[1] =
578 OMAP_MMC_READ(host, RSP4) |
579 (OMAP_MMC_READ(host, RSP5) << 16);
580 cmd->resp[0] =
581 OMAP_MMC_READ(host, RSP6) |
582 (OMAP_MMC_READ(host, RSP7) << 16);
583 } else {
584 /* response types 1, 1b, 3, 4, 5, 6 */
585 cmd->resp[0] =
586 OMAP_MMC_READ(host, RSP6) |
587 (OMAP_MMC_READ(host, RSP7) << 16);
588 }
589 }
590
591 if (host->data == NULL || cmd->error) {
592 struct mmc_host *mmc;
593
594 if (host->data != NULL)
595 mmc_omap_abort_xfer(host, host->data);
596 host->mrq = NULL;
597 mmc = host->mmc;
598 mmc_omap_release_slot(host->current_slot, 1);
599 mmc_request_done(mmc, cmd->mrq);
600 }
601}
602
603/*
604 * Abort stuck command. Can occur when card is removed while it is being
605 * read.
606 */
607static void mmc_omap_abort_command(struct work_struct *work)
608{
609 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
610 cmd_abort_work);
611 BUG_ON(!host->cmd);
612
613 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
614 host->cmd->opcode);
615
616 if (host->cmd->error == 0)
617 host->cmd->error = -ETIMEDOUT;
618
619 if (host->data == NULL) {
620 struct mmc_command *cmd;
621 struct mmc_host *mmc;
622
623 cmd = host->cmd;
624 host->cmd = NULL;
625 mmc_omap_send_abort(host, 10000);
626
627 host->mrq = NULL;
628 mmc = host->mmc;
629 mmc_omap_release_slot(host->current_slot, 1);
630 mmc_request_done(mmc, cmd->mrq);
631 } else
632 mmc_omap_cmd_done(host, host->cmd);
633
634 host->abort = 0;
635 enable_irq(host->irq);
636}
637
638static void
639mmc_omap_cmd_timer(struct timer_list *t)
640{
641 struct mmc_omap_host *host = from_timer(host, t, cmd_abort_timer);
642 unsigned long flags;
643
644 spin_lock_irqsave(&host->slot_lock, flags);
645 if (host->cmd != NULL && !host->abort) {
646 OMAP_MMC_WRITE(host, IE, 0);
647 disable_irq(host->irq);
648 host->abort = 1;
649 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
650 }
651 spin_unlock_irqrestore(&host->slot_lock, flags);
652}
653
654/* PIO only */
655static void
656mmc_omap_sg_to_buf(struct mmc_omap_host *host)
657{
658 struct scatterlist *sg;
659
660 sg = host->data->sg + host->sg_idx;
661 host->buffer_bytes_left = sg->length;
662 host->buffer = sg_virt(sg);
663 if (host->buffer_bytes_left > host->total_bytes_left)
664 host->buffer_bytes_left = host->total_bytes_left;
665}
666
667static void
668mmc_omap_clk_timer(struct timer_list *t)
669{
670 struct mmc_omap_host *host = from_timer(host, t, clk_timer);
671
672 mmc_omap_fclk_enable(host, 0);
673}
674
675/* PIO only */
676static void
677mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
678{
679 int n, nwords;
680
681 if (host->buffer_bytes_left == 0) {
682 host->sg_idx++;
683 BUG_ON(host->sg_idx == host->sg_len);
684 mmc_omap_sg_to_buf(host);
685 }
686 n = 64;
687 if (n > host->buffer_bytes_left)
688 n = host->buffer_bytes_left;
689
690 /* Round up to handle odd number of bytes to transfer */
691 nwords = DIV_ROUND_UP(n, 2);
692
693 host->buffer_bytes_left -= n;
694 host->total_bytes_left -= n;
695 host->data->bytes_xfered += n;
696
697 if (write) {
698 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
699 host->buffer, nwords);
700 } else {
701 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
702 host->buffer, nwords);
703 }
704
705 host->buffer += nwords;
706}
707
708#ifdef CONFIG_MMC_DEBUG
709static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
710{
711 static const char *mmc_omap_status_bits[] = {
712 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
713 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
714 };
715 int i;
716 char res[64], *buf = res;
717
718 buf += sprintf(buf, "MMC IRQ 0x%x:", status);
719
720 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
721 if (status & (1 << i))
722 buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
723 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
724}
725#else
726static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
727{
728}
729#endif
730
731
732static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
733{
734 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
735 u16 status;
736 int end_command;
737 int end_transfer;
738 int transfer_error, cmd_error;
739
740 if (host->cmd == NULL && host->data == NULL) {
741 status = OMAP_MMC_READ(host, STAT);
742 dev_info(mmc_dev(host->slots[0]->mmc),
743 "Spurious IRQ 0x%04x\n", status);
744 if (status != 0) {
745 OMAP_MMC_WRITE(host, STAT, status);
746 OMAP_MMC_WRITE(host, IE, 0);
747 }
748 return IRQ_HANDLED;
749 }
750
751 end_command = 0;
752 end_transfer = 0;
753 transfer_error = 0;
754 cmd_error = 0;
755
756 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
757 int cmd;
758
759 OMAP_MMC_WRITE(host, STAT, status);
760 if (host->cmd != NULL)
761 cmd = host->cmd->opcode;
762 else
763 cmd = -1;
764 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
765 status, cmd);
766 mmc_omap_report_irq(host, status);
767
768 if (host->total_bytes_left) {
769 if ((status & OMAP_MMC_STAT_A_FULL) ||
770 (status & OMAP_MMC_STAT_END_OF_DATA))
771 mmc_omap_xfer_data(host, 0);
772 if (status & OMAP_MMC_STAT_A_EMPTY)
773 mmc_omap_xfer_data(host, 1);
774 }
775
776 if (status & OMAP_MMC_STAT_END_OF_DATA)
777 end_transfer = 1;
778
779 if (status & OMAP_MMC_STAT_DATA_TOUT) {
780 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
781 cmd);
782 if (host->data) {
783 host->data->error = -ETIMEDOUT;
784 transfer_error = 1;
785 }
786 }
787
788 if (status & OMAP_MMC_STAT_DATA_CRC) {
789 if (host->data) {
790 host->data->error = -EILSEQ;
791 dev_dbg(mmc_dev(host->mmc),
792 "data CRC error, bytes left %d\n",
793 host->total_bytes_left);
794 transfer_error = 1;
795 } else {
796 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
797 }
798 }
799
800 if (status & OMAP_MMC_STAT_CMD_TOUT) {
801 /* Timeouts are routine with some commands */
802 if (host->cmd) {
803 struct mmc_omap_slot *slot =
804 host->current_slot;
805 if (slot == NULL ||
806 !mmc_omap_cover_is_open(slot))
807 dev_err(mmc_dev(host->mmc),
808 "command timeout (CMD%d)\n",
809 cmd);
810 host->cmd->error = -ETIMEDOUT;
811 end_command = 1;
812 cmd_error = 1;
813 }
814 }
815
816 if (status & OMAP_MMC_STAT_CMD_CRC) {
817 if (host->cmd) {
818 dev_err(mmc_dev(host->mmc),
819 "command CRC error (CMD%d, arg 0x%08x)\n",
820 cmd, host->cmd->arg);
821 host->cmd->error = -EILSEQ;
822 end_command = 1;
823 cmd_error = 1;
824 } else
825 dev_err(mmc_dev(host->mmc),
826 "command CRC error without cmd?\n");
827 }
828
829 if (status & OMAP_MMC_STAT_CARD_ERR) {
830 dev_dbg(mmc_dev(host->mmc),
831 "ignoring card status error (CMD%d)\n",
832 cmd);
833 end_command = 1;
834 }
835
836 /*
837 * NOTE: On 1610 the END_OF_CMD may come too early when
838 * starting a write
839 */
840 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
841 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
842 end_command = 1;
843 }
844 }
845
846 if (cmd_error && host->data) {
847 del_timer(&host->cmd_abort_timer);
848 host->abort = 1;
849 OMAP_MMC_WRITE(host, IE, 0);
850 disable_irq_nosync(host->irq);
851 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
852 return IRQ_HANDLED;
853 }
854
855 if (end_command && host->cmd)
856 mmc_omap_cmd_done(host, host->cmd);
857 if (host->data != NULL) {
858 if (transfer_error)
859 mmc_omap_xfer_done(host, host->data);
860 else if (end_transfer)
861 mmc_omap_end_of_data(host, host->data);
862 }
863
864 return IRQ_HANDLED;
865}
866
867void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
868{
869 int cover_open;
870 struct mmc_omap_host *host = dev_get_drvdata(dev);
871 struct mmc_omap_slot *slot = host->slots[num];
872
873 BUG_ON(num >= host->nr_slots);
874
875 /* Other subsystems can call in here before we're initialised. */
876 if (host->nr_slots == 0 || !host->slots[num])
877 return;
878
879 cover_open = mmc_omap_cover_is_open(slot);
880 if (cover_open != slot->cover_open) {
881 slot->cover_open = cover_open;
882 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
883 }
884
885 tasklet_hi_schedule(&slot->cover_tasklet);
886}
887
888static void mmc_omap_cover_timer(struct timer_list *t)
889{
890 struct mmc_omap_slot *slot = from_timer(slot, t, cover_timer);
891 tasklet_schedule(&slot->cover_tasklet);
892}
893
894static void mmc_omap_cover_handler(struct tasklet_struct *t)
895{
896 struct mmc_omap_slot *slot = from_tasklet(slot, t, cover_tasklet);
897 int cover_open = mmc_omap_cover_is_open(slot);
898
899 mmc_detect_change(slot->mmc, 0);
900 if (!cover_open)
901 return;
902
903 /*
904 * If no card is inserted, we postpone polling until
905 * the cover has been closed.
906 */
907 if (slot->mmc->card == NULL)
908 return;
909
910 mod_timer(&slot->cover_timer,
911 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
912}
913
914static void mmc_omap_dma_callback(void *priv)
915{
916 struct mmc_omap_host *host = priv;
917 struct mmc_data *data = host->data;
918
919 /* If we got to the end of DMA, assume everything went well */
920 data->bytes_xfered += data->blocks * data->blksz;
921
922 mmc_omap_dma_done(host, data);
923}
924
925static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
926{
927 u16 reg;
928
929 reg = OMAP_MMC_READ(host, SDIO);
930 reg &= ~(1 << 5);
931 OMAP_MMC_WRITE(host, SDIO, reg);
932 /* Set maximum timeout */
933 OMAP_MMC_WRITE(host, CTO, 0xfd);
934}
935
936static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
937{
938 unsigned int timeout, cycle_ns;
939 u16 reg;
940
941 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
942 timeout = req->data->timeout_ns / cycle_ns;
943 timeout += req->data->timeout_clks;
944
945 /* Check if we need to use timeout multiplier register */
946 reg = OMAP_MMC_READ(host, SDIO);
947 if (timeout > 0xffff) {
948 reg |= (1 << 5);
949 timeout /= 1024;
950 } else
951 reg &= ~(1 << 5);
952 OMAP_MMC_WRITE(host, SDIO, reg);
953 OMAP_MMC_WRITE(host, DTO, timeout);
954}
955
956static void
957mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
958{
959 struct mmc_data *data = req->data;
960 int i, use_dma = 1, block_size;
961 struct scatterlist *sg;
962 unsigned sg_len;
963
964 host->data = data;
965 if (data == NULL) {
966 OMAP_MMC_WRITE(host, BLEN, 0);
967 OMAP_MMC_WRITE(host, NBLK, 0);
968 OMAP_MMC_WRITE(host, BUF, 0);
969 host->dma_in_use = 0;
970 set_cmd_timeout(host, req);
971 return;
972 }
973
974 block_size = data->blksz;
975
976 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
977 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
978 set_data_timeout(host, req);
979
980 /* cope with calling layer confusion; it issues "single
981 * block" writes using multi-block scatterlists.
982 */
983 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
984
985 /* Only do DMA for entire blocks */
986 for_each_sg(data->sg, sg, sg_len, i) {
987 if ((sg->length % block_size) != 0) {
988 use_dma = 0;
989 break;
990 }
991 }
992
993 host->sg_idx = 0;
994 if (use_dma) {
995 enum dma_data_direction dma_data_dir;
996 struct dma_async_tx_descriptor *tx;
997 struct dma_chan *c;
998 u32 burst, *bp;
999 u16 buf;
1000
1001 /*
1002 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
1003 * and 24xx. Use 16 or 32 word frames when the
1004 * blocksize is at least that large. Blocksize is
1005 * usually 512 bytes; but not for some SD reads.
1006 */
1007 burst = mmc_omap15xx() ? 32 : 64;
1008 if (burst > data->blksz)
1009 burst = data->blksz;
1010
1011 burst >>= 1;
1012
1013 if (data->flags & MMC_DATA_WRITE) {
1014 c = host->dma_tx;
1015 bp = &host->dma_tx_burst;
1016 buf = 0x0f80 | (burst - 1) << 0;
1017 dma_data_dir = DMA_TO_DEVICE;
1018 } else {
1019 c = host->dma_rx;
1020 bp = &host->dma_rx_burst;
1021 buf = 0x800f | (burst - 1) << 8;
1022 dma_data_dir = DMA_FROM_DEVICE;
1023 }
1024
1025 if (!c)
1026 goto use_pio;
1027
1028 /* Only reconfigure if we have a different burst size */
1029 if (*bp != burst) {
1030 struct dma_slave_config cfg = {
1031 .src_addr = host->phys_base +
1032 OMAP_MMC_REG(host, DATA),
1033 .dst_addr = host->phys_base +
1034 OMAP_MMC_REG(host, DATA),
1035 .src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
1036 .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
1037 .src_maxburst = burst,
1038 .dst_maxburst = burst,
1039 };
1040
1041 if (dmaengine_slave_config(c, &cfg))
1042 goto use_pio;
1043
1044 *bp = burst;
1045 }
1046
1047 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1048 dma_data_dir);
1049 if (host->sg_len == 0)
1050 goto use_pio;
1051
1052 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1053 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1054 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1055 if (!tx)
1056 goto use_pio;
1057
1058 OMAP_MMC_WRITE(host, BUF, buf);
1059
1060 tx->callback = mmc_omap_dma_callback;
1061 tx->callback_param = host;
1062 dmaengine_submit(tx);
1063 host->brs_received = 0;
1064 host->dma_done = 0;
1065 host->dma_in_use = 1;
1066 return;
1067 }
1068 use_pio:
1069
1070 /* Revert to PIO? */
1071 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1072 host->total_bytes_left = data->blocks * block_size;
1073 host->sg_len = sg_len;
1074 mmc_omap_sg_to_buf(host);
1075 host->dma_in_use = 0;
1076}
1077
1078static void mmc_omap_start_request(struct mmc_omap_host *host,
1079 struct mmc_request *req)
1080{
1081 BUG_ON(host->mrq != NULL);
1082
1083 host->mrq = req;
1084
1085 /* only touch fifo AFTER the controller readies it */
1086 mmc_omap_prepare_data(host, req);
1087 mmc_omap_start_command(host, req->cmd);
1088 if (host->dma_in_use) {
1089 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1090 host->dma_tx : host->dma_rx;
1091
1092 dma_async_issue_pending(c);
1093 }
1094}
1095
1096static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1097{
1098 struct mmc_omap_slot *slot = mmc_priv(mmc);
1099 struct mmc_omap_host *host = slot->host;
1100 unsigned long flags;
1101
1102 spin_lock_irqsave(&host->slot_lock, flags);
1103 if (host->mmc != NULL) {
1104 BUG_ON(slot->mrq != NULL);
1105 slot->mrq = req;
1106 spin_unlock_irqrestore(&host->slot_lock, flags);
1107 return;
1108 } else
1109 host->mmc = mmc;
1110 spin_unlock_irqrestore(&host->slot_lock, flags);
1111 mmc_omap_select_slot(slot, 1);
1112 mmc_omap_start_request(host, req);
1113}
1114
1115static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1116 int vdd)
1117{
1118 struct mmc_omap_host *host;
1119
1120 host = slot->host;
1121
1122 if (slot->vsd)
1123 gpiod_set_value(slot->vsd, power_on);
1124 if (slot->vio)
1125 gpiod_set_value(slot->vio, power_on);
1126
1127 if (slot->pdata->set_power != NULL)
1128 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1129 vdd);
1130 if (mmc_omap2()) {
1131 u16 w;
1132
1133 if (power_on) {
1134 w = OMAP_MMC_READ(host, CON);
1135 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1136 } else {
1137 w = OMAP_MMC_READ(host, CON);
1138 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1139 }
1140 }
1141}
1142
1143static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1144{
1145 struct mmc_omap_slot *slot = mmc_priv(mmc);
1146 struct mmc_omap_host *host = slot->host;
1147 int func_clk_rate = clk_get_rate(host->fclk);
1148 int dsor;
1149
1150 if (ios->clock == 0)
1151 return 0;
1152
1153 dsor = func_clk_rate / ios->clock;
1154 if (dsor < 1)
1155 dsor = 1;
1156
1157 if (func_clk_rate / dsor > ios->clock)
1158 dsor++;
1159
1160 if (dsor > 250)
1161 dsor = 250;
1162
1163 slot->fclk_freq = func_clk_rate / dsor;
1164
1165 if (ios->bus_width == MMC_BUS_WIDTH_4)
1166 dsor |= 1 << 15;
1167
1168 return dsor;
1169}
1170
1171static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1172{
1173 struct mmc_omap_slot *slot = mmc_priv(mmc);
1174 struct mmc_omap_host *host = slot->host;
1175 int i, dsor;
1176 int clk_enabled, init_stream;
1177
1178 mmc_omap_select_slot(slot, 0);
1179
1180 dsor = mmc_omap_calc_divisor(mmc, ios);
1181
1182 if (ios->vdd != slot->vdd)
1183 slot->vdd = ios->vdd;
1184
1185 clk_enabled = 0;
1186 init_stream = 0;
1187 switch (ios->power_mode) {
1188 case MMC_POWER_OFF:
1189 mmc_omap_set_power(slot, 0, ios->vdd);
1190 break;
1191 case MMC_POWER_UP:
1192 /* Cannot touch dsor yet, just power up MMC */
1193 mmc_omap_set_power(slot, 1, ios->vdd);
1194 slot->power_mode = ios->power_mode;
1195 goto exit;
1196 case MMC_POWER_ON:
1197 mmc_omap_fclk_enable(host, 1);
1198 clk_enabled = 1;
1199 dsor |= 1 << 11;
1200 if (slot->power_mode != MMC_POWER_ON)
1201 init_stream = 1;
1202 break;
1203 }
1204 slot->power_mode = ios->power_mode;
1205
1206 if (slot->bus_mode != ios->bus_mode) {
1207 if (slot->pdata->set_bus_mode != NULL)
1208 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1209 ios->bus_mode);
1210 slot->bus_mode = ios->bus_mode;
1211 }
1212
1213 /* On insanely high arm_per frequencies something sometimes
1214 * goes somehow out of sync, and the POW bit is not being set,
1215 * which results in the while loop below getting stuck.
1216 * Writing to the CON register twice seems to do the trick. */
1217 for (i = 0; i < 2; i++)
1218 OMAP_MMC_WRITE(host, CON, dsor);
1219 slot->saved_con = dsor;
1220 if (init_stream) {
1221 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1222 int usecs = 250;
1223
1224 /* Send clock cycles, poll completion */
1225 OMAP_MMC_WRITE(host, IE, 0);
1226 OMAP_MMC_WRITE(host, STAT, 0xffff);
1227 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1228 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1229 udelay(1);
1230 usecs--;
1231 }
1232 OMAP_MMC_WRITE(host, STAT, 1);
1233 }
1234
1235exit:
1236 mmc_omap_release_slot(slot, clk_enabled);
1237}
1238
1239static const struct mmc_host_ops mmc_omap_ops = {
1240 .request = mmc_omap_request,
1241 .set_ios = mmc_omap_set_ios,
1242};
1243
1244static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1245{
1246 struct mmc_omap_slot *slot = NULL;
1247 struct mmc_host *mmc;
1248 int r;
1249
1250 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1251 if (mmc == NULL)
1252 return -ENOMEM;
1253
1254 slot = mmc_priv(mmc);
1255 slot->host = host;
1256 slot->mmc = mmc;
1257 slot->id = id;
1258 slot->power_mode = MMC_POWER_UNDEFINED;
1259 slot->pdata = &host->pdata->slots[id];
1260
1261 /* Check for some optional GPIO controls */
1262 slot->vsd = gpiod_get_index_optional(host->dev, "vsd",
1263 id, GPIOD_OUT_LOW);
1264 if (IS_ERR(slot->vsd))
1265 return dev_err_probe(host->dev, PTR_ERR(slot->vsd),
1266 "error looking up VSD GPIO\n");
1267 slot->vio = gpiod_get_index_optional(host->dev, "vio",
1268 id, GPIOD_OUT_LOW);
1269 if (IS_ERR(slot->vio))
1270 return dev_err_probe(host->dev, PTR_ERR(slot->vio),
1271 "error looking up VIO GPIO\n");
1272 slot->cover = gpiod_get_index_optional(host->dev, "cover",
1273 id, GPIOD_IN);
1274 if (IS_ERR(slot->cover))
1275 return dev_err_probe(host->dev, PTR_ERR(slot->cover),
1276 "error looking up cover switch GPIO\n");
1277
1278 host->slots[id] = slot;
1279
1280 mmc->caps = 0;
1281 if (host->pdata->slots[id].wires >= 4)
1282 mmc->caps |= MMC_CAP_4_BIT_DATA;
1283
1284 mmc->ops = &mmc_omap_ops;
1285 mmc->f_min = 400000;
1286
1287 if (mmc_omap2())
1288 mmc->f_max = 48000000;
1289 else
1290 mmc->f_max = 24000000;
1291 if (host->pdata->max_freq)
1292 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1293 mmc->ocr_avail = slot->pdata->ocr_mask;
1294
1295 /* Use scatterlist DMA to reduce per-transfer costs.
1296 * NOTE max_seg_size assumption that small blocks aren't
1297 * normally used (except e.g. for reading SD registers).
1298 */
1299 mmc->max_segs = 32;
1300 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1301 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1302 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1303 mmc->max_seg_size = mmc->max_req_size;
1304
1305 if (slot->pdata->get_cover_state != NULL) {
1306 timer_setup(&slot->cover_timer, mmc_omap_cover_timer, 0);
1307 tasklet_setup(&slot->cover_tasklet, mmc_omap_cover_handler);
1308 }
1309
1310 r = mmc_add_host(mmc);
1311 if (r < 0)
1312 goto err_remove_host;
1313
1314 if (slot->pdata->name != NULL) {
1315 r = device_create_file(&mmc->class_dev,
1316 &dev_attr_slot_name);
1317 if (r < 0)
1318 goto err_remove_host;
1319 }
1320
1321 if (slot->pdata->get_cover_state != NULL) {
1322 r = device_create_file(&mmc->class_dev,
1323 &dev_attr_cover_switch);
1324 if (r < 0)
1325 goto err_remove_slot_name;
1326 tasklet_schedule(&slot->cover_tasklet);
1327 }
1328
1329 return 0;
1330
1331err_remove_slot_name:
1332 if (slot->pdata->name != NULL)
1333 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1334err_remove_host:
1335 mmc_remove_host(mmc);
1336 mmc_free_host(mmc);
1337 return r;
1338}
1339
1340static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1341{
1342 struct mmc_host *mmc = slot->mmc;
1343
1344 if (slot->pdata->name != NULL)
1345 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1346 if (slot->pdata->get_cover_state != NULL)
1347 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1348
1349 tasklet_kill(&slot->cover_tasklet);
1350 del_timer_sync(&slot->cover_timer);
1351 flush_workqueue(slot->host->mmc_omap_wq);
1352
1353 mmc_remove_host(mmc);
1354 mmc_free_host(mmc);
1355}
1356
1357static int mmc_omap_probe(struct platform_device *pdev)
1358{
1359 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1360 struct mmc_omap_host *host = NULL;
1361 struct resource *res;
1362 int i, ret = 0;
1363 int irq;
1364
1365 if (pdata == NULL) {
1366 dev_err(&pdev->dev, "platform data missing\n");
1367 return -ENXIO;
1368 }
1369 if (pdata->nr_slots == 0) {
1370 dev_err(&pdev->dev, "no slots\n");
1371 return -EPROBE_DEFER;
1372 }
1373
1374 host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host),
1375 GFP_KERNEL);
1376 if (host == NULL)
1377 return -ENOMEM;
1378
1379 irq = platform_get_irq(pdev, 0);
1380 if (irq < 0)
1381 return irq;
1382
1383 host->virt_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1384 if (IS_ERR(host->virt_base))
1385 return PTR_ERR(host->virt_base);
1386
1387 host->slot_switch = gpiod_get_optional(host->dev, "switch",
1388 GPIOD_OUT_LOW);
1389 if (IS_ERR(host->slot_switch))
1390 return dev_err_probe(host->dev, PTR_ERR(host->slot_switch),
1391 "error looking up slot switch GPIO\n");
1392
1393
1394 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1395 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1396
1397 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1398 timer_setup(&host->cmd_abort_timer, mmc_omap_cmd_timer, 0);
1399
1400 spin_lock_init(&host->clk_lock);
1401 timer_setup(&host->clk_timer, mmc_omap_clk_timer, 0);
1402
1403 spin_lock_init(&host->dma_lock);
1404 spin_lock_init(&host->slot_lock);
1405 init_waitqueue_head(&host->slot_wq);
1406
1407 host->pdata = pdata;
1408 host->features = host->pdata->slots[0].features;
1409 host->dev = &pdev->dev;
1410 platform_set_drvdata(pdev, host);
1411
1412 host->id = pdev->id;
1413 host->irq = irq;
1414 host->phys_base = res->start;
1415 host->iclk = clk_get(&pdev->dev, "ick");
1416 if (IS_ERR(host->iclk))
1417 return PTR_ERR(host->iclk);
1418 clk_prepare_enable(host->iclk);
1419
1420 host->fclk = clk_get(&pdev->dev, "fck");
1421 if (IS_ERR(host->fclk)) {
1422 ret = PTR_ERR(host->fclk);
1423 goto err_free_iclk;
1424 }
1425
1426 ret = clk_prepare(host->fclk);
1427 if (ret)
1428 goto err_put_fclk;
1429
1430 host->dma_tx_burst = -1;
1431 host->dma_rx_burst = -1;
1432
1433 host->dma_tx = dma_request_chan(&pdev->dev, "tx");
1434 if (IS_ERR(host->dma_tx)) {
1435 ret = PTR_ERR(host->dma_tx);
1436 if (ret == -EPROBE_DEFER)
1437 goto err_free_fclk;
1438
1439 host->dma_tx = NULL;
1440 dev_warn(host->dev, "TX DMA channel request failed\n");
1441 }
1442
1443 host->dma_rx = dma_request_chan(&pdev->dev, "rx");
1444 if (IS_ERR(host->dma_rx)) {
1445 ret = PTR_ERR(host->dma_rx);
1446 if (ret == -EPROBE_DEFER) {
1447 if (host->dma_tx)
1448 dma_release_channel(host->dma_tx);
1449 goto err_free_fclk;
1450 }
1451
1452 host->dma_rx = NULL;
1453 dev_warn(host->dev, "RX DMA channel request failed\n");
1454 }
1455
1456 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1457 if (ret)
1458 goto err_free_dma;
1459
1460 if (pdata->init != NULL) {
1461 ret = pdata->init(&pdev->dev);
1462 if (ret < 0)
1463 goto err_free_irq;
1464 }
1465
1466 host->nr_slots = pdata->nr_slots;
1467 host->reg_shift = (mmc_omap7xx() ? 1 : 2);
1468
1469 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1470 if (!host->mmc_omap_wq) {
1471 ret = -ENOMEM;
1472 goto err_plat_cleanup;
1473 }
1474
1475 for (i = 0; i < pdata->nr_slots; i++) {
1476 ret = mmc_omap_new_slot(host, i);
1477 if (ret < 0) {
1478 while (--i >= 0)
1479 mmc_omap_remove_slot(host->slots[i]);
1480
1481 goto err_destroy_wq;
1482 }
1483 }
1484
1485 return 0;
1486
1487err_destroy_wq:
1488 destroy_workqueue(host->mmc_omap_wq);
1489err_plat_cleanup:
1490 if (pdata->cleanup)
1491 pdata->cleanup(&pdev->dev);
1492err_free_irq:
1493 free_irq(host->irq, host);
1494err_free_dma:
1495 if (host->dma_tx)
1496 dma_release_channel(host->dma_tx);
1497 if (host->dma_rx)
1498 dma_release_channel(host->dma_rx);
1499err_free_fclk:
1500 clk_unprepare(host->fclk);
1501err_put_fclk:
1502 clk_put(host->fclk);
1503err_free_iclk:
1504 clk_disable_unprepare(host->iclk);
1505 clk_put(host->iclk);
1506 return ret;
1507}
1508
1509static void mmc_omap_remove(struct platform_device *pdev)
1510{
1511 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1512 int i;
1513
1514 BUG_ON(host == NULL);
1515
1516 for (i = 0; i < host->nr_slots; i++)
1517 mmc_omap_remove_slot(host->slots[i]);
1518
1519 if (host->pdata->cleanup)
1520 host->pdata->cleanup(&pdev->dev);
1521
1522 mmc_omap_fclk_enable(host, 0);
1523 free_irq(host->irq, host);
1524 clk_unprepare(host->fclk);
1525 clk_put(host->fclk);
1526 clk_disable_unprepare(host->iclk);
1527 clk_put(host->iclk);
1528
1529 if (host->dma_tx)
1530 dma_release_channel(host->dma_tx);
1531 if (host->dma_rx)
1532 dma_release_channel(host->dma_rx);
1533
1534 destroy_workqueue(host->mmc_omap_wq);
1535}
1536
1537#if IS_BUILTIN(CONFIG_OF)
1538static const struct of_device_id mmc_omap_match[] = {
1539 { .compatible = "ti,omap2420-mmc", },
1540 { },
1541};
1542MODULE_DEVICE_TABLE(of, mmc_omap_match);
1543#endif
1544
1545static struct platform_driver mmc_omap_driver = {
1546 .probe = mmc_omap_probe,
1547 .remove_new = mmc_omap_remove,
1548 .driver = {
1549 .name = DRIVER_NAME,
1550 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1551 .of_match_table = of_match_ptr(mmc_omap_match),
1552 },
1553};
1554
1555module_platform_driver(mmc_omap_driver);
1556MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1557MODULE_LICENSE("GPL");
1558MODULE_ALIAS("platform:" DRIVER_NAME);
1559MODULE_AUTHOR("Juha Yrjölä");
1/*
2 * linux/drivers/mmc/host/omap.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/ioport.h>
18#include <linux/platform_device.h>
19#include <linux/interrupt.h>
20#include <linux/dma-mapping.h>
21#include <linux/delay.h>
22#include <linux/spinlock.h>
23#include <linux/timer.h>
24#include <linux/mmc/host.h>
25#include <linux/mmc/card.h>
26#include <linux/clk.h>
27#include <linux/scatterlist.h>
28#include <linux/i2c/tps65010.h>
29#include <linux/slab.h>
30
31#include <asm/io.h>
32#include <asm/irq.h>
33
34#include <plat/board.h>
35#include <plat/mmc.h>
36#include <mach/gpio.h>
37#include <plat/dma.h>
38#include <plat/mux.h>
39#include <plat/fpga.h>
40
41#define OMAP_MMC_REG_CMD 0x00
42#define OMAP_MMC_REG_ARGL 0x01
43#define OMAP_MMC_REG_ARGH 0x02
44#define OMAP_MMC_REG_CON 0x03
45#define OMAP_MMC_REG_STAT 0x04
46#define OMAP_MMC_REG_IE 0x05
47#define OMAP_MMC_REG_CTO 0x06
48#define OMAP_MMC_REG_DTO 0x07
49#define OMAP_MMC_REG_DATA 0x08
50#define OMAP_MMC_REG_BLEN 0x09
51#define OMAP_MMC_REG_NBLK 0x0a
52#define OMAP_MMC_REG_BUF 0x0b
53#define OMAP_MMC_REG_SDIO 0x0d
54#define OMAP_MMC_REG_REV 0x0f
55#define OMAP_MMC_REG_RSP0 0x10
56#define OMAP_MMC_REG_RSP1 0x11
57#define OMAP_MMC_REG_RSP2 0x12
58#define OMAP_MMC_REG_RSP3 0x13
59#define OMAP_MMC_REG_RSP4 0x14
60#define OMAP_MMC_REG_RSP5 0x15
61#define OMAP_MMC_REG_RSP6 0x16
62#define OMAP_MMC_REG_RSP7 0x17
63#define OMAP_MMC_REG_IOSR 0x18
64#define OMAP_MMC_REG_SYSC 0x19
65#define OMAP_MMC_REG_SYSS 0x1a
66
67#define OMAP_MMC_STAT_CARD_ERR (1 << 14)
68#define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
69#define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
70#define OMAP_MMC_STAT_A_EMPTY (1 << 11)
71#define OMAP_MMC_STAT_A_FULL (1 << 10)
72#define OMAP_MMC_STAT_CMD_CRC (1 << 8)
73#define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
74#define OMAP_MMC_STAT_DATA_CRC (1 << 6)
75#define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
76#define OMAP_MMC_STAT_END_BUSY (1 << 4)
77#define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
78#define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
79#define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
80
81#define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
82#define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
83#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
84
85/*
86 * Command types
87 */
88#define OMAP_MMC_CMDTYPE_BC 0
89#define OMAP_MMC_CMDTYPE_BCR 1
90#define OMAP_MMC_CMDTYPE_AC 2
91#define OMAP_MMC_CMDTYPE_ADTC 3
92
93
94#define DRIVER_NAME "mmci-omap"
95
96/* Specifies how often in millisecs to poll for card status changes
97 * when the cover switch is open */
98#define OMAP_MMC_COVER_POLL_DELAY 500
99
100struct mmc_omap_host;
101
102struct mmc_omap_slot {
103 int id;
104 unsigned int vdd;
105 u16 saved_con;
106 u16 bus_mode;
107 unsigned int fclk_freq;
108 unsigned powered:1;
109
110 struct tasklet_struct cover_tasklet;
111 struct timer_list cover_timer;
112 unsigned cover_open;
113
114 struct mmc_request *mrq;
115 struct mmc_omap_host *host;
116 struct mmc_host *mmc;
117 struct omap_mmc_slot_data *pdata;
118};
119
120struct mmc_omap_host {
121 int initialized;
122 int suspended;
123 struct mmc_request * mrq;
124 struct mmc_command * cmd;
125 struct mmc_data * data;
126 struct mmc_host * mmc;
127 struct device * dev;
128 unsigned char id; /* 16xx chips have 2 MMC blocks */
129 struct clk * iclk;
130 struct clk * fclk;
131 struct resource *mem_res;
132 void __iomem *virt_base;
133 unsigned int phys_base;
134 int irq;
135 unsigned char bus_mode;
136 unsigned char hw_bus_mode;
137 unsigned int reg_shift;
138
139 struct work_struct cmd_abort_work;
140 unsigned abort:1;
141 struct timer_list cmd_abort_timer;
142
143 struct work_struct slot_release_work;
144 struct mmc_omap_slot *next_slot;
145 struct work_struct send_stop_work;
146 struct mmc_data *stop_data;
147
148 unsigned int sg_len;
149 int sg_idx;
150 u16 * buffer;
151 u32 buffer_bytes_left;
152 u32 total_bytes_left;
153
154 unsigned use_dma:1;
155 unsigned brs_received:1, dma_done:1;
156 unsigned dma_is_read:1;
157 unsigned dma_in_use:1;
158 int dma_ch;
159 spinlock_t dma_lock;
160 struct timer_list dma_timer;
161 unsigned dma_len;
162
163 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
164 struct mmc_omap_slot *current_slot;
165 spinlock_t slot_lock;
166 wait_queue_head_t slot_wq;
167 int nr_slots;
168
169 struct timer_list clk_timer;
170 spinlock_t clk_lock; /* for changing enabled state */
171 unsigned int fclk_enabled:1;
172
173 struct omap_mmc_platform_data *pdata;
174};
175
176static struct workqueue_struct *mmc_omap_wq;
177
178static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
179{
180 unsigned long tick_ns;
181
182 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
183 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
184 ndelay(8 * tick_ns);
185 }
186}
187
188static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
189{
190 unsigned long flags;
191
192 spin_lock_irqsave(&host->clk_lock, flags);
193 if (host->fclk_enabled != enable) {
194 host->fclk_enabled = enable;
195 if (enable)
196 clk_enable(host->fclk);
197 else
198 clk_disable(host->fclk);
199 }
200 spin_unlock_irqrestore(&host->clk_lock, flags);
201}
202
203static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
204{
205 struct mmc_omap_host *host = slot->host;
206 unsigned long flags;
207
208 if (claimed)
209 goto no_claim;
210 spin_lock_irqsave(&host->slot_lock, flags);
211 while (host->mmc != NULL) {
212 spin_unlock_irqrestore(&host->slot_lock, flags);
213 wait_event(host->slot_wq, host->mmc == NULL);
214 spin_lock_irqsave(&host->slot_lock, flags);
215 }
216 host->mmc = slot->mmc;
217 spin_unlock_irqrestore(&host->slot_lock, flags);
218no_claim:
219 del_timer(&host->clk_timer);
220 if (host->current_slot != slot || !claimed)
221 mmc_omap_fclk_offdelay(host->current_slot);
222
223 if (host->current_slot != slot) {
224 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
225 if (host->pdata->switch_slot != NULL)
226 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
227 host->current_slot = slot;
228 }
229
230 if (claimed) {
231 mmc_omap_fclk_enable(host, 1);
232
233 /* Doing the dummy read here seems to work around some bug
234 * at least in OMAP24xx silicon where the command would not
235 * start after writing the CMD register. Sigh. */
236 OMAP_MMC_READ(host, CON);
237
238 OMAP_MMC_WRITE(host, CON, slot->saved_con);
239 } else
240 mmc_omap_fclk_enable(host, 0);
241}
242
243static void mmc_omap_start_request(struct mmc_omap_host *host,
244 struct mmc_request *req);
245
246static void mmc_omap_slot_release_work(struct work_struct *work)
247{
248 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
249 slot_release_work);
250 struct mmc_omap_slot *next_slot = host->next_slot;
251 struct mmc_request *rq;
252
253 host->next_slot = NULL;
254 mmc_omap_select_slot(next_slot, 1);
255
256 rq = next_slot->mrq;
257 next_slot->mrq = NULL;
258 mmc_omap_start_request(host, rq);
259}
260
261static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
262{
263 struct mmc_omap_host *host = slot->host;
264 unsigned long flags;
265 int i;
266
267 BUG_ON(slot == NULL || host->mmc == NULL);
268
269 if (clk_enabled)
270 /* Keeps clock running for at least 8 cycles on valid freq */
271 mod_timer(&host->clk_timer, jiffies + HZ/10);
272 else {
273 del_timer(&host->clk_timer);
274 mmc_omap_fclk_offdelay(slot);
275 mmc_omap_fclk_enable(host, 0);
276 }
277
278 spin_lock_irqsave(&host->slot_lock, flags);
279 /* Check for any pending requests */
280 for (i = 0; i < host->nr_slots; i++) {
281 struct mmc_omap_slot *new_slot;
282
283 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
284 continue;
285
286 BUG_ON(host->next_slot != NULL);
287 new_slot = host->slots[i];
288 /* The current slot should not have a request in queue */
289 BUG_ON(new_slot == host->current_slot);
290
291 host->next_slot = new_slot;
292 host->mmc = new_slot->mmc;
293 spin_unlock_irqrestore(&host->slot_lock, flags);
294 queue_work(mmc_omap_wq, &host->slot_release_work);
295 return;
296 }
297
298 host->mmc = NULL;
299 wake_up(&host->slot_wq);
300 spin_unlock_irqrestore(&host->slot_lock, flags);
301}
302
303static inline
304int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
305{
306 if (slot->pdata->get_cover_state)
307 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
308 slot->id);
309 return 0;
310}
311
312static ssize_t
313mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
314 char *buf)
315{
316 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
317 struct mmc_omap_slot *slot = mmc_priv(mmc);
318
319 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
320 "closed");
321}
322
323static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
324
325static ssize_t
326mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
327 char *buf)
328{
329 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
330 struct mmc_omap_slot *slot = mmc_priv(mmc);
331
332 return sprintf(buf, "%s\n", slot->pdata->name);
333}
334
335static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
336
337static void
338mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
339{
340 u32 cmdreg;
341 u32 resptype;
342 u32 cmdtype;
343
344 host->cmd = cmd;
345
346 resptype = 0;
347 cmdtype = 0;
348
349 /* Our hardware needs to know exact type */
350 switch (mmc_resp_type(cmd)) {
351 case MMC_RSP_NONE:
352 break;
353 case MMC_RSP_R1:
354 case MMC_RSP_R1B:
355 /* resp 1, 1b, 6, 7 */
356 resptype = 1;
357 break;
358 case MMC_RSP_R2:
359 resptype = 2;
360 break;
361 case MMC_RSP_R3:
362 resptype = 3;
363 break;
364 default:
365 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
366 break;
367 }
368
369 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
370 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
371 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
372 cmdtype = OMAP_MMC_CMDTYPE_BC;
373 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
374 cmdtype = OMAP_MMC_CMDTYPE_BCR;
375 } else {
376 cmdtype = OMAP_MMC_CMDTYPE_AC;
377 }
378
379 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
380
381 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
382 cmdreg |= 1 << 6;
383
384 if (cmd->flags & MMC_RSP_BUSY)
385 cmdreg |= 1 << 11;
386
387 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
388 cmdreg |= 1 << 15;
389
390 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
391
392 OMAP_MMC_WRITE(host, CTO, 200);
393 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
394 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
395 OMAP_MMC_WRITE(host, IE,
396 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
397 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
398 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
399 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
400 OMAP_MMC_STAT_END_OF_DATA);
401 OMAP_MMC_WRITE(host, CMD, cmdreg);
402}
403
404static void
405mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
406 int abort)
407{
408 enum dma_data_direction dma_data_dir;
409
410 BUG_ON(host->dma_ch < 0);
411 if (data->error)
412 omap_stop_dma(host->dma_ch);
413 /* Release DMA channel lazily */
414 mod_timer(&host->dma_timer, jiffies + HZ);
415 if (data->flags & MMC_DATA_WRITE)
416 dma_data_dir = DMA_TO_DEVICE;
417 else
418 dma_data_dir = DMA_FROM_DEVICE;
419 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
420 dma_data_dir);
421}
422
423static void mmc_omap_send_stop_work(struct work_struct *work)
424{
425 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
426 send_stop_work);
427 struct mmc_omap_slot *slot = host->current_slot;
428 struct mmc_data *data = host->stop_data;
429 unsigned long tick_ns;
430
431 tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
432 ndelay(8*tick_ns);
433
434 mmc_omap_start_command(host, data->stop);
435}
436
437static void
438mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
439{
440 if (host->dma_in_use)
441 mmc_omap_release_dma(host, data, data->error);
442
443 host->data = NULL;
444 host->sg_len = 0;
445
446 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
447 * dozens of requests until the card finishes writing data.
448 * It'd be cheaper to just wait till an EOFB interrupt arrives...
449 */
450
451 if (!data->stop) {
452 struct mmc_host *mmc;
453
454 host->mrq = NULL;
455 mmc = host->mmc;
456 mmc_omap_release_slot(host->current_slot, 1);
457 mmc_request_done(mmc, data->mrq);
458 return;
459 }
460
461 host->stop_data = data;
462 queue_work(mmc_omap_wq, &host->send_stop_work);
463}
464
465static void
466mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
467{
468 struct mmc_omap_slot *slot = host->current_slot;
469 unsigned int restarts, passes, timeout;
470 u16 stat = 0;
471
472 /* Sending abort takes 80 clocks. Have some extra and round up */
473 timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
474 restarts = 0;
475 while (restarts < maxloops) {
476 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
477 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
478
479 passes = 0;
480 while (passes < timeout) {
481 stat = OMAP_MMC_READ(host, STAT);
482 if (stat & OMAP_MMC_STAT_END_OF_CMD)
483 goto out;
484 udelay(1);
485 passes++;
486 }
487
488 restarts++;
489 }
490out:
491 OMAP_MMC_WRITE(host, STAT, stat);
492}
493
494static void
495mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
496{
497 if (host->dma_in_use)
498 mmc_omap_release_dma(host, data, 1);
499
500 host->data = NULL;
501 host->sg_len = 0;
502
503 mmc_omap_send_abort(host, 10000);
504}
505
506static void
507mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
508{
509 unsigned long flags;
510 int done;
511
512 if (!host->dma_in_use) {
513 mmc_omap_xfer_done(host, data);
514 return;
515 }
516 done = 0;
517 spin_lock_irqsave(&host->dma_lock, flags);
518 if (host->dma_done)
519 done = 1;
520 else
521 host->brs_received = 1;
522 spin_unlock_irqrestore(&host->dma_lock, flags);
523 if (done)
524 mmc_omap_xfer_done(host, data);
525}
526
527static void
528mmc_omap_dma_timer(unsigned long data)
529{
530 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
531
532 BUG_ON(host->dma_ch < 0);
533 omap_free_dma(host->dma_ch);
534 host->dma_ch = -1;
535}
536
537static void
538mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
539{
540 unsigned long flags;
541 int done;
542
543 done = 0;
544 spin_lock_irqsave(&host->dma_lock, flags);
545 if (host->brs_received)
546 done = 1;
547 else
548 host->dma_done = 1;
549 spin_unlock_irqrestore(&host->dma_lock, flags);
550 if (done)
551 mmc_omap_xfer_done(host, data);
552}
553
554static void
555mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
556{
557 host->cmd = NULL;
558
559 del_timer(&host->cmd_abort_timer);
560
561 if (cmd->flags & MMC_RSP_PRESENT) {
562 if (cmd->flags & MMC_RSP_136) {
563 /* response type 2 */
564 cmd->resp[3] =
565 OMAP_MMC_READ(host, RSP0) |
566 (OMAP_MMC_READ(host, RSP1) << 16);
567 cmd->resp[2] =
568 OMAP_MMC_READ(host, RSP2) |
569 (OMAP_MMC_READ(host, RSP3) << 16);
570 cmd->resp[1] =
571 OMAP_MMC_READ(host, RSP4) |
572 (OMAP_MMC_READ(host, RSP5) << 16);
573 cmd->resp[0] =
574 OMAP_MMC_READ(host, RSP6) |
575 (OMAP_MMC_READ(host, RSP7) << 16);
576 } else {
577 /* response types 1, 1b, 3, 4, 5, 6 */
578 cmd->resp[0] =
579 OMAP_MMC_READ(host, RSP6) |
580 (OMAP_MMC_READ(host, RSP7) << 16);
581 }
582 }
583
584 if (host->data == NULL || cmd->error) {
585 struct mmc_host *mmc;
586
587 if (host->data != NULL)
588 mmc_omap_abort_xfer(host, host->data);
589 host->mrq = NULL;
590 mmc = host->mmc;
591 mmc_omap_release_slot(host->current_slot, 1);
592 mmc_request_done(mmc, cmd->mrq);
593 }
594}
595
596/*
597 * Abort stuck command. Can occur when card is removed while it is being
598 * read.
599 */
600static void mmc_omap_abort_command(struct work_struct *work)
601{
602 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
603 cmd_abort_work);
604 BUG_ON(!host->cmd);
605
606 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
607 host->cmd->opcode);
608
609 if (host->cmd->error == 0)
610 host->cmd->error = -ETIMEDOUT;
611
612 if (host->data == NULL) {
613 struct mmc_command *cmd;
614 struct mmc_host *mmc;
615
616 cmd = host->cmd;
617 host->cmd = NULL;
618 mmc_omap_send_abort(host, 10000);
619
620 host->mrq = NULL;
621 mmc = host->mmc;
622 mmc_omap_release_slot(host->current_slot, 1);
623 mmc_request_done(mmc, cmd->mrq);
624 } else
625 mmc_omap_cmd_done(host, host->cmd);
626
627 host->abort = 0;
628 enable_irq(host->irq);
629}
630
631static void
632mmc_omap_cmd_timer(unsigned long data)
633{
634 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
635 unsigned long flags;
636
637 spin_lock_irqsave(&host->slot_lock, flags);
638 if (host->cmd != NULL && !host->abort) {
639 OMAP_MMC_WRITE(host, IE, 0);
640 disable_irq(host->irq);
641 host->abort = 1;
642 queue_work(mmc_omap_wq, &host->cmd_abort_work);
643 }
644 spin_unlock_irqrestore(&host->slot_lock, flags);
645}
646
647/* PIO only */
648static void
649mmc_omap_sg_to_buf(struct mmc_omap_host *host)
650{
651 struct scatterlist *sg;
652
653 sg = host->data->sg + host->sg_idx;
654 host->buffer_bytes_left = sg->length;
655 host->buffer = sg_virt(sg);
656 if (host->buffer_bytes_left > host->total_bytes_left)
657 host->buffer_bytes_left = host->total_bytes_left;
658}
659
660static void
661mmc_omap_clk_timer(unsigned long data)
662{
663 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
664
665 mmc_omap_fclk_enable(host, 0);
666}
667
668/* PIO only */
669static void
670mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
671{
672 int n;
673
674 if (host->buffer_bytes_left == 0) {
675 host->sg_idx++;
676 BUG_ON(host->sg_idx == host->sg_len);
677 mmc_omap_sg_to_buf(host);
678 }
679 n = 64;
680 if (n > host->buffer_bytes_left)
681 n = host->buffer_bytes_left;
682 host->buffer_bytes_left -= n;
683 host->total_bytes_left -= n;
684 host->data->bytes_xfered += n;
685
686 if (write) {
687 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA), host->buffer, n);
688 } else {
689 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA), host->buffer, n);
690 }
691}
692
693static inline void mmc_omap_report_irq(u16 status)
694{
695 static const char *mmc_omap_status_bits[] = {
696 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
697 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
698 };
699 int i, c = 0;
700
701 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
702 if (status & (1 << i)) {
703 if (c)
704 printk(" ");
705 printk("%s", mmc_omap_status_bits[i]);
706 c++;
707 }
708}
709
710static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
711{
712 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
713 u16 status;
714 int end_command;
715 int end_transfer;
716 int transfer_error, cmd_error;
717
718 if (host->cmd == NULL && host->data == NULL) {
719 status = OMAP_MMC_READ(host, STAT);
720 dev_info(mmc_dev(host->slots[0]->mmc),
721 "Spurious IRQ 0x%04x\n", status);
722 if (status != 0) {
723 OMAP_MMC_WRITE(host, STAT, status);
724 OMAP_MMC_WRITE(host, IE, 0);
725 }
726 return IRQ_HANDLED;
727 }
728
729 end_command = 0;
730 end_transfer = 0;
731 transfer_error = 0;
732 cmd_error = 0;
733
734 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
735 int cmd;
736
737 OMAP_MMC_WRITE(host, STAT, status);
738 if (host->cmd != NULL)
739 cmd = host->cmd->opcode;
740 else
741 cmd = -1;
742#ifdef CONFIG_MMC_DEBUG
743 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
744 status, cmd);
745 mmc_omap_report_irq(status);
746 printk("\n");
747#endif
748 if (host->total_bytes_left) {
749 if ((status & OMAP_MMC_STAT_A_FULL) ||
750 (status & OMAP_MMC_STAT_END_OF_DATA))
751 mmc_omap_xfer_data(host, 0);
752 if (status & OMAP_MMC_STAT_A_EMPTY)
753 mmc_omap_xfer_data(host, 1);
754 }
755
756 if (status & OMAP_MMC_STAT_END_OF_DATA)
757 end_transfer = 1;
758
759 if (status & OMAP_MMC_STAT_DATA_TOUT) {
760 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
761 cmd);
762 if (host->data) {
763 host->data->error = -ETIMEDOUT;
764 transfer_error = 1;
765 }
766 }
767
768 if (status & OMAP_MMC_STAT_DATA_CRC) {
769 if (host->data) {
770 host->data->error = -EILSEQ;
771 dev_dbg(mmc_dev(host->mmc),
772 "data CRC error, bytes left %d\n",
773 host->total_bytes_left);
774 transfer_error = 1;
775 } else {
776 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
777 }
778 }
779
780 if (status & OMAP_MMC_STAT_CMD_TOUT) {
781 /* Timeouts are routine with some commands */
782 if (host->cmd) {
783 struct mmc_omap_slot *slot =
784 host->current_slot;
785 if (slot == NULL ||
786 !mmc_omap_cover_is_open(slot))
787 dev_err(mmc_dev(host->mmc),
788 "command timeout (CMD%d)\n",
789 cmd);
790 host->cmd->error = -ETIMEDOUT;
791 end_command = 1;
792 cmd_error = 1;
793 }
794 }
795
796 if (status & OMAP_MMC_STAT_CMD_CRC) {
797 if (host->cmd) {
798 dev_err(mmc_dev(host->mmc),
799 "command CRC error (CMD%d, arg 0x%08x)\n",
800 cmd, host->cmd->arg);
801 host->cmd->error = -EILSEQ;
802 end_command = 1;
803 cmd_error = 1;
804 } else
805 dev_err(mmc_dev(host->mmc),
806 "command CRC error without cmd?\n");
807 }
808
809 if (status & OMAP_MMC_STAT_CARD_ERR) {
810 dev_dbg(mmc_dev(host->mmc),
811 "ignoring card status error (CMD%d)\n",
812 cmd);
813 end_command = 1;
814 }
815
816 /*
817 * NOTE: On 1610 the END_OF_CMD may come too early when
818 * starting a write
819 */
820 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
821 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
822 end_command = 1;
823 }
824 }
825
826 if (cmd_error && host->data) {
827 del_timer(&host->cmd_abort_timer);
828 host->abort = 1;
829 OMAP_MMC_WRITE(host, IE, 0);
830 disable_irq_nosync(host->irq);
831 queue_work(mmc_omap_wq, &host->cmd_abort_work);
832 return IRQ_HANDLED;
833 }
834
835 if (end_command && host->cmd)
836 mmc_omap_cmd_done(host, host->cmd);
837 if (host->data != NULL) {
838 if (transfer_error)
839 mmc_omap_xfer_done(host, host->data);
840 else if (end_transfer)
841 mmc_omap_end_of_data(host, host->data);
842 }
843
844 return IRQ_HANDLED;
845}
846
847void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
848{
849 int cover_open;
850 struct mmc_omap_host *host = dev_get_drvdata(dev);
851 struct mmc_omap_slot *slot = host->slots[num];
852
853 BUG_ON(num >= host->nr_slots);
854
855 /* Other subsystems can call in here before we're initialised. */
856 if (host->nr_slots == 0 || !host->slots[num])
857 return;
858
859 cover_open = mmc_omap_cover_is_open(slot);
860 if (cover_open != slot->cover_open) {
861 slot->cover_open = cover_open;
862 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
863 }
864
865 tasklet_hi_schedule(&slot->cover_tasklet);
866}
867
868static void mmc_omap_cover_timer(unsigned long arg)
869{
870 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
871 tasklet_schedule(&slot->cover_tasklet);
872}
873
874static void mmc_omap_cover_handler(unsigned long param)
875{
876 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
877 int cover_open = mmc_omap_cover_is_open(slot);
878
879 mmc_detect_change(slot->mmc, 0);
880 if (!cover_open)
881 return;
882
883 /*
884 * If no card is inserted, we postpone polling until
885 * the cover has been closed.
886 */
887 if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
888 return;
889
890 mod_timer(&slot->cover_timer,
891 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
892}
893
894/* Prepare to transfer the next segment of a scatterlist */
895static void
896mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
897{
898 int dma_ch = host->dma_ch;
899 unsigned long data_addr;
900 u16 buf, frame;
901 u32 count;
902 struct scatterlist *sg = &data->sg[host->sg_idx];
903 int src_port = 0;
904 int dst_port = 0;
905 int sync_dev = 0;
906
907 data_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
908 frame = data->blksz;
909 count = sg_dma_len(sg);
910
911 if ((data->blocks == 1) && (count > data->blksz))
912 count = frame;
913
914 host->dma_len = count;
915
916 /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
917 * Use 16 or 32 word frames when the blocksize is at least that large.
918 * Blocksize is usually 512 bytes; but not for some SD reads.
919 */
920 if (cpu_is_omap15xx() && frame > 32)
921 frame = 32;
922 else if (frame > 64)
923 frame = 64;
924 count /= frame;
925 frame >>= 1;
926
927 if (!(data->flags & MMC_DATA_WRITE)) {
928 buf = 0x800f | ((frame - 1) << 8);
929
930 if (cpu_class_is_omap1()) {
931 src_port = OMAP_DMA_PORT_TIPB;
932 dst_port = OMAP_DMA_PORT_EMIFF;
933 }
934 if (cpu_is_omap24xx())
935 sync_dev = OMAP24XX_DMA_MMC1_RX;
936
937 omap_set_dma_src_params(dma_ch, src_port,
938 OMAP_DMA_AMODE_CONSTANT,
939 data_addr, 0, 0);
940 omap_set_dma_dest_params(dma_ch, dst_port,
941 OMAP_DMA_AMODE_POST_INC,
942 sg_dma_address(sg), 0, 0);
943 omap_set_dma_dest_data_pack(dma_ch, 1);
944 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
945 } else {
946 buf = 0x0f80 | ((frame - 1) << 0);
947
948 if (cpu_class_is_omap1()) {
949 src_port = OMAP_DMA_PORT_EMIFF;
950 dst_port = OMAP_DMA_PORT_TIPB;
951 }
952 if (cpu_is_omap24xx())
953 sync_dev = OMAP24XX_DMA_MMC1_TX;
954
955 omap_set_dma_dest_params(dma_ch, dst_port,
956 OMAP_DMA_AMODE_CONSTANT,
957 data_addr, 0, 0);
958 omap_set_dma_src_params(dma_ch, src_port,
959 OMAP_DMA_AMODE_POST_INC,
960 sg_dma_address(sg), 0, 0);
961 omap_set_dma_src_data_pack(dma_ch, 1);
962 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
963 }
964
965 /* Max limit for DMA frame count is 0xffff */
966 BUG_ON(count > 0xffff);
967
968 OMAP_MMC_WRITE(host, BUF, buf);
969 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
970 frame, count, OMAP_DMA_SYNC_FRAME,
971 sync_dev, 0);
972}
973
974/* A scatterlist segment completed */
975static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
976{
977 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
978 struct mmc_data *mmcdat = host->data;
979
980 if (unlikely(host->dma_ch < 0)) {
981 dev_err(mmc_dev(host->mmc),
982 "DMA callback while DMA not enabled\n");
983 return;
984 }
985 /* FIXME: We really should do something to _handle_ the errors */
986 if (ch_status & OMAP1_DMA_TOUT_IRQ) {
987 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
988 return;
989 }
990 if (ch_status & OMAP_DMA_DROP_IRQ) {
991 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
992 return;
993 }
994 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
995 return;
996 }
997 mmcdat->bytes_xfered += host->dma_len;
998 host->sg_idx++;
999 if (host->sg_idx < host->sg_len) {
1000 mmc_omap_prepare_dma(host, host->data);
1001 omap_start_dma(host->dma_ch);
1002 } else
1003 mmc_omap_dma_done(host, host->data);
1004}
1005
1006static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
1007{
1008 const char *dma_dev_name;
1009 int sync_dev, dma_ch, is_read, r;
1010
1011 is_read = !(data->flags & MMC_DATA_WRITE);
1012 del_timer_sync(&host->dma_timer);
1013 if (host->dma_ch >= 0) {
1014 if (is_read == host->dma_is_read)
1015 return 0;
1016 omap_free_dma(host->dma_ch);
1017 host->dma_ch = -1;
1018 }
1019
1020 if (is_read) {
1021 if (host->id == 0) {
1022 sync_dev = OMAP_DMA_MMC_RX;
1023 dma_dev_name = "MMC1 read";
1024 } else {
1025 sync_dev = OMAP_DMA_MMC2_RX;
1026 dma_dev_name = "MMC2 read";
1027 }
1028 } else {
1029 if (host->id == 0) {
1030 sync_dev = OMAP_DMA_MMC_TX;
1031 dma_dev_name = "MMC1 write";
1032 } else {
1033 sync_dev = OMAP_DMA_MMC2_TX;
1034 dma_dev_name = "MMC2 write";
1035 }
1036 }
1037 r = omap_request_dma(sync_dev, dma_dev_name, mmc_omap_dma_cb,
1038 host, &dma_ch);
1039 if (r != 0) {
1040 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
1041 return r;
1042 }
1043 host->dma_ch = dma_ch;
1044 host->dma_is_read = is_read;
1045
1046 return 0;
1047}
1048
1049static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
1050{
1051 u16 reg;
1052
1053 reg = OMAP_MMC_READ(host, SDIO);
1054 reg &= ~(1 << 5);
1055 OMAP_MMC_WRITE(host, SDIO, reg);
1056 /* Set maximum timeout */
1057 OMAP_MMC_WRITE(host, CTO, 0xff);
1058}
1059
1060static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
1061{
1062 unsigned int timeout, cycle_ns;
1063 u16 reg;
1064
1065 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
1066 timeout = req->data->timeout_ns / cycle_ns;
1067 timeout += req->data->timeout_clks;
1068
1069 /* Check if we need to use timeout multiplier register */
1070 reg = OMAP_MMC_READ(host, SDIO);
1071 if (timeout > 0xffff) {
1072 reg |= (1 << 5);
1073 timeout /= 1024;
1074 } else
1075 reg &= ~(1 << 5);
1076 OMAP_MMC_WRITE(host, SDIO, reg);
1077 OMAP_MMC_WRITE(host, DTO, timeout);
1078}
1079
1080static void
1081mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
1082{
1083 struct mmc_data *data = req->data;
1084 int i, use_dma, block_size;
1085 unsigned sg_len;
1086
1087 host->data = data;
1088 if (data == NULL) {
1089 OMAP_MMC_WRITE(host, BLEN, 0);
1090 OMAP_MMC_WRITE(host, NBLK, 0);
1091 OMAP_MMC_WRITE(host, BUF, 0);
1092 host->dma_in_use = 0;
1093 set_cmd_timeout(host, req);
1094 return;
1095 }
1096
1097 block_size = data->blksz;
1098
1099 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
1100 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
1101 set_data_timeout(host, req);
1102
1103 /* cope with calling layer confusion; it issues "single
1104 * block" writes using multi-block scatterlists.
1105 */
1106 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
1107
1108 /* Only do DMA for entire blocks */
1109 use_dma = host->use_dma;
1110 if (use_dma) {
1111 for (i = 0; i < sg_len; i++) {
1112 if ((data->sg[i].length % block_size) != 0) {
1113 use_dma = 0;
1114 break;
1115 }
1116 }
1117 }
1118
1119 host->sg_idx = 0;
1120 if (use_dma) {
1121 if (mmc_omap_get_dma_channel(host, data) == 0) {
1122 enum dma_data_direction dma_data_dir;
1123
1124 if (data->flags & MMC_DATA_WRITE)
1125 dma_data_dir = DMA_TO_DEVICE;
1126 else
1127 dma_data_dir = DMA_FROM_DEVICE;
1128
1129 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1130 sg_len, dma_data_dir);
1131 host->total_bytes_left = 0;
1132 mmc_omap_prepare_dma(host, req->data);
1133 host->brs_received = 0;
1134 host->dma_done = 0;
1135 host->dma_in_use = 1;
1136 } else
1137 use_dma = 0;
1138 }
1139
1140 /* Revert to PIO? */
1141 if (!use_dma) {
1142 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1143 host->total_bytes_left = data->blocks * block_size;
1144 host->sg_len = sg_len;
1145 mmc_omap_sg_to_buf(host);
1146 host->dma_in_use = 0;
1147 }
1148}
1149
1150static void mmc_omap_start_request(struct mmc_omap_host *host,
1151 struct mmc_request *req)
1152{
1153 BUG_ON(host->mrq != NULL);
1154
1155 host->mrq = req;
1156
1157 /* only touch fifo AFTER the controller readies it */
1158 mmc_omap_prepare_data(host, req);
1159 mmc_omap_start_command(host, req->cmd);
1160 if (host->dma_in_use)
1161 omap_start_dma(host->dma_ch);
1162}
1163
1164static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1165{
1166 struct mmc_omap_slot *slot = mmc_priv(mmc);
1167 struct mmc_omap_host *host = slot->host;
1168 unsigned long flags;
1169
1170 spin_lock_irqsave(&host->slot_lock, flags);
1171 if (host->mmc != NULL) {
1172 BUG_ON(slot->mrq != NULL);
1173 slot->mrq = req;
1174 spin_unlock_irqrestore(&host->slot_lock, flags);
1175 return;
1176 } else
1177 host->mmc = mmc;
1178 spin_unlock_irqrestore(&host->slot_lock, flags);
1179 mmc_omap_select_slot(slot, 1);
1180 mmc_omap_start_request(host, req);
1181}
1182
1183static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1184 int vdd)
1185{
1186 struct mmc_omap_host *host;
1187
1188 host = slot->host;
1189
1190 if (slot->pdata->set_power != NULL)
1191 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1192 vdd);
1193
1194 if (cpu_is_omap24xx()) {
1195 u16 w;
1196
1197 if (power_on) {
1198 w = OMAP_MMC_READ(host, CON);
1199 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1200 } else {
1201 w = OMAP_MMC_READ(host, CON);
1202 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1203 }
1204 }
1205}
1206
1207static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1208{
1209 struct mmc_omap_slot *slot = mmc_priv(mmc);
1210 struct mmc_omap_host *host = slot->host;
1211 int func_clk_rate = clk_get_rate(host->fclk);
1212 int dsor;
1213
1214 if (ios->clock == 0)
1215 return 0;
1216
1217 dsor = func_clk_rate / ios->clock;
1218 if (dsor < 1)
1219 dsor = 1;
1220
1221 if (func_clk_rate / dsor > ios->clock)
1222 dsor++;
1223
1224 if (dsor > 250)
1225 dsor = 250;
1226
1227 slot->fclk_freq = func_clk_rate / dsor;
1228
1229 if (ios->bus_width == MMC_BUS_WIDTH_4)
1230 dsor |= 1 << 15;
1231
1232 return dsor;
1233}
1234
1235static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1236{
1237 struct mmc_omap_slot *slot = mmc_priv(mmc);
1238 struct mmc_omap_host *host = slot->host;
1239 int i, dsor;
1240 int clk_enabled;
1241
1242 mmc_omap_select_slot(slot, 0);
1243
1244 dsor = mmc_omap_calc_divisor(mmc, ios);
1245
1246 if (ios->vdd != slot->vdd)
1247 slot->vdd = ios->vdd;
1248
1249 clk_enabled = 0;
1250 switch (ios->power_mode) {
1251 case MMC_POWER_OFF:
1252 mmc_omap_set_power(slot, 0, ios->vdd);
1253 break;
1254 case MMC_POWER_UP:
1255 /* Cannot touch dsor yet, just power up MMC */
1256 mmc_omap_set_power(slot, 1, ios->vdd);
1257 goto exit;
1258 case MMC_POWER_ON:
1259 mmc_omap_fclk_enable(host, 1);
1260 clk_enabled = 1;
1261 dsor |= 1 << 11;
1262 break;
1263 }
1264
1265 if (slot->bus_mode != ios->bus_mode) {
1266 if (slot->pdata->set_bus_mode != NULL)
1267 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1268 ios->bus_mode);
1269 slot->bus_mode = ios->bus_mode;
1270 }
1271
1272 /* On insanely high arm_per frequencies something sometimes
1273 * goes somehow out of sync, and the POW bit is not being set,
1274 * which results in the while loop below getting stuck.
1275 * Writing to the CON register twice seems to do the trick. */
1276 for (i = 0; i < 2; i++)
1277 OMAP_MMC_WRITE(host, CON, dsor);
1278 slot->saved_con = dsor;
1279 if (ios->power_mode == MMC_POWER_ON) {
1280 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1281 int usecs = 250;
1282
1283 /* Send clock cycles, poll completion */
1284 OMAP_MMC_WRITE(host, IE, 0);
1285 OMAP_MMC_WRITE(host, STAT, 0xffff);
1286 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1287 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1288 udelay(1);
1289 usecs--;
1290 }
1291 OMAP_MMC_WRITE(host, STAT, 1);
1292 }
1293
1294exit:
1295 mmc_omap_release_slot(slot, clk_enabled);
1296}
1297
1298static const struct mmc_host_ops mmc_omap_ops = {
1299 .request = mmc_omap_request,
1300 .set_ios = mmc_omap_set_ios,
1301};
1302
1303static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1304{
1305 struct mmc_omap_slot *slot = NULL;
1306 struct mmc_host *mmc;
1307 int r;
1308
1309 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1310 if (mmc == NULL)
1311 return -ENOMEM;
1312
1313 slot = mmc_priv(mmc);
1314 slot->host = host;
1315 slot->mmc = mmc;
1316 slot->id = id;
1317 slot->pdata = &host->pdata->slots[id];
1318
1319 host->slots[id] = slot;
1320
1321 mmc->caps = 0;
1322 if (host->pdata->slots[id].wires >= 4)
1323 mmc->caps |= MMC_CAP_4_BIT_DATA;
1324
1325 mmc->ops = &mmc_omap_ops;
1326 mmc->f_min = 400000;
1327
1328 if (cpu_class_is_omap2())
1329 mmc->f_max = 48000000;
1330 else
1331 mmc->f_max = 24000000;
1332 if (host->pdata->max_freq)
1333 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1334 mmc->ocr_avail = slot->pdata->ocr_mask;
1335
1336 /* Use scatterlist DMA to reduce per-transfer costs.
1337 * NOTE max_seg_size assumption that small blocks aren't
1338 * normally used (except e.g. for reading SD registers).
1339 */
1340 mmc->max_segs = 32;
1341 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1342 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1343 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1344 mmc->max_seg_size = mmc->max_req_size;
1345
1346 r = mmc_add_host(mmc);
1347 if (r < 0)
1348 goto err_remove_host;
1349
1350 if (slot->pdata->name != NULL) {
1351 r = device_create_file(&mmc->class_dev,
1352 &dev_attr_slot_name);
1353 if (r < 0)
1354 goto err_remove_host;
1355 }
1356
1357 if (slot->pdata->get_cover_state != NULL) {
1358 r = device_create_file(&mmc->class_dev,
1359 &dev_attr_cover_switch);
1360 if (r < 0)
1361 goto err_remove_slot_name;
1362
1363 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1364 (unsigned long)slot);
1365 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1366 (unsigned long)slot);
1367 tasklet_schedule(&slot->cover_tasklet);
1368 }
1369
1370 return 0;
1371
1372err_remove_slot_name:
1373 if (slot->pdata->name != NULL)
1374 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1375err_remove_host:
1376 mmc_remove_host(mmc);
1377 mmc_free_host(mmc);
1378 return r;
1379}
1380
1381static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1382{
1383 struct mmc_host *mmc = slot->mmc;
1384
1385 if (slot->pdata->name != NULL)
1386 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1387 if (slot->pdata->get_cover_state != NULL)
1388 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1389
1390 tasklet_kill(&slot->cover_tasklet);
1391 del_timer_sync(&slot->cover_timer);
1392 flush_workqueue(mmc_omap_wq);
1393
1394 mmc_remove_host(mmc);
1395 mmc_free_host(mmc);
1396}
1397
1398static int __init mmc_omap_probe(struct platform_device *pdev)
1399{
1400 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1401 struct mmc_omap_host *host = NULL;
1402 struct resource *res;
1403 int i, ret = 0;
1404 int irq;
1405
1406 if (pdata == NULL) {
1407 dev_err(&pdev->dev, "platform data missing\n");
1408 return -ENXIO;
1409 }
1410 if (pdata->nr_slots == 0) {
1411 dev_err(&pdev->dev, "no slots\n");
1412 return -ENXIO;
1413 }
1414
1415 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1416 irq = platform_get_irq(pdev, 0);
1417 if (res == NULL || irq < 0)
1418 return -ENXIO;
1419
1420 res = request_mem_region(res->start, resource_size(res),
1421 pdev->name);
1422 if (res == NULL)
1423 return -EBUSY;
1424
1425 host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1426 if (host == NULL) {
1427 ret = -ENOMEM;
1428 goto err_free_mem_region;
1429 }
1430
1431 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1432 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1433
1434 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1435 setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1436 (unsigned long) host);
1437
1438 spin_lock_init(&host->clk_lock);
1439 setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1440
1441 spin_lock_init(&host->dma_lock);
1442 setup_timer(&host->dma_timer, mmc_omap_dma_timer, (unsigned long) host);
1443 spin_lock_init(&host->slot_lock);
1444 init_waitqueue_head(&host->slot_wq);
1445
1446 host->pdata = pdata;
1447 host->dev = &pdev->dev;
1448 platform_set_drvdata(pdev, host);
1449
1450 host->id = pdev->id;
1451 host->mem_res = res;
1452 host->irq = irq;
1453
1454 host->use_dma = 1;
1455 host->dev->dma_mask = &pdata->dma_mask;
1456 host->dma_ch = -1;
1457
1458 host->irq = irq;
1459 host->phys_base = host->mem_res->start;
1460 host->virt_base = ioremap(res->start, resource_size(res));
1461 if (!host->virt_base)
1462 goto err_ioremap;
1463
1464 host->iclk = clk_get(&pdev->dev, "ick");
1465 if (IS_ERR(host->iclk)) {
1466 ret = PTR_ERR(host->iclk);
1467 goto err_free_mmc_host;
1468 }
1469 clk_enable(host->iclk);
1470
1471 host->fclk = clk_get(&pdev->dev, "fck");
1472 if (IS_ERR(host->fclk)) {
1473 ret = PTR_ERR(host->fclk);
1474 goto err_free_iclk;
1475 }
1476
1477 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1478 if (ret)
1479 goto err_free_fclk;
1480
1481 if (pdata->init != NULL) {
1482 ret = pdata->init(&pdev->dev);
1483 if (ret < 0)
1484 goto err_free_irq;
1485 }
1486
1487 host->nr_slots = pdata->nr_slots;
1488 for (i = 0; i < pdata->nr_slots; i++) {
1489 ret = mmc_omap_new_slot(host, i);
1490 if (ret < 0) {
1491 while (--i >= 0)
1492 mmc_omap_remove_slot(host->slots[i]);
1493
1494 goto err_plat_cleanup;
1495 }
1496 }
1497
1498 host->reg_shift = (cpu_is_omap7xx() ? 1 : 2);
1499
1500 return 0;
1501
1502err_plat_cleanup:
1503 if (pdata->cleanup)
1504 pdata->cleanup(&pdev->dev);
1505err_free_irq:
1506 free_irq(host->irq, host);
1507err_free_fclk:
1508 clk_put(host->fclk);
1509err_free_iclk:
1510 clk_disable(host->iclk);
1511 clk_put(host->iclk);
1512err_free_mmc_host:
1513 iounmap(host->virt_base);
1514err_ioremap:
1515 kfree(host);
1516err_free_mem_region:
1517 release_mem_region(res->start, resource_size(res));
1518 return ret;
1519}
1520
1521static int mmc_omap_remove(struct platform_device *pdev)
1522{
1523 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1524 int i;
1525
1526 platform_set_drvdata(pdev, NULL);
1527
1528 BUG_ON(host == NULL);
1529
1530 for (i = 0; i < host->nr_slots; i++)
1531 mmc_omap_remove_slot(host->slots[i]);
1532
1533 if (host->pdata->cleanup)
1534 host->pdata->cleanup(&pdev->dev);
1535
1536 mmc_omap_fclk_enable(host, 0);
1537 free_irq(host->irq, host);
1538 clk_put(host->fclk);
1539 clk_disable(host->iclk);
1540 clk_put(host->iclk);
1541
1542 iounmap(host->virt_base);
1543 release_mem_region(pdev->resource[0].start,
1544 pdev->resource[0].end - pdev->resource[0].start + 1);
1545
1546 kfree(host);
1547
1548 return 0;
1549}
1550
1551#ifdef CONFIG_PM
1552static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1553{
1554 int i, ret = 0;
1555 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1556
1557 if (host == NULL || host->suspended)
1558 return 0;
1559
1560 for (i = 0; i < host->nr_slots; i++) {
1561 struct mmc_omap_slot *slot;
1562
1563 slot = host->slots[i];
1564 ret = mmc_suspend_host(slot->mmc);
1565 if (ret < 0) {
1566 while (--i >= 0) {
1567 slot = host->slots[i];
1568 mmc_resume_host(slot->mmc);
1569 }
1570 return ret;
1571 }
1572 }
1573 host->suspended = 1;
1574 return 0;
1575}
1576
1577static int mmc_omap_resume(struct platform_device *pdev)
1578{
1579 int i, ret = 0;
1580 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1581
1582 if (host == NULL || !host->suspended)
1583 return 0;
1584
1585 for (i = 0; i < host->nr_slots; i++) {
1586 struct mmc_omap_slot *slot;
1587 slot = host->slots[i];
1588 ret = mmc_resume_host(slot->mmc);
1589 if (ret < 0)
1590 return ret;
1591
1592 host->suspended = 0;
1593 }
1594 return 0;
1595}
1596#else
1597#define mmc_omap_suspend NULL
1598#define mmc_omap_resume NULL
1599#endif
1600
1601static struct platform_driver mmc_omap_driver = {
1602 .remove = mmc_omap_remove,
1603 .suspend = mmc_omap_suspend,
1604 .resume = mmc_omap_resume,
1605 .driver = {
1606 .name = DRIVER_NAME,
1607 .owner = THIS_MODULE,
1608 },
1609};
1610
1611static int __init mmc_omap_init(void)
1612{
1613 int ret;
1614
1615 mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1616 if (!mmc_omap_wq)
1617 return -ENOMEM;
1618
1619 ret = platform_driver_probe(&mmc_omap_driver, mmc_omap_probe);
1620 if (ret)
1621 destroy_workqueue(mmc_omap_wq);
1622 return ret;
1623}
1624
1625static void __exit mmc_omap_exit(void)
1626{
1627 platform_driver_unregister(&mmc_omap_driver);
1628 destroy_workqueue(mmc_omap_wq);
1629}
1630
1631module_init(mmc_omap_init);
1632module_exit(mmc_omap_exit);
1633
1634MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1635MODULE_LICENSE("GPL");
1636MODULE_ALIAS("platform:" DRIVER_NAME);
1637MODULE_AUTHOR("Juha Yrjölä");