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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2022-2023, NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <soc/tegra/mc.h>
7
8#include <dt-bindings/memory/tegra234-mc.h>
9#include <linux/interconnect.h>
10#include <linux/tegra-icc.h>
11
12#include <soc/tegra/bpmp.h>
13#include "mc.h"
14
15/*
16 * MC Client entries are sorted in the increasing order of the
17 * override and security register offsets.
18 */
19static const struct tegra_mc_client tegra234_mc_clients[] = {
20 {
21 .id = TEGRA234_MEMORY_CLIENT_HDAR,
22 .name = "hdar",
23 .bpmp_id = TEGRA_ICC_BPMP_HDA,
24 .type = TEGRA_ICC_ISO_AUDIO,
25 .sid = TEGRA234_SID_HDA,
26 .regs = {
27 .sid = {
28 .override = 0xa8,
29 .security = 0xac,
30 },
31 },
32 }, {
33 .id = TEGRA234_MEMORY_CLIENT_NVENCSRD,
34 .name = "nvencsrd",
35 .bpmp_id = TEGRA_ICC_BPMP_NVENC,
36 .type = TEGRA_ICC_NISO,
37 .sid = TEGRA234_SID_NVENC,
38 .regs = {
39 .sid = {
40 .override = 0xe0,
41 .security = 0xe4,
42 },
43 },
44 }, {
45 .id = TEGRA234_MEMORY_CLIENT_PCIE6AR,
46 .name = "pcie6ar",
47 .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
48 .type = TEGRA_ICC_NISO,
49 .sid = TEGRA234_SID_PCIE6,
50 .regs = {
51 .sid = {
52 .override = 0x140,
53 .security = 0x144,
54 },
55 },
56 }, {
57 .id = TEGRA234_MEMORY_CLIENT_PCIE6AW,
58 .name = "pcie6aw",
59 .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
60 .type = TEGRA_ICC_NISO,
61 .sid = TEGRA234_SID_PCIE6,
62 .regs = {
63 .sid = {
64 .override = 0x148,
65 .security = 0x14c,
66 },
67 },
68 }, {
69 .id = TEGRA234_MEMORY_CLIENT_PCIE7AR,
70 .name = "pcie7ar",
71 .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
72 .type = TEGRA_ICC_NISO,
73 .sid = TEGRA234_SID_PCIE7,
74 .regs = {
75 .sid = {
76 .override = 0x150,
77 .security = 0x154,
78 },
79 },
80 }, {
81 .id = TEGRA234_MEMORY_CLIENT_NVENCSWR,
82 .name = "nvencswr",
83 .bpmp_id = TEGRA_ICC_BPMP_NVENC,
84 .type = TEGRA_ICC_NISO,
85 .sid = TEGRA234_SID_NVENC,
86 .regs = {
87 .sid = {
88 .override = 0x158,
89 .security = 0x15c,
90 },
91 },
92 }, {
93 .id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
94 .name = "dla0rdb",
95 .sid = TEGRA234_SID_NVDLA0,
96 .regs = {
97 .sid = {
98 .override = 0x160,
99 .security = 0x164,
100 },
101 },
102 }, {
103 .id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
104 .name = "dla0rdb1",
105 .sid = TEGRA234_SID_NVDLA0,
106 .regs = {
107 .sid = {
108 .override = 0x168,
109 .security = 0x16c,
110 },
111 },
112 }, {
113 .id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
114 .name = "dla0wrb",
115 .sid = TEGRA234_SID_NVDLA0,
116 .regs = {
117 .sid = {
118 .override = 0x170,
119 .security = 0x174,
120 },
121 },
122 }, {
123 .id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
124 .name = "dla0rdb",
125 .sid = TEGRA234_SID_NVDLA1,
126 .regs = {
127 .sid = {
128 .override = 0x178,
129 .security = 0x17c,
130 },
131 },
132 }, {
133 .id = TEGRA234_MEMORY_CLIENT_PCIE7AW,
134 .name = "pcie7aw",
135 .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
136 .type = TEGRA_ICC_NISO,
137 .sid = TEGRA234_SID_PCIE7,
138 .regs = {
139 .sid = {
140 .override = 0x180,
141 .security = 0x184,
142 },
143 },
144 }, {
145 .id = TEGRA234_MEMORY_CLIENT_PCIE8AR,
146 .name = "pcie8ar",
147 .bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
148 .type = TEGRA_ICC_NISO,
149 .sid = TEGRA234_SID_PCIE8,
150 .regs = {
151 .sid = {
152 .override = 0x190,
153 .security = 0x194,
154 },
155 },
156 }, {
157 .id = TEGRA234_MEMORY_CLIENT_HDAW,
158 .name = "hdaw",
159 .bpmp_id = TEGRA_ICC_BPMP_HDA,
160 .type = TEGRA_ICC_ISO_AUDIO,
161 .sid = TEGRA234_SID_HDA,
162 .regs = {
163 .sid = {
164 .override = 0x1a8,
165 .security = 0x1ac,
166 },
167 },
168 }, {
169 .id = TEGRA234_MEMORY_CLIENT_PCIE8AW,
170 .name = "pcie8aw",
171 .bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
172 .type = TEGRA_ICC_NISO,
173 .sid = TEGRA234_SID_PCIE8,
174 .regs = {
175 .sid = {
176 .override = 0x1d8,
177 .security = 0x1dc,
178 },
179 },
180 }, {
181 .id = TEGRA234_MEMORY_CLIENT_PCIE9AR,
182 .name = "pcie9ar",
183 .bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
184 .type = TEGRA_ICC_NISO,
185 .sid = TEGRA234_SID_PCIE9,
186 .regs = {
187 .sid = {
188 .override = 0x1e0,
189 .security = 0x1e4,
190 },
191 },
192 }, {
193 .id = TEGRA234_MEMORY_CLIENT_PCIE6AR1,
194 .name = "pcie6ar1",
195 .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
196 .type = TEGRA_ICC_NISO,
197 .sid = TEGRA234_SID_PCIE6,
198 .regs = {
199 .sid = {
200 .override = 0x1e8,
201 .security = 0x1ec,
202 },
203 },
204 }, {
205 .id = TEGRA234_MEMORY_CLIENT_PCIE9AW,
206 .name = "pcie9aw",
207 .bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
208 .type = TEGRA_ICC_NISO,
209 .sid = TEGRA234_SID_PCIE9,
210 .regs = {
211 .sid = {
212 .override = 0x1f0,
213 .security = 0x1f4,
214 },
215 },
216 }, {
217 .id = TEGRA234_MEMORY_CLIENT_PCIE10AR,
218 .name = "pcie10ar",
219 .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
220 .type = TEGRA_ICC_NISO,
221 .sid = TEGRA234_SID_PCIE10,
222 .regs = {
223 .sid = {
224 .override = 0x1f8,
225 .security = 0x1fc,
226 },
227 },
228 }, {
229 .id = TEGRA234_MEMORY_CLIENT_PCIE10AW,
230 .name = "pcie10aw",
231 .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
232 .type = TEGRA_ICC_NISO,
233 .sid = TEGRA234_SID_PCIE10,
234 .regs = {
235 .sid = {
236 .override = 0x200,
237 .security = 0x204,
238 },
239 },
240 }, {
241 .id = TEGRA234_MEMORY_CLIENT_PCIE10AR1,
242 .name = "pcie10ar1",
243 .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
244 .type = TEGRA_ICC_NISO,
245 .sid = TEGRA234_SID_PCIE10,
246 .regs = {
247 .sid = {
248 .override = 0x240,
249 .security = 0x244,
250 },
251 },
252 }, {
253 .id = TEGRA234_MEMORY_CLIENT_PCIE7AR1,
254 .name = "pcie7ar1",
255 .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
256 .type = TEGRA_ICC_NISO,
257 .sid = TEGRA234_SID_PCIE7,
258 .regs = {
259 .sid = {
260 .override = 0x248,
261 .security = 0x24c,
262 },
263 },
264 }, {
265 .id = TEGRA234_MEMORY_CLIENT_MGBEARD,
266 .name = "mgbeard",
267 .bpmp_id = TEGRA_ICC_BPMP_EQOS,
268 .type = TEGRA_ICC_NISO,
269 .sid = TEGRA234_SID_MGBE,
270 .regs = {
271 .sid = {
272 .override = 0x2c0,
273 .security = 0x2c4,
274 },
275 },
276 }, {
277 .id = TEGRA234_MEMORY_CLIENT_MGBEBRD,
278 .name = "mgbebrd",
279 .bpmp_id = TEGRA_ICC_BPMP_EQOS,
280 .type = TEGRA_ICC_NISO,
281 .sid = TEGRA234_SID_MGBE_VF1,
282 .regs = {
283 .sid = {
284 .override = 0x2c8,
285 .security = 0x2cc,
286 },
287 },
288 }, {
289 .id = TEGRA234_MEMORY_CLIENT_MGBECRD,
290 .name = "mgbecrd",
291 .bpmp_id = TEGRA_ICC_BPMP_EQOS,
292 .type = TEGRA_ICC_NISO,
293 .sid = TEGRA234_SID_MGBE_VF2,
294 .regs = {
295 .sid = {
296 .override = 0x2d0,
297 .security = 0x2d4,
298 },
299 },
300 }, {
301 .id = TEGRA234_MEMORY_CLIENT_MGBEDRD,
302 .name = "mgbedrd",
303 .bpmp_id = TEGRA_ICC_BPMP_EQOS,
304 .type = TEGRA_ICC_NISO,
305 .sid = TEGRA234_SID_MGBE_VF3,
306 .regs = {
307 .sid = {
308 .override = 0x2d8,
309 .security = 0x2dc,
310 },
311 },
312 }, {
313 .id = TEGRA234_MEMORY_CLIENT_MGBEAWR,
314 .bpmp_id = TEGRA_ICC_BPMP_EQOS,
315 .type = TEGRA_ICC_NISO,
316 .name = "mgbeawr",
317 .sid = TEGRA234_SID_MGBE,
318 .regs = {
319 .sid = {
320 .override = 0x2e0,
321 .security = 0x2e4,
322 },
323 },
324 }, {
325 .id = TEGRA234_MEMORY_CLIENT_MGBEBWR,
326 .name = "mgbebwr",
327 .bpmp_id = TEGRA_ICC_BPMP_EQOS,
328 .type = TEGRA_ICC_NISO,
329 .sid = TEGRA234_SID_MGBE_VF1,
330 .regs = {
331 .sid = {
332 .override = 0x2f8,
333 .security = 0x2fc,
334 },
335 },
336 }, {
337 .id = TEGRA234_MEMORY_CLIENT_MGBECWR,
338 .name = "mgbecwr",
339 .bpmp_id = TEGRA_ICC_BPMP_EQOS,
340 .type = TEGRA_ICC_NISO,
341 .sid = TEGRA234_SID_MGBE_VF2,
342 .regs = {
343 .sid = {
344 .override = 0x308,
345 .security = 0x30c,
346 },
347 },
348 }, {
349 .id = TEGRA234_MEMORY_CLIENT_SDMMCRAB,
350 .name = "sdmmcrab",
351 .bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,
352 .type = TEGRA_ICC_NISO,
353 .sid = TEGRA234_SID_SDMMC4,
354 .regs = {
355 .sid = {
356 .override = 0x318,
357 .security = 0x31c,
358 },
359 },
360 }, {
361 .id = TEGRA234_MEMORY_CLIENT_MGBEDWR,
362 .name = "mgbedwr",
363 .bpmp_id = TEGRA_ICC_BPMP_EQOS,
364 .type = TEGRA_ICC_NISO,
365 .sid = TEGRA234_SID_MGBE_VF3,
366 .regs = {
367 .sid = {
368 .override = 0x328,
369 .security = 0x32c,
370 },
371 },
372 }, {
373 .id = TEGRA234_MEMORY_CLIENT_SDMMCWAB,
374 .name = "sdmmcwab",
375 .bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,
376 .type = TEGRA_ICC_NISO,
377 .sid = TEGRA234_SID_SDMMC4,
378 .regs = {
379 .sid = {
380 .override = 0x338,
381 .security = 0x33c,
382 },
383 },
384 }, {
385 .id = TEGRA234_MEMORY_CLIENT_VICSRD,
386 .name = "vicsrd",
387 .bpmp_id = TEGRA_ICC_BPMP_VIC,
388 .type = TEGRA_ICC_NISO,
389 .sid = TEGRA234_SID_VIC,
390 .regs = {
391 .sid = {
392 .override = 0x360,
393 .security = 0x364,
394 },
395 },
396 }, {
397 .id = TEGRA234_MEMORY_CLIENT_VICSWR,
398 .name = "vicswr",
399 .bpmp_id = TEGRA_ICC_BPMP_VIC,
400 .type = TEGRA_ICC_NISO,
401 .sid = TEGRA234_SID_VIC,
402 .regs = {
403 .sid = {
404 .override = 0x368,
405 .security = 0x36c,
406 },
407 },
408 }, {
409 .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
410 .name = "dla0rdb1",
411 .sid = TEGRA234_SID_NVDLA1,
412 .regs = {
413 .sid = {
414 .override = 0x370,
415 .security = 0x374,
416 },
417 },
418 }, {
419 .id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
420 .name = "dla0wrb",
421 .sid = TEGRA234_SID_NVDLA1,
422 .regs = {
423 .sid = {
424 .override = 0x378,
425 .security = 0x37c,
426 },
427 },
428 }, {
429 .id = TEGRA234_MEMORY_CLIENT_VI2W,
430 .name = "vi2w",
431 .bpmp_id = TEGRA_ICC_BPMP_VI2,
432 .type = TEGRA_ICC_ISO_VI,
433 .sid = TEGRA234_SID_ISO_VI2,
434 .regs = {
435 .sid = {
436 .override = 0x380,
437 .security = 0x384,
438 },
439 },
440 }, {
441 .id = TEGRA234_MEMORY_CLIENT_VI2FALR,
442 .name = "vi2falr",
443 .bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
444 .type = TEGRA_ICC_ISO_VIFAL,
445 .sid = TEGRA234_SID_ISO_VI2FALC,
446 .regs = {
447 .sid = {
448 .override = 0x388,
449 .security = 0x38c,
450 },
451 },
452 }, {
453 .id = TEGRA234_MEMORY_CLIENT_VIW,
454 .name = "viw",
455 .bpmp_id = TEGRA_ICC_BPMP_VI,
456 .type = TEGRA_ICC_ISO_VI,
457 .sid = TEGRA234_SID_ISO_VI,
458 .regs = {
459 .sid = {
460 .override = 0x390,
461 .security = 0x394,
462 },
463 },
464 }, {
465 .id = TEGRA234_MEMORY_CLIENT_NVDECSRD,
466 .name = "nvdecsrd",
467 .bpmp_id = TEGRA_ICC_BPMP_NVDEC,
468 .type = TEGRA_ICC_NISO,
469 .sid = TEGRA234_SID_NVDEC,
470 .regs = {
471 .sid = {
472 .override = 0x3c0,
473 .security = 0x3c4,
474 },
475 },
476 }, {
477 .id = TEGRA234_MEMORY_CLIENT_NVDECSWR,
478 .name = "nvdecswr",
479 .bpmp_id = TEGRA_ICC_BPMP_NVDEC,
480 .type = TEGRA_ICC_NISO,
481 .sid = TEGRA234_SID_NVDEC,
482 .regs = {
483 .sid = {
484 .override = 0x3c8,
485 .security = 0x3cc,
486 },
487 },
488 }, {
489 .id = TEGRA234_MEMORY_CLIENT_APER,
490 .name = "aper",
491 .bpmp_id = TEGRA_ICC_BPMP_APE,
492 .type = TEGRA_ICC_ISO_AUDIO,
493 .sid = TEGRA234_SID_APE,
494 .regs = {
495 .sid = {
496 .override = 0x3d0,
497 .security = 0x3d4,
498 },
499 },
500 }, {
501 .id = TEGRA234_MEMORY_CLIENT_APEW,
502 .name = "apew",
503 .bpmp_id = TEGRA_ICC_BPMP_APE,
504 .type = TEGRA_ICC_ISO_AUDIO,
505 .sid = TEGRA234_SID_APE,
506 .regs = {
507 .sid = {
508 .override = 0x3d8,
509 .security = 0x3dc,
510 },
511 },
512 }, {
513 .id = TEGRA234_MEMORY_CLIENT_VI2FALW,
514 .name = "vi2falw",
515 .bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
516 .type = TEGRA_ICC_ISO_VIFAL,
517 .sid = TEGRA234_SID_ISO_VI2FALC,
518 .regs = {
519 .sid = {
520 .override = 0x3e0,
521 .security = 0x3e4,
522 },
523 },
524 }, {
525 .id = TEGRA234_MEMORY_CLIENT_NVJPGSRD,
526 .name = "nvjpgsrd",
527 .bpmp_id = TEGRA_ICC_BPMP_NVJPG_0,
528 .type = TEGRA_ICC_NISO,
529 .sid = TEGRA234_SID_NVJPG,
530 .regs = {
531 .sid = {
532 .override = 0x3f0,
533 .security = 0x3f4,
534 },
535 },
536 }, {
537 .id = TEGRA234_MEMORY_CLIENT_NVJPGSWR,
538 .name = "nvjpgswr",
539 .bpmp_id = TEGRA_ICC_BPMP_NVJPG_0,
540 .type = TEGRA_ICC_NISO,
541 .sid = TEGRA234_SID_NVJPG,
542 .regs = {
543 .sid = {
544 .override = 0x3f8,
545 .security = 0x3fc,
546 },
547 },
548 }, {
549 .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
550 .name = "nvdisplayr",
551 .bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
552 .type = TEGRA_ICC_ISO_DISPLAY,
553 .sid = TEGRA234_SID_ISO_NVDISPLAY,
554 .regs = {
555 .sid = {
556 .override = 0x490,
557 .security = 0x494,
558 },
559 },
560 }, {
561 .id = TEGRA234_MEMORY_CLIENT_BPMPR,
562 .name = "bpmpr",
563 .sid = TEGRA234_SID_BPMP,
564 .regs = {
565 .sid = {
566 .override = 0x498,
567 .security = 0x49c,
568 },
569 },
570 }, {
571 .id = TEGRA234_MEMORY_CLIENT_BPMPW,
572 .name = "bpmpw",
573 .sid = TEGRA234_SID_BPMP,
574 .regs = {
575 .sid = {
576 .override = 0x4a0,
577 .security = 0x4a4,
578 },
579 },
580 }, {
581 .id = TEGRA234_MEMORY_CLIENT_BPMPDMAR,
582 .name = "bpmpdmar",
583 .sid = TEGRA234_SID_BPMP,
584 .regs = {
585 .sid = {
586 .override = 0x4a8,
587 .security = 0x4ac,
588 },
589 },
590 }, {
591 .id = TEGRA234_MEMORY_CLIENT_BPMPDMAW,
592 .name = "bpmpdmaw",
593 .sid = TEGRA234_SID_BPMP,
594 .regs = {
595 .sid = {
596 .override = 0x4b0,
597 .security = 0x4b4,
598 },
599 },
600 }, {
601 .id = TEGRA234_MEMORY_CLIENT_APEDMAR,
602 .name = "apedmar",
603 .bpmp_id = TEGRA_ICC_BPMP_APEDMA,
604 .type = TEGRA_ICC_ISO_AUDIO,
605 .sid = TEGRA234_SID_APE,
606 .regs = {
607 .sid = {
608 .override = 0x4f8,
609 .security = 0x4fc,
610 },
611 },
612 }, {
613 .id = TEGRA234_MEMORY_CLIENT_APEDMAW,
614 .name = "apedmaw",
615 .bpmp_id = TEGRA_ICC_BPMP_APEDMA,
616 .type = TEGRA_ICC_ISO_AUDIO,
617 .sid = TEGRA234_SID_APE,
618 .regs = {
619 .sid = {
620 .override = 0x500,
621 .security = 0x504,
622 },
623 },
624 }, {
625 .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
626 .name = "nvdisplayr1",
627 .bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
628 .type = TEGRA_ICC_ISO_DISPLAY,
629 .sid = TEGRA234_SID_ISO_NVDISPLAY,
630 .regs = {
631 .sid = {
632 .override = 0x508,
633 .security = 0x50c,
634 },
635 },
636 }, {
637 .id = TEGRA234_MEMORY_CLIENT_VIFALR,
638 .name = "vifalr",
639 .bpmp_id = TEGRA_ICC_BPMP_VIFAL,
640 .type = TEGRA_ICC_ISO_VIFAL,
641 .sid = TEGRA234_SID_ISO_VIFALC,
642 .regs = {
643 .sid = {
644 .override = 0x5e0,
645 .security = 0x5e4,
646 },
647 },
648 }, {
649 .id = TEGRA234_MEMORY_CLIENT_VIFALW,
650 .name = "vifalw",
651 .bpmp_id = TEGRA_ICC_BPMP_VIFAL,
652 .type = TEGRA_ICC_ISO_VIFAL,
653 .sid = TEGRA234_SID_ISO_VIFALC,
654 .regs = {
655 .sid = {
656 .override = 0x5e8,
657 .security = 0x5ec,
658 },
659 },
660 }, {
661 .id = TEGRA234_MEMORY_CLIENT_DLA0RDA,
662 .name = "dla0rda",
663 .sid = TEGRA234_SID_NVDLA0,
664 .regs = {
665 .sid = {
666 .override = 0x5f0,
667 .security = 0x5f4,
668 },
669 },
670 }, {
671 .id = TEGRA234_MEMORY_CLIENT_DLA0FALRDB,
672 .name = "dla0falrdb",
673 .sid = TEGRA234_SID_NVDLA0,
674 .regs = {
675 .sid = {
676 .override = 0x5f8,
677 .security = 0x5fc,
678 },
679 },
680 }, {
681 .id = TEGRA234_MEMORY_CLIENT_DLA0WRA,
682 .name = "dla0wra",
683 .sid = TEGRA234_SID_NVDLA0,
684 .regs = {
685 .sid = {
686 .override = 0x600,
687 .security = 0x604,
688 },
689 },
690 }, {
691 .id = TEGRA234_MEMORY_CLIENT_DLA0FALWRB,
692 .name = "dla0falwrb",
693 .sid = TEGRA234_SID_NVDLA0,
694 .regs = {
695 .sid = {
696 .override = 0x608,
697 .security = 0x60c,
698 },
699 },
700 }, {
701 .id = TEGRA234_MEMORY_CLIENT_DLA1RDA,
702 .name = "dla0rda",
703 .sid = TEGRA234_SID_NVDLA1,
704 .regs = {
705 .sid = {
706 .override = 0x610,
707 .security = 0x614,
708 },
709 },
710 }, {
711 .id = TEGRA234_MEMORY_CLIENT_DLA1FALRDB,
712 .name = "dla0falrdb",
713 .sid = TEGRA234_SID_NVDLA1,
714 .regs = {
715 .sid = {
716 .override = 0x618,
717 .security = 0x61c,
718 },
719 },
720 }, {
721 .id = TEGRA234_MEMORY_CLIENT_DLA1WRA,
722 .name = "dla0wra",
723 .sid = TEGRA234_SID_NVDLA1,
724 .regs = {
725 .sid = {
726 .override = 0x620,
727 .security = 0x624,
728 },
729 },
730 }, {
731 .id = TEGRA234_MEMORY_CLIENT_DLA1FALWRB,
732 .name = "dla0falwrb",
733 .sid = TEGRA234_SID_NVDLA1,
734 .regs = {
735 .sid = {
736 .override = 0x628,
737 .security = 0x62c,
738 },
739 },
740 }, {
741 .id = TEGRA234_MEMORY_CLIENT_RCER,
742 .name = "rcer",
743 .bpmp_id = TEGRA_ICC_BPMP_RCE,
744 .type = TEGRA_ICC_NISO,
745 .sid = TEGRA234_SID_RCE,
746 .regs = {
747 .sid = {
748 .override = 0x690,
749 .security = 0x694,
750 },
751 },
752 }, {
753 .id = TEGRA234_MEMORY_CLIENT_RCEW,
754 .name = "rcew",
755 .bpmp_id = TEGRA_ICC_BPMP_RCE,
756 .type = TEGRA_ICC_NISO,
757 .sid = TEGRA234_SID_RCE,
758 .regs = {
759 .sid = {
760 .override = 0x698,
761 .security = 0x69c,
762 },
763 },
764 }, {
765 .id = TEGRA234_MEMORY_CLIENT_PCIE0R,
766 .name = "pcie0r",
767 .bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
768 .type = TEGRA_ICC_NISO,
769 .sid = TEGRA234_SID_PCIE0,
770 .regs = {
771 .sid = {
772 .override = 0x6c0,
773 .security = 0x6c4,
774 },
775 },
776 }, {
777 .id = TEGRA234_MEMORY_CLIENT_PCIE0W,
778 .name = "pcie0w",
779 .bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
780 .type = TEGRA_ICC_NISO,
781 .sid = TEGRA234_SID_PCIE0,
782 .regs = {
783 .sid = {
784 .override = 0x6c8,
785 .security = 0x6cc,
786 },
787 },
788 }, {
789 .id = TEGRA234_MEMORY_CLIENT_PCIE1R,
790 .name = "pcie1r",
791 .bpmp_id = TEGRA_ICC_BPMP_PCIE_1,
792 .type = TEGRA_ICC_NISO,
793 .sid = TEGRA234_SID_PCIE1,
794 .regs = {
795 .sid = {
796 .override = 0x6d0,
797 .security = 0x6d4,
798 },
799 },
800 }, {
801 .id = TEGRA234_MEMORY_CLIENT_PCIE1W,
802 .name = "pcie1w",
803 .bpmp_id = TEGRA_ICC_BPMP_PCIE_1,
804 .type = TEGRA_ICC_NISO,
805 .sid = TEGRA234_SID_PCIE1,
806 .regs = {
807 .sid = {
808 .override = 0x6d8,
809 .security = 0x6dc,
810 },
811 },
812 }, {
813 .id = TEGRA234_MEMORY_CLIENT_PCIE2AR,
814 .name = "pcie2ar",
815 .bpmp_id = TEGRA_ICC_BPMP_PCIE_2,
816 .type = TEGRA_ICC_NISO,
817 .sid = TEGRA234_SID_PCIE2,
818 .regs = {
819 .sid = {
820 .override = 0x6e0,
821 .security = 0x6e4,
822 },
823 },
824 }, {
825 .id = TEGRA234_MEMORY_CLIENT_PCIE2AW,
826 .name = "pcie2aw",
827 .bpmp_id = TEGRA_ICC_BPMP_PCIE_2,
828 .type = TEGRA_ICC_NISO,
829 .sid = TEGRA234_SID_PCIE2,
830 .regs = {
831 .sid = {
832 .override = 0x6e8,
833 .security = 0x6ec,
834 },
835 },
836 }, {
837 .id = TEGRA234_MEMORY_CLIENT_PCIE3R,
838 .name = "pcie3r",
839 .bpmp_id = TEGRA_ICC_BPMP_PCIE_3,
840 .type = TEGRA_ICC_NISO,
841 .sid = TEGRA234_SID_PCIE3,
842 .regs = {
843 .sid = {
844 .override = 0x6f0,
845 .security = 0x6f4,
846 },
847 },
848 }, {
849 .id = TEGRA234_MEMORY_CLIENT_PCIE3W,
850 .name = "pcie3w",
851 .bpmp_id = TEGRA_ICC_BPMP_PCIE_3,
852 .type = TEGRA_ICC_NISO,
853 .sid = TEGRA234_SID_PCIE3,
854 .regs = {
855 .sid = {
856 .override = 0x6f8,
857 .security = 0x6fc,
858 },
859 },
860 }, {
861 .id = TEGRA234_MEMORY_CLIENT_PCIE4R,
862 .name = "pcie4r",
863 .bpmp_id = TEGRA_ICC_BPMP_PCIE_4,
864 .type = TEGRA_ICC_NISO,
865 .sid = TEGRA234_SID_PCIE4,
866 .regs = {
867 .sid = {
868 .override = 0x700,
869 .security = 0x704,
870 },
871 },
872 }, {
873 .id = TEGRA234_MEMORY_CLIENT_PCIE4W,
874 .name = "pcie4w",
875 .bpmp_id = TEGRA_ICC_BPMP_PCIE_4,
876 .type = TEGRA_ICC_NISO,
877 .sid = TEGRA234_SID_PCIE4,
878 .regs = {
879 .sid = {
880 .override = 0x708,
881 .security = 0x70c,
882 },
883 },
884 }, {
885 .id = TEGRA234_MEMORY_CLIENT_PCIE5R,
886 .name = "pcie5r",
887 .bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
888 .type = TEGRA_ICC_NISO,
889 .sid = TEGRA234_SID_PCIE5,
890 .regs = {
891 .sid = {
892 .override = 0x710,
893 .security = 0x714,
894 },
895 },
896 }, {
897 .id = TEGRA234_MEMORY_CLIENT_PCIE5W,
898 .name = "pcie5w",
899 .bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
900 .type = TEGRA_ICC_NISO,
901 .sid = TEGRA234_SID_PCIE5,
902 .regs = {
903 .sid = {
904 .override = 0x718,
905 .security = 0x71c,
906 },
907 },
908 }, {
909 .id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
910 .name = "dla0rda1",
911 .sid = TEGRA234_SID_NVDLA0,
912 .regs = {
913 .sid = {
914 .override = 0x748,
915 .security = 0x74c,
916 },
917 },
918 }, {
919 .id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
920 .name = "dla0rda1",
921 .sid = TEGRA234_SID_NVDLA1,
922 .regs = {
923 .sid = {
924 .override = 0x750,
925 .security = 0x754,
926 },
927 },
928 }, {
929 .id = TEGRA234_MEMORY_CLIENT_PCIE5R1,
930 .name = "pcie5r1",
931 .bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
932 .type = TEGRA_ICC_NISO,
933 .sid = TEGRA234_SID_PCIE5,
934 .regs = {
935 .sid = {
936 .override = 0x778,
937 .security = 0x77c,
938 },
939 },
940 }, {
941 .id = TEGRA234_MEMORY_CLIENT_NVJPG1SRD,
942 .name = "nvjpg1srd",
943 .bpmp_id = TEGRA_ICC_BPMP_NVJPG_1,
944 .type = TEGRA_ICC_NISO,
945 .sid = TEGRA234_SID_NVJPG1,
946 .regs = {
947 .sid = {
948 .override = 0x918,
949 .security = 0x91c,
950 },
951 },
952 }, {
953 .id = TEGRA234_MEMORY_CLIENT_NVJPG1SWR,
954 .name = "nvjpg1swr",
955 .bpmp_id = TEGRA_ICC_BPMP_NVJPG_1,
956 .type = TEGRA_ICC_NISO,
957 .sid = TEGRA234_SID_NVJPG1,
958 .regs = {
959 .sid = {
960 .override = 0x920,
961 .security = 0x924,
962 },
963 },
964 }, {
965 .id = TEGRA_ICC_MC_CPU_CLUSTER0,
966 .name = "sw_cluster0",
967 .bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER0,
968 .type = TEGRA_ICC_NISO,
969 }, {
970 .id = TEGRA_ICC_MC_CPU_CLUSTER1,
971 .name = "sw_cluster1",
972 .bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER1,
973 .type = TEGRA_ICC_NISO,
974 }, {
975 .id = TEGRA_ICC_MC_CPU_CLUSTER2,
976 .name = "sw_cluster2",
977 .bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER2,
978 .type = TEGRA_ICC_NISO,
979 }, {
980 .id = TEGRA234_MEMORY_CLIENT_NVL1R,
981 .name = "nvl1r",
982 .bpmp_id = TEGRA_ICC_BPMP_GPU,
983 .type = TEGRA_ICC_NISO,
984 }, {
985 .id = TEGRA234_MEMORY_CLIENT_NVL1W,
986 .name = "nvl1w",
987 .bpmp_id = TEGRA_ICC_BPMP_GPU,
988 .type = TEGRA_ICC_NISO,
989 },
990};
991
992/*
993 * tegra234_mc_icc_set() - Pass MC client info to the BPMP-FW
994 * @src: ICC node for Memory Controller's (MC) Client
995 * @dst: ICC node for Memory Controller (MC)
996 *
997 * Passing the current request info from the MC to the BPMP-FW where
998 * LA and PTSA registers are accessed and the final EMC freq is set
999 * based on client_id, type, latency and bandwidth.
1000 * icc_set_bw() makes set_bw calls for both MC and EMC providers in
1001 * sequence. Both the calls are protected by 'mutex_lock(&icc_lock)'.
1002 * So, the data passed won't be updated by concurrent set calls from
1003 * other clients.
1004 */
1005static int tegra234_mc_icc_set(struct icc_node *src, struct icc_node *dst)
1006{
1007 struct tegra_mc *mc = icc_provider_to_tegra_mc(dst->provider);
1008 struct mrq_bwmgr_int_request bwmgr_req = { 0 };
1009 struct mrq_bwmgr_int_response bwmgr_resp = { 0 };
1010 const struct tegra_mc_client *pclient = src->data;
1011 struct tegra_bpmp_message msg;
1012 int ret;
1013
1014 /*
1015 * Same Src and Dst node will happen during boot from icc_node_add().
1016 * This can be used to pre-initialize and set bandwidth for all clients
1017 * before their drivers are loaded. We are skipping this case as for us,
1018 * the pre-initialization already happened in Bootloader(MB2) and BPMP-FW.
1019 */
1020 if (src->id == dst->id)
1021 return 0;
1022
1023 if (!mc->bwmgr_mrq_supported)
1024 return 0;
1025
1026 if (!mc->bpmp) {
1027 dev_err(mc->dev, "BPMP reference NULL\n");
1028 return -ENOENT;
1029 }
1030
1031 if (pclient->type == TEGRA_ICC_NISO)
1032 bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw;
1033 else
1034 bwmgr_req.bwmgr_calc_set_req.iso_bw = src->avg_bw;
1035
1036 bwmgr_req.bwmgr_calc_set_req.client_id = pclient->bpmp_id;
1037
1038 bwmgr_req.cmd = CMD_BWMGR_INT_CALC_AND_SET;
1039 bwmgr_req.bwmgr_calc_set_req.mc_floor = src->peak_bw;
1040 bwmgr_req.bwmgr_calc_set_req.floor_unit = BWMGR_INT_UNIT_KBPS;
1041
1042 memset(&msg, 0, sizeof(msg));
1043 msg.mrq = MRQ_BWMGR_INT;
1044 msg.tx.data = &bwmgr_req;
1045 msg.tx.size = sizeof(bwmgr_req);
1046 msg.rx.data = &bwmgr_resp;
1047 msg.rx.size = sizeof(bwmgr_resp);
1048
1049 if (pclient->bpmp_id >= TEGRA_ICC_BPMP_CPU_CLUSTER0 &&
1050 pclient->bpmp_id <= TEGRA_ICC_BPMP_CPU_CLUSTER2)
1051 msg.flags = TEGRA_BPMP_MESSAGE_RESET;
1052
1053 ret = tegra_bpmp_transfer(mc->bpmp, &msg);
1054 if (ret < 0) {
1055 dev_err(mc->dev, "BPMP transfer failed: %d\n", ret);
1056 goto error;
1057 }
1058 if (msg.rx.ret < 0) {
1059 pr_err("failed to set bandwidth for %u: %d\n",
1060 bwmgr_req.bwmgr_calc_set_req.client_id, msg.rx.ret);
1061 ret = -EINVAL;
1062 }
1063
1064error:
1065 return ret;
1066}
1067
1068static int tegra234_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
1069 u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
1070{
1071 struct icc_provider *p = node->provider;
1072 struct tegra_mc *mc = icc_provider_to_tegra_mc(p);
1073
1074 if (!mc->bwmgr_mrq_supported)
1075 return 0;
1076
1077 if (node->id == TEGRA_ICC_MC_CPU_CLUSTER0 ||
1078 node->id == TEGRA_ICC_MC_CPU_CLUSTER1 ||
1079 node->id == TEGRA_ICC_MC_CPU_CLUSTER2) {
1080 if (mc)
1081 peak_bw = peak_bw * mc->num_channels;
1082 }
1083
1084 *agg_avg += avg_bw;
1085 *agg_peak = max(*agg_peak, peak_bw);
1086
1087 return 0;
1088}
1089
1090static int tegra234_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak)
1091{
1092 *avg = 0;
1093 *peak = 0;
1094
1095 return 0;
1096}
1097
1098static const struct tegra_mc_icc_ops tegra234_mc_icc_ops = {
1099 .xlate = tegra_mc_icc_xlate,
1100 .aggregate = tegra234_mc_icc_aggregate,
1101 .get_bw = tegra234_mc_icc_get_init_bw,
1102 .set = tegra234_mc_icc_set,
1103};
1104
1105const struct tegra_mc_soc tegra234_mc_soc = {
1106 .num_clients = ARRAY_SIZE(tegra234_mc_clients),
1107 .clients = tegra234_mc_clients,
1108 .num_address_bits = 40,
1109 .num_channels = 16,
1110 .client_id_mask = 0x1ff,
1111 .intmask = MC_INT_DECERR_ROUTE_SANITY |
1112 MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
1113 MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1114 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1115 .has_addr_hi_reg = true,
1116 .ops = &tegra186_mc_ops,
1117 .icc_ops = &tegra234_mc_icc_ops,
1118 .ch_intmask = 0x0000ff00,
1119 .global_intstatus_channel_shift = 8,
1120 /*
1121 * Additionally, there are lite carveouts but those are not currently
1122 * supported.
1123 */
1124 .num_carveouts = 32,
1125};