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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/firmware.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28
29#include "amdgpu.h"
30#include "amdgpu_ucode.h"
31#include "amdgpu_trace.h"
32
33#include "gc/gc_10_1_0_offset.h"
34#include "gc/gc_10_1_0_sh_mask.h"
35#include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36#include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37
38#include "soc15_common.h"
39#include "soc15.h"
40#include "navi10_sdma_pkt_open.h"
41#include "nbio_v2_3.h"
42#include "sdma_common.h"
43#include "sdma_v5_0.h"
44
45MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
46MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
47
48MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
49MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
50
51MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
52MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
53
54MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin");
55MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin");
56
57#define SDMA1_REG_OFFSET 0x600
58#define SDMA0_HYP_DEC_REG_START 0x5880
59#define SDMA0_HYP_DEC_REG_END 0x5893
60#define SDMA1_HYP_DEC_REG_OFFSET 0x20
61
62static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
63static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
64static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
65static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
66
67static const struct soc15_reg_golden golden_settings_sdma_5[] = {
68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
89 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
90 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
91 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
92};
93
94static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
115};
116
117static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
120};
121
122static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
125};
126
127static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
134};
135
136static const struct soc15_reg_golden golden_settings_sdma_cyan_skillfish[] = {
137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00),
151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00)
165};
166
167static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
168{
169 u32 base;
170
171 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
172 internal_offset <= SDMA0_HYP_DEC_REG_END) {
173 base = adev->reg_offset[GC_HWIP][0][1];
174 if (instance == 1)
175 internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
176 } else {
177 base = adev->reg_offset[GC_HWIP][0][0];
178 if (instance == 1)
179 internal_offset += SDMA1_REG_OFFSET;
180 }
181
182 return base + internal_offset;
183}
184
185static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
186{
187 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
188 case IP_VERSION(5, 0, 0):
189 soc15_program_register_sequence(adev,
190 golden_settings_sdma_5,
191 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
192 soc15_program_register_sequence(adev,
193 golden_settings_sdma_nv10,
194 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
195 break;
196 case IP_VERSION(5, 0, 2):
197 soc15_program_register_sequence(adev,
198 golden_settings_sdma_5,
199 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
200 soc15_program_register_sequence(adev,
201 golden_settings_sdma_nv14,
202 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
203 break;
204 case IP_VERSION(5, 0, 5):
205 if (amdgpu_sriov_vf(adev))
206 soc15_program_register_sequence(adev,
207 golden_settings_sdma_5_sriov,
208 (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
209 else
210 soc15_program_register_sequence(adev,
211 golden_settings_sdma_5,
212 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
213 soc15_program_register_sequence(adev,
214 golden_settings_sdma_nv12,
215 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
216 break;
217 case IP_VERSION(5, 0, 1):
218 soc15_program_register_sequence(adev,
219 golden_settings_sdma_cyan_skillfish,
220 (const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish));
221 break;
222 default:
223 break;
224 }
225}
226
227/**
228 * sdma_v5_0_init_microcode - load ucode images from disk
229 *
230 * @adev: amdgpu_device pointer
231 *
232 * Use the firmware interface to load the ucode images into
233 * the driver (not loaded into hw).
234 * Returns 0 on success, error on failure.
235 */
236
237// emulation only, won't work on real chip
238// navi10 real chip need to use PSP to load firmware
239static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
240{
241 int ret, i;
242
243 for (i = 0; i < adev->sdma.num_instances; i++) {
244 ret = amdgpu_sdma_init_microcode(adev, i, false);
245 if (ret)
246 return ret;
247 }
248
249 return ret;
250}
251
252static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
253{
254 unsigned ret;
255
256 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
257 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
258 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
259 amdgpu_ring_write(ring, 1);
260 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
261 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
262
263 return ret;
264}
265
266static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
267 unsigned offset)
268{
269 unsigned cur;
270
271 BUG_ON(offset > ring->buf_mask);
272 BUG_ON(ring->ring[offset] != 0x55aa55aa);
273
274 cur = (ring->wptr - 1) & ring->buf_mask;
275 if (cur > offset)
276 ring->ring[offset] = cur - offset;
277 else
278 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
279}
280
281/**
282 * sdma_v5_0_ring_get_rptr - get the current read pointer
283 *
284 * @ring: amdgpu ring pointer
285 *
286 * Get the current rptr from the hardware (NAVI10+).
287 */
288static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
289{
290 u64 *rptr;
291
292 /* XXX check if swapping is necessary on BE */
293 rptr = (u64 *)ring->rptr_cpu_addr;
294
295 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
296 return ((*rptr) >> 2);
297}
298
299/**
300 * sdma_v5_0_ring_get_wptr - get the current write pointer
301 *
302 * @ring: amdgpu ring pointer
303 *
304 * Get the current wptr from the hardware (NAVI10+).
305 */
306static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
307{
308 struct amdgpu_device *adev = ring->adev;
309 u64 wptr;
310
311 if (ring->use_doorbell) {
312 /* XXX check if swapping is necessary on BE */
313 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
314 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
315 } else {
316 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
317 wptr = wptr << 32;
318 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
319 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
320 }
321
322 return wptr >> 2;
323}
324
325/**
326 * sdma_v5_0_ring_set_wptr - commit the write pointer
327 *
328 * @ring: amdgpu ring pointer
329 *
330 * Write the wptr back to the hardware (NAVI10+).
331 */
332static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
333{
334 struct amdgpu_device *adev = ring->adev;
335 uint32_t *wptr_saved;
336 uint32_t *is_queue_unmap;
337 uint64_t aggregated_db_index;
338 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;
339
340 DRM_DEBUG("Setting write pointer\n");
341 if (ring->is_mes_queue) {
342 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
343 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
344 sizeof(uint32_t));
345 aggregated_db_index =
346 amdgpu_mes_get_aggregated_doorbell_index(adev,
347 AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
348
349 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
350 ring->wptr << 2);
351 *wptr_saved = ring->wptr << 2;
352 if (*is_queue_unmap) {
353 WDOORBELL64(aggregated_db_index, ring->wptr << 2);
354 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
355 ring->doorbell_index, ring->wptr << 2);
356 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
357 } else {
358 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
359 ring->doorbell_index, ring->wptr << 2);
360 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
361
362 if (*is_queue_unmap)
363 WDOORBELL64(aggregated_db_index,
364 ring->wptr << 2);
365 }
366 } else {
367 if (ring->use_doorbell) {
368 DRM_DEBUG("Using doorbell -- "
369 "wptr_offs == 0x%08x "
370 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
371 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
372 ring->wptr_offs,
373 lower_32_bits(ring->wptr << 2),
374 upper_32_bits(ring->wptr << 2));
375 /* XXX check if swapping is necessary on BE */
376 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
377 ring->wptr << 2);
378 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
379 ring->doorbell_index, ring->wptr << 2);
380 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
381 } else {
382 DRM_DEBUG("Not using doorbell -- "
383 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
384 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
385 ring->me,
386 lower_32_bits(ring->wptr << 2),
387 ring->me,
388 upper_32_bits(ring->wptr << 2));
389 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
390 ring->me, mmSDMA0_GFX_RB_WPTR),
391 lower_32_bits(ring->wptr << 2));
392 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
393 ring->me, mmSDMA0_GFX_RB_WPTR_HI),
394 upper_32_bits(ring->wptr << 2));
395 }
396 }
397}
398
399static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
400{
401 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
402 int i;
403
404 for (i = 0; i < count; i++)
405 if (sdma && sdma->burst_nop && (i == 0))
406 amdgpu_ring_write(ring, ring->funcs->nop |
407 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
408 else
409 amdgpu_ring_write(ring, ring->funcs->nop);
410}
411
412/**
413 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
414 *
415 * @ring: amdgpu ring pointer
416 * @job: job to retrieve vmid from
417 * @ib: IB object to schedule
418 * @flags: unused
419 *
420 * Schedule an IB in the DMA ring (NAVI10).
421 */
422static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
423 struct amdgpu_job *job,
424 struct amdgpu_ib *ib,
425 uint32_t flags)
426{
427 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
428 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
429
430 /* An IB packet must end on a 8 DW boundary--the next dword
431 * must be on a 8-dword boundary. Our IB packet below is 6
432 * dwords long, thus add x number of NOPs, such that, in
433 * modular arithmetic,
434 * wptr + 6 + x = 8k, k >= 0, which in C is,
435 * (wptr + 6 + x) % 8 = 0.
436 * The expression below, is a solution of x.
437 */
438 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
439
440 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
441 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
442 /* base must be 32 byte aligned */
443 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
444 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
445 amdgpu_ring_write(ring, ib->length_dw);
446 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
447 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
448}
449
450/**
451 * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
452 *
453 * @ring: amdgpu ring pointer
454 *
455 * flush the IB by graphics cache rinse.
456 */
457static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
458{
459 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
460 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
461 SDMA_GCR_GLI_INV(1);
462
463 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
464 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
465 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
466 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
467 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
468 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
469 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
470 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
471 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
472}
473
474/**
475 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
476 *
477 * @ring: amdgpu ring pointer
478 *
479 * Emit an hdp flush packet on the requested DMA ring.
480 */
481static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
482{
483 struct amdgpu_device *adev = ring->adev;
484 u32 ref_and_mask = 0;
485 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
486
487 if (ring->me == 0)
488 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
489 else
490 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
491
492 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
493 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
494 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
495 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
496 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
497 amdgpu_ring_write(ring, ref_and_mask); /* reference */
498 amdgpu_ring_write(ring, ref_and_mask); /* mask */
499 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
500 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
501}
502
503/**
504 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
505 *
506 * @ring: amdgpu ring pointer
507 * @addr: address
508 * @seq: sequence number
509 * @flags: fence related flags
510 *
511 * Add a DMA fence packet to the ring to write
512 * the fence seq number and DMA trap packet to generate
513 * an interrupt if needed (NAVI10).
514 */
515static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
516 unsigned flags)
517{
518 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
519 /* write the fence */
520 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
521 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
522 /* zero in first two bits */
523 BUG_ON(addr & 0x3);
524 amdgpu_ring_write(ring, lower_32_bits(addr));
525 amdgpu_ring_write(ring, upper_32_bits(addr));
526 amdgpu_ring_write(ring, lower_32_bits(seq));
527
528 /* optionally write high bits as well */
529 if (write64bit) {
530 addr += 4;
531 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
532 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
533 /* zero in first two bits */
534 BUG_ON(addr & 0x3);
535 amdgpu_ring_write(ring, lower_32_bits(addr));
536 amdgpu_ring_write(ring, upper_32_bits(addr));
537 amdgpu_ring_write(ring, upper_32_bits(seq));
538 }
539
540 if (flags & AMDGPU_FENCE_FLAG_INT) {
541 uint32_t ctx = ring->is_mes_queue ?
542 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
543 /* generate an interrupt */
544 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
545 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
546 }
547}
548
549
550/**
551 * sdma_v5_0_gfx_stop - stop the gfx async dma engines
552 *
553 * @adev: amdgpu_device pointer
554 *
555 * Stop the gfx async dma ring buffers (NAVI10).
556 */
557static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
558{
559 u32 rb_cntl, ib_cntl;
560 int i;
561
562 for (i = 0; i < adev->sdma.num_instances; i++) {
563 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
564 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
565 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
566 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
567 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
568 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
569 }
570}
571
572/**
573 * sdma_v5_0_rlc_stop - stop the compute async dma engines
574 *
575 * @adev: amdgpu_device pointer
576 *
577 * Stop the compute async dma queues (NAVI10).
578 */
579static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
580{
581 /* XXX todo */
582}
583
584/**
585 * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch
586 *
587 * @adev: amdgpu_device pointer
588 * @enable: enable/disable the DMA MEs context switch.
589 *
590 * Halt or unhalt the async dma engines context switch (NAVI10).
591 */
592static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
593{
594 u32 f32_cntl = 0, phase_quantum = 0;
595 int i;
596
597 if (amdgpu_sdma_phase_quantum) {
598 unsigned value = amdgpu_sdma_phase_quantum;
599 unsigned unit = 0;
600
601 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
602 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
603 value = (value + 1) >> 1;
604 unit++;
605 }
606 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
607 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
608 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
609 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
610 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
611 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
612 WARN_ONCE(1,
613 "clamping sdma_phase_quantum to %uK clock cycles\n",
614 value << unit);
615 }
616 phase_quantum =
617 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
618 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
619 }
620
621 for (i = 0; i < adev->sdma.num_instances; i++) {
622 if (!amdgpu_sriov_vf(adev)) {
623 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
624 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
625 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
626 }
627
628 if (enable && amdgpu_sdma_phase_quantum) {
629 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
630 phase_quantum);
631 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
632 phase_quantum);
633 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
634 phase_quantum);
635 }
636 if (!amdgpu_sriov_vf(adev))
637 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
638 }
639
640}
641
642/**
643 * sdma_v5_0_enable - stop the async dma engines
644 *
645 * @adev: amdgpu_device pointer
646 * @enable: enable/disable the DMA MEs.
647 *
648 * Halt or unhalt the async dma engines (NAVI10).
649 */
650static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
651{
652 u32 f32_cntl;
653 int i;
654
655 if (!enable) {
656 sdma_v5_0_gfx_stop(adev);
657 sdma_v5_0_rlc_stop(adev);
658 }
659
660 if (amdgpu_sriov_vf(adev))
661 return;
662
663 for (i = 0; i < adev->sdma.num_instances; i++) {
664 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
665 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
666 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
667 }
668}
669
670/**
671 * sdma_v5_0_gfx_resume - setup and start the async dma engines
672 *
673 * @adev: amdgpu_device pointer
674 *
675 * Set up the gfx DMA ring buffers and enable them (NAVI10).
676 * Returns 0 for success, error for failure.
677 */
678static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
679{
680 struct amdgpu_ring *ring;
681 u32 rb_cntl, ib_cntl;
682 u32 rb_bufsz;
683 u32 doorbell;
684 u32 doorbell_offset;
685 u32 temp;
686 u32 wptr_poll_cntl;
687 u64 wptr_gpu_addr;
688 int i, r;
689
690 for (i = 0; i < adev->sdma.num_instances; i++) {
691 ring = &adev->sdma.instance[i].ring;
692
693 if (!amdgpu_sriov_vf(adev))
694 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
695
696 /* Set ring buffer size in dwords */
697 rb_bufsz = order_base_2(ring->ring_size / 4);
698 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
699 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
700#ifdef __BIG_ENDIAN
701 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
702 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
703 RPTR_WRITEBACK_SWAP_ENABLE, 1);
704#endif
705 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
706
707 /* Initialize the ring buffer's read and write pointers */
708 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
709 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
710 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
711 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
712
713 /* setup the wptr shadow polling */
714 wptr_gpu_addr = ring->wptr_gpu_addr;
715 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
716 lower_32_bits(wptr_gpu_addr));
717 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
718 upper_32_bits(wptr_gpu_addr));
719 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
720 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
721 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
722 SDMA0_GFX_RB_WPTR_POLL_CNTL,
723 F32_POLL_ENABLE, 1);
724 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
725 wptr_poll_cntl);
726
727 /* set the wb address whether it's enabled or not */
728 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
729 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
730 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
731 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
732
733 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
734
735 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
736 ring->gpu_addr >> 8);
737 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
738 ring->gpu_addr >> 40);
739
740 ring->wptr = 0;
741
742 /* before programing wptr to a less value, need set minor_ptr_update first */
743 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
744
745 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
746 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
747 lower_32_bits(ring->wptr << 2));
748 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
749 upper_32_bits(ring->wptr << 2));
750 }
751
752 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
753 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
754 mmSDMA0_GFX_DOORBELL_OFFSET));
755
756 if (ring->use_doorbell) {
757 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
758 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
759 OFFSET, ring->doorbell_index);
760 } else {
761 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
762 }
763 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
764 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
765 doorbell_offset);
766
767 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
768 ring->doorbell_index, 20);
769
770 if (amdgpu_sriov_vf(adev))
771 sdma_v5_0_ring_set_wptr(ring);
772
773 /* set minor_ptr_update to 0 after wptr programed */
774 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
775
776 if (!amdgpu_sriov_vf(adev)) {
777 /* set utc l1 enable flag always to 1 */
778 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
779 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
780
781 /* enable MCBP */
782 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
783 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
784
785 /* Set up RESP_MODE to non-copy addresses */
786 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
787 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
788 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
789 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
790
791 /* program default cache read and write policy */
792 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
793 /* clean read policy and write policy bits */
794 temp &= 0xFF0FFF;
795 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
796 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
797 }
798
799 if (!amdgpu_sriov_vf(adev)) {
800 /* unhalt engine */
801 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
802 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
803 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
804 }
805
806 /* enable DMA RB */
807 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
808 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
809
810 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
811 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
812#ifdef __BIG_ENDIAN
813 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
814#endif
815 /* enable DMA IBs */
816 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
817
818 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
819 sdma_v5_0_ctx_switch_enable(adev, true);
820 sdma_v5_0_enable(adev, true);
821 }
822
823 r = amdgpu_ring_test_helper(ring);
824 if (r)
825 return r;
826 }
827
828 return 0;
829}
830
831/**
832 * sdma_v5_0_rlc_resume - setup and start the async dma engines
833 *
834 * @adev: amdgpu_device pointer
835 *
836 * Set up the compute DMA queues and enable them (NAVI10).
837 * Returns 0 for success, error for failure.
838 */
839static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
840{
841 return 0;
842}
843
844/**
845 * sdma_v5_0_load_microcode - load the sDMA ME ucode
846 *
847 * @adev: amdgpu_device pointer
848 *
849 * Loads the sDMA0/1 ucode.
850 * Returns 0 for success, -EINVAL if the ucode is not available.
851 */
852static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
853{
854 const struct sdma_firmware_header_v1_0 *hdr;
855 const __le32 *fw_data;
856 u32 fw_size;
857 int i, j;
858
859 /* halt the MEs */
860 sdma_v5_0_enable(adev, false);
861
862 for (i = 0; i < adev->sdma.num_instances; i++) {
863 if (!adev->sdma.instance[i].fw)
864 return -EINVAL;
865
866 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
867 amdgpu_ucode_print_sdma_hdr(&hdr->header);
868 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
869
870 fw_data = (const __le32 *)
871 (adev->sdma.instance[i].fw->data +
872 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
873
874 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
875
876 for (j = 0; j < fw_size; j++) {
877 if (amdgpu_emu_mode == 1 && j % 500 == 0)
878 msleep(1);
879 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
880 }
881
882 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
883 }
884
885 return 0;
886}
887
888/**
889 * sdma_v5_0_start - setup and start the async dma engines
890 *
891 * @adev: amdgpu_device pointer
892 *
893 * Set up the DMA engines and enable them (NAVI10).
894 * Returns 0 for success, error for failure.
895 */
896static int sdma_v5_0_start(struct amdgpu_device *adev)
897{
898 int r = 0;
899
900 if (amdgpu_sriov_vf(adev)) {
901 sdma_v5_0_ctx_switch_enable(adev, false);
902 sdma_v5_0_enable(adev, false);
903
904 /* set RB registers */
905 r = sdma_v5_0_gfx_resume(adev);
906 return r;
907 }
908
909 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
910 r = sdma_v5_0_load_microcode(adev);
911 if (r)
912 return r;
913 }
914
915 /* unhalt the MEs */
916 sdma_v5_0_enable(adev, true);
917 /* enable sdma ring preemption */
918 sdma_v5_0_ctx_switch_enable(adev, true);
919
920 /* start the gfx rings and rlc compute queues */
921 r = sdma_v5_0_gfx_resume(adev);
922 if (r)
923 return r;
924 r = sdma_v5_0_rlc_resume(adev);
925
926 return r;
927}
928
929static int sdma_v5_0_mqd_init(struct amdgpu_device *adev, void *mqd,
930 struct amdgpu_mqd_prop *prop)
931{
932 struct v10_sdma_mqd *m = mqd;
933 uint64_t wb_gpu_addr;
934
935 m->sdmax_rlcx_rb_cntl =
936 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
937 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
938 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
939 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
940
941 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
942 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
943
944 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
945 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
946
947 wb_gpu_addr = prop->wptr_gpu_addr;
948 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
949 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
950
951 wb_gpu_addr = prop->rptr_gpu_addr;
952 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
953 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
954
955 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
956 mmSDMA0_GFX_IB_CNTL));
957
958 m->sdmax_rlcx_doorbell_offset =
959 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
960
961 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
962
963 return 0;
964}
965
966static void sdma_v5_0_set_mqd_funcs(struct amdgpu_device *adev)
967{
968 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
969 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_0_mqd_init;
970}
971
972/**
973 * sdma_v5_0_ring_test_ring - simple async dma engine test
974 *
975 * @ring: amdgpu_ring structure holding ring information
976 *
977 * Test the DMA engine by writing using it to write an
978 * value to memory. (NAVI10).
979 * Returns 0 for success, error for failure.
980 */
981static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
982{
983 struct amdgpu_device *adev = ring->adev;
984 unsigned i;
985 unsigned index;
986 int r;
987 u32 tmp;
988 u64 gpu_addr;
989 volatile uint32_t *cpu_ptr = NULL;
990
991 tmp = 0xCAFEDEAD;
992
993 if (ring->is_mes_queue) {
994 uint32_t offset = 0;
995 offset = amdgpu_mes_ctx_get_offs(ring,
996 AMDGPU_MES_CTX_PADDING_OFFS);
997 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
998 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
999 *cpu_ptr = tmp;
1000 } else {
1001 r = amdgpu_device_wb_get(adev, &index);
1002 if (r) {
1003 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
1004 return r;
1005 }
1006
1007 gpu_addr = adev->wb.gpu_addr + (index * 4);
1008 adev->wb.wb[index] = cpu_to_le32(tmp);
1009 }
1010
1011 r = amdgpu_ring_alloc(ring, 20);
1012 if (r) {
1013 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
1014 amdgpu_device_wb_free(adev, index);
1015 return r;
1016 }
1017
1018 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1019 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1020 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1021 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1022 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1023 amdgpu_ring_write(ring, 0xDEADBEEF);
1024 amdgpu_ring_commit(ring);
1025
1026 for (i = 0; i < adev->usec_timeout; i++) {
1027 if (ring->is_mes_queue)
1028 tmp = le32_to_cpu(*cpu_ptr);
1029 else
1030 tmp = le32_to_cpu(adev->wb.wb[index]);
1031 if (tmp == 0xDEADBEEF)
1032 break;
1033 if (amdgpu_emu_mode == 1)
1034 msleep(1);
1035 else
1036 udelay(1);
1037 }
1038
1039 if (i >= adev->usec_timeout)
1040 r = -ETIMEDOUT;
1041
1042 if (!ring->is_mes_queue)
1043 amdgpu_device_wb_free(adev, index);
1044
1045 return r;
1046}
1047
1048/**
1049 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
1050 *
1051 * @ring: amdgpu_ring structure holding ring information
1052 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1053 *
1054 * Test a simple IB in the DMA ring (NAVI10).
1055 * Returns 0 on success, error on failure.
1056 */
1057static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1058{
1059 struct amdgpu_device *adev = ring->adev;
1060 struct amdgpu_ib ib;
1061 struct dma_fence *f = NULL;
1062 unsigned index;
1063 long r;
1064 u32 tmp = 0;
1065 u64 gpu_addr;
1066 volatile uint32_t *cpu_ptr = NULL;
1067
1068 tmp = 0xCAFEDEAD;
1069 memset(&ib, 0, sizeof(ib));
1070
1071 if (ring->is_mes_queue) {
1072 uint32_t offset = 0;
1073 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
1074 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1075 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1076
1077 offset = amdgpu_mes_ctx_get_offs(ring,
1078 AMDGPU_MES_CTX_PADDING_OFFS);
1079 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1080 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1081 *cpu_ptr = tmp;
1082 } else {
1083 r = amdgpu_device_wb_get(adev, &index);
1084 if (r) {
1085 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1086 return r;
1087 }
1088
1089 gpu_addr = adev->wb.gpu_addr + (index * 4);
1090 adev->wb.wb[index] = cpu_to_le32(tmp);
1091
1092 r = amdgpu_ib_get(adev, NULL, 256,
1093 AMDGPU_IB_POOL_DIRECT, &ib);
1094 if (r) {
1095 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1096 goto err0;
1097 }
1098 }
1099
1100 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1101 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1102 ib.ptr[1] = lower_32_bits(gpu_addr);
1103 ib.ptr[2] = upper_32_bits(gpu_addr);
1104 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1105 ib.ptr[4] = 0xDEADBEEF;
1106 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1107 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1108 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1109 ib.length_dw = 8;
1110
1111 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1112 if (r)
1113 goto err1;
1114
1115 r = dma_fence_wait_timeout(f, false, timeout);
1116 if (r == 0) {
1117 DRM_ERROR("amdgpu: IB test timed out\n");
1118 r = -ETIMEDOUT;
1119 goto err1;
1120 } else if (r < 0) {
1121 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1122 goto err1;
1123 }
1124
1125 if (ring->is_mes_queue)
1126 tmp = le32_to_cpu(*cpu_ptr);
1127 else
1128 tmp = le32_to_cpu(adev->wb.wb[index]);
1129
1130 if (tmp == 0xDEADBEEF)
1131 r = 0;
1132 else
1133 r = -EINVAL;
1134
1135err1:
1136 amdgpu_ib_free(adev, &ib, NULL);
1137 dma_fence_put(f);
1138err0:
1139 if (!ring->is_mes_queue)
1140 amdgpu_device_wb_free(adev, index);
1141 return r;
1142}
1143
1144
1145/**
1146 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1147 *
1148 * @ib: indirect buffer to fill with commands
1149 * @pe: addr of the page entry
1150 * @src: src addr to copy from
1151 * @count: number of page entries to update
1152 *
1153 * Update PTEs by copying them from the GART using sDMA (NAVI10).
1154 */
1155static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1156 uint64_t pe, uint64_t src,
1157 unsigned count)
1158{
1159 unsigned bytes = count * 8;
1160
1161 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1162 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1163 ib->ptr[ib->length_dw++] = bytes - 1;
1164 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1165 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1166 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1167 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1168 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1169
1170}
1171
1172/**
1173 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1174 *
1175 * @ib: indirect buffer to fill with commands
1176 * @pe: addr of the page entry
1177 * @value: dst addr to write into pe
1178 * @count: number of page entries to update
1179 * @incr: increase next addr by incr bytes
1180 *
1181 * Update PTEs by writing them manually using sDMA (NAVI10).
1182 */
1183static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1184 uint64_t value, unsigned count,
1185 uint32_t incr)
1186{
1187 unsigned ndw = count * 2;
1188
1189 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1190 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1191 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1192 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1193 ib->ptr[ib->length_dw++] = ndw - 1;
1194 for (; ndw > 0; ndw -= 2) {
1195 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1196 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1197 value += incr;
1198 }
1199}
1200
1201/**
1202 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1203 *
1204 * @ib: indirect buffer to fill with commands
1205 * @pe: addr of the page entry
1206 * @addr: dst addr to write into pe
1207 * @count: number of page entries to update
1208 * @incr: increase next addr by incr bytes
1209 * @flags: access flags
1210 *
1211 * Update the page tables using sDMA (NAVI10).
1212 */
1213static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1214 uint64_t pe,
1215 uint64_t addr, unsigned count,
1216 uint32_t incr, uint64_t flags)
1217{
1218 /* for physically contiguous pages (vram) */
1219 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1220 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1221 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1222 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1223 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1224 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1225 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1226 ib->ptr[ib->length_dw++] = incr; /* increment size */
1227 ib->ptr[ib->length_dw++] = 0;
1228 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1229}
1230
1231/**
1232 * sdma_v5_0_ring_pad_ib - pad the IB
1233 * @ring: amdgpu_ring structure holding ring information
1234 * @ib: indirect buffer to fill with padding
1235 *
1236 * Pad the IB with NOPs to a boundary multiple of 8.
1237 */
1238static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1239{
1240 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1241 u32 pad_count;
1242 int i;
1243
1244 pad_count = (-ib->length_dw) & 0x7;
1245 for (i = 0; i < pad_count; i++)
1246 if (sdma && sdma->burst_nop && (i == 0))
1247 ib->ptr[ib->length_dw++] =
1248 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1249 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1250 else
1251 ib->ptr[ib->length_dw++] =
1252 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1253}
1254
1255
1256/**
1257 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1258 *
1259 * @ring: amdgpu_ring pointer
1260 *
1261 * Make sure all previous operations are completed (CIK).
1262 */
1263static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1264{
1265 uint32_t seq = ring->fence_drv.sync_seq;
1266 uint64_t addr = ring->fence_drv.gpu_addr;
1267
1268 /* wait for idle */
1269 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1270 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1271 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1272 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1273 amdgpu_ring_write(ring, addr & 0xfffffffc);
1274 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1275 amdgpu_ring_write(ring, seq); /* reference */
1276 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1277 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1278 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1279}
1280
1281
1282/**
1283 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1284 *
1285 * @ring: amdgpu_ring pointer
1286 * @vmid: vmid number to use
1287 * @pd_addr: address
1288 *
1289 * Update the page table base and flush the VM TLB
1290 * using sDMA (NAVI10).
1291 */
1292static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1293 unsigned vmid, uint64_t pd_addr)
1294{
1295 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1296}
1297
1298static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1299 uint32_t reg, uint32_t val)
1300{
1301 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1302 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1303 amdgpu_ring_write(ring, reg);
1304 amdgpu_ring_write(ring, val);
1305}
1306
1307static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1308 uint32_t val, uint32_t mask)
1309{
1310 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1311 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1312 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1313 amdgpu_ring_write(ring, reg << 2);
1314 amdgpu_ring_write(ring, 0);
1315 amdgpu_ring_write(ring, val); /* reference */
1316 amdgpu_ring_write(ring, mask); /* mask */
1317 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1318 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1319}
1320
1321static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1322 uint32_t reg0, uint32_t reg1,
1323 uint32_t ref, uint32_t mask)
1324{
1325 amdgpu_ring_emit_wreg(ring, reg0, ref);
1326 /* wait for a cycle to reset vm_inv_eng*_ack */
1327 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1328 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1329}
1330
1331static int sdma_v5_0_early_init(void *handle)
1332{
1333 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1334 int r;
1335
1336 r = sdma_v5_0_init_microcode(adev);
1337 if (r)
1338 return r;
1339
1340 sdma_v5_0_set_ring_funcs(adev);
1341 sdma_v5_0_set_buffer_funcs(adev);
1342 sdma_v5_0_set_vm_pte_funcs(adev);
1343 sdma_v5_0_set_irq_funcs(adev);
1344 sdma_v5_0_set_mqd_funcs(adev);
1345
1346 return 0;
1347}
1348
1349
1350static int sdma_v5_0_sw_init(void *handle)
1351{
1352 struct amdgpu_ring *ring;
1353 int r, i;
1354 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1355
1356 /* SDMA trap event */
1357 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1358 SDMA0_5_0__SRCID__SDMA_TRAP,
1359 &adev->sdma.trap_irq);
1360 if (r)
1361 return r;
1362
1363 /* SDMA trap event */
1364 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1365 SDMA1_5_0__SRCID__SDMA_TRAP,
1366 &adev->sdma.trap_irq);
1367 if (r)
1368 return r;
1369
1370 for (i = 0; i < adev->sdma.num_instances; i++) {
1371 ring = &adev->sdma.instance[i].ring;
1372 ring->ring_obj = NULL;
1373 ring->use_doorbell = true;
1374
1375 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1376 ring->use_doorbell?"true":"false");
1377
1378 ring->doorbell_index = (i == 0) ?
1379 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1380 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1381
1382 ring->vm_hub = AMDGPU_GFXHUB(0);
1383 sprintf(ring->name, "sdma%d", i);
1384 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1385 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1386 AMDGPU_SDMA_IRQ_INSTANCE1,
1387 AMDGPU_RING_PRIO_DEFAULT, NULL);
1388 if (r)
1389 return r;
1390 }
1391
1392 return r;
1393}
1394
1395static int sdma_v5_0_sw_fini(void *handle)
1396{
1397 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1398 int i;
1399
1400 for (i = 0; i < adev->sdma.num_instances; i++)
1401 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1402
1403 amdgpu_sdma_destroy_inst_ctx(adev, false);
1404
1405 return 0;
1406}
1407
1408static int sdma_v5_0_hw_init(void *handle)
1409{
1410 int r;
1411 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1412
1413 sdma_v5_0_init_golden_registers(adev);
1414
1415 r = sdma_v5_0_start(adev);
1416
1417 return r;
1418}
1419
1420static int sdma_v5_0_hw_fini(void *handle)
1421{
1422 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1423
1424 if (amdgpu_sriov_vf(adev))
1425 return 0;
1426
1427 sdma_v5_0_ctx_switch_enable(adev, false);
1428 sdma_v5_0_enable(adev, false);
1429
1430 return 0;
1431}
1432
1433static int sdma_v5_0_suspend(void *handle)
1434{
1435 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1436
1437 return sdma_v5_0_hw_fini(adev);
1438}
1439
1440static int sdma_v5_0_resume(void *handle)
1441{
1442 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1443
1444 return sdma_v5_0_hw_init(adev);
1445}
1446
1447static bool sdma_v5_0_is_idle(void *handle)
1448{
1449 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1450 u32 i;
1451
1452 for (i = 0; i < adev->sdma.num_instances; i++) {
1453 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1454
1455 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1456 return false;
1457 }
1458
1459 return true;
1460}
1461
1462static int sdma_v5_0_wait_for_idle(void *handle)
1463{
1464 unsigned i;
1465 u32 sdma0, sdma1;
1466 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1467
1468 for (i = 0; i < adev->usec_timeout; i++) {
1469 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1470 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1471
1472 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1473 return 0;
1474 udelay(1);
1475 }
1476 return -ETIMEDOUT;
1477}
1478
1479static int sdma_v5_0_soft_reset(void *handle)
1480{
1481 /* todo */
1482
1483 return 0;
1484}
1485
1486static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1487{
1488 int i, r = 0;
1489 struct amdgpu_device *adev = ring->adev;
1490 u32 index = 0;
1491 u64 sdma_gfx_preempt;
1492
1493 amdgpu_sdma_get_index_from_ring(ring, &index);
1494 if (index == 0)
1495 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1496 else
1497 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1498
1499 /* assert preemption condition */
1500 amdgpu_ring_set_preempt_cond_exec(ring, false);
1501
1502 /* emit the trailing fence */
1503 ring->trail_seq += 1;
1504 amdgpu_ring_alloc(ring, 10);
1505 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1506 ring->trail_seq, 0);
1507 amdgpu_ring_commit(ring);
1508
1509 /* assert IB preemption */
1510 WREG32(sdma_gfx_preempt, 1);
1511
1512 /* poll the trailing fence */
1513 for (i = 0; i < adev->usec_timeout; i++) {
1514 if (ring->trail_seq ==
1515 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1516 break;
1517 udelay(1);
1518 }
1519
1520 if (i >= adev->usec_timeout) {
1521 r = -EINVAL;
1522 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1523 }
1524
1525 /* deassert IB preemption */
1526 WREG32(sdma_gfx_preempt, 0);
1527
1528 /* deassert the preemption condition */
1529 amdgpu_ring_set_preempt_cond_exec(ring, true);
1530 return r;
1531}
1532
1533static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1534 struct amdgpu_irq_src *source,
1535 unsigned type,
1536 enum amdgpu_interrupt_state state)
1537{
1538 u32 sdma_cntl;
1539
1540 if (!amdgpu_sriov_vf(adev)) {
1541 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1542 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1543 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1544
1545 sdma_cntl = RREG32(reg_offset);
1546 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1547 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1548 WREG32(reg_offset, sdma_cntl);
1549 }
1550
1551 return 0;
1552}
1553
1554static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1555 struct amdgpu_irq_src *source,
1556 struct amdgpu_iv_entry *entry)
1557{
1558 uint32_t mes_queue_id = entry->src_data[0];
1559
1560 DRM_DEBUG("IH: SDMA trap\n");
1561
1562 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1563 struct amdgpu_mes_queue *queue;
1564
1565 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1566
1567 spin_lock(&adev->mes.queue_id_lock);
1568 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1569 if (queue) {
1570 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1571 amdgpu_fence_process(queue->ring);
1572 }
1573 spin_unlock(&adev->mes.queue_id_lock);
1574 return 0;
1575 }
1576
1577 switch (entry->client_id) {
1578 case SOC15_IH_CLIENTID_SDMA0:
1579 switch (entry->ring_id) {
1580 case 0:
1581 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1582 break;
1583 case 1:
1584 /* XXX compute */
1585 break;
1586 case 2:
1587 /* XXX compute */
1588 break;
1589 case 3:
1590 /* XXX page queue*/
1591 break;
1592 }
1593 break;
1594 case SOC15_IH_CLIENTID_SDMA1:
1595 switch (entry->ring_id) {
1596 case 0:
1597 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1598 break;
1599 case 1:
1600 /* XXX compute */
1601 break;
1602 case 2:
1603 /* XXX compute */
1604 break;
1605 case 3:
1606 /* XXX page queue*/
1607 break;
1608 }
1609 break;
1610 }
1611 return 0;
1612}
1613
1614static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1615 struct amdgpu_irq_src *source,
1616 struct amdgpu_iv_entry *entry)
1617{
1618 return 0;
1619}
1620
1621static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1622 bool enable)
1623{
1624 uint32_t data, def;
1625 int i;
1626
1627 for (i = 0; i < adev->sdma.num_instances; i++) {
1628 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1629 /* Enable sdma clock gating */
1630 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1631 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1632 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1633 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1634 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1635 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1636 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1637 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1638 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1639 if (def != data)
1640 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1641 } else {
1642 /* Disable sdma clock gating */
1643 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1644 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1645 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1646 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1647 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1648 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1649 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1650 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1651 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1652 if (def != data)
1653 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1654 }
1655 }
1656}
1657
1658static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1659 bool enable)
1660{
1661 uint32_t data, def;
1662 int i;
1663
1664 for (i = 0; i < adev->sdma.num_instances; i++) {
1665 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1666 /* Enable sdma mem light sleep */
1667 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1668 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1669 if (def != data)
1670 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1671
1672 } else {
1673 /* Disable sdma mem light sleep */
1674 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1675 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1676 if (def != data)
1677 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1678
1679 }
1680 }
1681}
1682
1683static int sdma_v5_0_set_clockgating_state(void *handle,
1684 enum amd_clockgating_state state)
1685{
1686 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1687
1688 if (amdgpu_sriov_vf(adev))
1689 return 0;
1690
1691 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1692 case IP_VERSION(5, 0, 0):
1693 case IP_VERSION(5, 0, 2):
1694 case IP_VERSION(5, 0, 5):
1695 sdma_v5_0_update_medium_grain_clock_gating(adev,
1696 state == AMD_CG_STATE_GATE);
1697 sdma_v5_0_update_medium_grain_light_sleep(adev,
1698 state == AMD_CG_STATE_GATE);
1699 break;
1700 default:
1701 break;
1702 }
1703
1704 return 0;
1705}
1706
1707static int sdma_v5_0_set_powergating_state(void *handle,
1708 enum amd_powergating_state state)
1709{
1710 return 0;
1711}
1712
1713static void sdma_v5_0_get_clockgating_state(void *handle, u64 *flags)
1714{
1715 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1716 int data;
1717
1718 if (amdgpu_sriov_vf(adev))
1719 *flags = 0;
1720
1721 /* AMD_CG_SUPPORT_SDMA_MGCG */
1722 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1723 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1724 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1725
1726 /* AMD_CG_SUPPORT_SDMA_LS */
1727 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1728 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1729 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1730}
1731
1732const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1733 .name = "sdma_v5_0",
1734 .early_init = sdma_v5_0_early_init,
1735 .late_init = NULL,
1736 .sw_init = sdma_v5_0_sw_init,
1737 .sw_fini = sdma_v5_0_sw_fini,
1738 .hw_init = sdma_v5_0_hw_init,
1739 .hw_fini = sdma_v5_0_hw_fini,
1740 .suspend = sdma_v5_0_suspend,
1741 .resume = sdma_v5_0_resume,
1742 .is_idle = sdma_v5_0_is_idle,
1743 .wait_for_idle = sdma_v5_0_wait_for_idle,
1744 .soft_reset = sdma_v5_0_soft_reset,
1745 .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1746 .set_powergating_state = sdma_v5_0_set_powergating_state,
1747 .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1748};
1749
1750static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1751 .type = AMDGPU_RING_TYPE_SDMA,
1752 .align_mask = 0xf,
1753 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1754 .support_64bit_ptrs = true,
1755 .secure_submission_supported = true,
1756 .get_rptr = sdma_v5_0_ring_get_rptr,
1757 .get_wptr = sdma_v5_0_ring_get_wptr,
1758 .set_wptr = sdma_v5_0_ring_set_wptr,
1759 .emit_frame_size =
1760 5 + /* sdma_v5_0_ring_init_cond_exec */
1761 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1762 3 + /* hdp_invalidate */
1763 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1764 /* sdma_v5_0_ring_emit_vm_flush */
1765 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1766 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1767 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1768 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1769 .emit_ib = sdma_v5_0_ring_emit_ib,
1770 .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync,
1771 .emit_fence = sdma_v5_0_ring_emit_fence,
1772 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1773 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1774 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1775 .test_ring = sdma_v5_0_ring_test_ring,
1776 .test_ib = sdma_v5_0_ring_test_ib,
1777 .insert_nop = sdma_v5_0_ring_insert_nop,
1778 .pad_ib = sdma_v5_0_ring_pad_ib,
1779 .emit_wreg = sdma_v5_0_ring_emit_wreg,
1780 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1781 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1782 .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1783 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1784 .preempt_ib = sdma_v5_0_ring_preempt_ib,
1785};
1786
1787static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1788{
1789 int i;
1790
1791 for (i = 0; i < adev->sdma.num_instances; i++) {
1792 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1793 adev->sdma.instance[i].ring.me = i;
1794 }
1795}
1796
1797static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1798 .set = sdma_v5_0_set_trap_irq_state,
1799 .process = sdma_v5_0_process_trap_irq,
1800};
1801
1802static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1803 .process = sdma_v5_0_process_illegal_inst_irq,
1804};
1805
1806static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1807{
1808 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1809 adev->sdma.num_instances;
1810 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1811 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1812}
1813
1814/**
1815 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1816 *
1817 * @ib: indirect buffer to copy to
1818 * @src_offset: src GPU address
1819 * @dst_offset: dst GPU address
1820 * @byte_count: number of bytes to xfer
1821 * @tmz: if a secure copy should be used
1822 *
1823 * Copy GPU buffers using the DMA engine (NAVI10).
1824 * Used by the amdgpu ttm implementation to move pages if
1825 * registered as the asic copy callback.
1826 */
1827static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1828 uint64_t src_offset,
1829 uint64_t dst_offset,
1830 uint32_t byte_count,
1831 bool tmz)
1832{
1833 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1834 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1835 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1836 ib->ptr[ib->length_dw++] = byte_count - 1;
1837 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1838 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1839 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1840 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1841 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1842}
1843
1844/**
1845 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1846 *
1847 * @ib: indirect buffer to fill
1848 * @src_data: value to write to buffer
1849 * @dst_offset: dst GPU address
1850 * @byte_count: number of bytes to xfer
1851 *
1852 * Fill GPU buffers using the DMA engine (NAVI10).
1853 */
1854static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1855 uint32_t src_data,
1856 uint64_t dst_offset,
1857 uint32_t byte_count)
1858{
1859 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1860 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1861 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1862 ib->ptr[ib->length_dw++] = src_data;
1863 ib->ptr[ib->length_dw++] = byte_count - 1;
1864}
1865
1866static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1867 .copy_max_bytes = 0x400000,
1868 .copy_num_dw = 7,
1869 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1870
1871 .fill_max_bytes = 0x400000,
1872 .fill_num_dw = 5,
1873 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1874};
1875
1876static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1877{
1878 if (adev->mman.buffer_funcs == NULL) {
1879 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1880 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1881 }
1882}
1883
1884static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1885 .copy_pte_num_dw = 7,
1886 .copy_pte = sdma_v5_0_vm_copy_pte,
1887 .write_pte = sdma_v5_0_vm_write_pte,
1888 .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1889};
1890
1891static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1892{
1893 unsigned i;
1894
1895 if (adev->vm_manager.vm_pte_funcs == NULL) {
1896 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1897 for (i = 0; i < adev->sdma.num_instances; i++) {
1898 adev->vm_manager.vm_pte_scheds[i] =
1899 &adev->sdma.instance[i].ring.sched;
1900 }
1901 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1902 }
1903}
1904
1905const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1906 .type = AMD_IP_BLOCK_TYPE_SDMA,
1907 .major = 5,
1908 .minor = 0,
1909 .rev = 0,
1910 .funcs = &sdma_v5_0_ip_funcs,
1911};