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1/*
2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#include <drm/amdgpu_drm.h>
26#include <drm/drm_drv.h>
27#include <drm/drm_fbdev_generic.h>
28#include <drm/drm_gem.h>
29#include <drm/drm_managed.h>
30#include <drm/drm_pciids.h>
31#include <drm/drm_probe_helper.h>
32#include <drm/drm_vblank.h>
33
34#include <linux/cc_platform.h>
35#include <linux/dynamic_debug.h>
36#include <linux/module.h>
37#include <linux/mmu_notifier.h>
38#include <linux/pm_runtime.h>
39#include <linux/suspend.h>
40#include <linux/vga_switcheroo.h>
41
42#include "amdgpu.h"
43#include "amdgpu_amdkfd.h"
44#include "amdgpu_dma_buf.h"
45#include "amdgpu_drv.h"
46#include "amdgpu_fdinfo.h"
47#include "amdgpu_irq.h"
48#include "amdgpu_psp.h"
49#include "amdgpu_ras.h"
50#include "amdgpu_reset.h"
51#include "amdgpu_sched.h"
52#include "amdgpu_xgmi.h"
53#include "../amdxcp/amdgpu_xcp_drv.h"
54
55/*
56 * KMS wrapper.
57 * - 3.0.0 - initial driver
58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
60 * at the end of IBs.
61 * - 3.3.0 - Add VM support for UVD on supported hardware.
62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
63 * - 3.5.0 - Add support for new UVD_NO_OP register.
64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
65 * - 3.7.0 - Add support for VCE clock list packet
66 * - 3.8.0 - Add support raster config init in the kernel
67 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
70 * - 3.12.0 - Add query for double offchip LDS buffers
71 * - 3.13.0 - Add PRT support
72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
73 * - 3.15.0 - Export more gpu info for gfx9
74 * - 3.16.0 - Add reserved vmid support
75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
76 * - 3.18.0 - Export gpu always on cu bitmap
77 * - 3.19.0 - Add support for UVD MJPEG decode
78 * - 3.20.0 - Add support for local BOs
79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
81 * - 3.23.0 - Add query for VRAM lost counter
82 * - 3.24.0 - Add high priority compute support for gfx9
83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
94 * - 3.36.0 - Allow reading more status registers on si/cik
95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
99 * - 3.41.0 - Add video codec query
100 * - 3.42.0 - Add 16bpc fixed point display support
101 * - 3.43.0 - Add device hot plug/unplug support
102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
103 * - 3.45.0 - Add context ioctl stable pstate interface
104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
106 * - 3.48.0 - Add IP discovery version info to HW INFO
107 * - 3.49.0 - Add gang submit into CS IOCTL
108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock
110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl
111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields:
112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size,
113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi
114 * 3.53.0 - Support for GFX11 CP GFX shadowing
115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support
116 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query
117 * - 3.56.0 - Update IB start address and size alignment for decode and encode
118 * - 3.57.0 - Compute tunneling on GFX10+
119 */
120#define KMS_DRIVER_MAJOR 3
121#define KMS_DRIVER_MINOR 57
122#define KMS_DRIVER_PATCHLEVEL 0
123
124/*
125 * amdgpu.debug module options. Are all disabled by default
126 */
127enum AMDGPU_DEBUG_MASK {
128 AMDGPU_DEBUG_VM = BIT(0),
129 AMDGPU_DEBUG_LARGEBAR = BIT(1),
130 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2),
131 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3),
132};
133
134unsigned int amdgpu_vram_limit = UINT_MAX;
135int amdgpu_vis_vram_limit;
136int amdgpu_gart_size = -1; /* auto */
137int amdgpu_gtt_size = -1; /* auto */
138int amdgpu_moverate = -1; /* auto */
139int amdgpu_audio = -1;
140int amdgpu_disp_priority;
141int amdgpu_hw_i2c;
142int amdgpu_pcie_gen2 = -1;
143int amdgpu_msi = -1;
144char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
145int amdgpu_dpm = -1;
146int amdgpu_fw_load_type = -1;
147int amdgpu_aspm = -1;
148int amdgpu_runtime_pm = -1;
149uint amdgpu_ip_block_mask = 0xffffffff;
150int amdgpu_bapm = -1;
151int amdgpu_deep_color;
152int amdgpu_vm_size = -1;
153int amdgpu_vm_fragment_size = -1;
154int amdgpu_vm_block_size = -1;
155int amdgpu_vm_fault_stop;
156int amdgpu_vm_update_mode = -1;
157int amdgpu_exp_hw_support;
158int amdgpu_dc = -1;
159int amdgpu_sched_jobs = 32;
160int amdgpu_sched_hw_submission = 2;
161uint amdgpu_pcie_gen_cap;
162uint amdgpu_pcie_lane_cap;
163u64 amdgpu_cg_mask = 0xffffffffffffffff;
164uint amdgpu_pg_mask = 0xffffffff;
165uint amdgpu_sdma_phase_quantum = 32;
166char *amdgpu_disable_cu;
167char *amdgpu_virtual_display;
168bool enforce_isolation;
169/*
170 * OverDrive(bit 14) disabled by default
171 * GFX DCS(bit 19) disabled by default
172 */
173uint amdgpu_pp_feature_mask = 0xfff7bfff;
174uint amdgpu_force_long_training;
175int amdgpu_lbpw = -1;
176int amdgpu_compute_multipipe = -1;
177int amdgpu_gpu_recovery = -1; /* auto */
178int amdgpu_emu_mode;
179uint amdgpu_smu_memory_pool_size;
180int amdgpu_smu_pptable_id = -1;
181/*
182 * FBC (bit 0) disabled by default
183 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
184 * - With this, for multiple monitors in sync(e.g. with the same model),
185 * mclk switching will be allowed. And the mclk will be not foced to the
186 * highest. That helps saving some idle power.
187 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
188 * PSR (bit 3) disabled by default
189 * EDP NO POWER SEQUENCING (bit 4) disabled by default
190 */
191uint amdgpu_dc_feature_mask = 2;
192uint amdgpu_dc_debug_mask;
193uint amdgpu_dc_visual_confirm;
194int amdgpu_async_gfx_ring = 1;
195int amdgpu_mcbp = -1;
196int amdgpu_discovery = -1;
197int amdgpu_mes;
198int amdgpu_mes_kiq;
199int amdgpu_noretry = -1;
200int amdgpu_force_asic_type = -1;
201int amdgpu_tmz = -1; /* auto */
202int amdgpu_reset_method = -1; /* auto */
203int amdgpu_num_kcq = -1;
204int amdgpu_smartshift_bias;
205int amdgpu_use_xgmi_p2p = 1;
206int amdgpu_vcnfw_log;
207int amdgpu_sg_display = -1; /* auto */
208int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
209int amdgpu_umsch_mm;
210int amdgpu_seamless = -1; /* auto */
211uint amdgpu_debug_mask;
212int amdgpu_agp = -1; /* auto */
213int amdgpu_wbrf = -1;
214int amdgpu_damage_clips = -1; /* auto */
215
216static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
217
218DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
219 "DRM_UT_CORE",
220 "DRM_UT_DRIVER",
221 "DRM_UT_KMS",
222 "DRM_UT_PRIME",
223 "DRM_UT_ATOMIC",
224 "DRM_UT_VBL",
225 "DRM_UT_STATE",
226 "DRM_UT_LEASE",
227 "DRM_UT_DP",
228 "DRM_UT_DRMRES");
229
230struct amdgpu_mgpu_info mgpu_info = {
231 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
232 .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
233 mgpu_info.delayed_reset_work,
234 amdgpu_drv_delayed_reset_work_handler, 0),
235};
236int amdgpu_ras_enable = -1;
237uint amdgpu_ras_mask = 0xffffffff;
238int amdgpu_bad_page_threshold = -1;
239struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
240 .timeout_fatal_disable = false,
241 .period = 0x0, /* default to 0x0 (timeout disable) */
242};
243
244/**
245 * DOC: vramlimit (int)
246 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
247 */
248MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
249module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
250
251/**
252 * DOC: vis_vramlimit (int)
253 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
254 */
255MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
256module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
257
258/**
259 * DOC: gartsize (uint)
260 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing.
261 * The default is -1 (The size depends on asic).
262 */
263MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");
264module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
265
266/**
267 * DOC: gttsize (int)
268 * Restrict the size of GTT domain (for userspace use) in MiB for testing.
269 * The default is -1 (Use 1/2 RAM, minimum value is 3GB).
270 */
271MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
272module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
273
274/**
275 * DOC: moverate (int)
276 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
277 */
278MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
279module_param_named(moverate, amdgpu_moverate, int, 0600);
280
281/**
282 * DOC: audio (int)
283 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
284 */
285MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
286module_param_named(audio, amdgpu_audio, int, 0444);
287
288/**
289 * DOC: disp_priority (int)
290 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
291 */
292MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
293module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
294
295/**
296 * DOC: hw_i2c (int)
297 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
298 */
299MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
300module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
301
302/**
303 * DOC: pcie_gen2 (int)
304 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
305 */
306MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
307module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
308
309/**
310 * DOC: msi (int)
311 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
312 */
313MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
314module_param_named(msi, amdgpu_msi, int, 0444);
315
316/**
317 * DOC: lockup_timeout (string)
318 * Set GPU scheduler timeout value in ms.
319 *
320 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
321 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
322 * to the default timeout.
323 *
324 * - With one value specified, the setting will apply to all non-compute jobs.
325 * - With multiple values specified, the first one will be for GFX.
326 * The second one is for Compute. The third and fourth ones are
327 * for SDMA and Video.
328 *
329 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
330 * jobs is 10000. The timeout for compute is 60000.
331 */
332MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
333 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
334 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
335module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
336
337/**
338 * DOC: dpm (int)
339 * Override for dynamic power management setting
340 * (0 = disable, 1 = enable)
341 * The default is -1 (auto).
342 */
343MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
344module_param_named(dpm, amdgpu_dpm, int, 0444);
345
346/**
347 * DOC: fw_load_type (int)
348 * Set different firmware loading type for debugging, if supported.
349 * Set to 0 to force direct loading if supported by the ASIC. Set
350 * to -1 to select the default loading mode for the ASIC, as defined
351 * by the driver. The default is -1 (auto).
352 */
353MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
354module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
355
356/**
357 * DOC: aspm (int)
358 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
359 */
360MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
361module_param_named(aspm, amdgpu_aspm, int, 0444);
362
363/**
364 * DOC: runpm (int)
365 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
366 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
367 * Setting the value to 0 disables this functionality.
368 * Setting the value to -2 is auto enabled with power down when displays are attached.
369 */
370MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = autowith displays)");
371module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
372
373/**
374 * DOC: ip_block_mask (uint)
375 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
376 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
377 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
378 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
379 */
380MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
381module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
382
383/**
384 * DOC: bapm (int)
385 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
386 * The default -1 (auto, enabled)
387 */
388MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
389module_param_named(bapm, amdgpu_bapm, int, 0444);
390
391/**
392 * DOC: deep_color (int)
393 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
394 */
395MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
396module_param_named(deep_color, amdgpu_deep_color, int, 0444);
397
398/**
399 * DOC: vm_size (int)
400 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
401 */
402MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
403module_param_named(vm_size, amdgpu_vm_size, int, 0444);
404
405/**
406 * DOC: vm_fragment_size (int)
407 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
408 */
409MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
410module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
411
412/**
413 * DOC: vm_block_size (int)
414 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
415 */
416MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
417module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
418
419/**
420 * DOC: vm_fault_stop (int)
421 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
422 */
423MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
424module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
425
426/**
427 * DOC: vm_update_mode (int)
428 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
429 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
430 */
431MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
432module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
433
434/**
435 * DOC: exp_hw_support (int)
436 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
437 */
438MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
439module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
440
441/**
442 * DOC: dc (int)
443 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
444 */
445MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
446module_param_named(dc, amdgpu_dc, int, 0444);
447
448/**
449 * DOC: sched_jobs (int)
450 * Override the max number of jobs supported in the sw queue. The default is 32.
451 */
452MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
453module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
454
455/**
456 * DOC: sched_hw_submission (int)
457 * Override the max number of HW submissions. The default is 2.
458 */
459MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
460module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
461
462/**
463 * DOC: ppfeaturemask (hexint)
464 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
465 * The default is the current set of stable power features.
466 */
467MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
468module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
469
470/**
471 * DOC: forcelongtraining (uint)
472 * Force long memory training in resume.
473 * The default is zero, indicates short training in resume.
474 */
475MODULE_PARM_DESC(forcelongtraining, "force memory long training");
476module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
477
478/**
479 * DOC: pcie_gen_cap (uint)
480 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
481 * The default is 0 (automatic for each asic).
482 */
483MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
484module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
485
486/**
487 * DOC: pcie_lane_cap (uint)
488 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
489 * The default is 0 (automatic for each asic).
490 */
491MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
492module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
493
494/**
495 * DOC: cg_mask (ullong)
496 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
497 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
498 */
499MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
500module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
501
502/**
503 * DOC: pg_mask (uint)
504 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
505 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
506 */
507MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
508module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
509
510/**
511 * DOC: sdma_phase_quantum (uint)
512 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
513 */
514MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
515module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
516
517/**
518 * DOC: disable_cu (charp)
519 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
520 */
521MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
522module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
523
524/**
525 * DOC: virtual_display (charp)
526 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
527 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
528 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
529 * device at 26:00.0. The default is NULL.
530 */
531MODULE_PARM_DESC(virtual_display,
532 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
533module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
534
535/**
536 * DOC: lbpw (int)
537 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
538 */
539MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
540module_param_named(lbpw, amdgpu_lbpw, int, 0444);
541
542MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
543module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
544
545/**
546 * DOC: gpu_recovery (int)
547 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
548 */
549MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
550module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
551
552/**
553 * DOC: emu_mode (int)
554 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
555 */
556MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
557module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
558
559/**
560 * DOC: ras_enable (int)
561 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
562 */
563MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
564module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
565
566/**
567 * DOC: ras_mask (uint)
568 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
569 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
570 */
571MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
572module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
573
574/**
575 * DOC: timeout_fatal_disable (bool)
576 * Disable Watchdog timeout fatal error event
577 */
578MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
579module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
580
581/**
582 * DOC: timeout_period (uint)
583 * Modify the watchdog timeout max_cycles as (1 << period)
584 */
585MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
586module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
587
588/**
589 * DOC: si_support (int)
590 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
591 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
592 * otherwise using amdgpu driver.
593 */
594#ifdef CONFIG_DRM_AMDGPU_SI
595
596#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
597int amdgpu_si_support = 0;
598MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
599#else
600int amdgpu_si_support = 1;
601MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
602#endif
603
604module_param_named(si_support, amdgpu_si_support, int, 0444);
605#endif
606
607/**
608 * DOC: cik_support (int)
609 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
610 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
611 * otherwise using amdgpu driver.
612 */
613#ifdef CONFIG_DRM_AMDGPU_CIK
614
615#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
616int amdgpu_cik_support = 0;
617MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
618#else
619int amdgpu_cik_support = 1;
620MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
621#endif
622
623module_param_named(cik_support, amdgpu_cik_support, int, 0444);
624#endif
625
626/**
627 * DOC: smu_memory_pool_size (uint)
628 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
629 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
630 */
631MODULE_PARM_DESC(smu_memory_pool_size,
632 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
633module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
634
635/**
636 * DOC: async_gfx_ring (int)
637 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
638 */
639MODULE_PARM_DESC(async_gfx_ring,
640 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
641module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
642
643/**
644 * DOC: mcbp (int)
645 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default))
646 */
647MODULE_PARM_DESC(mcbp,
648 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)");
649module_param_named(mcbp, amdgpu_mcbp, int, 0444);
650
651/**
652 * DOC: discovery (int)
653 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
654 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
655 */
656MODULE_PARM_DESC(discovery,
657 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
658module_param_named(discovery, amdgpu_discovery, int, 0444);
659
660/**
661 * DOC: mes (int)
662 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
663 * (0 = disabled (default), 1 = enabled)
664 */
665MODULE_PARM_DESC(mes,
666 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
667module_param_named(mes, amdgpu_mes, int, 0444);
668
669/**
670 * DOC: mes_kiq (int)
671 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
672 * (0 = disabled (default), 1 = enabled)
673 */
674MODULE_PARM_DESC(mes_kiq,
675 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
676module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);
677
678/**
679 * DOC: noretry (int)
680 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
681 * do not support per-process XNACK this also disables retry page faults.
682 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
683 */
684MODULE_PARM_DESC(noretry,
685 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
686module_param_named(noretry, amdgpu_noretry, int, 0644);
687
688/**
689 * DOC: force_asic_type (int)
690 * A non negative value used to specify the asic type for all supported GPUs.
691 */
692MODULE_PARM_DESC(force_asic_type,
693 "A non negative value used to specify the asic type for all supported GPUs");
694module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
695
696/**
697 * DOC: use_xgmi_p2p (int)
698 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
699 */
700MODULE_PARM_DESC(use_xgmi_p2p,
701 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
702module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
703
704
705#ifdef CONFIG_HSA_AMD
706/**
707 * DOC: sched_policy (int)
708 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
709 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
710 * assigns queues to HQDs.
711 */
712int sched_policy = KFD_SCHED_POLICY_HWS;
713module_param(sched_policy, int, 0444);
714MODULE_PARM_DESC(sched_policy,
715 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
716
717/**
718 * DOC: hws_max_conc_proc (int)
719 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
720 * number of VMIDs assigned to the HWS, which is also the default.
721 */
722int hws_max_conc_proc = -1;
723module_param(hws_max_conc_proc, int, 0444);
724MODULE_PARM_DESC(hws_max_conc_proc,
725 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
726
727/**
728 * DOC: cwsr_enable (int)
729 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
730 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
731 * disables it.
732 */
733int cwsr_enable = 1;
734module_param(cwsr_enable, int, 0444);
735MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
736
737/**
738 * DOC: max_num_of_queues_per_device (int)
739 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
740 * is 4096.
741 */
742int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
743module_param(max_num_of_queues_per_device, int, 0444);
744MODULE_PARM_DESC(max_num_of_queues_per_device,
745 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
746
747/**
748 * DOC: send_sigterm (int)
749 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
750 * but just print errors on dmesg. Setting 1 enables sending sigterm.
751 */
752int send_sigterm;
753module_param(send_sigterm, int, 0444);
754MODULE_PARM_DESC(send_sigterm,
755 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
756
757/**
758 * DOC: halt_if_hws_hang (int)
759 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
760 * Setting 1 enables halt on hang.
761 */
762int halt_if_hws_hang;
763module_param(halt_if_hws_hang, int, 0644);
764MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
765
766/**
767 * DOC: hws_gws_support(bool)
768 * Assume that HWS supports GWS barriers regardless of what firmware version
769 * check says. Default value: false (rely on MEC2 firmware version check).
770 */
771bool hws_gws_support;
772module_param(hws_gws_support, bool, 0444);
773MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
774
775/**
776 * DOC: queue_preemption_timeout_ms (int)
777 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
778 */
779int queue_preemption_timeout_ms = 9000;
780module_param(queue_preemption_timeout_ms, int, 0644);
781MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
782
783/**
784 * DOC: debug_evictions(bool)
785 * Enable extra debug messages to help determine the cause of evictions
786 */
787bool debug_evictions;
788module_param(debug_evictions, bool, 0644);
789MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
790
791/**
792 * DOC: no_system_mem_limit(bool)
793 * Disable system memory limit, to support multiple process shared memory
794 */
795bool no_system_mem_limit;
796module_param(no_system_mem_limit, bool, 0644);
797MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
798
799/**
800 * DOC: no_queue_eviction_on_vm_fault (int)
801 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
802 */
803int amdgpu_no_queue_eviction_on_vm_fault;
804MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
805module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
806#endif
807
808/**
809 * DOC: mtype_local (int)
810 */
811int amdgpu_mtype_local;
812MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)");
813module_param_named(mtype_local, amdgpu_mtype_local, int, 0444);
814
815/**
816 * DOC: pcie_p2p (bool)
817 * Enable PCIe P2P (requires large-BAR). Default value: true (on)
818 */
819#ifdef CONFIG_HSA_AMD_P2P
820bool pcie_p2p = true;
821module_param(pcie_p2p, bool, 0444);
822MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
823#endif
824
825/**
826 * DOC: dcfeaturemask (uint)
827 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
828 * The default is the current set of stable display features.
829 */
830MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
831module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
832
833/**
834 * DOC: dcdebugmask (uint)
835 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
836 */
837MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
838module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
839
840MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
841module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
842
843/**
844 * DOC: abmlevel (uint)
845 * Override the default ABM (Adaptive Backlight Management) level used for DC
846 * enabled hardware. Requires DMCU to be supported and loaded.
847 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
848 * default. Values 1-4 control the maximum allowable brightness reduction via
849 * the ABM algorithm, with 1 being the least reduction and 4 being the most
850 * reduction.
851 *
852 * Defaults to 0, or disabled. Userspace can still override this level later
853 * after boot.
854 */
855uint amdgpu_dm_abm_level;
856MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
857module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
858
859int amdgpu_backlight = -1;
860MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
861module_param_named(backlight, amdgpu_backlight, bint, 0444);
862
863/**
864 * DOC: damageclips (int)
865 * Enable or disable damage clips support. If damage clips support is disabled,
866 * we will force full frame updates, irrespective of what user space sends to
867 * us.
868 *
869 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected).
870 */
871MODULE_PARM_DESC(damageclips,
872 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))");
873module_param_named(damageclips, amdgpu_damage_clips, int, 0444);
874
875/**
876 * DOC: tmz (int)
877 * Trusted Memory Zone (TMZ) is a method to protect data being written
878 * to or read from memory.
879 *
880 * The default value: 0 (off). TODO: change to auto till it is completed.
881 */
882MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
883module_param_named(tmz, amdgpu_tmz, int, 0444);
884
885/**
886 * DOC: reset_method (int)
887 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
888 */
889MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
890module_param_named(reset_method, amdgpu_reset_method, int, 0444);
891
892/**
893 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
894 * threshold value of faulty pages detected by RAS ECC, which may
895 * result in the GPU entering bad status when the number of total
896 * faulty pages by ECC exceeds the threshold value.
897 */
898MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)");
899module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
900
901MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
902module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
903
904/**
905 * DOC: vcnfw_log (int)
906 * Enable vcnfw log output for debugging, the default is disabled.
907 */
908MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
909module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
910
911/**
912 * DOC: sg_display (int)
913 * Disable S/G (scatter/gather) display (i.e., display from system memory).
914 * This option is only relevant on APUs. Set this option to 0 to disable
915 * S/G display if you experience flickering or other issues under memory
916 * pressure and report the issue.
917 */
918MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
919module_param_named(sg_display, amdgpu_sg_display, int, 0444);
920
921/**
922 * DOC: umsch_mm (int)
923 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE.
924 * (0 = disabled (default), 1 = enabled)
925 */
926MODULE_PARM_DESC(umsch_mm,
927 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)");
928module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444);
929
930/**
931 * DOC: smu_pptable_id (int)
932 * Used to override pptable id. id = 0 use VBIOS pptable.
933 * id > 0 use the soft pptable with specicfied id.
934 */
935MODULE_PARM_DESC(smu_pptable_id,
936 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
937module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
938
939/**
940 * DOC: partition_mode (int)
941 * Used to override the default SPX mode.
942 */
943MODULE_PARM_DESC(
944 user_partt_mode,
945 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \
946 0 = AMDGPU_SPX_PARTITION_MODE, \
947 1 = AMDGPU_DPX_PARTITION_MODE, \
948 2 = AMDGPU_TPX_PARTITION_MODE, \
949 3 = AMDGPU_QPX_PARTITION_MODE, \
950 4 = AMDGPU_CPX_PARTITION_MODE)");
951module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444);
952
953
954/**
955 * DOC: enforce_isolation (bool)
956 * enforce process isolation between graphics and compute via using the same reserved vmid.
957 */
958module_param(enforce_isolation, bool, 0444);
959MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on");
960
961/**
962 * DOC: seamless (int)
963 * Seamless boot will keep the image on the screen during the boot process.
964 */
965MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)");
966module_param_named(seamless, amdgpu_seamless, int, 0444);
967
968/**
969 * DOC: debug_mask (uint)
970 * Debug options for amdgpu, work as a binary mask with the following options:
971 *
972 * - 0x1: Debug VM handling
973 * - 0x2: Enable simulating large-bar capability on non-large bar system. This
974 * limits the VRAM size reported to ROCm applications to the visible
975 * size, usually 256MB.
976 * - 0x4: Disable GPU soft recovery, always do a full reset
977 */
978MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default");
979module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444);
980
981/**
982 * DOC: agp (int)
983 * Enable the AGP aperture. This provides an aperture in the GPU's internal
984 * address space for direct access to system memory. Note that these accesses
985 * are non-snooped, so they are only used for access to uncached memory.
986 */
987MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)");
988module_param_named(agp, amdgpu_agp, int, 0444);
989
990/**
991 * DOC: wbrf (int)
992 * Enable Wifi RFI interference mitigation feature.
993 * Due to electrical and mechanical constraints there may be likely interference of
994 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio
995 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference,
996 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based
997 * on active list of frequencies in-use (to be avoided) as part of initial setting or
998 * P-state transition. However, there may be potential performance impact with this
999 * feature enabled.
1000 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported))
1001 */
1002MODULE_PARM_DESC(wbrf,
1003 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)");
1004module_param_named(wbrf, amdgpu_wbrf, int, 0444);
1005
1006/* These devices are not supported by amdgpu.
1007 * They are supported by the mach64, r128, radeon drivers
1008 */
1009static const u16 amdgpu_unsupported_pciidlist[] = {
1010 /* mach64 */
1011 0x4354,
1012 0x4358,
1013 0x4554,
1014 0x4742,
1015 0x4744,
1016 0x4749,
1017 0x474C,
1018 0x474D,
1019 0x474E,
1020 0x474F,
1021 0x4750,
1022 0x4751,
1023 0x4752,
1024 0x4753,
1025 0x4754,
1026 0x4755,
1027 0x4756,
1028 0x4757,
1029 0x4758,
1030 0x4759,
1031 0x475A,
1032 0x4C42,
1033 0x4C44,
1034 0x4C47,
1035 0x4C49,
1036 0x4C4D,
1037 0x4C4E,
1038 0x4C50,
1039 0x4C51,
1040 0x4C52,
1041 0x4C53,
1042 0x5654,
1043 0x5655,
1044 0x5656,
1045 /* r128 */
1046 0x4c45,
1047 0x4c46,
1048 0x4d46,
1049 0x4d4c,
1050 0x5041,
1051 0x5042,
1052 0x5043,
1053 0x5044,
1054 0x5045,
1055 0x5046,
1056 0x5047,
1057 0x5048,
1058 0x5049,
1059 0x504A,
1060 0x504B,
1061 0x504C,
1062 0x504D,
1063 0x504E,
1064 0x504F,
1065 0x5050,
1066 0x5051,
1067 0x5052,
1068 0x5053,
1069 0x5054,
1070 0x5055,
1071 0x5056,
1072 0x5057,
1073 0x5058,
1074 0x5245,
1075 0x5246,
1076 0x5247,
1077 0x524b,
1078 0x524c,
1079 0x534d,
1080 0x5446,
1081 0x544C,
1082 0x5452,
1083 /* radeon */
1084 0x3150,
1085 0x3151,
1086 0x3152,
1087 0x3154,
1088 0x3155,
1089 0x3E50,
1090 0x3E54,
1091 0x4136,
1092 0x4137,
1093 0x4144,
1094 0x4145,
1095 0x4146,
1096 0x4147,
1097 0x4148,
1098 0x4149,
1099 0x414A,
1100 0x414B,
1101 0x4150,
1102 0x4151,
1103 0x4152,
1104 0x4153,
1105 0x4154,
1106 0x4155,
1107 0x4156,
1108 0x4237,
1109 0x4242,
1110 0x4336,
1111 0x4337,
1112 0x4437,
1113 0x4966,
1114 0x4967,
1115 0x4A48,
1116 0x4A49,
1117 0x4A4A,
1118 0x4A4B,
1119 0x4A4C,
1120 0x4A4D,
1121 0x4A4E,
1122 0x4A4F,
1123 0x4A50,
1124 0x4A54,
1125 0x4B48,
1126 0x4B49,
1127 0x4B4A,
1128 0x4B4B,
1129 0x4B4C,
1130 0x4C57,
1131 0x4C58,
1132 0x4C59,
1133 0x4C5A,
1134 0x4C64,
1135 0x4C66,
1136 0x4C67,
1137 0x4E44,
1138 0x4E45,
1139 0x4E46,
1140 0x4E47,
1141 0x4E48,
1142 0x4E49,
1143 0x4E4A,
1144 0x4E4B,
1145 0x4E50,
1146 0x4E51,
1147 0x4E52,
1148 0x4E53,
1149 0x4E54,
1150 0x4E56,
1151 0x5144,
1152 0x5145,
1153 0x5146,
1154 0x5147,
1155 0x5148,
1156 0x514C,
1157 0x514D,
1158 0x5157,
1159 0x5158,
1160 0x5159,
1161 0x515A,
1162 0x515E,
1163 0x5460,
1164 0x5462,
1165 0x5464,
1166 0x5548,
1167 0x5549,
1168 0x554A,
1169 0x554B,
1170 0x554C,
1171 0x554D,
1172 0x554E,
1173 0x554F,
1174 0x5550,
1175 0x5551,
1176 0x5552,
1177 0x5554,
1178 0x564A,
1179 0x564B,
1180 0x564F,
1181 0x5652,
1182 0x5653,
1183 0x5657,
1184 0x5834,
1185 0x5835,
1186 0x5954,
1187 0x5955,
1188 0x5974,
1189 0x5975,
1190 0x5960,
1191 0x5961,
1192 0x5962,
1193 0x5964,
1194 0x5965,
1195 0x5969,
1196 0x5a41,
1197 0x5a42,
1198 0x5a61,
1199 0x5a62,
1200 0x5b60,
1201 0x5b62,
1202 0x5b63,
1203 0x5b64,
1204 0x5b65,
1205 0x5c61,
1206 0x5c63,
1207 0x5d48,
1208 0x5d49,
1209 0x5d4a,
1210 0x5d4c,
1211 0x5d4d,
1212 0x5d4e,
1213 0x5d4f,
1214 0x5d50,
1215 0x5d52,
1216 0x5d57,
1217 0x5e48,
1218 0x5e4a,
1219 0x5e4b,
1220 0x5e4c,
1221 0x5e4d,
1222 0x5e4f,
1223 0x6700,
1224 0x6701,
1225 0x6702,
1226 0x6703,
1227 0x6704,
1228 0x6705,
1229 0x6706,
1230 0x6707,
1231 0x6708,
1232 0x6709,
1233 0x6718,
1234 0x6719,
1235 0x671c,
1236 0x671d,
1237 0x671f,
1238 0x6720,
1239 0x6721,
1240 0x6722,
1241 0x6723,
1242 0x6724,
1243 0x6725,
1244 0x6726,
1245 0x6727,
1246 0x6728,
1247 0x6729,
1248 0x6738,
1249 0x6739,
1250 0x673e,
1251 0x6740,
1252 0x6741,
1253 0x6742,
1254 0x6743,
1255 0x6744,
1256 0x6745,
1257 0x6746,
1258 0x6747,
1259 0x6748,
1260 0x6749,
1261 0x674A,
1262 0x6750,
1263 0x6751,
1264 0x6758,
1265 0x6759,
1266 0x675B,
1267 0x675D,
1268 0x675F,
1269 0x6760,
1270 0x6761,
1271 0x6762,
1272 0x6763,
1273 0x6764,
1274 0x6765,
1275 0x6766,
1276 0x6767,
1277 0x6768,
1278 0x6770,
1279 0x6771,
1280 0x6772,
1281 0x6778,
1282 0x6779,
1283 0x677B,
1284 0x6840,
1285 0x6841,
1286 0x6842,
1287 0x6843,
1288 0x6849,
1289 0x684C,
1290 0x6850,
1291 0x6858,
1292 0x6859,
1293 0x6880,
1294 0x6888,
1295 0x6889,
1296 0x688A,
1297 0x688C,
1298 0x688D,
1299 0x6898,
1300 0x6899,
1301 0x689b,
1302 0x689c,
1303 0x689d,
1304 0x689e,
1305 0x68a0,
1306 0x68a1,
1307 0x68a8,
1308 0x68a9,
1309 0x68b0,
1310 0x68b8,
1311 0x68b9,
1312 0x68ba,
1313 0x68be,
1314 0x68bf,
1315 0x68c0,
1316 0x68c1,
1317 0x68c7,
1318 0x68c8,
1319 0x68c9,
1320 0x68d8,
1321 0x68d9,
1322 0x68da,
1323 0x68de,
1324 0x68e0,
1325 0x68e1,
1326 0x68e4,
1327 0x68e5,
1328 0x68e8,
1329 0x68e9,
1330 0x68f1,
1331 0x68f2,
1332 0x68f8,
1333 0x68f9,
1334 0x68fa,
1335 0x68fe,
1336 0x7100,
1337 0x7101,
1338 0x7102,
1339 0x7103,
1340 0x7104,
1341 0x7105,
1342 0x7106,
1343 0x7108,
1344 0x7109,
1345 0x710A,
1346 0x710B,
1347 0x710C,
1348 0x710E,
1349 0x710F,
1350 0x7140,
1351 0x7141,
1352 0x7142,
1353 0x7143,
1354 0x7144,
1355 0x7145,
1356 0x7146,
1357 0x7147,
1358 0x7149,
1359 0x714A,
1360 0x714B,
1361 0x714C,
1362 0x714D,
1363 0x714E,
1364 0x714F,
1365 0x7151,
1366 0x7152,
1367 0x7153,
1368 0x715E,
1369 0x715F,
1370 0x7180,
1371 0x7181,
1372 0x7183,
1373 0x7186,
1374 0x7187,
1375 0x7188,
1376 0x718A,
1377 0x718B,
1378 0x718C,
1379 0x718D,
1380 0x718F,
1381 0x7193,
1382 0x7196,
1383 0x719B,
1384 0x719F,
1385 0x71C0,
1386 0x71C1,
1387 0x71C2,
1388 0x71C3,
1389 0x71C4,
1390 0x71C5,
1391 0x71C6,
1392 0x71C7,
1393 0x71CD,
1394 0x71CE,
1395 0x71D2,
1396 0x71D4,
1397 0x71D5,
1398 0x71D6,
1399 0x71DA,
1400 0x71DE,
1401 0x7200,
1402 0x7210,
1403 0x7211,
1404 0x7240,
1405 0x7243,
1406 0x7244,
1407 0x7245,
1408 0x7246,
1409 0x7247,
1410 0x7248,
1411 0x7249,
1412 0x724A,
1413 0x724B,
1414 0x724C,
1415 0x724D,
1416 0x724E,
1417 0x724F,
1418 0x7280,
1419 0x7281,
1420 0x7283,
1421 0x7284,
1422 0x7287,
1423 0x7288,
1424 0x7289,
1425 0x728B,
1426 0x728C,
1427 0x7290,
1428 0x7291,
1429 0x7293,
1430 0x7297,
1431 0x7834,
1432 0x7835,
1433 0x791e,
1434 0x791f,
1435 0x793f,
1436 0x7941,
1437 0x7942,
1438 0x796c,
1439 0x796d,
1440 0x796e,
1441 0x796f,
1442 0x9400,
1443 0x9401,
1444 0x9402,
1445 0x9403,
1446 0x9405,
1447 0x940A,
1448 0x940B,
1449 0x940F,
1450 0x94A0,
1451 0x94A1,
1452 0x94A3,
1453 0x94B1,
1454 0x94B3,
1455 0x94B4,
1456 0x94B5,
1457 0x94B9,
1458 0x9440,
1459 0x9441,
1460 0x9442,
1461 0x9443,
1462 0x9444,
1463 0x9446,
1464 0x944A,
1465 0x944B,
1466 0x944C,
1467 0x944E,
1468 0x9450,
1469 0x9452,
1470 0x9456,
1471 0x945A,
1472 0x945B,
1473 0x945E,
1474 0x9460,
1475 0x9462,
1476 0x946A,
1477 0x946B,
1478 0x947A,
1479 0x947B,
1480 0x9480,
1481 0x9487,
1482 0x9488,
1483 0x9489,
1484 0x948A,
1485 0x948F,
1486 0x9490,
1487 0x9491,
1488 0x9495,
1489 0x9498,
1490 0x949C,
1491 0x949E,
1492 0x949F,
1493 0x94C0,
1494 0x94C1,
1495 0x94C3,
1496 0x94C4,
1497 0x94C5,
1498 0x94C6,
1499 0x94C7,
1500 0x94C8,
1501 0x94C9,
1502 0x94CB,
1503 0x94CC,
1504 0x94CD,
1505 0x9500,
1506 0x9501,
1507 0x9504,
1508 0x9505,
1509 0x9506,
1510 0x9507,
1511 0x9508,
1512 0x9509,
1513 0x950F,
1514 0x9511,
1515 0x9515,
1516 0x9517,
1517 0x9519,
1518 0x9540,
1519 0x9541,
1520 0x9542,
1521 0x954E,
1522 0x954F,
1523 0x9552,
1524 0x9553,
1525 0x9555,
1526 0x9557,
1527 0x955f,
1528 0x9580,
1529 0x9581,
1530 0x9583,
1531 0x9586,
1532 0x9587,
1533 0x9588,
1534 0x9589,
1535 0x958A,
1536 0x958B,
1537 0x958C,
1538 0x958D,
1539 0x958E,
1540 0x958F,
1541 0x9590,
1542 0x9591,
1543 0x9593,
1544 0x9595,
1545 0x9596,
1546 0x9597,
1547 0x9598,
1548 0x9599,
1549 0x959B,
1550 0x95C0,
1551 0x95C2,
1552 0x95C4,
1553 0x95C5,
1554 0x95C6,
1555 0x95C7,
1556 0x95C9,
1557 0x95CC,
1558 0x95CD,
1559 0x95CE,
1560 0x95CF,
1561 0x9610,
1562 0x9611,
1563 0x9612,
1564 0x9613,
1565 0x9614,
1566 0x9615,
1567 0x9616,
1568 0x9640,
1569 0x9641,
1570 0x9642,
1571 0x9643,
1572 0x9644,
1573 0x9645,
1574 0x9647,
1575 0x9648,
1576 0x9649,
1577 0x964a,
1578 0x964b,
1579 0x964c,
1580 0x964e,
1581 0x964f,
1582 0x9710,
1583 0x9711,
1584 0x9712,
1585 0x9713,
1586 0x9714,
1587 0x9715,
1588 0x9802,
1589 0x9803,
1590 0x9804,
1591 0x9805,
1592 0x9806,
1593 0x9807,
1594 0x9808,
1595 0x9809,
1596 0x980A,
1597 0x9900,
1598 0x9901,
1599 0x9903,
1600 0x9904,
1601 0x9905,
1602 0x9906,
1603 0x9907,
1604 0x9908,
1605 0x9909,
1606 0x990A,
1607 0x990B,
1608 0x990C,
1609 0x990D,
1610 0x990E,
1611 0x990F,
1612 0x9910,
1613 0x9913,
1614 0x9917,
1615 0x9918,
1616 0x9919,
1617 0x9990,
1618 0x9991,
1619 0x9992,
1620 0x9993,
1621 0x9994,
1622 0x9995,
1623 0x9996,
1624 0x9997,
1625 0x9998,
1626 0x9999,
1627 0x999A,
1628 0x999B,
1629 0x999C,
1630 0x999D,
1631 0x99A0,
1632 0x99A2,
1633 0x99A4,
1634 /* radeon secondary ids */
1635 0x3171,
1636 0x3e70,
1637 0x4164,
1638 0x4165,
1639 0x4166,
1640 0x4168,
1641 0x4170,
1642 0x4171,
1643 0x4172,
1644 0x4173,
1645 0x496e,
1646 0x4a69,
1647 0x4a6a,
1648 0x4a6b,
1649 0x4a70,
1650 0x4a74,
1651 0x4b69,
1652 0x4b6b,
1653 0x4b6c,
1654 0x4c6e,
1655 0x4e64,
1656 0x4e65,
1657 0x4e66,
1658 0x4e67,
1659 0x4e68,
1660 0x4e69,
1661 0x4e6a,
1662 0x4e71,
1663 0x4f73,
1664 0x5569,
1665 0x556b,
1666 0x556d,
1667 0x556f,
1668 0x5571,
1669 0x5854,
1670 0x5874,
1671 0x5940,
1672 0x5941,
1673 0x5b70,
1674 0x5b72,
1675 0x5b73,
1676 0x5b74,
1677 0x5b75,
1678 0x5d44,
1679 0x5d45,
1680 0x5d6d,
1681 0x5d6f,
1682 0x5d72,
1683 0x5d77,
1684 0x5e6b,
1685 0x5e6d,
1686 0x7120,
1687 0x7124,
1688 0x7129,
1689 0x712e,
1690 0x712f,
1691 0x7162,
1692 0x7163,
1693 0x7166,
1694 0x7167,
1695 0x7172,
1696 0x7173,
1697 0x71a0,
1698 0x71a1,
1699 0x71a3,
1700 0x71a7,
1701 0x71bb,
1702 0x71e0,
1703 0x71e1,
1704 0x71e2,
1705 0x71e6,
1706 0x71e7,
1707 0x71f2,
1708 0x7269,
1709 0x726b,
1710 0x726e,
1711 0x72a0,
1712 0x72a8,
1713 0x72b1,
1714 0x72b3,
1715 0x793f,
1716};
1717
1718static const struct pci_device_id pciidlist[] = {
1719#ifdef CONFIG_DRM_AMDGPU_SI
1720 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1721 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1722 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1723 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1724 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1725 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1726 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1727 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1728 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1729 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1730 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1731 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1732 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1733 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1734 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1735 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1736 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1737 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1738 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1739 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1740 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1741 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1742 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1743 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1744 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1745 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1746 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1747 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1748 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1749 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1750 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1751 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1752 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1753 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1754 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1755 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1756 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1757 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1758 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1759 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1760 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1761 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1762 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1763 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1764 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1765 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1766 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1767 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1768 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1769 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1770 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1771 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1772 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1773 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1774 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1775 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1776 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1777 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1778 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1779 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1780 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1781 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1782 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1783 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1784 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1785 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1786 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1787 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1788 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1789 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1790 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1791 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1792#endif
1793#ifdef CONFIG_DRM_AMDGPU_CIK
1794 /* Kaveri */
1795 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1796 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1797 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1798 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1799 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1800 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1801 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1802 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1803 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1804 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1805 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1806 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1807 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1808 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1809 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1810 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1811 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1812 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1813 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1814 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1815 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1816 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1817 /* Bonaire */
1818 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1819 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1820 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1821 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1822 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1823 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1824 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1825 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1826 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1827 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1828 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1829 /* Hawaii */
1830 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1831 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1832 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1833 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1834 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1835 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1836 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1837 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1838 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1839 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1840 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1841 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1842 /* Kabini */
1843 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1844 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1845 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1846 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1847 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1848 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1849 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1850 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1851 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1852 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1853 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1854 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1855 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1856 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1857 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1858 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1859 /* mullins */
1860 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1861 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1862 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1863 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1864 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1865 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1866 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1867 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1868 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1869 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1870 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1871 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1872 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1873 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1874 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1875 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1876#endif
1877 /* topaz */
1878 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1879 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1880 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1881 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1882 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1883 /* tonga */
1884 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1885 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1886 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1887 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1888 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1889 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1890 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1891 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1892 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1893 /* fiji */
1894 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1895 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1896 /* carrizo */
1897 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1898 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1899 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1900 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1901 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1902 /* stoney */
1903 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
1904 /* Polaris11 */
1905 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1906 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1907 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1908 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1909 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1910 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1911 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1912 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1913 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1914 /* Polaris10 */
1915 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1916 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1917 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1918 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1919 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1920 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1921 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1922 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1923 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1924 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1925 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1926 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1927 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1928 /* Polaris12 */
1929 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1930 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1931 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1932 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1933 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1934 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1935 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1936 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1937 /* VEGAM */
1938 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1939 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1940 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1941 /* Vega 10 */
1942 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1943 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1944 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1945 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1946 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1947 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1948 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1949 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1950 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1951 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1952 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1953 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1954 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1955 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1956 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1957 /* Vega 12 */
1958 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1959 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1960 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1961 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1962 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1963 /* Vega 20 */
1964 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1965 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1966 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1967 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1968 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1969 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1970 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1971 /* Raven */
1972 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1973 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1974 /* Arcturus */
1975 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1976 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1977 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1978 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1979 /* Navi10 */
1980 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1981 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1982 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1983 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1984 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1985 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1986 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1987 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1988 /* Navi14 */
1989 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1990 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1991 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1992 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1993
1994 /* Renoir */
1995 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1996 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1997 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1998 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1999
2000 /* Navi12 */
2001 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
2002 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
2003
2004 /* Sienna_Cichlid */
2005 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2006 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2007 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2008 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2009 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2010 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2011 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2012 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2013 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2014 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2015 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2016 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2017 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2018
2019 /* Yellow Carp */
2020 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
2021 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
2022
2023 /* Navy_Flounder */
2024 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2025 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2026 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2027 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2028 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2029 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2030 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2031 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2032 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2033
2034 /* DIMGREY_CAVEFISH */
2035 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2036 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2037 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2038 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2039 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2040 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2041 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2042 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2043 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2044 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2045 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2046 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2047
2048 /* Aldebaran */
2049 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2050 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2051 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2052 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2053
2054 /* CYAN_SKILLFISH */
2055 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2056 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2057
2058 /* BEIGE_GOBY */
2059 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2060 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2061 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2062 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2063 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2064 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2065
2066 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2067 .class = PCI_CLASS_DISPLAY_VGA << 8,
2068 .class_mask = 0xffffff,
2069 .driver_data = CHIP_IP_DISCOVERY },
2070
2071 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2072 .class = PCI_CLASS_DISPLAY_OTHER << 8,
2073 .class_mask = 0xffffff,
2074 .driver_data = CHIP_IP_DISCOVERY },
2075
2076 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2077 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8,
2078 .class_mask = 0xffffff,
2079 .driver_data = CHIP_IP_DISCOVERY },
2080
2081 {0, 0, 0}
2082};
2083
2084MODULE_DEVICE_TABLE(pci, pciidlist);
2085
2086static const struct amdgpu_asic_type_quirk asic_type_quirks[] = {
2087 /* differentiate between P10 and P11 asics with the same DID */
2088 {0x67FF, 0xE3, CHIP_POLARIS10},
2089 {0x67FF, 0xE7, CHIP_POLARIS10},
2090 {0x67FF, 0xF3, CHIP_POLARIS10},
2091 {0x67FF, 0xF7, CHIP_POLARIS10},
2092};
2093
2094static const struct drm_driver amdgpu_kms_driver;
2095
2096static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
2097{
2098 struct pci_dev *p = NULL;
2099 int i;
2100
2101 /* 0 - GPU
2102 * 1 - audio
2103 * 2 - USB
2104 * 3 - UCSI
2105 */
2106 for (i = 1; i < 4; i++) {
2107 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
2108 adev->pdev->bus->number, i);
2109 if (p) {
2110 pm_runtime_get_sync(&p->dev);
2111 pm_runtime_mark_last_busy(&p->dev);
2112 pm_runtime_put_autosuspend(&p->dev);
2113 pci_dev_put(p);
2114 }
2115 }
2116}
2117
2118static void amdgpu_init_debug_options(struct amdgpu_device *adev)
2119{
2120 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) {
2121 pr_info("debug: VM handling debug enabled\n");
2122 adev->debug_vm = true;
2123 }
2124
2125 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) {
2126 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n");
2127 adev->debug_largebar = true;
2128 }
2129
2130 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) {
2131 pr_info("debug: soft reset for GPU recovery disabled\n");
2132 adev->debug_disable_soft_recovery = true;
2133 }
2134
2135 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) {
2136 pr_info("debug: place fw in vram for frontdoor loading\n");
2137 adev->debug_use_vram_fw_buf = true;
2138 }
2139}
2140
2141static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)
2142{
2143 int i;
2144
2145 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) {
2146 if (pdev->device == asic_type_quirks[i].device &&
2147 pdev->revision == asic_type_quirks[i].revision) {
2148 flags &= ~AMD_ASIC_MASK;
2149 flags |= asic_type_quirks[i].type;
2150 break;
2151 }
2152 }
2153
2154 return flags;
2155}
2156
2157static int amdgpu_pci_probe(struct pci_dev *pdev,
2158 const struct pci_device_id *ent)
2159{
2160 struct drm_device *ddev;
2161 struct amdgpu_device *adev;
2162 unsigned long flags = ent->driver_data;
2163 int ret, retry = 0, i;
2164 bool supports_atomic = false;
2165
2166 /* skip devices which are owned by radeon */
2167 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2168 if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2169 return -ENODEV;
2170 }
2171
2172 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2173 amdgpu_aspm = 0;
2174
2175 if (amdgpu_virtual_display ||
2176 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2177 supports_atomic = true;
2178
2179 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
2180 DRM_INFO("This hardware requires experimental hardware support.\n"
2181 "See modparam exp_hw_support\n");
2182 return -ENODEV;
2183 }
2184
2185 flags = amdgpu_fix_asic_type(pdev, flags);
2186
2187 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2188 * however, SME requires an indirect IOMMU mapping because the encryption
2189 * bit is beyond the DMA mask of the chip.
2190 */
2191 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2192 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
2193 dev_info(&pdev->dev,
2194 "SME is not compatible with RAVEN\n");
2195 return -ENOTSUPP;
2196 }
2197
2198#ifdef CONFIG_DRM_AMDGPU_SI
2199 if (!amdgpu_si_support) {
2200 switch (flags & AMD_ASIC_MASK) {
2201 case CHIP_TAHITI:
2202 case CHIP_PITCAIRN:
2203 case CHIP_VERDE:
2204 case CHIP_OLAND:
2205 case CHIP_HAINAN:
2206 dev_info(&pdev->dev,
2207 "SI support provided by radeon.\n");
2208 dev_info(&pdev->dev,
2209 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2210 );
2211 return -ENODEV;
2212 }
2213 }
2214#endif
2215#ifdef CONFIG_DRM_AMDGPU_CIK
2216 if (!amdgpu_cik_support) {
2217 switch (flags & AMD_ASIC_MASK) {
2218 case CHIP_KAVERI:
2219 case CHIP_BONAIRE:
2220 case CHIP_HAWAII:
2221 case CHIP_KABINI:
2222 case CHIP_MULLINS:
2223 dev_info(&pdev->dev,
2224 "CIK support provided by radeon.\n");
2225 dev_info(&pdev->dev,
2226 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2227 );
2228 return -ENODEV;
2229 }
2230 }
2231#endif
2232
2233 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
2234 if (IS_ERR(adev))
2235 return PTR_ERR(adev);
2236
2237 adev->dev = &pdev->dev;
2238 adev->pdev = pdev;
2239 ddev = adev_to_drm(adev);
2240
2241 if (!supports_atomic)
2242 ddev->driver_features &= ~DRIVER_ATOMIC;
2243
2244 ret = pci_enable_device(pdev);
2245 if (ret)
2246 return ret;
2247
2248 pci_set_drvdata(pdev, ddev);
2249
2250 amdgpu_init_debug_options(adev);
2251
2252 ret = amdgpu_driver_load_kms(adev, flags);
2253 if (ret)
2254 goto err_pci;
2255
2256retry_init:
2257 ret = drm_dev_register(ddev, flags);
2258 if (ret == -EAGAIN && ++retry <= 3) {
2259 DRM_INFO("retry init %d\n", retry);
2260 /* Don't request EX mode too frequently which is attacking */
2261 msleep(5000);
2262 goto retry_init;
2263 } else if (ret) {
2264 goto err_pci;
2265 }
2266
2267 ret = amdgpu_xcp_dev_register(adev, ent);
2268 if (ret)
2269 goto err_pci;
2270
2271 ret = amdgpu_amdkfd_drm_client_create(adev);
2272 if (ret)
2273 goto err_pci;
2274
2275 /*
2276 * 1. don't init fbdev on hw without DCE
2277 * 2. don't init fbdev if there are no connectors
2278 */
2279 if (adev->mode_info.mode_config_initialized &&
2280 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2281 /* select 8 bpp console on low vram cards */
2282 if (adev->gmc.real_vram_size <= (32*1024*1024))
2283 drm_fbdev_generic_setup(adev_to_drm(adev), 8);
2284 else
2285 drm_fbdev_generic_setup(adev_to_drm(adev), 32);
2286 }
2287
2288 ret = amdgpu_debugfs_init(adev);
2289 if (ret)
2290 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2291
2292 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2293 /* only need to skip on ATPX */
2294 if (amdgpu_device_supports_px(ddev))
2295 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2296 /* we want direct complete for BOCO */
2297 if (amdgpu_device_supports_boco(ddev))
2298 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2299 DPM_FLAG_SMART_SUSPEND |
2300 DPM_FLAG_MAY_SKIP_RESUME);
2301 pm_runtime_use_autosuspend(ddev->dev);
2302 pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2303
2304 pm_runtime_allow(ddev->dev);
2305
2306 pm_runtime_mark_last_busy(ddev->dev);
2307 pm_runtime_put_autosuspend(ddev->dev);
2308
2309 pci_wake_from_d3(pdev, TRUE);
2310
2311 /*
2312 * For runpm implemented via BACO, PMFW will handle the
2313 * timing for BACO in and out:
2314 * - put ASIC into BACO state only when both video and
2315 * audio functions are in D3 state.
2316 * - pull ASIC out of BACO state when either video or
2317 * audio function is in D0 state.
2318 * Also, at startup, PMFW assumes both functions are in
2319 * D0 state.
2320 *
2321 * So if snd driver was loaded prior to amdgpu driver
2322 * and audio function was put into D3 state, there will
2323 * be no PMFW-aware D-state transition(D0->D3) on runpm
2324 * suspend. Thus the BACO will be not correctly kicked in.
2325 *
2326 * Via amdgpu_get_secondary_funcs(), the audio dev is put
2327 * into D0 state. Then there will be a PMFW-aware D-state
2328 * transition(D0->D3) on runpm suspend.
2329 */
2330 if (amdgpu_device_supports_baco(ddev) &&
2331 !(adev->flags & AMD_IS_APU) &&
2332 (adev->asic_type >= CHIP_NAVI10))
2333 amdgpu_get_secondary_funcs(adev);
2334 }
2335
2336 return 0;
2337
2338err_pci:
2339 pci_disable_device(pdev);
2340 return ret;
2341}
2342
2343static void
2344amdgpu_pci_remove(struct pci_dev *pdev)
2345{
2346 struct drm_device *dev = pci_get_drvdata(pdev);
2347 struct amdgpu_device *adev = drm_to_adev(dev);
2348
2349 amdgpu_xcp_dev_unplug(adev);
2350 drm_dev_unplug(dev);
2351
2352 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2353 pm_runtime_get_sync(dev->dev);
2354 pm_runtime_forbid(dev->dev);
2355 }
2356
2357 amdgpu_driver_unload_kms(dev);
2358
2359 /*
2360 * Flush any in flight DMA operations from device.
2361 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2362 * StatusTransactions Pending bit.
2363 */
2364 pci_disable_device(pdev);
2365 pci_wait_for_pending_transaction(pdev);
2366}
2367
2368static void
2369amdgpu_pci_shutdown(struct pci_dev *pdev)
2370{
2371 struct drm_device *dev = pci_get_drvdata(pdev);
2372 struct amdgpu_device *adev = drm_to_adev(dev);
2373
2374 if (amdgpu_ras_intr_triggered())
2375 return;
2376
2377 /* if we are running in a VM, make sure the device
2378 * torn down properly on reboot/shutdown.
2379 * unfortunately we can't detect certain
2380 * hypervisors so just do this all the time.
2381 */
2382 if (!amdgpu_passthrough(adev))
2383 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2384 amdgpu_device_ip_suspend(adev);
2385 adev->mp1_state = PP_MP1_STATE_NONE;
2386}
2387
2388/**
2389 * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2390 *
2391 * @work: work_struct.
2392 */
2393static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2394{
2395 struct list_head device_list;
2396 struct amdgpu_device *adev;
2397 int i, r;
2398 struct amdgpu_reset_context reset_context;
2399
2400 memset(&reset_context, 0, sizeof(reset_context));
2401
2402 mutex_lock(&mgpu_info.mutex);
2403 if (mgpu_info.pending_reset == true) {
2404 mutex_unlock(&mgpu_info.mutex);
2405 return;
2406 }
2407 mgpu_info.pending_reset = true;
2408 mutex_unlock(&mgpu_info.mutex);
2409
2410 /* Use a common context, just need to make sure full reset is done */
2411 reset_context.method = AMD_RESET_METHOD_NONE;
2412 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2413
2414 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2415 adev = mgpu_info.gpu_ins[i].adev;
2416 reset_context.reset_req_dev = adev;
2417 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
2418 if (r) {
2419 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2420 r, adev_to_drm(adev)->unique);
2421 }
2422 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2423 r = -EALREADY;
2424 }
2425 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2426 adev = mgpu_info.gpu_ins[i].adev;
2427 flush_work(&adev->xgmi_reset_work);
2428 adev->gmc.xgmi.pending_reset = false;
2429 }
2430
2431 /* reset function will rebuild the xgmi hive info , clear it now */
2432 for (i = 0; i < mgpu_info.num_dgpu; i++)
2433 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2434
2435 INIT_LIST_HEAD(&device_list);
2436
2437 for (i = 0; i < mgpu_info.num_dgpu; i++)
2438 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2439
2440 /* unregister the GPU first, reset function will add them back */
2441 list_for_each_entry(adev, &device_list, reset_list)
2442 amdgpu_unregister_gpu_instance(adev);
2443
2444 /* Use a common context, just need to make sure full reset is done */
2445 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2446 r = amdgpu_do_asic_reset(&device_list, &reset_context);
2447
2448 if (r) {
2449 DRM_ERROR("reinit gpus failure");
2450 return;
2451 }
2452 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2453 adev = mgpu_info.gpu_ins[i].adev;
2454 if (!adev->kfd.init_complete)
2455 amdgpu_amdkfd_device_init(adev);
2456 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2457 }
2458}
2459
2460static int amdgpu_pmops_prepare(struct device *dev)
2461{
2462 struct drm_device *drm_dev = dev_get_drvdata(dev);
2463 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2464
2465 /* Return a positive number here so
2466 * DPM_FLAG_SMART_SUSPEND works properly
2467 */
2468 if (amdgpu_device_supports_boco(drm_dev) &&
2469 pm_runtime_suspended(dev))
2470 return 1;
2471
2472 /* if we will not support s3 or s2i for the device
2473 * then skip suspend
2474 */
2475 if (!amdgpu_acpi_is_s0ix_active(adev) &&
2476 !amdgpu_acpi_is_s3_active(adev))
2477 return 1;
2478
2479 return amdgpu_device_prepare(drm_dev);
2480}
2481
2482static void amdgpu_pmops_complete(struct device *dev)
2483{
2484 /* nothing to do */
2485}
2486
2487static int amdgpu_pmops_suspend(struct device *dev)
2488{
2489 struct drm_device *drm_dev = dev_get_drvdata(dev);
2490 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2491
2492 adev->suspend_complete = false;
2493 if (amdgpu_acpi_is_s0ix_active(adev))
2494 adev->in_s0ix = true;
2495 else if (amdgpu_acpi_is_s3_active(adev))
2496 adev->in_s3 = true;
2497 if (!adev->in_s0ix && !adev->in_s3)
2498 return 0;
2499 return amdgpu_device_suspend(drm_dev, true);
2500}
2501
2502static int amdgpu_pmops_suspend_noirq(struct device *dev)
2503{
2504 struct drm_device *drm_dev = dev_get_drvdata(dev);
2505 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2506
2507 adev->suspend_complete = true;
2508 if (amdgpu_acpi_should_gpu_reset(adev))
2509 return amdgpu_asic_reset(adev);
2510
2511 return 0;
2512}
2513
2514static int amdgpu_pmops_resume(struct device *dev)
2515{
2516 struct drm_device *drm_dev = dev_get_drvdata(dev);
2517 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2518 int r;
2519
2520 if (!adev->in_s0ix && !adev->in_s3)
2521 return 0;
2522
2523 /* Avoids registers access if device is physically gone */
2524 if (!pci_device_is_present(adev->pdev))
2525 adev->no_hw_access = true;
2526
2527 r = amdgpu_device_resume(drm_dev, true);
2528 if (amdgpu_acpi_is_s0ix_active(adev))
2529 adev->in_s0ix = false;
2530 else
2531 adev->in_s3 = false;
2532 return r;
2533}
2534
2535static int amdgpu_pmops_freeze(struct device *dev)
2536{
2537 struct drm_device *drm_dev = dev_get_drvdata(dev);
2538 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2539 int r;
2540
2541 adev->in_s4 = true;
2542 r = amdgpu_device_suspend(drm_dev, true);
2543 adev->in_s4 = false;
2544 if (r)
2545 return r;
2546
2547 if (amdgpu_acpi_should_gpu_reset(adev))
2548 return amdgpu_asic_reset(adev);
2549 return 0;
2550}
2551
2552static int amdgpu_pmops_thaw(struct device *dev)
2553{
2554 struct drm_device *drm_dev = dev_get_drvdata(dev);
2555
2556 return amdgpu_device_resume(drm_dev, true);
2557}
2558
2559static int amdgpu_pmops_poweroff(struct device *dev)
2560{
2561 struct drm_device *drm_dev = dev_get_drvdata(dev);
2562
2563 return amdgpu_device_suspend(drm_dev, true);
2564}
2565
2566static int amdgpu_pmops_restore(struct device *dev)
2567{
2568 struct drm_device *drm_dev = dev_get_drvdata(dev);
2569
2570 return amdgpu_device_resume(drm_dev, true);
2571}
2572
2573static int amdgpu_runtime_idle_check_display(struct device *dev)
2574{
2575 struct pci_dev *pdev = to_pci_dev(dev);
2576 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2577 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2578
2579 if (adev->mode_info.num_crtc) {
2580 struct drm_connector *list_connector;
2581 struct drm_connector_list_iter iter;
2582 int ret = 0;
2583
2584 if (amdgpu_runtime_pm != -2) {
2585 /* XXX: Return busy if any displays are connected to avoid
2586 * possible display wakeups after runtime resume due to
2587 * hotplug events in case any displays were connected while
2588 * the GPU was in suspend. Remove this once that is fixed.
2589 */
2590 mutex_lock(&drm_dev->mode_config.mutex);
2591 drm_connector_list_iter_begin(drm_dev, &iter);
2592 drm_for_each_connector_iter(list_connector, &iter) {
2593 if (list_connector->status == connector_status_connected) {
2594 ret = -EBUSY;
2595 break;
2596 }
2597 }
2598 drm_connector_list_iter_end(&iter);
2599 mutex_unlock(&drm_dev->mode_config.mutex);
2600
2601 if (ret)
2602 return ret;
2603 }
2604
2605 if (adev->dc_enabled) {
2606 struct drm_crtc *crtc;
2607
2608 drm_for_each_crtc(crtc, drm_dev) {
2609 drm_modeset_lock(&crtc->mutex, NULL);
2610 if (crtc->state->active)
2611 ret = -EBUSY;
2612 drm_modeset_unlock(&crtc->mutex);
2613 if (ret < 0)
2614 break;
2615 }
2616 } else {
2617 mutex_lock(&drm_dev->mode_config.mutex);
2618 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2619
2620 drm_connector_list_iter_begin(drm_dev, &iter);
2621 drm_for_each_connector_iter(list_connector, &iter) {
2622 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2623 ret = -EBUSY;
2624 break;
2625 }
2626 }
2627
2628 drm_connector_list_iter_end(&iter);
2629
2630 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2631 mutex_unlock(&drm_dev->mode_config.mutex);
2632 }
2633 if (ret)
2634 return ret;
2635 }
2636
2637 return 0;
2638}
2639
2640static int amdgpu_pmops_runtime_suspend(struct device *dev)
2641{
2642 struct pci_dev *pdev = to_pci_dev(dev);
2643 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2644 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2645 int ret, i;
2646
2647 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2648 pm_runtime_forbid(dev);
2649 return -EBUSY;
2650 }
2651
2652 ret = amdgpu_runtime_idle_check_display(dev);
2653 if (ret)
2654 return ret;
2655
2656 /* wait for all rings to drain before suspending */
2657 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2658 struct amdgpu_ring *ring = adev->rings[i];
2659
2660 if (ring && ring->sched.ready) {
2661 ret = amdgpu_fence_wait_empty(ring);
2662 if (ret)
2663 return -EBUSY;
2664 }
2665 }
2666
2667 adev->in_runpm = true;
2668 if (amdgpu_device_supports_px(drm_dev))
2669 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2670
2671 /*
2672 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2673 * proper cleanups and put itself into a state ready for PNP. That
2674 * can address some random resuming failure observed on BOCO capable
2675 * platforms.
2676 * TODO: this may be also needed for PX capable platform.
2677 */
2678 if (amdgpu_device_supports_boco(drm_dev))
2679 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2680
2681 ret = amdgpu_device_prepare(drm_dev);
2682 if (ret)
2683 return ret;
2684 ret = amdgpu_device_suspend(drm_dev, false);
2685 if (ret) {
2686 adev->in_runpm = false;
2687 if (amdgpu_device_supports_boco(drm_dev))
2688 adev->mp1_state = PP_MP1_STATE_NONE;
2689 return ret;
2690 }
2691
2692 if (amdgpu_device_supports_boco(drm_dev))
2693 adev->mp1_state = PP_MP1_STATE_NONE;
2694
2695 if (amdgpu_device_supports_px(drm_dev)) {
2696 /* Only need to handle PCI state in the driver for ATPX
2697 * PCI core handles it for _PR3.
2698 */
2699 amdgpu_device_cache_pci_state(pdev);
2700 pci_disable_device(pdev);
2701 pci_ignore_hotplug(pdev);
2702 pci_set_power_state(pdev, PCI_D3cold);
2703 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
2704 } else if (amdgpu_device_supports_boco(drm_dev)) {
2705 /* nothing to do */
2706 } else if (amdgpu_device_supports_baco(drm_dev)) {
2707 amdgpu_device_baco_enter(drm_dev);
2708 }
2709
2710 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n");
2711
2712 return 0;
2713}
2714
2715static int amdgpu_pmops_runtime_resume(struct device *dev)
2716{
2717 struct pci_dev *pdev = to_pci_dev(dev);
2718 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2719 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2720 int ret;
2721
2722 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
2723 return -EINVAL;
2724
2725 /* Avoids registers access if device is physically gone */
2726 if (!pci_device_is_present(adev->pdev))
2727 adev->no_hw_access = true;
2728
2729 if (amdgpu_device_supports_px(drm_dev)) {
2730 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2731
2732 /* Only need to handle PCI state in the driver for ATPX
2733 * PCI core handles it for _PR3.
2734 */
2735 pci_set_power_state(pdev, PCI_D0);
2736 amdgpu_device_load_pci_state(pdev);
2737 ret = pci_enable_device(pdev);
2738 if (ret)
2739 return ret;
2740 pci_set_master(pdev);
2741 } else if (amdgpu_device_supports_boco(drm_dev)) {
2742 /* Only need to handle PCI state in the driver for ATPX
2743 * PCI core handles it for _PR3.
2744 */
2745 pci_set_master(pdev);
2746 } else if (amdgpu_device_supports_baco(drm_dev)) {
2747 amdgpu_device_baco_exit(drm_dev);
2748 }
2749 ret = amdgpu_device_resume(drm_dev, false);
2750 if (ret) {
2751 if (amdgpu_device_supports_px(drm_dev))
2752 pci_disable_device(pdev);
2753 return ret;
2754 }
2755
2756 if (amdgpu_device_supports_px(drm_dev))
2757 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
2758 adev->in_runpm = false;
2759 return 0;
2760}
2761
2762static int amdgpu_pmops_runtime_idle(struct device *dev)
2763{
2764 struct drm_device *drm_dev = dev_get_drvdata(dev);
2765 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2766 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2767 int ret = 1;
2768
2769 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2770 pm_runtime_forbid(dev);
2771 return -EBUSY;
2772 }
2773
2774 ret = amdgpu_runtime_idle_check_display(dev);
2775
2776 pm_runtime_mark_last_busy(dev);
2777 pm_runtime_autosuspend(dev);
2778 return ret;
2779}
2780
2781long amdgpu_drm_ioctl(struct file *filp,
2782 unsigned int cmd, unsigned long arg)
2783{
2784 struct drm_file *file_priv = filp->private_data;
2785 struct drm_device *dev;
2786 long ret;
2787
2788 dev = file_priv->minor->dev;
2789 ret = pm_runtime_get_sync(dev->dev);
2790 if (ret < 0)
2791 goto out;
2792
2793 ret = drm_ioctl(filp, cmd, arg);
2794
2795 pm_runtime_mark_last_busy(dev->dev);
2796out:
2797 pm_runtime_put_autosuspend(dev->dev);
2798 return ret;
2799}
2800
2801static const struct dev_pm_ops amdgpu_pm_ops = {
2802 .prepare = amdgpu_pmops_prepare,
2803 .complete = amdgpu_pmops_complete,
2804 .suspend = amdgpu_pmops_suspend,
2805 .suspend_noirq = amdgpu_pmops_suspend_noirq,
2806 .resume = amdgpu_pmops_resume,
2807 .freeze = amdgpu_pmops_freeze,
2808 .thaw = amdgpu_pmops_thaw,
2809 .poweroff = amdgpu_pmops_poweroff,
2810 .restore = amdgpu_pmops_restore,
2811 .runtime_suspend = amdgpu_pmops_runtime_suspend,
2812 .runtime_resume = amdgpu_pmops_runtime_resume,
2813 .runtime_idle = amdgpu_pmops_runtime_idle,
2814};
2815
2816static int amdgpu_flush(struct file *f, fl_owner_t id)
2817{
2818 struct drm_file *file_priv = f->private_data;
2819 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
2820 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
2821
2822 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2823 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
2824
2825 return timeout >= 0 ? 0 : timeout;
2826}
2827
2828static const struct file_operations amdgpu_driver_kms_fops = {
2829 .owner = THIS_MODULE,
2830 .open = drm_open,
2831 .flush = amdgpu_flush,
2832 .release = drm_release,
2833 .unlocked_ioctl = amdgpu_drm_ioctl,
2834 .mmap = drm_gem_mmap,
2835 .poll = drm_poll,
2836 .read = drm_read,
2837#ifdef CONFIG_COMPAT
2838 .compat_ioctl = amdgpu_kms_compat_ioctl,
2839#endif
2840#ifdef CONFIG_PROC_FS
2841 .show_fdinfo = drm_show_fdinfo,
2842#endif
2843};
2844
2845int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2846{
2847 struct drm_file *file;
2848
2849 if (!filp)
2850 return -EINVAL;
2851
2852 if (filp->f_op != &amdgpu_driver_kms_fops)
2853 return -EINVAL;
2854
2855 file = filp->private_data;
2856 *fpriv = file->driver_priv;
2857 return 0;
2858}
2859
2860const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2861 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2862 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2863 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2864 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2865 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2866 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2867 /* KMS */
2868 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2869 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2870 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2871 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2872 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2873 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2874 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2875 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2876 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2877 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2878};
2879
2880static const struct drm_driver amdgpu_kms_driver = {
2881 .driver_features =
2882 DRIVER_ATOMIC |
2883 DRIVER_GEM |
2884 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2885 DRIVER_SYNCOBJ_TIMELINE,
2886 .open = amdgpu_driver_open_kms,
2887 .postclose = amdgpu_driver_postclose_kms,
2888 .lastclose = amdgpu_driver_lastclose_kms,
2889 .ioctls = amdgpu_ioctls_kms,
2890 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
2891 .dumb_create = amdgpu_mode_dumb_create,
2892 .dumb_map_offset = amdgpu_mode_dumb_mmap,
2893 .fops = &amdgpu_driver_kms_fops,
2894 .release = &amdgpu_driver_release_kms,
2895#ifdef CONFIG_PROC_FS
2896 .show_fdinfo = amdgpu_show_fdinfo,
2897#endif
2898
2899 .gem_prime_import = amdgpu_gem_prime_import,
2900
2901 .name = DRIVER_NAME,
2902 .desc = DRIVER_DESC,
2903 .date = DRIVER_DATE,
2904 .major = KMS_DRIVER_MAJOR,
2905 .minor = KMS_DRIVER_MINOR,
2906 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2907};
2908
2909const struct drm_driver amdgpu_partition_driver = {
2910 .driver_features =
2911 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ |
2912 DRIVER_SYNCOBJ_TIMELINE,
2913 .open = amdgpu_driver_open_kms,
2914 .postclose = amdgpu_driver_postclose_kms,
2915 .lastclose = amdgpu_driver_lastclose_kms,
2916 .ioctls = amdgpu_ioctls_kms,
2917 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
2918 .dumb_create = amdgpu_mode_dumb_create,
2919 .dumb_map_offset = amdgpu_mode_dumb_mmap,
2920 .fops = &amdgpu_driver_kms_fops,
2921 .release = &amdgpu_driver_release_kms,
2922
2923 .gem_prime_import = amdgpu_gem_prime_import,
2924
2925 .name = DRIVER_NAME,
2926 .desc = DRIVER_DESC,
2927 .date = DRIVER_DATE,
2928 .major = KMS_DRIVER_MAJOR,
2929 .minor = KMS_DRIVER_MINOR,
2930 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2931};
2932
2933static struct pci_error_handlers amdgpu_pci_err_handler = {
2934 .error_detected = amdgpu_pci_error_detected,
2935 .mmio_enabled = amdgpu_pci_mmio_enabled,
2936 .slot_reset = amdgpu_pci_slot_reset,
2937 .resume = amdgpu_pci_resume,
2938};
2939
2940static const struct attribute_group *amdgpu_sysfs_groups[] = {
2941 &amdgpu_vram_mgr_attr_group,
2942 &amdgpu_gtt_mgr_attr_group,
2943 &amdgpu_flash_attr_group,
2944 NULL,
2945};
2946
2947static struct pci_driver amdgpu_kms_pci_driver = {
2948 .name = DRIVER_NAME,
2949 .id_table = pciidlist,
2950 .probe = amdgpu_pci_probe,
2951 .remove = amdgpu_pci_remove,
2952 .shutdown = amdgpu_pci_shutdown,
2953 .driver.pm = &amdgpu_pm_ops,
2954 .err_handler = &amdgpu_pci_err_handler,
2955 .dev_groups = amdgpu_sysfs_groups,
2956};
2957
2958static int __init amdgpu_init(void)
2959{
2960 int r;
2961
2962 if (drm_firmware_drivers_only())
2963 return -EINVAL;
2964
2965 r = amdgpu_sync_init();
2966 if (r)
2967 goto error_sync;
2968
2969 r = amdgpu_fence_slab_init();
2970 if (r)
2971 goto error_fence;
2972
2973 DRM_INFO("amdgpu kernel modesetting enabled.\n");
2974 amdgpu_register_atpx_handler();
2975 amdgpu_acpi_detect();
2976
2977 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2978 amdgpu_amdkfd_init();
2979
2980 /* let modprobe override vga console setting */
2981 return pci_register_driver(&amdgpu_kms_pci_driver);
2982
2983error_fence:
2984 amdgpu_sync_fini();
2985
2986error_sync:
2987 return r;
2988}
2989
2990static void __exit amdgpu_exit(void)
2991{
2992 amdgpu_amdkfd_fini();
2993 pci_unregister_driver(&amdgpu_kms_pci_driver);
2994 amdgpu_unregister_atpx_handler();
2995 amdgpu_acpi_release();
2996 amdgpu_sync_fini();
2997 amdgpu_fence_slab_fini();
2998 mmu_notifier_synchronize();
2999 amdgpu_xcp_drv_release();
3000}
3001
3002module_init(amdgpu_init);
3003module_exit(amdgpu_exit);
3004
3005MODULE_AUTHOR(DRIVER_AUTHOR);
3006MODULE_DESCRIPTION(DRIVER_DESC);
3007MODULE_LICENSE("GPL and additional rights");