Loading...
1/*
2 * AMD64 class Memory Controller kernel module
3 *
4 * Copyright (c) 2009 SoftwareBitMaker.
5 * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
6 *
7 * This file may be distributed under the terms of the
8 * GNU General Public License.
9 */
10
11#include <linux/module.h>
12#include <linux/ctype.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/pci_ids.h>
16#include <linux/slab.h>
17#include <linux/mmzone.h>
18#include <linux/edac.h>
19#include <linux/bitfield.h>
20#include <asm/cpu_device_id.h>
21#include <asm/msr.h>
22#include "edac_module.h"
23#include "mce_amd.h"
24
25#define amd64_info(fmt, arg...) \
26 edac_printk(KERN_INFO, "amd64", fmt, ##arg)
27
28#define amd64_warn(fmt, arg...) \
29 edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg)
30
31#define amd64_err(fmt, arg...) \
32 edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg)
33
34#define amd64_mc_warn(mci, fmt, arg...) \
35 edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
36
37#define amd64_mc_err(mci, fmt, arg...) \
38 edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
39
40/*
41 * Throughout the comments in this code, the following terms are used:
42 *
43 * SysAddr, DramAddr, and InputAddr
44 *
45 * These terms come directly from the amd64 documentation
46 * (AMD publication #26094). They are defined as follows:
47 *
48 * SysAddr:
49 * This is a physical address generated by a CPU core or a device
50 * doing DMA. If generated by a CPU core, a SysAddr is the result of
51 * a virtual to physical address translation by the CPU core's address
52 * translation mechanism (MMU).
53 *
54 * DramAddr:
55 * A DramAddr is derived from a SysAddr by subtracting an offset that
56 * depends on which node the SysAddr maps to and whether the SysAddr
57 * is within a range affected by memory hoisting. The DRAM Base
58 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
59 * determine which node a SysAddr maps to.
60 *
61 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
62 * is within the range of addresses specified by this register, then
63 * a value x from the DHAR is subtracted from the SysAddr to produce a
64 * DramAddr. Here, x represents the base address for the node that
65 * the SysAddr maps to plus an offset due to memory hoisting. See
66 * section 3.4.8 and the comments in amd64_get_dram_hole_info() and
67 * sys_addr_to_dram_addr() below for more information.
68 *
69 * If the SysAddr is not affected by the DHAR then a value y is
70 * subtracted from the SysAddr to produce a DramAddr. Here, y is the
71 * base address for the node that the SysAddr maps to. See section
72 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
73 * information.
74 *
75 * InputAddr:
76 * A DramAddr is translated to an InputAddr before being passed to the
77 * memory controller for the node that the DramAddr is associated
78 * with. The memory controller then maps the InputAddr to a csrow.
79 * If node interleaving is not in use, then the InputAddr has the same
80 * value as the DramAddr. Otherwise, the InputAddr is produced by
81 * discarding the bits used for node interleaving from the DramAddr.
82 * See section 3.4.4 for more information.
83 *
84 * The memory controller for a given node uses its DRAM CS Base and
85 * DRAM CS Mask registers to map an InputAddr to a csrow. See
86 * sections 3.5.4 and 3.5.5 for more information.
87 */
88
89#define EDAC_MOD_STR "amd64_edac"
90
91/* Extended Model from CPUID, for CPU Revision numbers */
92#define K8_REV_D 1
93#define K8_REV_E 2
94#define K8_REV_F 4
95
96/* Hardware limit on ChipSelect rows per MC and processors per system */
97#define NUM_CHIPSELECTS 8
98#define DRAM_RANGES 8
99#define NUM_CONTROLLERS 12
100
101#define ON true
102#define OFF false
103
104/*
105 * PCI-defined configuration space registers
106 */
107#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
108#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
109#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
110#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
111#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
112#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
113#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
114#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
115#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
116#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
117
118/*
119 * Function 1 - Address Map
120 */
121#define DRAM_BASE_LO 0x40
122#define DRAM_LIMIT_LO 0x44
123
124/*
125 * F15 M30h D18F1x2[1C:00]
126 */
127#define DRAM_CONT_BASE 0x200
128#define DRAM_CONT_LIMIT 0x204
129
130/*
131 * F15 M30h D18F1x2[4C:40]
132 */
133#define DRAM_CONT_HIGH_OFF 0x240
134
135#define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
136#define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
137#define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
138
139#define DHAR 0xf0
140#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
141#define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
142#define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
143
144 /* NOTE: Extra mask bit vs K8 */
145#define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
146
147#define DCT_CFG_SEL 0x10C
148
149#define DRAM_LOCAL_NODE_BASE 0x120
150#define DRAM_LOCAL_NODE_LIM 0x124
151
152#define DRAM_BASE_HI 0x140
153#define DRAM_LIMIT_HI 0x144
154
155
156/*
157 * Function 2 - DRAM controller
158 */
159#define DCSB0 0x40
160#define DCSB1 0x140
161#define DCSB_CS_ENABLE BIT(0)
162
163#define DCSM0 0x60
164#define DCSM1 0x160
165
166#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
167#define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
168
169#define DRAM_CONTROL 0x78
170
171#define DBAM0 0x80
172#define DBAM1 0x180
173
174/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
175#define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF)
176
177#define DBAM_MAX_VALUE 11
178
179#define DCLR0 0x90
180#define DCLR1 0x190
181#define REVE_WIDTH_128 BIT(16)
182#define WIDTH_128 BIT(11)
183
184#define DCHR0 0x94
185#define DCHR1 0x194
186#define DDR3_MODE BIT(8)
187
188#define DCT_SEL_LO 0x110
189#define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
190#define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
191
192#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
193
194#define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
195#define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
196
197#define SWAP_INTLV_REG 0x10c
198
199#define DCT_SEL_HI 0x114
200
201#define F15H_M60H_SCRCTRL 0x1C8
202
203/*
204 * Function 3 - Misc Control
205 */
206#define NBCTL 0x40
207
208#define NBCFG 0x44
209#define NBCFG_CHIPKILL BIT(23)
210#define NBCFG_ECC_ENABLE BIT(22)
211
212/* F3x48: NBSL */
213#define F10_NBSL_EXT_ERR_ECC 0x8
214#define NBSL_PP_OBS 0x2
215
216#define SCRCTRL 0x58
217
218#define F10_ONLINE_SPARE 0xB0
219#define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
220#define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
221
222#define F10_NB_ARRAY_ADDR 0xB8
223#define F10_NB_ARRAY_DRAM BIT(31)
224
225/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
226#define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1)
227
228#define F10_NB_ARRAY_DATA 0xBC
229#define F10_NB_ARR_ECC_WR_REQ BIT(17)
230#define SET_NB_DRAM_INJECTION_WRITE(inj) \
231 (BIT(((inj.word) & 0xF) + 20) | \
232 F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
233#define SET_NB_DRAM_INJECTION_READ(inj) \
234 (BIT(((inj.word) & 0xF) + 20) | \
235 BIT(16) | inj.bit_map)
236
237
238#define NBCAP 0xE8
239#define NBCAP_CHIPKILL BIT(4)
240#define NBCAP_SECDED BIT(3)
241#define NBCAP_DCT_DUAL BIT(0)
242
243#define EXT_NB_MCA_CFG 0x180
244
245/* MSRs */
246#define MSR_MCGCTL_NBE BIT(4)
247
248/* F17h */
249
250/* F0: */
251#define DF_DHAR 0x104
252
253/* UMC CH register offsets */
254#define UMCCH_BASE_ADDR 0x0
255#define UMCCH_BASE_ADDR_SEC 0x10
256#define UMCCH_ADDR_MASK 0x20
257#define UMCCH_ADDR_MASK_SEC 0x28
258#define UMCCH_ADDR_MASK_SEC_DDR5 0x30
259#define UMCCH_ADDR_CFG 0x30
260#define UMCCH_ADDR_CFG_DDR5 0x40
261#define UMCCH_DIMM_CFG 0x80
262#define UMCCH_DIMM_CFG_DDR5 0x90
263#define UMCCH_UMC_CFG 0x100
264#define UMCCH_SDP_CTRL 0x104
265#define UMCCH_ECC_CTRL 0x14C
266#define UMCCH_ECC_BAD_SYMBOL 0xD90
267#define UMCCH_UMC_CAP 0xDF0
268#define UMCCH_UMC_CAP_HI 0xDF4
269
270/* UMC CH bitfields */
271#define UMC_ECC_CHIPKILL_CAP BIT(31)
272#define UMC_ECC_ENABLED BIT(30)
273
274#define UMC_SDP_INIT BIT(31)
275
276/* Error injection control structure */
277struct error_injection {
278 u32 section;
279 u32 word;
280 u32 bit_map;
281};
282
283/* low and high part of PCI config space regs */
284struct reg_pair {
285 u32 lo, hi;
286};
287
288/*
289 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
290 */
291struct dram_range {
292 struct reg_pair base;
293 struct reg_pair lim;
294};
295
296/* A DCT chip selects collection */
297struct chip_select {
298 u32 csbases[NUM_CHIPSELECTS];
299 u32 csbases_sec[NUM_CHIPSELECTS];
300 u8 b_cnt;
301
302 u32 csmasks[NUM_CHIPSELECTS];
303 u32 csmasks_sec[NUM_CHIPSELECTS];
304 u8 m_cnt;
305};
306
307struct amd64_umc {
308 u32 dimm_cfg; /* DIMM Configuration reg */
309 u32 umc_cfg; /* Configuration reg */
310 u32 sdp_ctrl; /* SDP Control reg */
311 u32 ecc_ctrl; /* DRAM ECC Control reg */
312 u32 umc_cap_hi; /* Capabilities High reg */
313
314 /* cache the dram_type */
315 enum mem_type dram_type;
316};
317
318struct amd64_family_flags {
319 /*
320 * Indicates that the system supports the new register offsets, etc.
321 * first introduced with Family 19h Model 10h.
322 */
323 __u64 zn_regs_v2 : 1,
324
325 __reserved : 63;
326};
327
328struct amd64_pvt {
329 struct low_ops *ops;
330
331 /* pci_device handles which we utilize */
332 struct pci_dev *F1, *F2, *F3;
333
334 u16 mc_node_id; /* MC index of this MC node */
335 u8 fam; /* CPU family */
336 u8 model; /* ... model */
337 u8 stepping; /* ... stepping */
338
339 int ext_model; /* extended model value of this node */
340
341 /* Raw registers */
342 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
343 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
344 u32 dchr0; /* DRAM Configuration High DCT0 reg */
345 u32 dchr1; /* DRAM Configuration High DCT1 reg */
346 u32 nbcap; /* North Bridge Capabilities */
347 u32 nbcfg; /* F10 North Bridge Configuration */
348 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
349 u32 dhar; /* DRAM Hoist reg */
350 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
351 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
352
353 /* one for each DCT/UMC */
354 struct chip_select csels[NUM_CONTROLLERS];
355
356 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
357 struct dram_range ranges[DRAM_RANGES];
358
359 u64 top_mem; /* top of memory below 4GB */
360 u64 top_mem2; /* top of memory above 4GB */
361
362 u32 dct_sel_lo; /* DRAM Controller Select Low */
363 u32 dct_sel_hi; /* DRAM Controller Select High */
364 u32 online_spare; /* On-Line spare Reg */
365 u32 gpu_umc_base; /* Base address used for channel selection on GPUs */
366
367 /* x4, x8, or x16 syndromes in use */
368 u8 ecc_sym_sz;
369
370 const char *ctl_name;
371 u16 f1_id, f2_id;
372 /* Maximum number of memory controllers per die/node. */
373 u8 max_mcs;
374
375 struct amd64_family_flags flags;
376 /* place to store error injection parameters prior to issue */
377 struct error_injection injection;
378
379 /*
380 * cache the dram_type
381 *
382 * NOTE: Don't use this for Family 17h and later.
383 * Use dram_type in struct amd64_umc instead.
384 */
385 enum mem_type dram_type;
386
387 struct amd64_umc *umc; /* UMC registers */
388};
389
390enum err_codes {
391 DECODE_OK = 0,
392 ERR_NODE = -1,
393 ERR_CSROW = -2,
394 ERR_CHANNEL = -3,
395 ERR_SYND = -4,
396 ERR_NORM_ADDR = -5,
397};
398
399struct err_info {
400 int err_code;
401 struct mem_ctl_info *src_mci;
402 int csrow;
403 int channel;
404 u16 syndrome;
405 u32 page;
406 u32 offset;
407};
408
409static inline u32 get_umc_base(u8 channel)
410{
411 /* chY: 0xY50000 */
412 return 0x50000 + (channel << 20);
413}
414
415static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
416{
417 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
418
419 if (boot_cpu_data.x86 == 0xf)
420 return addr;
421
422 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
423}
424
425static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
426{
427 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
428
429 if (boot_cpu_data.x86 == 0xf)
430 return lim;
431
432 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
433}
434
435static inline u16 extract_syndrome(u64 status)
436{
437 return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
438}
439
440static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
441{
442 if (pvt->fam == 0x15 && pvt->model >= 0x30)
443 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
444 ((pvt->dct_sel_lo >> 6) & 0x3);
445
446 return ((pvt)->dct_sel_lo >> 6) & 0x3;
447}
448/*
449 * per-node ECC settings descriptor
450 */
451struct ecc_settings {
452 u32 old_nbctl;
453 bool nbctl_valid;
454
455 struct flags {
456 unsigned long nb_mce_enable:1;
457 unsigned long nb_ecc_prev:1;
458 } flags;
459};
460
461/*
462 * Each of the PCI Device IDs types have their own set of hardware accessor
463 * functions and per device encoding/decoding logic.
464 */
465struct low_ops {
466 void (*map_sysaddr_to_csrow)(struct mem_ctl_info *mci, u64 sys_addr,
467 struct err_info *err);
468 int (*dbam_to_cs)(struct amd64_pvt *pvt, u8 dct,
469 unsigned int cs_mode, int cs_mask_nr);
470 int (*hw_info_get)(struct amd64_pvt *pvt);
471 bool (*ecc_enabled)(struct amd64_pvt *pvt);
472 void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci);
473 void (*dump_misc_regs)(struct amd64_pvt *pvt);
474 void (*get_err_info)(struct mce *m, struct err_info *err);
475};
476
477int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
478 u32 *val, const char *func);
479int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
480 u32 val, const char *func);
481
482#define amd64_read_pci_cfg(pdev, offset, val) \
483 __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
484
485#define amd64_write_pci_cfg(pdev, offset, val) \
486 __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
487
488#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
489
490/* Injection helpers */
491static inline void disable_caches(void *dummy)
492{
493 write_cr0(read_cr0() | X86_CR0_CD);
494 wbinvd();
495}
496
497static inline void enable_caches(void *dummy)
498{
499 write_cr0(read_cr0() & ~X86_CR0_CD);
500}
501
502static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
503{
504 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
505 u32 tmp;
506 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
507 return (u8) tmp & 0xF;
508 }
509 return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
510}
511
512static inline u8 dhar_valid(struct amd64_pvt *pvt)
513{
514 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
515 u32 tmp;
516 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
517 return (tmp >> 1) & BIT(0);
518 }
519 return (pvt)->dhar & BIT(0);
520}
521
522static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
523{
524 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
525 u32 tmp;
526 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
527 return (tmp >> 11) & 0x1FFF;
528 }
529 return (pvt)->dct_sel_lo & 0xFFFFF800;
530}
1/*
2 * AMD64 class Memory Controller kernel module
3 *
4 * Copyright (c) 2009 SoftwareBitMaker.
5 * Copyright (c) 2009 Advanced Micro Devices, Inc.
6 *
7 * This file may be distributed under the terms of the
8 * GNU General Public License.
9 *
10 * Originally Written by Thayne Harbaugh
11 *
12 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
13 * - K8 CPU Revision D and greater support
14 *
15 * Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>:
16 * - Module largely rewritten, with new (and hopefully correct)
17 * code for dealing with node and chip select interleaving,
18 * various code cleanup, and bug fixes
19 * - Added support for memory hoisting using DRAM hole address
20 * register
21 *
22 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
23 * -K8 Rev (1207) revision support added, required Revision
24 * specific mini-driver code to support Rev F as well as
25 * prior revisions
26 *
27 * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>:
28 * -Family 10h revision support added. New PCI Device IDs,
29 * indicating new changes. Actual registers modified
30 * were slight, less than the Rev E to Rev F transition
31 * but changing the PCI Device ID was the proper thing to
32 * do, as it provides for almost automactic family
33 * detection. The mods to Rev F required more family
34 * information detection.
35 *
36 * Changes/Fixes by Borislav Petkov <borislav.petkov@amd.com>:
37 * - misc fixes and code cleanups
38 *
39 * This module is based on the following documents
40 * (available from http://www.amd.com/):
41 *
42 * Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
43 * Opteron Processors
44 * AMD publication #: 26094
45 *` Revision: 3.26
46 *
47 * Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
48 * Processors
49 * AMD publication #: 32559
50 * Revision: 3.00
51 * Issue Date: May 2006
52 *
53 * Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
54 * Processors
55 * AMD publication #: 31116
56 * Revision: 3.00
57 * Issue Date: September 07, 2007
58 *
59 * Sections in the first 2 documents are no longer in sync with each other.
60 * The Family 10h BKDG was totally re-written from scratch with a new
61 * presentation model.
62 * Therefore, comments that refer to a Document section might be off.
63 */
64
65#include <linux/module.h>
66#include <linux/ctype.h>
67#include <linux/init.h>
68#include <linux/pci.h>
69#include <linux/pci_ids.h>
70#include <linux/slab.h>
71#include <linux/mmzone.h>
72#include <linux/edac.h>
73#include <asm/msr.h>
74#include "edac_core.h"
75#include "mce_amd.h"
76
77#define amd64_debug(fmt, arg...) \
78 edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)
79
80#define amd64_info(fmt, arg...) \
81 edac_printk(KERN_INFO, "amd64", fmt, ##arg)
82
83#define amd64_notice(fmt, arg...) \
84 edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)
85
86#define amd64_warn(fmt, arg...) \
87 edac_printk(KERN_WARNING, "amd64", fmt, ##arg)
88
89#define amd64_err(fmt, arg...) \
90 edac_printk(KERN_ERR, "amd64", fmt, ##arg)
91
92#define amd64_mc_warn(mci, fmt, arg...) \
93 edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
94
95#define amd64_mc_err(mci, fmt, arg...) \
96 edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
97
98/*
99 * Throughout the comments in this code, the following terms are used:
100 *
101 * SysAddr, DramAddr, and InputAddr
102 *
103 * These terms come directly from the amd64 documentation
104 * (AMD publication #26094). They are defined as follows:
105 *
106 * SysAddr:
107 * This is a physical address generated by a CPU core or a device
108 * doing DMA. If generated by a CPU core, a SysAddr is the result of
109 * a virtual to physical address translation by the CPU core's address
110 * translation mechanism (MMU).
111 *
112 * DramAddr:
113 * A DramAddr is derived from a SysAddr by subtracting an offset that
114 * depends on which node the SysAddr maps to and whether the SysAddr
115 * is within a range affected by memory hoisting. The DRAM Base
116 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
117 * determine which node a SysAddr maps to.
118 *
119 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
120 * is within the range of addresses specified by this register, then
121 * a value x from the DHAR is subtracted from the SysAddr to produce a
122 * DramAddr. Here, x represents the base address for the node that
123 * the SysAddr maps to plus an offset due to memory hoisting. See
124 * section 3.4.8 and the comments in amd64_get_dram_hole_info() and
125 * sys_addr_to_dram_addr() below for more information.
126 *
127 * If the SysAddr is not affected by the DHAR then a value y is
128 * subtracted from the SysAddr to produce a DramAddr. Here, y is the
129 * base address for the node that the SysAddr maps to. See section
130 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
131 * information.
132 *
133 * InputAddr:
134 * A DramAddr is translated to an InputAddr before being passed to the
135 * memory controller for the node that the DramAddr is associated
136 * with. The memory controller then maps the InputAddr to a csrow.
137 * If node interleaving is not in use, then the InputAddr has the same
138 * value as the DramAddr. Otherwise, the InputAddr is produced by
139 * discarding the bits used for node interleaving from the DramAddr.
140 * See section 3.4.4 for more information.
141 *
142 * The memory controller for a given node uses its DRAM CS Base and
143 * DRAM CS Mask registers to map an InputAddr to a csrow. See
144 * sections 3.5.4 and 3.5.5 for more information.
145 */
146
147#define EDAC_AMD64_VERSION "3.4.0"
148#define EDAC_MOD_STR "amd64_edac"
149
150/* Extended Model from CPUID, for CPU Revision numbers */
151#define K8_REV_D 1
152#define K8_REV_E 2
153#define K8_REV_F 4
154
155/* Hardware limit on ChipSelect rows per MC and processors per system */
156#define NUM_CHIPSELECTS 8
157#define DRAM_RANGES 8
158
159#define ON true
160#define OFF false
161
162/*
163 * Create a contiguous bitmask starting at bit position @lo and ending at
164 * position @hi. For example
165 *
166 * GENMASK(21, 39) gives us the 64bit vector 0x000000ffffe00000.
167 */
168#define GENMASK(lo, hi) (((1ULL << ((hi) - (lo) + 1)) - 1) << (lo))
169
170/*
171 * PCI-defined configuration space registers
172 */
173#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
174#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
175
176
177/*
178 * Function 1 - Address Map
179 */
180#define DRAM_BASE_LO 0x40
181#define DRAM_LIMIT_LO 0x44
182
183#define dram_intlv_en(pvt, i) ((u8)((pvt->ranges[i].base.lo >> 8) & 0x7))
184#define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
185#define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
186#define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
187
188#define DHAR 0xf0
189#define dhar_valid(pvt) ((pvt)->dhar & BIT(0))
190#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
191#define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
192#define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
193
194 /* NOTE: Extra mask bit vs K8 */
195#define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
196
197#define DCT_CFG_SEL 0x10C
198
199#define DRAM_LOCAL_NODE_BASE 0x120
200#define DRAM_LOCAL_NODE_LIM 0x124
201
202#define DRAM_BASE_HI 0x140
203#define DRAM_LIMIT_HI 0x144
204
205
206/*
207 * Function 2 - DRAM controller
208 */
209#define DCSB0 0x40
210#define DCSB1 0x140
211#define DCSB_CS_ENABLE BIT(0)
212
213#define DCSM0 0x60
214#define DCSM1 0x160
215
216#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
217
218#define DBAM0 0x80
219#define DBAM1 0x180
220
221/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
222#define DBAM_DIMM(i, reg) ((((reg) >> (4*i))) & 0xF)
223
224#define DBAM_MAX_VALUE 11
225
226#define DCLR0 0x90
227#define DCLR1 0x190
228#define REVE_WIDTH_128 BIT(16)
229#define WIDTH_128 BIT(11)
230
231#define DCHR0 0x94
232#define DCHR1 0x194
233#define DDR3_MODE BIT(8)
234
235#define DCT_SEL_LO 0x110
236#define dct_sel_baseaddr(pvt) ((pvt)->dct_sel_lo & 0xFFFFF800)
237#define dct_sel_interleave_addr(pvt) (((pvt)->dct_sel_lo >> 6) & 0x3)
238#define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
239#define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
240
241#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
242
243#define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
244#define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
245
246#define SWAP_INTLV_REG 0x10c
247
248#define DCT_SEL_HI 0x114
249
250/*
251 * Function 3 - Misc Control
252 */
253#define NBCTL 0x40
254
255#define NBCFG 0x44
256#define NBCFG_CHIPKILL BIT(23)
257#define NBCFG_ECC_ENABLE BIT(22)
258
259/* F3x48: NBSL */
260#define F10_NBSL_EXT_ERR_ECC 0x8
261#define NBSL_PP_OBS 0x2
262
263#define SCRCTRL 0x58
264
265#define F10_ONLINE_SPARE 0xB0
266#define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
267#define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
268
269#define F10_NB_ARRAY_ADDR 0xB8
270#define F10_NB_ARRAY_DRAM_ECC BIT(31)
271
272/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
273#define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1)
274
275#define F10_NB_ARRAY_DATA 0xBC
276#define SET_NB_DRAM_INJECTION_WRITE(word, bits) \
277 (BIT(((word) & 0xF) + 20) | \
278 BIT(17) | bits)
279#define SET_NB_DRAM_INJECTION_READ(word, bits) \
280 (BIT(((word) & 0xF) + 20) | \
281 BIT(16) | bits)
282
283#define NBCAP 0xE8
284#define NBCAP_CHIPKILL BIT(4)
285#define NBCAP_SECDED BIT(3)
286#define NBCAP_DCT_DUAL BIT(0)
287
288#define EXT_NB_MCA_CFG 0x180
289
290/* MSRs */
291#define MSR_MCGCTL_NBE BIT(4)
292
293/* AMD sets the first MC device at device ID 0x18. */
294static inline u8 get_node_id(struct pci_dev *pdev)
295{
296 return PCI_SLOT(pdev->devfn) - 0x18;
297}
298
299enum amd_families {
300 K8_CPUS = 0,
301 F10_CPUS,
302 F15_CPUS,
303 NUM_FAMILIES,
304};
305
306/* Error injection control structure */
307struct error_injection {
308 u32 section;
309 u32 word;
310 u32 bit_map;
311};
312
313/* low and high part of PCI config space regs */
314struct reg_pair {
315 u32 lo, hi;
316};
317
318/*
319 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
320 */
321struct dram_range {
322 struct reg_pair base;
323 struct reg_pair lim;
324};
325
326/* A DCT chip selects collection */
327struct chip_select {
328 u32 csbases[NUM_CHIPSELECTS];
329 u8 b_cnt;
330
331 u32 csmasks[NUM_CHIPSELECTS];
332 u8 m_cnt;
333};
334
335struct amd64_pvt {
336 struct low_ops *ops;
337
338 /* pci_device handles which we utilize */
339 struct pci_dev *F1, *F2, *F3;
340
341 unsigned mc_node_id; /* MC index of this MC node */
342 int ext_model; /* extended model value of this node */
343 int channel_count;
344
345 /* Raw registers */
346 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
347 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
348 u32 dchr0; /* DRAM Configuration High DCT0 reg */
349 u32 dchr1; /* DRAM Configuration High DCT1 reg */
350 u32 nbcap; /* North Bridge Capabilities */
351 u32 nbcfg; /* F10 North Bridge Configuration */
352 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
353 u32 dhar; /* DRAM Hoist reg */
354 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
355 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
356
357 /* one for each DCT */
358 struct chip_select csels[2];
359
360 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
361 struct dram_range ranges[DRAM_RANGES];
362
363 u64 top_mem; /* top of memory below 4GB */
364 u64 top_mem2; /* top of memory above 4GB */
365
366 u32 dct_sel_lo; /* DRAM Controller Select Low */
367 u32 dct_sel_hi; /* DRAM Controller Select High */
368 u32 online_spare; /* On-Line spare Reg */
369
370 /* x4 or x8 syndromes in use */
371 u8 ecc_sym_sz;
372
373 /* place to store error injection parameters prior to issue */
374 struct error_injection injection;
375};
376
377static inline u64 get_dram_base(struct amd64_pvt *pvt, unsigned i)
378{
379 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
380
381 if (boot_cpu_data.x86 == 0xf)
382 return addr;
383
384 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
385}
386
387static inline u64 get_dram_limit(struct amd64_pvt *pvt, unsigned i)
388{
389 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
390
391 if (boot_cpu_data.x86 == 0xf)
392 return lim;
393
394 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
395}
396
397static inline u16 extract_syndrome(u64 status)
398{
399 return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
400}
401
402/*
403 * per-node ECC settings descriptor
404 */
405struct ecc_settings {
406 u32 old_nbctl;
407 bool nbctl_valid;
408
409 struct flags {
410 unsigned long nb_mce_enable:1;
411 unsigned long nb_ecc_prev:1;
412 } flags;
413};
414
415#ifdef CONFIG_EDAC_DEBUG
416#define NUM_DBG_ATTRS 5
417#else
418#define NUM_DBG_ATTRS 0
419#endif
420
421#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
422#define NUM_INJ_ATTRS 5
423#else
424#define NUM_INJ_ATTRS 0
425#endif
426
427extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS],
428 amd64_inj_attrs[NUM_INJ_ATTRS];
429
430/*
431 * Each of the PCI Device IDs types have their own set of hardware accessor
432 * functions and per device encoding/decoding logic.
433 */
434struct low_ops {
435 int (*early_channel_count) (struct amd64_pvt *pvt);
436 void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr,
437 u16 syndrome);
438 int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, unsigned cs_mode);
439 int (*read_dct_pci_cfg) (struct amd64_pvt *pvt, int offset,
440 u32 *val, const char *func);
441};
442
443struct amd64_family_type {
444 const char *ctl_name;
445 u16 f1_id, f3_id;
446 struct low_ops ops;
447};
448
449int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
450 u32 val, const char *func);
451
452#define amd64_read_pci_cfg(pdev, offset, val) \
453 __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
454
455#define amd64_write_pci_cfg(pdev, offset, val) \
456 __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
457
458#define amd64_read_dct_pci_cfg(pvt, offset, val) \
459 pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__)
460
461int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
462 u64 *hole_offset, u64 *hole_size);