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1#
2# EDAC Kconfig
3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4# Licensed and distributed under the GPL
5
6config EDAC_ATOMIC_SCRUB
7 bool
8
9config EDAC_SUPPORT
10 bool
11
12menuconfig EDAC
13 tristate "EDAC (Error Detection And Correction) reporting"
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
15 help
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
18 in the CPU or supporting chipset or other subsystems:
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
20 If unsure, select 'Y'.
21
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
23
24if EDAC
25
26config EDAC_LEGACY_SYSFS
27 bool "EDAC legacy sysfs"
28 default y
29 help
30 Enable the compatibility sysfs nodes.
31 Use 'Y' if your edac utilities aren't ported to work with the newer
32 structures.
33
34config EDAC_DEBUG
35 bool "Debugging"
36 select DEBUG_FS
37 help
38 This turns on debugging information for the entire EDAC subsystem.
39 You do so by inserting edac_module with "edac_debug_level=x." Valid
40 levels are 0-4 (from low to high) and by default it is set to 2.
41 Usually you should select 'N' here.
42
43config EDAC_DECODE_MCE
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
45 depends on CPU_SUP_AMD && X86_MCE_AMD
46 default y
47 help
48 Enable this option if you want to decode Machine Check Exceptions
49 occurring on your machine in human-readable form.
50
51 You should definitely say Y here in case you want to decode MCEs
52 which occur really early upon boot, before the module infrastructure
53 has been initialized.
54
55config EDAC_GHES
56 tristate "Output ACPI APEI/GHES BIOS detected errors via EDAC"
57 depends on ACPI_APEI_GHES
58 select UEFI_CPER
59 help
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
62 APEI/GHES driver. By enabling this option, the error reports provided
63 by GHES are sent to userspace via the EDAC API.
64
65 When this option is enabled, it will disable the hardware-driven
66 mechanisms, if a GHES BIOS is detected, entering into the
67 "Firmware First" mode.
68
69 It should be noticed that keeping both GHES and a hardware-driven
70 error mechanism won't work well, as BIOS will race with OS, while
71 reading the error registers. So, if you want to not use "Firmware
72 first" GHES error mechanism, you should disable GHES either at
73 compilation time or by passing "ghes.disable=1" Kernel parameter
74 at boot time.
75
76 In doubt, say 'Y'.
77
78config EDAC_AMD64
79 tristate "AMD64 (Opteron, Athlon64)"
80 depends on AMD_NB && EDAC_DECODE_MCE
81 help
82 Support for error detection and correction of DRAM ECC errors on
83 the AMD64 families (>= K8) of memory controllers.
84
85 When EDAC_DEBUG is enabled, hardware error injection facilities
86 through sysfs are available:
87
88 AMD CPUs up to and excluding family 0x17 provide for Memory
89 Error Injection into the ECC detection circuits. The amd64_edac
90 module allows the operator/user to inject Uncorrectable and
91 Correctable errors into DRAM.
92
93 When enabled, in each of the respective memory controller directories
94 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
95
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
99
100 In addition, there are two control files, inject_read and inject_write,
101 which trigger the DRAM ECC Read and Write respectively.
102
103config EDAC_AL_MC
104 tristate "Amazon's Annapurna Lab Memory Controller"
105 depends on (ARCH_ALPINE || COMPILE_TEST)
106 help
107 Support for error detection and correction for Amazon's Annapurna
108 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
109
110config EDAC_AMD76X
111 tristate "AMD 76x (760, 762, 768)"
112 depends on PCI && X86_32
113 help
114 Support for error detection and correction on the AMD 76x
115 series of chipsets used with the Athlon processor.
116
117config EDAC_E7XXX
118 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
119 depends on PCI && X86_32
120 help
121 Support for error detection and correction on the Intel
122 E7205, E7500, E7501 and E7505 server chipsets.
123
124config EDAC_E752X
125 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
126 depends on PCI && X86
127 help
128 Support for error detection and correction on the Intel
129 E7520, E7525, E7320 server chipsets.
130
131config EDAC_I82443BXGX
132 tristate "Intel 82443BX/GX (440BX/GX)"
133 depends on PCI && X86_32
134 depends on BROKEN
135 help
136 Support for error detection and correction on the Intel
137 82443BX/GX memory controllers (440BX/GX chipsets).
138
139config EDAC_I82875P
140 tristate "Intel 82875p (D82875P, E7210)"
141 depends on PCI && X86_32
142 help
143 Support for error detection and correction on the Intel
144 DP82785P and E7210 server chipsets.
145
146config EDAC_I82975X
147 tristate "Intel 82975x (D82975x)"
148 depends on PCI && X86
149 help
150 Support for error detection and correction on the Intel
151 DP82975x server chipsets.
152
153config EDAC_I3000
154 tristate "Intel 3000/3010"
155 depends on PCI && X86
156 help
157 Support for error detection and correction on the Intel
158 3000 and 3010 server chipsets.
159
160config EDAC_I3200
161 tristate "Intel 3200"
162 depends on PCI && X86
163 help
164 Support for error detection and correction on the Intel
165 3200 and 3210 server chipsets.
166
167config EDAC_IE31200
168 tristate "Intel e312xx"
169 depends on PCI && X86
170 help
171 Support for error detection and correction on the Intel
172 E3-1200 based DRAM controllers.
173
174config EDAC_X38
175 tristate "Intel X38"
176 depends on PCI && X86
177 help
178 Support for error detection and correction on the Intel
179 X38 server chipsets.
180
181config EDAC_I5400
182 tristate "Intel 5400 (Seaburg) chipsets"
183 depends on PCI && X86
184 help
185 Support for error detection and correction the Intel
186 i5400 MCH chipset (Seaburg).
187
188config EDAC_I7CORE
189 tristate "Intel i7 Core (Nehalem) processors"
190 depends on PCI && X86 && X86_MCE_INTEL
191 help
192 Support for error detection and correction the Intel
193 i7 Core (Nehalem) Integrated Memory Controller that exists on
194 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
195 and Xeon 55xx processors.
196
197config EDAC_I82860
198 tristate "Intel 82860"
199 depends on PCI && X86_32
200 help
201 Support for error detection and correction on the Intel
202 82860 chipset.
203
204config EDAC_R82600
205 tristate "Radisys 82600 embedded chipset"
206 depends on PCI && X86_32
207 help
208 Support for error detection and correction on the Radisys
209 82600 embedded chipset.
210
211config EDAC_I5000
212 tristate "Intel Greencreek/Blackford chipset"
213 depends on X86 && PCI
214 depends on BROKEN
215 help
216 Support for error detection and correction the Intel
217 Greekcreek/Blackford chipsets.
218
219config EDAC_I5100
220 tristate "Intel San Clemente MCH"
221 depends on X86 && PCI
222 help
223 Support for error detection and correction the Intel
224 San Clemente MCH.
225
226config EDAC_I7300
227 tristate "Intel Clarksboro MCH"
228 depends on X86 && PCI
229 help
230 Support for error detection and correction the Intel
231 Clarksboro MCH (Intel 7300 chipset).
232
233config EDAC_SBRIDGE
234 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
235 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
236 help
237 Support for error detection and correction the Intel
238 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
239
240config EDAC_SKX
241 tristate "Intel Skylake server Integrated MC"
242 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
243 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
244 select DMI
245 select ACPI_ADXL
246 help
247 Support for error detection and correction the Intel
248 Skylake server Integrated Memory Controllers. If your
249 system has non-volatile DIMMs you should also manually
250 select CONFIG_ACPI_NFIT.
251
252config EDAC_I10NM
253 tristate "Intel 10nm server Integrated MC"
254 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
255 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
256 select DMI
257 select ACPI_ADXL
258 help
259 Support for error detection and correction the Intel
260 10nm server Integrated Memory Controllers. If your
261 system has non-volatile DIMMs you should also manually
262 select CONFIG_ACPI_NFIT.
263
264config EDAC_PND2
265 tristate "Intel Pondicherry2"
266 depends on PCI && X86_64 && X86_MCE_INTEL
267 select P2SB if X86
268 help
269 Support for error detection and correction on the Intel
270 Pondicherry2 Integrated Memory Controller. This SoC IP is
271 first used on the Apollo Lake platform and Denverton
272 micro-server but may appear on others in the future.
273
274config EDAC_IGEN6
275 tristate "Intel client SoC Integrated MC"
276 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
277 depends on X86_64 && X86_MCE_INTEL
278 help
279 Support for error detection and correction on the Intel
280 client SoC Integrated Memory Controller using In-Band ECC IP.
281 This In-Band ECC is first used on the Elkhart Lake SoC but
282 may appear on others in the future.
283
284config EDAC_MPC85XX
285 bool "Freescale MPC83xx / MPC85xx"
286 depends on FSL_SOC && EDAC=y
287 help
288 Support for error detection and correction on the Freescale
289 MPC8349, MPC8560, MPC8540, MPC8548, T4240
290
291config EDAC_LAYERSCAPE
292 tristate "Freescale Layerscape DDR"
293 depends on ARCH_LAYERSCAPE || SOC_LS1021A
294 help
295 Support for error detection and correction on Freescale memory
296 controllers on Layerscape SoCs.
297
298config EDAC_PASEMI
299 tristate "PA Semi PWRficient"
300 depends on PPC_PASEMI && PCI
301 help
302 Support for error detection and correction on PA Semi
303 PWRficient.
304
305config EDAC_CELL
306 tristate "Cell Broadband Engine memory controller"
307 depends on PPC_CELL_COMMON
308 help
309 Support for error detection and correction on the
310 Cell Broadband Engine internal memory controller
311 on platform without a hypervisor
312
313config EDAC_PPC4XX
314 tristate "PPC4xx IBM DDR2 Memory Controller"
315 depends on 4xx
316 help
317 This enables support for EDAC on the ECC memory used
318 with the IBM DDR2 memory controller found in various
319 PowerPC 4xx embedded processors such as the 405EX[r],
320 440SP, 440SPe, 460EX, 460GT and 460SX.
321
322config EDAC_AMD8131
323 tristate "AMD8131 HyperTransport PCI-X Tunnel"
324 depends on PCI && PPC_MAPLE
325 help
326 Support for error detection and correction on the
327 AMD8131 HyperTransport PCI-X Tunnel chip.
328 Note, add more Kconfig dependency if it's adopted
329 on some machine other than Maple.
330
331config EDAC_AMD8111
332 tristate "AMD8111 HyperTransport I/O Hub"
333 depends on PCI && PPC_MAPLE
334 help
335 Support for error detection and correction on the
336 AMD8111 HyperTransport I/O Hub chip.
337 Note, add more Kconfig dependency if it's adopted
338 on some machine other than Maple.
339
340config EDAC_CPC925
341 tristate "IBM CPC925 Memory Controller (PPC970FX)"
342 depends on PPC64
343 help
344 Support for error detection and correction on the
345 IBM CPC925 Bridge and Memory Controller, which is
346 a companion chip to the PowerPC 970 family of
347 processors.
348
349config EDAC_HIGHBANK_MC
350 tristate "Highbank Memory Controller"
351 depends on ARCH_HIGHBANK
352 help
353 Support for error detection and correction on the
354 Calxeda Highbank memory controller.
355
356config EDAC_HIGHBANK_L2
357 tristate "Highbank L2 Cache"
358 depends on ARCH_HIGHBANK
359 help
360 Support for error detection and correction on the
361 Calxeda Highbank memory controller.
362
363config EDAC_OCTEON_PC
364 tristate "Cavium Octeon Primary Caches"
365 depends on CPU_CAVIUM_OCTEON
366 help
367 Support for error detection and correction on the primary caches of
368 the cnMIPS cores of Cavium Octeon family SOCs.
369
370config EDAC_OCTEON_L2C
371 tristate "Cavium Octeon Secondary Caches (L2C)"
372 depends on CAVIUM_OCTEON_SOC
373 help
374 Support for error detection and correction on the
375 Cavium Octeon family of SOCs.
376
377config EDAC_OCTEON_LMC
378 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
379 depends on CAVIUM_OCTEON_SOC
380 help
381 Support for error detection and correction on the
382 Cavium Octeon family of SOCs.
383
384config EDAC_OCTEON_PCI
385 tristate "Cavium Octeon PCI Controller"
386 depends on PCI && CAVIUM_OCTEON_SOC
387 help
388 Support for error detection and correction on the
389 Cavium Octeon family of SOCs.
390
391config EDAC_THUNDERX
392 tristate "Cavium ThunderX EDAC"
393 depends on ARM64
394 depends on PCI
395 help
396 Support for error detection and correction on the
397 Cavium ThunderX memory controllers (LMC), Cache
398 Coherent Processor Interconnect (CCPI) and L2 cache
399 blocks (TAD, CBC, MCI).
400
401config EDAC_ALTERA
402 bool "Altera SOCFPGA ECC"
403 depends on EDAC=y && ARCH_INTEL_SOCFPGA
404 help
405 Support for error detection and correction on the
406 Altera SOCs. This is the global enable for the
407 various Altera peripherals.
408
409config EDAC_ALTERA_SDRAM
410 bool "Altera SDRAM ECC"
411 depends on EDAC_ALTERA=y
412 help
413 Support for error detection and correction on the
414 Altera SDRAM Memory for Altera SoCs. Note that the
415 preloader must initialize the SDRAM before loading
416 the kernel.
417
418config EDAC_ALTERA_L2C
419 bool "Altera L2 Cache ECC"
420 depends on EDAC_ALTERA=y && CACHE_L2X0
421 help
422 Support for error detection and correction on the
423 Altera L2 cache Memory for Altera SoCs. This option
424 requires L2 cache.
425
426config EDAC_ALTERA_OCRAM
427 bool "Altera On-Chip RAM ECC"
428 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
429 help
430 Support for error detection and correction on the
431 Altera On-Chip RAM Memory for Altera SoCs.
432
433config EDAC_ALTERA_ETHERNET
434 bool "Altera Ethernet FIFO ECC"
435 depends on EDAC_ALTERA=y
436 help
437 Support for error detection and correction on the
438 Altera Ethernet FIFO Memory for Altera SoCs.
439
440config EDAC_ALTERA_NAND
441 bool "Altera NAND FIFO ECC"
442 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
443 help
444 Support for error detection and correction on the
445 Altera NAND FIFO Memory for Altera SoCs.
446
447config EDAC_ALTERA_DMA
448 bool "Altera DMA FIFO ECC"
449 depends on EDAC_ALTERA=y && PL330_DMA=y
450 help
451 Support for error detection and correction on the
452 Altera DMA FIFO Memory for Altera SoCs.
453
454config EDAC_ALTERA_USB
455 bool "Altera USB FIFO ECC"
456 depends on EDAC_ALTERA=y && USB_DWC2
457 help
458 Support for error detection and correction on the
459 Altera USB FIFO Memory for Altera SoCs.
460
461config EDAC_ALTERA_QSPI
462 bool "Altera QSPI FIFO ECC"
463 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
464 help
465 Support for error detection and correction on the
466 Altera QSPI FIFO Memory for Altera SoCs.
467
468config EDAC_ALTERA_SDMMC
469 bool "Altera SDMMC FIFO ECC"
470 depends on EDAC_ALTERA=y && MMC_DW
471 help
472 Support for error detection and correction on the
473 Altera SDMMC FIFO Memory for Altera SoCs.
474
475config EDAC_SIFIVE
476 bool "Sifive platform EDAC driver"
477 depends on EDAC=y && SIFIVE_CCACHE
478 help
479 Support for error detection and correction on the SiFive SoCs.
480
481config EDAC_ARMADA_XP
482 bool "Marvell Armada XP DDR and L2 Cache ECC"
483 depends on MACH_MVEBU_V7
484 help
485 Support for error correction and detection on the Marvell Aramada XP
486 DDR RAM and L2 cache controllers.
487
488config EDAC_SYNOPSYS
489 tristate "Synopsys DDR Memory Controller"
490 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC
491 help
492 Support for error detection and correction on the Synopsys DDR
493 memory controller.
494
495config EDAC_XGENE
496 tristate "APM X-Gene SoC"
497 depends on (ARM64 || COMPILE_TEST)
498 help
499 Support for error detection and correction on the
500 APM X-Gene family of SOCs.
501
502config EDAC_TI
503 tristate "Texas Instruments DDR3 ECC Controller"
504 depends on ARCH_KEYSTONE || SOC_DRA7XX
505 help
506 Support for error detection and correction on the TI SoCs.
507
508config EDAC_QCOM
509 tristate "QCOM EDAC Controller"
510 depends on ARCH_QCOM && QCOM_LLCC
511 help
512 Support for error detection and correction on the
513 Qualcomm Technologies, Inc. SoCs.
514
515 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
516 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
517 of Tag RAM and Data RAM.
518
519 For debugging issues having to do with stability and overall system
520 health, you should probably say 'Y' here.
521
522config EDAC_ASPEED
523 tristate "Aspeed AST BMC SoC"
524 depends on ARCH_ASPEED
525 help
526 Support for error detection and correction on the Aspeed AST BMC SoC.
527
528 First, ECC must be configured in the bootloader. Then, this driver
529 will expose error counters via the EDAC kernel framework.
530
531config EDAC_BLUEFIELD
532 tristate "Mellanox BlueField Memory ECC"
533 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
534 help
535 Support for error detection and correction on the
536 Mellanox BlueField SoCs.
537
538config EDAC_DMC520
539 tristate "ARM DMC-520 ECC"
540 depends on ARM64
541 help
542 Support for error detection and correction on the
543 SoCs with ARM DMC-520 DRAM controller.
544
545config EDAC_ZYNQMP
546 tristate "Xilinx ZynqMP OCM Controller"
547 depends on ARCH_ZYNQMP || COMPILE_TEST
548 help
549 This driver supports error detection and correction for the
550 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be
551 built as a module. In that case it will be called zynqmp_edac.
552
553config EDAC_NPCM
554 tristate "Nuvoton NPCM DDR Memory Controller"
555 depends on (ARCH_NPCM || COMPILE_TEST)
556 help
557 Support for error detection and correction on the Nuvoton NPCM DDR
558 memory controller.
559
560 The memory controller supports single bit error correction, double bit
561 error detection (in-line ECC in which a section 1/8th of the memory
562 device used to store data is used for ECC storage).
563
564config EDAC_VERSAL
565 tristate "Xilinx Versal DDR Memory Controller"
566 depends on ARCH_ZYNQMP || COMPILE_TEST
567 help
568 Support for error detection and correction on the Xilinx Versal DDR
569 memory controller.
570
571 Report both single bit errors (CE) and double bit errors (UE).
572 Support injecting both correctable and uncorrectable errors
573 for debugging purposes.
574
575
576endif # EDAC
1#
2# EDAC Kconfig
3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4# Licensed and distributed under the GPL
5#
6
7menuconfig EDAC
8 bool "EDAC (Error Detection And Correction) reporting"
9 depends on HAS_IOMEM
10 depends on X86 || PPC || TILE
11 help
12 EDAC is designed to report errors in the core system.
13 These are low-level errors that are reported in the CPU or
14 supporting chipset or other subsystems:
15 memory errors, cache errors, PCI errors, thermal throttling, etc..
16 If unsure, select 'Y'.
17
18 If this code is reporting problems on your system, please
19 see the EDAC project web pages for more information at:
20
21 <http://bluesmoke.sourceforge.net/>
22
23 and:
24
25 <http://buttersideup.com/edacwiki>
26
27 There is also a mailing list for the EDAC project, which can
28 be found via the sourceforge page.
29
30if EDAC
31
32comment "Reporting subsystems"
33
34config EDAC_DEBUG
35 bool "Debugging"
36 help
37 This turns on debugging information for the entire EDAC
38 sub-system. You can insert module with "debug_level=x", current
39 there're four debug levels (x=0,1,2,3 from low to high).
40 Usually you should select 'N'.
41
42config EDAC_DECODE_MCE
43 tristate "Decode MCEs in human-readable form (only on AMD for now)"
44 depends on CPU_SUP_AMD && X86_MCE
45 default y
46 ---help---
47 Enable this option if you want to decode Machine Check Exceptions
48 occurring on your machine in human-readable form.
49
50 You should definitely say Y here in case you want to decode MCEs
51 which occur really early upon boot, before the module infrastructure
52 has been initialized.
53
54config EDAC_MCE_INJ
55 tristate "Simple MCE injection interface over /sysfs"
56 depends on EDAC_DECODE_MCE
57 default n
58 help
59 This is a simple interface to inject MCEs over /sysfs and test
60 the MCE decoding code in EDAC.
61
62 This is currently AMD-only.
63
64config EDAC_MM_EDAC
65 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
66 help
67 Some systems are able to detect and correct errors in main
68 memory. EDAC can report statistics on memory error
69 detection and correction (EDAC - or commonly referred to ECC
70 errors). EDAC will also try to decode where these errors
71 occurred so that a particular failing memory module can be
72 replaced. If unsure, select 'Y'.
73
74config EDAC_MCE
75 bool
76
77config EDAC_AMD64
78 tristate "AMD64 (Opteron, Athlon64) K8, F10h"
79 depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
80 help
81 Support for error detection and correction of DRAM ECC errors on
82 the AMD64 families of memory controllers (K8 and F10h)
83
84config EDAC_AMD64_ERROR_INJECTION
85 bool "Sysfs HW Error injection facilities"
86 depends on EDAC_AMD64
87 help
88 Recent Opterons (Family 10h and later) provide for Memory Error
89 Injection into the ECC detection circuits. The amd64_edac module
90 allows the operator/user to inject Uncorrectable and Correctable
91 errors into DRAM.
92
93 When enabled, in each of the respective memory controller directories
94 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
95
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
99
100 In addition, there are two control files, inject_read and inject_write,
101 which trigger the DRAM ECC Read and Write respectively.
102
103config EDAC_AMD76X
104 tristate "AMD 76x (760, 762, 768)"
105 depends on EDAC_MM_EDAC && PCI && X86_32
106 help
107 Support for error detection and correction on the AMD 76x
108 series of chipsets used with the Athlon processor.
109
110config EDAC_E7XXX
111 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
112 depends on EDAC_MM_EDAC && PCI && X86_32
113 help
114 Support for error detection and correction on the Intel
115 E7205, E7500, E7501 and E7505 server chipsets.
116
117config EDAC_E752X
118 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
119 depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
120 help
121 Support for error detection and correction on the Intel
122 E7520, E7525, E7320 server chipsets.
123
124config EDAC_I82443BXGX
125 tristate "Intel 82443BX/GX (440BX/GX)"
126 depends on EDAC_MM_EDAC && PCI && X86_32
127 depends on BROKEN
128 help
129 Support for error detection and correction on the Intel
130 82443BX/GX memory controllers (440BX/GX chipsets).
131
132config EDAC_I82875P
133 tristate "Intel 82875p (D82875P, E7210)"
134 depends on EDAC_MM_EDAC && PCI && X86_32
135 help
136 Support for error detection and correction on the Intel
137 DP82785P and E7210 server chipsets.
138
139config EDAC_I82975X
140 tristate "Intel 82975x (D82975x)"
141 depends on EDAC_MM_EDAC && PCI && X86
142 help
143 Support for error detection and correction on the Intel
144 DP82975x server chipsets.
145
146config EDAC_I3000
147 tristate "Intel 3000/3010"
148 depends on EDAC_MM_EDAC && PCI && X86
149 help
150 Support for error detection and correction on the Intel
151 3000 and 3010 server chipsets.
152
153config EDAC_I3200
154 tristate "Intel 3200"
155 depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
156 help
157 Support for error detection and correction on the Intel
158 3200 and 3210 server chipsets.
159
160config EDAC_X38
161 tristate "Intel X38"
162 depends on EDAC_MM_EDAC && PCI && X86
163 help
164 Support for error detection and correction on the Intel
165 X38 server chipsets.
166
167config EDAC_I5400
168 tristate "Intel 5400 (Seaburg) chipsets"
169 depends on EDAC_MM_EDAC && PCI && X86
170 help
171 Support for error detection and correction the Intel
172 i5400 MCH chipset (Seaburg).
173
174config EDAC_I7CORE
175 tristate "Intel i7 Core (Nehalem) processors"
176 depends on EDAC_MM_EDAC && PCI && X86
177 select EDAC_MCE
178 help
179 Support for error detection and correction the Intel
180 i7 Core (Nehalem) Integrated Memory Controller that exists on
181 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
182 and Xeon 55xx processors.
183
184config EDAC_I82860
185 tristate "Intel 82860"
186 depends on EDAC_MM_EDAC && PCI && X86_32
187 help
188 Support for error detection and correction on the Intel
189 82860 chipset.
190
191config EDAC_R82600
192 tristate "Radisys 82600 embedded chipset"
193 depends on EDAC_MM_EDAC && PCI && X86_32
194 help
195 Support for error detection and correction on the Radisys
196 82600 embedded chipset.
197
198config EDAC_I5000
199 tristate "Intel Greencreek/Blackford chipset"
200 depends on EDAC_MM_EDAC && X86 && PCI
201 help
202 Support for error detection and correction the Intel
203 Greekcreek/Blackford chipsets.
204
205config EDAC_I5100
206 tristate "Intel San Clemente MCH"
207 depends on EDAC_MM_EDAC && X86 && PCI
208 help
209 Support for error detection and correction the Intel
210 San Clemente MCH.
211
212config EDAC_I7300
213 tristate "Intel Clarksboro MCH"
214 depends on EDAC_MM_EDAC && X86 && PCI
215 help
216 Support for error detection and correction the Intel
217 Clarksboro MCH (Intel 7300 chipset).
218
219config EDAC_MPC85XX
220 tristate "Freescale MPC83xx / MPC85xx"
221 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
222 help
223 Support for error detection and correction on the Freescale
224 MPC8349, MPC8560, MPC8540, MPC8548
225
226config EDAC_MV64X60
227 tristate "Marvell MV64x60"
228 depends on EDAC_MM_EDAC && MV64X60
229 help
230 Support for error detection and correction on the Marvell
231 MV64360 and MV64460 chipsets.
232
233config EDAC_PASEMI
234 tristate "PA Semi PWRficient"
235 depends on EDAC_MM_EDAC && PCI
236 depends on PPC_PASEMI
237 help
238 Support for error detection and correction on PA Semi
239 PWRficient.
240
241config EDAC_CELL
242 tristate "Cell Broadband Engine memory controller"
243 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
244 help
245 Support for error detection and correction on the
246 Cell Broadband Engine internal memory controller
247 on platform without a hypervisor
248
249config EDAC_PPC4XX
250 tristate "PPC4xx IBM DDR2 Memory Controller"
251 depends on EDAC_MM_EDAC && 4xx
252 help
253 This enables support for EDAC on the ECC memory used
254 with the IBM DDR2 memory controller found in various
255 PowerPC 4xx embedded processors such as the 405EX[r],
256 440SP, 440SPe, 460EX, 460GT and 460SX.
257
258config EDAC_AMD8131
259 tristate "AMD8131 HyperTransport PCI-X Tunnel"
260 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
261 help
262 Support for error detection and correction on the
263 AMD8131 HyperTransport PCI-X Tunnel chip.
264 Note, add more Kconfig dependency if it's adopted
265 on some machine other than Maple.
266
267config EDAC_AMD8111
268 tristate "AMD8111 HyperTransport I/O Hub"
269 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
270 help
271 Support for error detection and correction on the
272 AMD8111 HyperTransport I/O Hub chip.
273 Note, add more Kconfig dependency if it's adopted
274 on some machine other than Maple.
275
276config EDAC_CPC925
277 tristate "IBM CPC925 Memory Controller (PPC970FX)"
278 depends on EDAC_MM_EDAC && PPC64
279 help
280 Support for error detection and correction on the
281 IBM CPC925 Bridge and Memory Controller, which is
282 a companion chip to the PowerPC 970 family of
283 processors.
284
285config EDAC_TILE
286 tristate "Tilera Memory Controller"
287 depends on EDAC_MM_EDAC && TILE
288 default y
289 help
290 Support for error detection and correction on the
291 Tilera memory controller.
292
293endif # EDAC