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1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright(c) 2022 Intel Corporation */
3#ifndef _ICP_QAT_FW_COMP_H_
4#define _ICP_QAT_FW_COMP_H_
5#include "icp_qat_fw.h"
6
7enum icp_qat_fw_comp_cmd_id {
8 ICP_QAT_FW_COMP_CMD_STATIC = 0,
9 ICP_QAT_FW_COMP_CMD_DYNAMIC = 1,
10 ICP_QAT_FW_COMP_CMD_DECOMPRESS = 2,
11 ICP_QAT_FW_COMP_CMD_DELIMITER
12};
13
14enum icp_qat_fw_comp_20_cmd_id {
15 ICP_QAT_FW_COMP_20_CMD_LZ4_COMPRESS = 3,
16 ICP_QAT_FW_COMP_20_CMD_LZ4_DECOMPRESS = 4,
17 ICP_QAT_FW_COMP_20_CMD_LZ4S_COMPRESS = 5,
18 ICP_QAT_FW_COMP_20_CMD_LZ4S_DECOMPRESS = 6,
19 ICP_QAT_FW_COMP_20_CMD_XP10_COMPRESS = 7,
20 ICP_QAT_FW_COMP_20_CMD_XP10_DECOMPRESS = 8,
21 ICP_QAT_FW_COMP_20_CMD_RESERVED_9 = 9,
22 ICP_QAT_FW_COMP_23_CMD_ZSTD_COMPRESS = 10,
23 ICP_QAT_FW_COMP_23_CMD_ZSTD_DECOMPRESS = 11,
24 ICP_QAT_FW_COMP_20_CMD_DELIMITER
25};
26
27#define ICP_QAT_FW_COMP_STATELESS_SESSION 0
28#define ICP_QAT_FW_COMP_STATEFUL_SESSION 1
29#define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST 0
30#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST 1
31#define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST 0
32#define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST 1
33#define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 0
34#define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 1
35#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF 1
36#define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF 0
37#define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS 2
38#define ICP_QAT_FW_COMP_SESSION_TYPE_MASK 0x1
39#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS 3
40#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK 0x1
41#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS 4
42#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK 0x1
43#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS 5
44#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1
45#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7
46#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1
47
48#define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb, \
49 ret_uncomp, secure_ram) \
50 ((((sesstype) & ICP_QAT_FW_COMP_SESSION_TYPE_MASK) << \
51 ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) | \
52 (((autoselect) & ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) << \
53 ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS) | \
54 (((enhanced_asb) & ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) << \
55 ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS) | \
56 (((ret_uncomp) & ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) << \
57 ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS) | \
58 (((secure_ram) & ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) << \
59 ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS))
60
61#define ICP_QAT_FW_COMP_SESSION_TYPE_GET(flags) \
62 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS, \
63 ICP_QAT_FW_COMP_SESSION_TYPE_MASK)
64
65#define ICP_QAT_FW_COMP_SESSION_TYPE_SET(flags, val) \
66 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS, \
67 ICP_QAT_FW_COMP_SESSION_TYPE_MASK)
68
69#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_GET(flags) \
70 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS, \
71 ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK)
72
73#define ICP_QAT_FW_COMP_EN_ASB_GET(flags) \
74 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS, \
75 ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK)
76
77#define ICP_QAT_FW_COMP_RET_UNCOMP_GET(flags) \
78 QAT_FIELD_GET(flags, \
79 ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS, \
80 ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK)
81
82#define ICP_QAT_FW_COMP_SECURE_RAM_USE_GET(flags) \
83 QAT_FIELD_GET(flags, \
84 ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS, \
85 ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK)
86
87struct icp_qat_fw_comp_req_hdr_cd_pars {
88 union {
89 struct {
90 __u64 content_desc_addr;
91 __u16 content_desc_resrvd1;
92 __u8 content_desc_params_sz;
93 __u8 content_desc_hdr_resrvd2;
94 __u32 content_desc_resrvd3;
95 } s;
96 struct {
97 __u32 comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2];
98 __u32 content_desc_resrvd4;
99 } sl;
100 } u;
101};
102
103struct icp_qat_fw_comp_req_params {
104 __u32 comp_len;
105 __u32 out_buffer_sz;
106 union {
107 struct {
108 __u32 initial_crc32;
109 __u32 initial_adler;
110 } legacy;
111 __u64 crc_data_addr;
112 } crc;
113 __u32 req_par_flags;
114 __u32 rsrvd;
115};
116
117#define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr, \
118 cnvdfx, crc, xxhash_acc, \
119 cnv_error_type, append_crc, \
120 drop_data) \
121 ((((sop) & ICP_QAT_FW_COMP_SOP_MASK) << \
122 ICP_QAT_FW_COMP_SOP_BITPOS) | \
123 (((eop) & ICP_QAT_FW_COMP_EOP_MASK) << \
124 ICP_QAT_FW_COMP_EOP_BITPOS) | \
125 (((bfinal) & ICP_QAT_FW_COMP_BFINAL_MASK) \
126 << ICP_QAT_FW_COMP_BFINAL_BITPOS) | \
127 (((cnv) & ICP_QAT_FW_COMP_CNV_MASK) << \
128 ICP_QAT_FW_COMP_CNV_BITPOS) | \
129 (((cnvnr) & ICP_QAT_FW_COMP_CNVNR_MASK) \
130 << ICP_QAT_FW_COMP_CNVNR_BITPOS) | \
131 (((cnvdfx) & ICP_QAT_FW_COMP_CNV_DFX_MASK) \
132 << ICP_QAT_FW_COMP_CNV_DFX_BITPOS) | \
133 (((crc) & ICP_QAT_FW_COMP_CRC_MODE_MASK) \
134 << ICP_QAT_FW_COMP_CRC_MODE_BITPOS) | \
135 (((xxhash_acc) & ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK) \
136 << ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS) | \
137 (((cnv_error_type) & ICP_QAT_FW_COMP_CNV_ERROR_MASK) \
138 << ICP_QAT_FW_COMP_CNV_ERROR_BITPOS) | \
139 (((append_crc) & ICP_QAT_FW_COMP_APPEND_CRC_MASK) \
140 << ICP_QAT_FW_COMP_APPEND_CRC_BITPOS) | \
141 (((drop_data) & ICP_QAT_FW_COMP_DROP_DATA_MASK) \
142 << ICP_QAT_FW_COMP_DROP_DATA_BITPOS))
143
144#define ICP_QAT_FW_COMP_NOT_SOP 0
145#define ICP_QAT_FW_COMP_SOP 1
146#define ICP_QAT_FW_COMP_NOT_EOP 0
147#define ICP_QAT_FW_COMP_EOP 1
148#define ICP_QAT_FW_COMP_NOT_BFINAL 0
149#define ICP_QAT_FW_COMP_BFINAL 1
150#define ICP_QAT_FW_COMP_NO_CNV 0
151#define ICP_QAT_FW_COMP_CNV 1
152#define ICP_QAT_FW_COMP_NO_CNV_RECOVERY 0
153#define ICP_QAT_FW_COMP_CNV_RECOVERY 1
154#define ICP_QAT_FW_COMP_NO_CNV_DFX 0
155#define ICP_QAT_FW_COMP_CNV_DFX 1
156#define ICP_QAT_FW_COMP_CRC_MODE_LEGACY 0
157#define ICP_QAT_FW_COMP_CRC_MODE_E2E 1
158#define ICP_QAT_FW_COMP_NO_XXHASH_ACC 0
159#define ICP_QAT_FW_COMP_XXHASH_ACC 1
160#define ICP_QAT_FW_COMP_APPEND_CRC 1
161#define ICP_QAT_FW_COMP_NO_APPEND_CRC 0
162#define ICP_QAT_FW_COMP_DROP_DATA 1
163#define ICP_QAT_FW_COMP_NO_DROP_DATA 0
164#define ICP_QAT_FW_COMP_SOP_BITPOS 0
165#define ICP_QAT_FW_COMP_SOP_MASK 0x1
166#define ICP_QAT_FW_COMP_EOP_BITPOS 1
167#define ICP_QAT_FW_COMP_EOP_MASK 0x1
168#define ICP_QAT_FW_COMP_BFINAL_BITPOS 6
169#define ICP_QAT_FW_COMP_BFINAL_MASK 0x1
170#define ICP_QAT_FW_COMP_CNV_BITPOS 16
171#define ICP_QAT_FW_COMP_CNV_MASK 0x1
172#define ICP_QAT_FW_COMP_CNVNR_BITPOS 17
173#define ICP_QAT_FW_COMP_CNVNR_MASK 0x1
174#define ICP_QAT_FW_COMP_CNV_DFX_BITPOS 18
175#define ICP_QAT_FW_COMP_CNV_DFX_MASK 0x1
176#define ICP_QAT_FW_COMP_CRC_MODE_BITPOS 19
177#define ICP_QAT_FW_COMP_CRC_MODE_MASK 0x1
178#define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS 20
179#define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK 0x1
180#define ICP_QAT_FW_COMP_CNV_ERROR_BITPOS 21
181#define ICP_QAT_FW_COMP_CNV_ERROR_MASK 0b111
182#define ICP_QAT_FW_COMP_CNV_ERROR_NONE 0b000
183#define ICP_QAT_FW_COMP_CNV_ERROR_CHECKSUM 0b001
184#define ICP_QAT_FW_COMP_CNV_ERROR_DCPR_OBC_DIFF 0b010
185#define ICP_QAT_FW_COMP_CNV_ERROR_DCPR 0b011
186#define ICP_QAT_FW_COMP_CNV_ERROR_XLT 0b100
187#define ICP_QAT_FW_COMP_CNV_ERROR_DCPR_IBC_DIFF 0b101
188#define ICP_QAT_FW_COMP_APPEND_CRC_BITPOS 24
189#define ICP_QAT_FW_COMP_APPEND_CRC_MASK 0x1
190#define ICP_QAT_FW_COMP_DROP_DATA_BITPOS 25
191#define ICP_QAT_FW_COMP_DROP_DATA_MASK 0x1
192
193#define ICP_QAT_FW_COMP_SOP_GET(flags) \
194 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_SOP_BITPOS, \
195 ICP_QAT_FW_COMP_SOP_MASK)
196
197#define ICP_QAT_FW_COMP_SOP_SET(flags, val) \
198 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_SOP_BITPOS, \
199 ICP_QAT_FW_COMP_SOP_MASK)
200
201#define ICP_QAT_FW_COMP_EOP_GET(flags) \
202 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_EOP_BITPOS, \
203 ICP_QAT_FW_COMP_EOP_MASK)
204
205#define ICP_QAT_FW_COMP_EOP_SET(flags, val) \
206 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_EOP_BITPOS, \
207 ICP_QAT_FW_COMP_EOP_MASK)
208
209#define ICP_QAT_FW_COMP_BFINAL_GET(flags) \
210 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_BFINAL_BITPOS, \
211 ICP_QAT_FW_COMP_BFINAL_MASK)
212
213#define ICP_QAT_FW_COMP_BFINAL_SET(flags, val) \
214 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_BFINAL_BITPOS, \
215 ICP_QAT_FW_COMP_BFINAL_MASK)
216
217#define ICP_QAT_FW_COMP_CNV_GET(flags) \
218 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CNV_BITPOS, \
219 ICP_QAT_FW_COMP_CNV_MASK)
220
221#define ICP_QAT_FW_COMP_CNVNR_GET(flags) \
222 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CNVNR_BITPOS, \
223 ICP_QAT_FW_COMP_CNVNR_MASK)
224
225#define ICP_QAT_FW_COMP_CNV_DFX_GET(flags) \
226 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CNV_DFX_BITPOS, \
227 ICP_QAT_FW_COMP_CNV_DFX_MASK)
228
229#define ICP_QAT_FW_COMP_CNV_DFX_SET(flags, val) \
230 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_CNV_DFX_BITPOS, \
231 ICP_QAT_FW_COMP_CNV_DFX_MASK)
232
233#define ICP_QAT_FW_COMP_CRC_MODE_GET(flags) \
234 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CRC_MODE_BITPOS, \
235 ICP_QAT_FW_COMP_CRC_MODE_MASK)
236
237#define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_GET(flags) \
238 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS, \
239 ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK)
240
241#define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_SET(flags, val) \
242 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS, \
243 ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK)
244
245#define ICP_QAT_FW_COMP_CNV_ERROR_TYPE_GET(flags) \
246 QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CNV_ERROR_BITPOS, \
247 ICP_QAT_FW_COMP_CNV_ERROR_MASK)
248
249#define ICP_QAT_FW_COMP_CNV_ERROR_TYPE_SET(flags, val) \
250 QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_CNV_ERROR_BITPOS, \
251 ICP_QAT_FW_COMP_CNV_ERROR_MASK)
252
253struct icp_qat_fw_xlt_req_params {
254 __u64 inter_buff_ptr;
255};
256
257struct icp_qat_fw_comp_cd_hdr {
258 __u16 ram_bank_flags;
259 __u8 comp_cfg_offset;
260 __u8 next_curr_id;
261 __u32 resrvd;
262 __u64 comp_state_addr;
263 __u64 ram_banks_addr;
264};
265
266#define COMP_CPR_INITIAL_CRC 0
267#define COMP_CPR_INITIAL_ADLER 1
268
269struct icp_qat_fw_xlt_cd_hdr {
270 __u16 resrvd1;
271 __u8 resrvd2;
272 __u8 next_curr_id;
273 __u32 resrvd3;
274};
275
276struct icp_qat_fw_comp_req {
277 struct icp_qat_fw_comn_req_hdr comn_hdr;
278 struct icp_qat_fw_comp_req_hdr_cd_pars cd_pars;
279 struct icp_qat_fw_comn_req_mid comn_mid;
280 struct icp_qat_fw_comp_req_params comp_pars;
281 union {
282 struct icp_qat_fw_xlt_req_params xlt_pars;
283 __u32 resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2];
284 } u1;
285 __u32 resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2];
286 struct icp_qat_fw_comp_cd_hdr comp_cd_ctrl;
287 union {
288 struct icp_qat_fw_xlt_cd_hdr xlt_cd_ctrl;
289 __u32 resrvd3[ICP_QAT_FW_NUM_LONGWORDS_2];
290 } u2;
291};
292
293struct icp_qat_fw_resp_comp_pars {
294 __u32 input_byte_counter;
295 __u32 output_byte_counter;
296 union {
297 struct {
298 __u32 curr_crc32;
299 __u32 curr_adler_32;
300 } legacy;
301 __u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_2];
302 } crc;
303};
304
305struct icp_qat_fw_comp_state {
306 __u32 rd8_counter;
307 __u32 status_flags;
308 __u32 in_counter;
309 __u32 out_counter;
310 __u64 intermediate_state;
311 __u32 lobc;
312 __u32 replaybc;
313 __u64 pcrc64_poly;
314 __u32 crc32;
315 __u32 adler_xxhash32;
316 __u64 pcrc64_xorout;
317 __u32 out_buf_size;
318 __u32 in_buf_size;
319 __u64 in_pcrc64;
320 __u64 out_pcrc64;
321 __u32 lobs;
322 __u32 libc;
323 __u64 reserved;
324 __u32 xxhash_state[4];
325 __u32 cleartext[4];
326};
327
328struct icp_qat_fw_comp_resp {
329 struct icp_qat_fw_comn_resp_hdr comn_resp;
330 __u64 opaque_data;
331 struct icp_qat_fw_resp_comp_pars comp_resp_pars;
332};
333
334#define QAT_FW_COMP_BANK_FLAG_MASK 0x1
335#define QAT_FW_COMP_BANK_I_BITPOS 8
336#define QAT_FW_COMP_BANK_H_BITPOS 7
337#define QAT_FW_COMP_BANK_G_BITPOS 6
338#define QAT_FW_COMP_BANK_F_BITPOS 5
339#define QAT_FW_COMP_BANK_E_BITPOS 4
340#define QAT_FW_COMP_BANK_D_BITPOS 3
341#define QAT_FW_COMP_BANK_C_BITPOS 2
342#define QAT_FW_COMP_BANK_B_BITPOS 1
343#define QAT_FW_COMP_BANK_A_BITPOS 0
344
345enum icp_qat_fw_comp_bank_enabled {
346 ICP_QAT_FW_COMP_BANK_DISABLED = 0,
347 ICP_QAT_FW_COMP_BANK_ENABLED = 1,
348 ICP_QAT_FW_COMP_BANK_DELIMITER = 2
349};
350
351#define ICP_QAT_FW_COMP_RAM_FLAGS_BUILD(bank_i_enable, bank_h_enable, \
352 bank_g_enable, bank_f_enable, \
353 bank_e_enable, bank_d_enable, \
354 bank_c_enable, bank_b_enable, \
355 bank_a_enable) \
356 ((((bank_i_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
357 QAT_FW_COMP_BANK_I_BITPOS) | \
358 (((bank_h_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
359 QAT_FW_COMP_BANK_H_BITPOS) | \
360 (((bank_g_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
361 QAT_FW_COMP_BANK_G_BITPOS) | \
362 (((bank_f_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
363 QAT_FW_COMP_BANK_F_BITPOS) | \
364 (((bank_e_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
365 QAT_FW_COMP_BANK_E_BITPOS) | \
366 (((bank_d_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
367 QAT_FW_COMP_BANK_D_BITPOS) | \
368 (((bank_c_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
369 QAT_FW_COMP_BANK_C_BITPOS) | \
370 (((bank_b_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
371 QAT_FW_COMP_BANK_B_BITPOS) | \
372 (((bank_a_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
373 QAT_FW_COMP_BANK_A_BITPOS))
374
375struct icp_qat_fw_comp_crc_data_struct {
376 __u32 crc32;
377 union {
378 __u32 adler;
379 __u32 xxhash;
380 } adler_xxhash_u;
381 __u32 cpr_in_crc_lo;
382 __u32 cpr_in_crc_hi;
383 __u32 cpr_out_crc_lo;
384 __u32 cpr_out_crc_hi;
385 __u32 xlt_in_crc_lo;
386 __u32 xlt_in_crc_hi;
387 __u32 xlt_out_crc_lo;
388 __u32 xlt_out_crc_hi;
389 __u32 prog_crc_poly_lo;
390 __u32 prog_crc_poly_hi;
391 __u32 xor_out_lo;
392 __u32 xor_out_hi;
393 __u32 append_crc_lo;
394 __u32 append_crc_hi;
395};
396
397struct xxhash_acc_state_buff {
398 __u32 in_counter;
399 __u32 out_counter;
400 __u32 xxhash_state[4];
401 __u32 clear_txt[4];
402};
403
404#endif