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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
4 */
5
6/dts-v1/;
7#include <dt-bindings/interrupt-controller/irq.h>
8
9#include "sg2042-cpus.dtsi"
10
11/ {
12 compatible = "sophgo,sg2042";
13 #address-cells = <2>;
14 #size-cells = <2>;
15 dma-noncoherent;
16
17 aliases {
18 serial0 = &uart0;
19 };
20
21 soc: soc {
22 compatible = "simple-bus";
23 #address-cells = <2>;
24 #size-cells = <2>;
25 ranges;
26
27 clint_mswi: interrupt-controller@7094000000 {
28 compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
29 reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
30 interrupts-extended = <&cpu0_intc 3>,
31 <&cpu1_intc 3>,
32 <&cpu2_intc 3>,
33 <&cpu3_intc 3>,
34 <&cpu4_intc 3>,
35 <&cpu5_intc 3>,
36 <&cpu6_intc 3>,
37 <&cpu7_intc 3>,
38 <&cpu8_intc 3>,
39 <&cpu9_intc 3>,
40 <&cpu10_intc 3>,
41 <&cpu11_intc 3>,
42 <&cpu12_intc 3>,
43 <&cpu13_intc 3>,
44 <&cpu14_intc 3>,
45 <&cpu15_intc 3>,
46 <&cpu16_intc 3>,
47 <&cpu17_intc 3>,
48 <&cpu18_intc 3>,
49 <&cpu19_intc 3>,
50 <&cpu20_intc 3>,
51 <&cpu21_intc 3>,
52 <&cpu22_intc 3>,
53 <&cpu23_intc 3>,
54 <&cpu24_intc 3>,
55 <&cpu25_intc 3>,
56 <&cpu26_intc 3>,
57 <&cpu27_intc 3>,
58 <&cpu28_intc 3>,
59 <&cpu29_intc 3>,
60 <&cpu30_intc 3>,
61 <&cpu31_intc 3>,
62 <&cpu32_intc 3>,
63 <&cpu33_intc 3>,
64 <&cpu34_intc 3>,
65 <&cpu35_intc 3>,
66 <&cpu36_intc 3>,
67 <&cpu37_intc 3>,
68 <&cpu38_intc 3>,
69 <&cpu39_intc 3>,
70 <&cpu40_intc 3>,
71 <&cpu41_intc 3>,
72 <&cpu42_intc 3>,
73 <&cpu43_intc 3>,
74 <&cpu44_intc 3>,
75 <&cpu45_intc 3>,
76 <&cpu46_intc 3>,
77 <&cpu47_intc 3>,
78 <&cpu48_intc 3>,
79 <&cpu49_intc 3>,
80 <&cpu50_intc 3>,
81 <&cpu51_intc 3>,
82 <&cpu52_intc 3>,
83 <&cpu53_intc 3>,
84 <&cpu54_intc 3>,
85 <&cpu55_intc 3>,
86 <&cpu56_intc 3>,
87 <&cpu57_intc 3>,
88 <&cpu58_intc 3>,
89 <&cpu59_intc 3>,
90 <&cpu60_intc 3>,
91 <&cpu61_intc 3>,
92 <&cpu62_intc 3>,
93 <&cpu63_intc 3>;
94 };
95
96 clint_mtimer0: timer@70ac004000 {
97 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
98 reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
99 reg-names = "mtimecmp";
100 interrupts-extended = <&cpu0_intc 7>,
101 <&cpu1_intc 7>,
102 <&cpu2_intc 7>,
103 <&cpu3_intc 7>;
104 };
105
106 clint_mtimer1: timer@70ac014000 {
107 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
108 reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
109 reg-names = "mtimecmp";
110 interrupts-extended = <&cpu4_intc 7>,
111 <&cpu5_intc 7>,
112 <&cpu6_intc 7>,
113 <&cpu7_intc 7>;
114 };
115
116 clint_mtimer2: timer@70ac024000 {
117 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
118 reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
119 reg-names = "mtimecmp";
120 interrupts-extended = <&cpu8_intc 7>,
121 <&cpu9_intc 7>,
122 <&cpu10_intc 7>,
123 <&cpu11_intc 7>;
124 };
125
126 clint_mtimer3: timer@70ac034000 {
127 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
128 reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
129 reg-names = "mtimecmp";
130 interrupts-extended = <&cpu12_intc 7>,
131 <&cpu13_intc 7>,
132 <&cpu14_intc 7>,
133 <&cpu15_intc 7>;
134 };
135
136 clint_mtimer4: timer@70ac044000 {
137 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
138 reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
139 reg-names = "mtimecmp";
140 interrupts-extended = <&cpu16_intc 7>,
141 <&cpu17_intc 7>,
142 <&cpu18_intc 7>,
143 <&cpu19_intc 7>;
144 };
145
146 clint_mtimer5: timer@70ac054000 {
147 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
148 reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
149 reg-names = "mtimecmp";
150 interrupts-extended = <&cpu20_intc 7>,
151 <&cpu21_intc 7>,
152 <&cpu22_intc 7>,
153 <&cpu23_intc 7>;
154 };
155
156 clint_mtimer6: timer@70ac064000 {
157 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
158 reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
159 reg-names = "mtimecmp";
160 interrupts-extended = <&cpu24_intc 7>,
161 <&cpu25_intc 7>,
162 <&cpu26_intc 7>,
163 <&cpu27_intc 7>;
164 };
165
166 clint_mtimer7: timer@70ac074000 {
167 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
168 reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
169 reg-names = "mtimecmp";
170 interrupts-extended = <&cpu28_intc 7>,
171 <&cpu29_intc 7>,
172 <&cpu30_intc 7>,
173 <&cpu31_intc 7>;
174 };
175
176 clint_mtimer8: timer@70ac084000 {
177 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
178 reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
179 reg-names = "mtimecmp";
180 interrupts-extended = <&cpu32_intc 7>,
181 <&cpu33_intc 7>,
182 <&cpu34_intc 7>,
183 <&cpu35_intc 7>;
184 };
185
186 clint_mtimer9: timer@70ac094000 {
187 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
188 reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
189 reg-names = "mtimecmp";
190 interrupts-extended = <&cpu36_intc 7>,
191 <&cpu37_intc 7>,
192 <&cpu38_intc 7>,
193 <&cpu39_intc 7>;
194 };
195
196 clint_mtimer10: timer@70ac0a4000 {
197 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
198 reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
199 reg-names = "mtimecmp";
200 interrupts-extended = <&cpu40_intc 7>,
201 <&cpu41_intc 7>,
202 <&cpu42_intc 7>,
203 <&cpu43_intc 7>;
204 };
205
206 clint_mtimer11: timer@70ac0b4000 {
207 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
208 reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
209 reg-names = "mtimecmp";
210 interrupts-extended = <&cpu44_intc 7>,
211 <&cpu45_intc 7>,
212 <&cpu46_intc 7>,
213 <&cpu47_intc 7>;
214 };
215
216 clint_mtimer12: timer@70ac0c4000 {
217 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
218 reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
219 reg-names = "mtimecmp";
220 interrupts-extended = <&cpu48_intc 7>,
221 <&cpu49_intc 7>,
222 <&cpu50_intc 7>,
223 <&cpu51_intc 7>;
224 };
225
226 clint_mtimer13: timer@70ac0d4000 {
227 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
228 reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
229 reg-names = "mtimecmp";
230 interrupts-extended = <&cpu52_intc 7>,
231 <&cpu53_intc 7>,
232 <&cpu54_intc 7>,
233 <&cpu55_intc 7>;
234 };
235
236 clint_mtimer14: timer@70ac0e4000 {
237 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
238 reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
239 reg-names = "mtimecmp";
240 interrupts-extended = <&cpu56_intc 7>,
241 <&cpu57_intc 7>,
242 <&cpu58_intc 7>,
243 <&cpu59_intc 7>;
244 };
245
246 clint_mtimer15: timer@70ac0f4000 {
247 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
248 reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
249 reg-names = "mtimecmp";
250 interrupts-extended = <&cpu60_intc 7>,
251 <&cpu61_intc 7>,
252 <&cpu62_intc 7>,
253 <&cpu63_intc 7>;
254 };
255
256 intc: interrupt-controller@7090000000 {
257 compatible = "sophgo,sg2042-plic", "thead,c900-plic";
258 #address-cells = <0>;
259 #interrupt-cells = <2>;
260 reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
261 interrupt-controller;
262 interrupts-extended =
263 <&cpu0_intc 11>, <&cpu0_intc 9>,
264 <&cpu1_intc 11>, <&cpu1_intc 9>,
265 <&cpu2_intc 11>, <&cpu2_intc 9>,
266 <&cpu3_intc 11>, <&cpu3_intc 9>,
267 <&cpu4_intc 11>, <&cpu4_intc 9>,
268 <&cpu5_intc 11>, <&cpu5_intc 9>,
269 <&cpu6_intc 11>, <&cpu6_intc 9>,
270 <&cpu7_intc 11>, <&cpu7_intc 9>,
271 <&cpu8_intc 11>, <&cpu8_intc 9>,
272 <&cpu9_intc 11>, <&cpu9_intc 9>,
273 <&cpu10_intc 11>, <&cpu10_intc 9>,
274 <&cpu11_intc 11>, <&cpu11_intc 9>,
275 <&cpu12_intc 11>, <&cpu12_intc 9>,
276 <&cpu13_intc 11>, <&cpu13_intc 9>,
277 <&cpu14_intc 11>, <&cpu14_intc 9>,
278 <&cpu15_intc 11>, <&cpu15_intc 9>,
279 <&cpu16_intc 11>, <&cpu16_intc 9>,
280 <&cpu17_intc 11>, <&cpu17_intc 9>,
281 <&cpu18_intc 11>, <&cpu18_intc 9>,
282 <&cpu19_intc 11>, <&cpu19_intc 9>,
283 <&cpu20_intc 11>, <&cpu20_intc 9>,
284 <&cpu21_intc 11>, <&cpu21_intc 9>,
285 <&cpu22_intc 11>, <&cpu22_intc 9>,
286 <&cpu23_intc 11>, <&cpu23_intc 9>,
287 <&cpu24_intc 11>, <&cpu24_intc 9>,
288 <&cpu25_intc 11>, <&cpu25_intc 9>,
289 <&cpu26_intc 11>, <&cpu26_intc 9>,
290 <&cpu27_intc 11>, <&cpu27_intc 9>,
291 <&cpu28_intc 11>, <&cpu28_intc 9>,
292 <&cpu29_intc 11>, <&cpu29_intc 9>,
293 <&cpu30_intc 11>, <&cpu30_intc 9>,
294 <&cpu31_intc 11>, <&cpu31_intc 9>,
295 <&cpu32_intc 11>, <&cpu32_intc 9>,
296 <&cpu33_intc 11>, <&cpu33_intc 9>,
297 <&cpu34_intc 11>, <&cpu34_intc 9>,
298 <&cpu35_intc 11>, <&cpu35_intc 9>,
299 <&cpu36_intc 11>, <&cpu36_intc 9>,
300 <&cpu37_intc 11>, <&cpu37_intc 9>,
301 <&cpu38_intc 11>, <&cpu38_intc 9>,
302 <&cpu39_intc 11>, <&cpu39_intc 9>,
303 <&cpu40_intc 11>, <&cpu40_intc 9>,
304 <&cpu41_intc 11>, <&cpu41_intc 9>,
305 <&cpu42_intc 11>, <&cpu42_intc 9>,
306 <&cpu43_intc 11>, <&cpu43_intc 9>,
307 <&cpu44_intc 11>, <&cpu44_intc 9>,
308 <&cpu45_intc 11>, <&cpu45_intc 9>,
309 <&cpu46_intc 11>, <&cpu46_intc 9>,
310 <&cpu47_intc 11>, <&cpu47_intc 9>,
311 <&cpu48_intc 11>, <&cpu48_intc 9>,
312 <&cpu49_intc 11>, <&cpu49_intc 9>,
313 <&cpu50_intc 11>, <&cpu50_intc 9>,
314 <&cpu51_intc 11>, <&cpu51_intc 9>,
315 <&cpu52_intc 11>, <&cpu52_intc 9>,
316 <&cpu53_intc 11>, <&cpu53_intc 9>,
317 <&cpu54_intc 11>, <&cpu54_intc 9>,
318 <&cpu55_intc 11>, <&cpu55_intc 9>,
319 <&cpu56_intc 11>, <&cpu56_intc 9>,
320 <&cpu57_intc 11>, <&cpu57_intc 9>,
321 <&cpu58_intc 11>, <&cpu58_intc 9>,
322 <&cpu59_intc 11>, <&cpu59_intc 9>,
323 <&cpu60_intc 11>, <&cpu60_intc 9>,
324 <&cpu61_intc 11>, <&cpu61_intc 9>,
325 <&cpu62_intc 11>, <&cpu62_intc 9>,
326 <&cpu63_intc 11>, <&cpu63_intc 9>;
327 riscv,ndev = <224>;
328 };
329
330 uart0: serial@7040000000 {
331 compatible = "snps,dw-apb-uart";
332 reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
333 interrupt-parent = <&intc>;
334 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
335 clock-frequency = <500000000>;
336 reg-shift = <2>;
337 reg-io-width = <4>;
338 status = "disabled";
339 };
340 };
341};