1// SPDX-License-Identifier: GPL-2.0
  2/***************************************************************************/
  3
  4/*
  5 *	sltimers.c -- generic ColdFire slice timer support.
  6 *
  7 *	Copyright (C) 2009-2010, Philippe De Muyter <phdm@macqel.be>
  8 *	based on
  9 *	timers.c -- generic ColdFire hardware timer support.
 10 *	Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
 11 */
 12
 13/***************************************************************************/
 14
 15#include <linux/kernel.h>
 16#include <linux/init.h>
 17#include <linux/sched.h>
 18#include <linux/interrupt.h>
 19#include <linux/irq.h>
 20#include <linux/profile.h>
 21#include <linux/clocksource.h>
 22#include <asm/io.h>
 23#include <asm/traps.h>
 24#include <asm/machdep.h>
 25#include <asm/coldfire.h>
 26#include <asm/mcfslt.h>
 27#include <asm/mcfsim.h>
 28
 29/***************************************************************************/
 30
 31#ifdef CONFIG_HIGHPROFILE
 32
 33/*
 34 *	By default use Slice Timer 1 as the profiler clock timer.
 35 */
 36#define	PA(a)	(MCFSLT_TIMER1 + (a))
 37
 38/*
 39 *	Choose a reasonably fast profile timer. Make it an odd value to
 40 *	try and get good coverage of kernel operations.
 41 */
 42#define	PROFILEHZ	1013
 43
 44irqreturn_t mcfslt_profile_tick(int irq, void *dummy)
 45{
 46	/* Reset Slice Timer 1 */
 47	__raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR));
 48	if (current->pid)
 49		profile_tick(CPU_PROFILING);
 50	return IRQ_HANDLED;
 51}
 52
 53void mcfslt_profile_init(void)
 54{
 55	int ret;
 56
 57	printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n",
 58	       PROFILEHZ);
 59
 60	ret = request_irq(MCF_IRQ_PROFILER, mcfslt_profile_tick, IRQF_TIMER,
 61			  "profile timer", NULL);
 62	if (ret) {
 63		pr_err("Failed to request irq %d (profile timer): %pe\n",
 64		       MCF_IRQ_PROFILER, ERR_PTR(ret));
 65	}
 66
 67	/* Set up TIMER 2 as high speed profile clock */
 68	__raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
 69	__raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
 70								PA(MCFSLT_SCR));
 71
 72}
 73
 74#endif	/* CONFIG_HIGHPROFILE */
 75
 76/***************************************************************************/
 77
 78/*
 79 *	By default use Slice Timer 0 as the system clock timer.
 80 */
 81#define	TA(a)	(MCFSLT_TIMER0 + (a))
 82
 83static u32 mcfslt_cycles_per_jiffy;
 84static u32 mcfslt_cnt;
 85
 86static irqreturn_t mcfslt_tick(int irq, void *dummy)
 87{
 88	/* Reset Slice Timer 0 */
 89	__raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
 90	mcfslt_cnt += mcfslt_cycles_per_jiffy;
 91	legacy_timer_tick(1);
 92	return IRQ_HANDLED;
 93}
 94
 95static u64 mcfslt_read_clk(struct clocksource *cs)
 96{
 97	unsigned long flags;
 98	u32 cycles, scnt;
 99
100	local_irq_save(flags);
101	scnt = __raw_readl(TA(MCFSLT_SCNT));
102	cycles = mcfslt_cnt;
103	if (__raw_readl(TA(MCFSLT_SSR)) & MCFSLT_SSR_TE) {
104		cycles += mcfslt_cycles_per_jiffy;
105		scnt = __raw_readl(TA(MCFSLT_SCNT));
106	}
107	local_irq_restore(flags);
108
109	/* subtract because slice timers count down */
110	return cycles + ((mcfslt_cycles_per_jiffy - 1) - scnt);
111}
112
113static struct clocksource mcfslt_clk = {
114	.name	= "slt",
115	.rating	= 250,
116	.read	= mcfslt_read_clk,
117	.mask	= CLOCKSOURCE_MASK(32),
118	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
119};
120
121void hw_timer_init(void)
122{
123	int r;
124
125	mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ;
126	/*
127	 *	The coldfire slice timer (SLT) runs from STCNT to 0 included,
128	 *	then STCNT again and so on.  It counts thus actually
129	 *	STCNT + 1 steps for 1 tick, not STCNT.  So if you want
130	 *	n cycles, initialize STCNT with n - 1.
131	 */
132	__raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
133	__raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
134								TA(MCFSLT_SCR));
135	/* initialize mcfslt_cnt knowing that slice timers count down */
136	mcfslt_cnt = mcfslt_cycles_per_jiffy;
137
138	r = request_irq(MCF_IRQ_TIMER, mcfslt_tick, IRQF_TIMER, "timer", NULL);
139	if (r) {
140		pr_err("Failed to request irq %d (timer): %pe\n", MCF_IRQ_TIMER,
141		       ERR_PTR(r));
142	}
143
144	clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK);
145
146#ifdef CONFIG_HIGHPROFILE
147	mcfslt_profile_init();
148#endif
149}