1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * SP7021 Pin Controller Driver.
  4 * Copyright (C) Sunplus Tech / Tibbo Tech.
  5 */
  6
  7#ifndef __SPPCTL_H__
  8#define __SPPCTL_H__
  9
 10#include <linux/bits.h>
 11#include <linux/gpio/driver.h>
 12#include <linux/kernel.h>
 13#include <linux/pinctrl/pinctrl.h>
 14#include <linux/spinlock.h>
 15#include <linux/types.h>
 16
 17#define SPPCTL_MODULE_NAME		"sppctl_sp7021"
 18
 19#define SPPCTL_GPIO_OFF_FIRST		0x00
 20#define SPPCTL_GPIO_OFF_MASTER		0x00
 21#define SPPCTL_GPIO_OFF_OE		0x20
 22#define SPPCTL_GPIO_OFF_OUT		0x40
 23#define SPPCTL_GPIO_OFF_IN		0x60
 24#define SPPCTL_GPIO_OFF_IINV		0x80
 25#define SPPCTL_GPIO_OFF_OINV		0xa0
 26#define SPPCTL_GPIO_OFF_OD		0xc0
 27
 28#define SPPCTL_FULLY_PINMUX_MASK_MASK	GENMASK(22, 16)
 29#define SPPCTL_FULLY_PINMUX_SEL_MASK	GENMASK(6, 0)
 30#define SPPCTL_FULLY_PINMUX_UPPER_SHIFT	8
 31
 32/*
 33 * Mask-fields and control-fields of MOON registers of SP7021 are
 34 * arranged as shown below:
 35 *
 36 *  register |  mask-fields | control-fields
 37 * ----------+--------------+----------------
 38 *  base[0]  |  (31 : 16)   |   (15 : 0)
 39 *  base[1]  |  (31 : 24)   |   (15 : 0)
 40 *  base[2]  |  (31 : 24)   |   (15 : 0)
 41 *     :     |      :       |       :
 42 *
 43 * where mask-fields are used to protect control-fields from write-in
 44 * accidentally. Set the corresponding bits in the mask-field before
 45 * you write a value into a control-field.
 46 */
 47#define SPPCTL_MOON_REG_MASK_SHIFT	16
 48#define SPPCTL_SET_MOON_REG_BIT(bit)	(BIT((bit) + SPPCTL_MOON_REG_MASK_SHIFT) | BIT(bit))
 49#define SPPCTL_CLR_MOON_REG_BIT(bit)	BIT((bit) + SPPCTL_MOON_REG_MASK_SHIFT)
 50
 51#define SPPCTL_IOP_CONFIGS		0xff
 52
 53#define FNCE(n, r, o, bo, bl, g) { \
 54	.name = n, \
 55	.type = r, \
 56	.roff = o, \
 57	.boff = bo, \
 58	.blen = bl, \
 59	.grps = (g), \
 60	.gnum = ARRAY_SIZE(g), \
 61}
 62
 63#define FNCN(n, r, o, bo, bl) { \
 64	.name = n, \
 65	.type = r, \
 66	.roff = o, \
 67	.boff = bo, \
 68	.blen = bl, \
 69	.grps = NULL, \
 70	.gnum = 0, \
 71}
 72
 73#define EGRP(n, v, p) { \
 74	.name = n, \
 75	.gval = (v), \
 76	.pins = (p), \
 77	.pnum = ARRAY_SIZE(p), \
 78}
 79
 80/**
 81 * enum mux_first_reg - Define modes of access of FIRST register
 82 * @mux_f_mux:  Set the corresponding pin to a fully-pinmux pin
 83 * @mux_f_gpio: Set the corresponding pin to a GPIO or IOP pin
 84 * @mux_f_keep: Don't change (keep intact)
 85 */
 86enum mux_first_reg {
 87	mux_f_mux = 0,
 88	mux_f_gpio = 1,
 89	mux_f_keep = 2,
 90};
 91
 92/**
 93 * enum mux_master_reg - Define modes of access of MASTER register
 94 * @mux_m_iop:  Set the corresponding pin to an IO processor (IOP) pin
 95 * @mux_m_gpio: Set the corresponding pin to a digital GPIO pin
 96 * @mux_m_keep: Don't change (keep intact)
 97 */
 98enum mux_master_reg {
 99	mux_m_iop = 0,
100	mux_m_gpio = 1,
101	mux_m_keep = 2,
102};
103
104/**
105 * enum pinmux_type - Define types of pinmux pins
106 * @pinmux_type_fpmx: A fully-pinmux pin
107 * @pinmux_type_grp:  A group-pinmux pin
108 */
109enum pinmux_type {
110	pinmux_type_fpmx,
111	pinmux_type_grp,
112};
113
114/**
115 * struct grp2fp_map - A map storing indexes
116 * @f_idx: an index to function table
117 * @g_idx: an index to group table
118 */
119struct grp2fp_map {
120	u16 f_idx;
121	u16 g_idx;
122};
123
124struct sppctl_gpio_chip;
125
126struct sppctl_pdata {
127	void __iomem *moon2_base;	/* MOON2                                 */
128	void __iomem *gpioxt_base;	/* MASTER, OE, OUT, IN, I_INV, O_INV, OD */
129	void __iomem *first_base;	/* FIRST                                 */
130	void __iomem *moon1_base;	/* MOON1               */
131
132	struct pinctrl_desc pctl_desc;
133	struct pinctrl_dev *pctl_dev;
134	struct pinctrl_gpio_range pctl_grange;
135	struct sppctl_gpio_chip *spp_gchip;
136
137	char const **unq_grps;
138	size_t unq_grps_sz;
139	struct grp2fp_map *g2fp_maps;
140};
141
142struct sppctl_grp {
143	const char * const name;
144	const u8 gval;                  /* group number   */
145	const unsigned * const pins;    /* list of pins   */
146	const unsigned int pnum;        /* number of pins */
147};
148
149struct sppctl_func {
150	const char * const name;
151	const enum pinmux_type type;    /* function type          */
152	const u8 roff;                  /* register offset        */
153	const u8 boff;                  /* bit offset             */
154	const u8 blen;                  /* bit length             */
155	const struct sppctl_grp * const grps; /* list of groups   */
156	const unsigned int gnum;        /* number of groups       */
157};
158
159extern const struct sppctl_func sppctl_list_funcs[];
160extern const char * const sppctl_pmux_list_s[];
161extern const char * const sppctl_gpio_list_s[];
162extern const struct pinctrl_pin_desc sppctl_pins_all[];
163extern const unsigned int sppctl_pins_gpio[];
164
165extern const size_t sppctl_list_funcs_sz;
166extern const size_t sppctl_pmux_list_sz;
167extern const size_t sppctl_gpio_list_sz;
168extern const size_t sppctl_pins_all_sz;
169
170#endif