1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * PCIe host controller driver for HiSilicon SoCs
  4 *
  5 * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
  6 *
  7 * Authors: Zhou Wang <wangzhou1@hisilicon.com>
  8 *          Dacai Zhu <zhudacai@hisilicon.com>
  9 *          Gabriele Paoloni <gabriele.paoloni@huawei.com>
 10 */
 11#include <linux/interrupt.h>
 12#include <linux/init.h>
 13#include <linux/platform_device.h>
 14#include <linux/pci.h>
 15#include <linux/pci-acpi.h>
 16#include <linux/pci-ecam.h>
 17#include "../../pci.h"
 18
 19#if defined(CONFIG_PCI_HISI) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
 20
 21struct hisi_pcie {
 22	void __iomem	*reg_base;
 23};
 24
 25static int hisi_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 26			     int size, u32 *val)
 27{
 28	struct pci_config_window *cfg = bus->sysdata;
 29	int dev = PCI_SLOT(devfn);
 30
 31	if (bus->number == cfg->busr.start) {
 32		/* access only one slot on each root port */
 33		if (dev > 0)
 34			return PCIBIOS_DEVICE_NOT_FOUND;
 35		else
 36			return pci_generic_config_read32(bus, devfn, where,
 37							 size, val);
 38	}
 39
 40	return pci_generic_config_read(bus, devfn, where, size, val);
 41}
 42
 43static int hisi_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 44			     int where, int size, u32 val)
 45{
 46	struct pci_config_window *cfg = bus->sysdata;
 47	int dev = PCI_SLOT(devfn);
 48
 49	if (bus->number == cfg->busr.start) {
 50		/* access only one slot on each root port */
 51		if (dev > 0)
 52			return PCIBIOS_DEVICE_NOT_FOUND;
 53		else
 54			return pci_generic_config_write32(bus, devfn, where,
 55							  size, val);
 56	}
 57
 58	return pci_generic_config_write(bus, devfn, where, size, val);
 59}
 60
 61static void __iomem *hisi_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
 62				       int where)
 63{
 64	struct pci_config_window *cfg = bus->sysdata;
 65	struct hisi_pcie *pcie = cfg->priv;
 66
 67	if (bus->number == cfg->busr.start)
 68		return pcie->reg_base + where;
 69	else
 70		return pci_ecam_map_bus(bus, devfn, where);
 71}
 72
 73#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
 74
 75static int hisi_pcie_init(struct pci_config_window *cfg)
 76{
 77	struct device *dev = cfg->parent;
 78	struct hisi_pcie *pcie;
 79	struct acpi_device *adev = to_acpi_device(dev);
 80	struct acpi_pci_root *root = acpi_driver_data(adev);
 81	struct resource *res;
 82	int ret;
 83
 84	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
 85	if (!pcie)
 86		return -ENOMEM;
 87
 88	/*
 89	 * Retrieve RC base and size from a HISI0081 device with _UID
 90	 * matching our segment.
 91	 */
 92	res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
 93	if (!res)
 94		return -ENOMEM;
 95
 96	ret = acpi_get_rc_resources(dev, "HISI0081", root->segment, res);
 97	if (ret) {
 98		dev_err(dev, "can't get rc base address\n");
 99		return -ENOMEM;
100	}
101
102	pcie->reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
103	if (!pcie->reg_base)
104		return -ENOMEM;
105
106	cfg->priv = pcie;
107	return 0;
108}
109
110const struct pci_ecam_ops hisi_pcie_ops = {
111	.init         =  hisi_pcie_init,
112	.pci_ops      = {
113		.map_bus    = hisi_pcie_map_bus,
114		.read       = hisi_pcie_rd_conf,
115		.write      = hisi_pcie_wr_conf,
116	}
117};
118
119#endif
120
121#ifdef CONFIG_PCI_HISI
122
123static int hisi_pcie_platform_init(struct pci_config_window *cfg)
124{
125	struct device *dev = cfg->parent;
126	struct hisi_pcie *pcie;
127	struct platform_device *pdev = to_platform_device(dev);
128	struct resource *res;
129
130	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
131	if (!pcie)
132		return -ENOMEM;
133
134	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
135	if (!res) {
136		dev_err(dev, "missing \"reg[1]\"property\n");
137		return -EINVAL;
138	}
139
140	pcie->reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
141	if (!pcie->reg_base)
142		return -ENOMEM;
143
144	cfg->priv = pcie;
145	return 0;
146}
147
148static const struct pci_ecam_ops hisi_pcie_platform_ops = {
149	.init         =  hisi_pcie_platform_init,
150	.pci_ops      = {
151		.map_bus    = hisi_pcie_map_bus,
152		.read       = hisi_pcie_rd_conf,
153		.write      = hisi_pcie_wr_conf,
154	}
155};
156
157static const struct of_device_id hisi_pcie_almost_ecam_of_match[] = {
158	{
159		.compatible =  "hisilicon,hip06-pcie-ecam",
160		.data	    =  &hisi_pcie_platform_ops,
161	},
162	{
163		.compatible =  "hisilicon,hip07-pcie-ecam",
164		.data       =  &hisi_pcie_platform_ops,
165	},
166	{},
167};
168
169static struct platform_driver hisi_pcie_almost_ecam_driver = {
170	.probe  = pci_host_common_probe,
171	.driver = {
172		   .name = "hisi-pcie-almost-ecam",
173		   .of_match_table = hisi_pcie_almost_ecam_of_match,
174		   .suppress_bind_attrs = true,
175	},
176};
177builtin_platform_driver(hisi_pcie_almost_ecam_driver);
178
179#endif
180#endif