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1/*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
4 * Copyright (C) 2008-2022, VMware, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
23 * Maintained by: pv-drivers@vmware.com
24 *
25 */
26
27#include <linux/module.h>
28#include <net/ip6_checksum.h>
29
30#include "vmxnet3_int.h"
31#include "vmxnet3_xdp.h"
32
33char vmxnet3_driver_name[] = "vmxnet3";
34#define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
35
36/*
37 * PCI Device ID Table
38 * Last entry must be all 0s
39 */
40static const struct pci_device_id vmxnet3_pciid_table[] = {
41 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
42 {0}
43};
44
45MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
46
47static int enable_mq = 1;
48
49static void
50vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, const u8 *mac);
51
52/*
53 * Enable/Disable the given intr
54 */
55static void
56vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
57{
58 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
59}
60
61
62static void
63vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
64{
65 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
66}
67
68
69/*
70 * Enable/Disable all intrs used by the device
71 */
72static void
73vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
74{
75 int i;
76
77 for (i = 0; i < adapter->intr.num_intrs; i++)
78 vmxnet3_enable_intr(adapter, i);
79 if (!VMXNET3_VERSION_GE_6(adapter) ||
80 !adapter->queuesExtEnabled) {
81 adapter->shared->devRead.intrConf.intrCtrl &=
82 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
83 } else {
84 adapter->shared->devReadExt.intrConfExt.intrCtrl &=
85 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
86 }
87}
88
89
90static void
91vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
92{
93 int i;
94
95 if (!VMXNET3_VERSION_GE_6(adapter) ||
96 !adapter->queuesExtEnabled) {
97 adapter->shared->devRead.intrConf.intrCtrl |=
98 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
99 } else {
100 adapter->shared->devReadExt.intrConfExt.intrCtrl |=
101 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
102 }
103 for (i = 0; i < adapter->intr.num_intrs; i++)
104 vmxnet3_disable_intr(adapter, i);
105}
106
107
108static void
109vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
110{
111 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
112}
113
114
115static bool
116vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
117{
118 return tq->stopped;
119}
120
121
122static void
123vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
124{
125 tq->stopped = false;
126 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
127}
128
129
130static void
131vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
132{
133 tq->stopped = false;
134 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
135}
136
137
138static void
139vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
140{
141 tq->stopped = true;
142 tq->num_stop++;
143 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
144}
145
146/* Check if capability is supported by UPT device or
147 * UPT is even requested
148 */
149bool
150vmxnet3_check_ptcapability(u32 cap_supported, u32 cap)
151{
152 if (cap_supported & (1UL << VMXNET3_DCR_ERROR) ||
153 cap_supported & (1UL << cap)) {
154 return true;
155 }
156
157 return false;
158}
159
160
161/*
162 * Check the link state. This may start or stop the tx queue.
163 */
164static void
165vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
166{
167 u32 ret;
168 int i;
169 unsigned long flags;
170
171 spin_lock_irqsave(&adapter->cmd_lock, flags);
172 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
173 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
174 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
175
176 adapter->link_speed = ret >> 16;
177 if (ret & 1) { /* Link is up. */
178 netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n",
179 adapter->link_speed);
180 netif_carrier_on(adapter->netdev);
181
182 if (affectTxQueue) {
183 for (i = 0; i < adapter->num_tx_queues; i++)
184 vmxnet3_tq_start(&adapter->tx_queue[i],
185 adapter);
186 }
187 } else {
188 netdev_info(adapter->netdev, "NIC Link is Down\n");
189 netif_carrier_off(adapter->netdev);
190
191 if (affectTxQueue) {
192 for (i = 0; i < adapter->num_tx_queues; i++)
193 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
194 }
195 }
196}
197
198static void
199vmxnet3_process_events(struct vmxnet3_adapter *adapter)
200{
201 int i;
202 unsigned long flags;
203 u32 events = le32_to_cpu(adapter->shared->ecr);
204 if (!events)
205 return;
206
207 vmxnet3_ack_events(adapter, events);
208
209 /* Check if link state has changed */
210 if (events & VMXNET3_ECR_LINK)
211 vmxnet3_check_link(adapter, true);
212
213 /* Check if there is an error on xmit/recv queues */
214 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
215 spin_lock_irqsave(&adapter->cmd_lock, flags);
216 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
217 VMXNET3_CMD_GET_QUEUE_STATUS);
218 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
219
220 for (i = 0; i < adapter->num_tx_queues; i++)
221 if (adapter->tqd_start[i].status.stopped)
222 dev_err(&adapter->netdev->dev,
223 "%s: tq[%d] error 0x%x\n",
224 adapter->netdev->name, i, le32_to_cpu(
225 adapter->tqd_start[i].status.error));
226 for (i = 0; i < adapter->num_rx_queues; i++)
227 if (adapter->rqd_start[i].status.stopped)
228 dev_err(&adapter->netdev->dev,
229 "%s: rq[%d] error 0x%x\n",
230 adapter->netdev->name, i,
231 adapter->rqd_start[i].status.error);
232
233 schedule_work(&adapter->work);
234 }
235}
236
237#ifdef __BIG_ENDIAN_BITFIELD
238/*
239 * The device expects the bitfields in shared structures to be written in
240 * little endian. When CPU is big endian, the following routines are used to
241 * correctly read and write into ABI.
242 * The general technique used here is : double word bitfields are defined in
243 * opposite order for big endian architecture. Then before reading them in
244 * driver the complete double word is translated using le32_to_cpu. Similarly
245 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
246 * double words into required format.
247 * In order to avoid touching bits in shared structure more than once, temporary
248 * descriptors are used. These are passed as srcDesc to following functions.
249 */
250static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
251 struct Vmxnet3_RxDesc *dstDesc)
252{
253 u32 *src = (u32 *)srcDesc + 2;
254 u32 *dst = (u32 *)dstDesc + 2;
255 dstDesc->addr = le64_to_cpu(srcDesc->addr);
256 *dst = le32_to_cpu(*src);
257 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
258}
259
260static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
261 struct Vmxnet3_TxDesc *dstDesc)
262{
263 int i;
264 u32 *src = (u32 *)(srcDesc + 1);
265 u32 *dst = (u32 *)(dstDesc + 1);
266
267 /* Working backwards so that the gen bit is set at the end. */
268 for (i = 2; i > 0; i--) {
269 src--;
270 dst--;
271 *dst = cpu_to_le32(*src);
272 }
273}
274
275
276static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
277 struct Vmxnet3_RxCompDesc *dstDesc)
278{
279 int i = 0;
280 u32 *src = (u32 *)srcDesc;
281 u32 *dst = (u32 *)dstDesc;
282 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
283 *dst = le32_to_cpu(*src);
284 src++;
285 dst++;
286 }
287}
288
289
290/* Used to read bitfield values from double words. */
291static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
292{
293 u32 temp = le32_to_cpu(*bitfield);
294 u32 mask = ((1 << size) - 1) << pos;
295 temp &= mask;
296 temp >>= pos;
297 return temp;
298}
299
300
301
302#endif /* __BIG_ENDIAN_BITFIELD */
303
304#ifdef __BIG_ENDIAN_BITFIELD
305
306# define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
307 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
308 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
309# define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
310 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
311 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
312# define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
313 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
314 VMXNET3_TCD_GEN_SIZE)
315# define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
316 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
317# define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
318 (dstrcd) = (tmp); \
319 vmxnet3_RxCompToCPU((rcd), (tmp)); \
320 } while (0)
321# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
322 (dstrxd) = (tmp); \
323 vmxnet3_RxDescToCPU((rxd), (tmp)); \
324 } while (0)
325
326#else
327
328# define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
329# define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
330# define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
331# define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
332# define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
333# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
334
335#endif /* __BIG_ENDIAN_BITFIELD */
336
337
338static void
339vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
340 struct pci_dev *pdev)
341{
342 u32 map_type = tbi->map_type;
343
344 if (map_type & VMXNET3_MAP_SINGLE)
345 dma_unmap_single(&pdev->dev, tbi->dma_addr, tbi->len,
346 DMA_TO_DEVICE);
347 else if (map_type & VMXNET3_MAP_PAGE)
348 dma_unmap_page(&pdev->dev, tbi->dma_addr, tbi->len,
349 DMA_TO_DEVICE);
350 else
351 BUG_ON(map_type & ~VMXNET3_MAP_XDP);
352
353 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
354}
355
356
357static int
358vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
359 struct pci_dev *pdev, struct vmxnet3_adapter *adapter,
360 struct xdp_frame_bulk *bq)
361{
362 struct vmxnet3_tx_buf_info *tbi;
363 int entries = 0;
364 u32 map_type;
365
366 /* no out of order completion */
367 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
368 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
369
370 tbi = &tq->buf_info[eop_idx];
371 BUG_ON(!tbi->skb);
372 map_type = tbi->map_type;
373 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
374
375 while (tq->tx_ring.next2comp != eop_idx) {
376 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
377 pdev);
378
379 /* update next2comp w/o tx_lock. Since we are marking more,
380 * instead of less, tx ring entries avail, the worst case is
381 * that the tx routine incorrectly re-queues a pkt due to
382 * insufficient tx ring entries.
383 */
384 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
385 entries++;
386 }
387
388 if (map_type & VMXNET3_MAP_XDP)
389 xdp_return_frame_bulk(tbi->xdpf, bq);
390 else
391 dev_kfree_skb_any(tbi->skb);
392
393 /* xdpf and skb are in an anonymous union. */
394 tbi->skb = NULL;
395
396 return entries;
397}
398
399
400static int
401vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
402 struct vmxnet3_adapter *adapter)
403{
404 union Vmxnet3_GenericDesc *gdesc;
405 struct xdp_frame_bulk bq;
406 int completed = 0;
407
408 xdp_frame_bulk_init(&bq);
409 rcu_read_lock();
410
411 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
412 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
413 /* Prevent any &gdesc->tcd field from being (speculatively)
414 * read before (&gdesc->tcd)->gen is read.
415 */
416 dma_rmb();
417
418 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
419 &gdesc->tcd), tq, adapter->pdev,
420 adapter, &bq);
421
422 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
423 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
424 }
425 xdp_flush_frame_bulk(&bq);
426 rcu_read_unlock();
427
428 if (completed) {
429 spin_lock(&tq->tx_lock);
430 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
431 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
432 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
433 netif_carrier_ok(adapter->netdev))) {
434 vmxnet3_tq_wake(tq, adapter);
435 }
436 spin_unlock(&tq->tx_lock);
437 }
438 return completed;
439}
440
441
442static void
443vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
444 struct vmxnet3_adapter *adapter)
445{
446 struct xdp_frame_bulk bq;
447 u32 map_type;
448 int i;
449
450 xdp_frame_bulk_init(&bq);
451 rcu_read_lock();
452
453 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
454 struct vmxnet3_tx_buf_info *tbi;
455
456 tbi = tq->buf_info + tq->tx_ring.next2comp;
457 map_type = tbi->map_type;
458
459 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
460 if (tbi->skb) {
461 if (map_type & VMXNET3_MAP_XDP)
462 xdp_return_frame_bulk(tbi->xdpf, &bq);
463 else
464 dev_kfree_skb_any(tbi->skb);
465 tbi->skb = NULL;
466 }
467 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
468 }
469
470 xdp_flush_frame_bulk(&bq);
471 rcu_read_unlock();
472
473 /* sanity check, verify all buffers are indeed unmapped */
474 for (i = 0; i < tq->tx_ring.size; i++)
475 BUG_ON(tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
476
477 tq->tx_ring.gen = VMXNET3_INIT_GEN;
478 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
479
480 tq->comp_ring.gen = VMXNET3_INIT_GEN;
481 tq->comp_ring.next2proc = 0;
482}
483
484
485static void
486vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
487 struct vmxnet3_adapter *adapter)
488{
489 if (tq->tx_ring.base) {
490 dma_free_coherent(&adapter->pdev->dev, tq->tx_ring.size *
491 sizeof(struct Vmxnet3_TxDesc),
492 tq->tx_ring.base, tq->tx_ring.basePA);
493 tq->tx_ring.base = NULL;
494 }
495 if (tq->data_ring.base) {
496 dma_free_coherent(&adapter->pdev->dev,
497 tq->data_ring.size * tq->txdata_desc_size,
498 tq->data_ring.base, tq->data_ring.basePA);
499 tq->data_ring.base = NULL;
500 }
501 if (tq->comp_ring.base) {
502 dma_free_coherent(&adapter->pdev->dev, tq->comp_ring.size *
503 sizeof(struct Vmxnet3_TxCompDesc),
504 tq->comp_ring.base, tq->comp_ring.basePA);
505 tq->comp_ring.base = NULL;
506 }
507 kfree(tq->buf_info);
508 tq->buf_info = NULL;
509}
510
511
512/* Destroy all tx queues */
513void
514vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
515{
516 int i;
517
518 for (i = 0; i < adapter->num_tx_queues; i++)
519 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
520}
521
522
523static void
524vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
525 struct vmxnet3_adapter *adapter)
526{
527 int i;
528
529 /* reset the tx ring contents to 0 and reset the tx ring states */
530 memset(tq->tx_ring.base, 0, tq->tx_ring.size *
531 sizeof(struct Vmxnet3_TxDesc));
532 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
533 tq->tx_ring.gen = VMXNET3_INIT_GEN;
534
535 memset(tq->data_ring.base, 0,
536 tq->data_ring.size * tq->txdata_desc_size);
537
538 /* reset the tx comp ring contents to 0 and reset comp ring states */
539 memset(tq->comp_ring.base, 0, tq->comp_ring.size *
540 sizeof(struct Vmxnet3_TxCompDesc));
541 tq->comp_ring.next2proc = 0;
542 tq->comp_ring.gen = VMXNET3_INIT_GEN;
543
544 /* reset the bookkeeping data */
545 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
546 for (i = 0; i < tq->tx_ring.size; i++)
547 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
548
549 /* stats are not reset */
550}
551
552
553static int
554vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
555 struct vmxnet3_adapter *adapter)
556{
557 BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
558 tq->comp_ring.base || tq->buf_info);
559
560 tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
561 tq->tx_ring.size * sizeof(struct Vmxnet3_TxDesc),
562 &tq->tx_ring.basePA, GFP_KERNEL);
563 if (!tq->tx_ring.base) {
564 netdev_err(adapter->netdev, "failed to allocate tx ring\n");
565 goto err;
566 }
567
568 tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
569 tq->data_ring.size * tq->txdata_desc_size,
570 &tq->data_ring.basePA, GFP_KERNEL);
571 if (!tq->data_ring.base) {
572 netdev_err(adapter->netdev, "failed to allocate tx data ring\n");
573 goto err;
574 }
575
576 tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
577 tq->comp_ring.size * sizeof(struct Vmxnet3_TxCompDesc),
578 &tq->comp_ring.basePA, GFP_KERNEL);
579 if (!tq->comp_ring.base) {
580 netdev_err(adapter->netdev, "failed to allocate tx comp ring\n");
581 goto err;
582 }
583
584 tq->buf_info = kcalloc_node(tq->tx_ring.size, sizeof(tq->buf_info[0]),
585 GFP_KERNEL,
586 dev_to_node(&adapter->pdev->dev));
587 if (!tq->buf_info)
588 goto err;
589
590 return 0;
591
592err:
593 vmxnet3_tq_destroy(tq, adapter);
594 return -ENOMEM;
595}
596
597static void
598vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
599{
600 int i;
601
602 for (i = 0; i < adapter->num_tx_queues; i++)
603 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
604}
605
606/*
607 * starting from ring->next2fill, allocate rx buffers for the given ring
608 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
609 * are allocated or allocation fails
610 */
611
612static int
613vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
614 int num_to_alloc, struct vmxnet3_adapter *adapter)
615{
616 int num_allocated = 0;
617 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
618 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
619 u32 val;
620
621 while (num_allocated <= num_to_alloc) {
622 struct vmxnet3_rx_buf_info *rbi;
623 union Vmxnet3_GenericDesc *gd;
624
625 rbi = rbi_base + ring->next2fill;
626 gd = ring->base + ring->next2fill;
627 rbi->comp_state = VMXNET3_RXD_COMP_PENDING;
628
629 if (rbi->buf_type == VMXNET3_RX_BUF_XDP) {
630 void *data = vmxnet3_pp_get_buff(rq->page_pool,
631 &rbi->dma_addr,
632 GFP_KERNEL);
633 if (!data) {
634 rq->stats.rx_buf_alloc_failure++;
635 break;
636 }
637 rbi->page = virt_to_page(data);
638 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
639 } else if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
640 if (rbi->skb == NULL) {
641 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev,
642 rbi->len,
643 GFP_KERNEL);
644 if (unlikely(rbi->skb == NULL)) {
645 rq->stats.rx_buf_alloc_failure++;
646 break;
647 }
648
649 rbi->dma_addr = dma_map_single(
650 &adapter->pdev->dev,
651 rbi->skb->data, rbi->len,
652 DMA_FROM_DEVICE);
653 if (dma_mapping_error(&adapter->pdev->dev,
654 rbi->dma_addr)) {
655 dev_kfree_skb_any(rbi->skb);
656 rbi->skb = NULL;
657 rq->stats.rx_buf_alloc_failure++;
658 break;
659 }
660 } else {
661 /* rx buffer skipped by the device */
662 }
663 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
664 } else {
665 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
666 rbi->len != PAGE_SIZE);
667
668 if (rbi->page == NULL) {
669 rbi->page = alloc_page(GFP_ATOMIC);
670 if (unlikely(rbi->page == NULL)) {
671 rq->stats.rx_buf_alloc_failure++;
672 break;
673 }
674 rbi->dma_addr = dma_map_page(
675 &adapter->pdev->dev,
676 rbi->page, 0, PAGE_SIZE,
677 DMA_FROM_DEVICE);
678 if (dma_mapping_error(&adapter->pdev->dev,
679 rbi->dma_addr)) {
680 put_page(rbi->page);
681 rbi->page = NULL;
682 rq->stats.rx_buf_alloc_failure++;
683 break;
684 }
685 } else {
686 /* rx buffers skipped by the device */
687 }
688 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
689 }
690
691 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
692 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
693 | val | rbi->len);
694
695 /* Fill the last buffer but dont mark it ready, or else the
696 * device will think that the queue is full */
697 if (num_allocated == num_to_alloc) {
698 rbi->comp_state = VMXNET3_RXD_COMP_DONE;
699 break;
700 }
701
702 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
703 num_allocated++;
704 vmxnet3_cmd_ring_adv_next2fill(ring);
705 }
706
707 netdev_dbg(adapter->netdev,
708 "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n",
709 num_allocated, ring->next2fill, ring->next2comp);
710
711 /* so that the device can distinguish a full ring and an empty ring */
712 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
713
714 return num_allocated;
715}
716
717
718static void
719vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
720 struct vmxnet3_rx_buf_info *rbi)
721{
722 skb_frag_t *frag = skb_shinfo(skb)->frags + skb_shinfo(skb)->nr_frags;
723
724 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
725
726 skb_frag_fill_page_desc(frag, rbi->page, 0, rcd->len);
727 skb->data_len += rcd->len;
728 skb->truesize += PAGE_SIZE;
729 skb_shinfo(skb)->nr_frags++;
730}
731
732
733static int
734vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
735 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
736 struct vmxnet3_adapter *adapter)
737{
738 u32 dw2, len;
739 unsigned long buf_offset;
740 int i;
741 union Vmxnet3_GenericDesc *gdesc;
742 struct vmxnet3_tx_buf_info *tbi = NULL;
743
744 BUG_ON(ctx->copy_size > skb_headlen(skb));
745
746 /* use the previous gen bit for the SOP desc */
747 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
748
749 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
750 gdesc = ctx->sop_txd; /* both loops below can be skipped */
751
752 /* no need to map the buffer if headers are copied */
753 if (ctx->copy_size) {
754 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
755 tq->tx_ring.next2fill *
756 tq->txdata_desc_size);
757 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
758 ctx->sop_txd->dword[3] = 0;
759
760 tbi = tq->buf_info + tq->tx_ring.next2fill;
761 tbi->map_type = VMXNET3_MAP_NONE;
762
763 netdev_dbg(adapter->netdev,
764 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
765 tq->tx_ring.next2fill,
766 le64_to_cpu(ctx->sop_txd->txd.addr),
767 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
768 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
769
770 /* use the right gen for non-SOP desc */
771 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
772 }
773
774 /* linear part can use multiple tx desc if it's big */
775 len = skb_headlen(skb) - ctx->copy_size;
776 buf_offset = ctx->copy_size;
777 while (len) {
778 u32 buf_size;
779
780 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
781 buf_size = len;
782 dw2 |= len;
783 } else {
784 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
785 /* spec says that for TxDesc.len, 0 == 2^14 */
786 }
787
788 tbi = tq->buf_info + tq->tx_ring.next2fill;
789 tbi->map_type = VMXNET3_MAP_SINGLE;
790 tbi->dma_addr = dma_map_single(&adapter->pdev->dev,
791 skb->data + buf_offset, buf_size,
792 DMA_TO_DEVICE);
793 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
794 return -EFAULT;
795
796 tbi->len = buf_size;
797
798 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
799 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
800
801 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
802 gdesc->dword[2] = cpu_to_le32(dw2);
803 gdesc->dword[3] = 0;
804
805 netdev_dbg(adapter->netdev,
806 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
807 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
808 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
809 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
810 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
811
812 len -= buf_size;
813 buf_offset += buf_size;
814 }
815
816 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
817 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
818 u32 buf_size;
819
820 buf_offset = 0;
821 len = skb_frag_size(frag);
822 while (len) {
823 tbi = tq->buf_info + tq->tx_ring.next2fill;
824 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
825 buf_size = len;
826 dw2 |= len;
827 } else {
828 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
829 /* spec says that for TxDesc.len, 0 == 2^14 */
830 }
831 tbi->map_type = VMXNET3_MAP_PAGE;
832 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag,
833 buf_offset, buf_size,
834 DMA_TO_DEVICE);
835 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
836 return -EFAULT;
837
838 tbi->len = buf_size;
839
840 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
841 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
842
843 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
844 gdesc->dword[2] = cpu_to_le32(dw2);
845 gdesc->dword[3] = 0;
846
847 netdev_dbg(adapter->netdev,
848 "txd[%u]: 0x%llx %u %u\n",
849 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
850 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
851 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
852 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
853
854 len -= buf_size;
855 buf_offset += buf_size;
856 }
857 }
858
859 ctx->eop_txd = gdesc;
860
861 /* set the last buf_info for the pkt */
862 tbi->skb = skb;
863 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
864
865 return 0;
866}
867
868
869/* Init all tx queues */
870static void
871vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
872{
873 int i;
874
875 for (i = 0; i < adapter->num_tx_queues; i++)
876 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
877}
878
879
880/*
881 * parse relevant protocol headers:
882 * For a tso pkt, relevant headers are L2/3/4 including options
883 * For a pkt requesting csum offloading, they are L2/3 and may include L4
884 * if it's a TCP/UDP pkt
885 *
886 * Returns:
887 * -1: error happens during parsing
888 * 0: protocol headers parsed, but too big to be copied
889 * 1: protocol headers parsed and copied
890 *
891 * Other effects:
892 * 1. related *ctx fields are updated.
893 * 2. ctx->copy_size is # of bytes copied
894 * 3. the portion to be copied is guaranteed to be in the linear part
895 *
896 */
897static int
898vmxnet3_parse_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
899 struct vmxnet3_tx_ctx *ctx,
900 struct vmxnet3_adapter *adapter)
901{
902 u8 protocol = 0;
903
904 if (ctx->mss) { /* TSO */
905 if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) {
906 ctx->l4_offset = skb_inner_transport_offset(skb);
907 ctx->l4_hdr_size = inner_tcp_hdrlen(skb);
908 ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size;
909 } else {
910 ctx->l4_offset = skb_transport_offset(skb);
911 ctx->l4_hdr_size = tcp_hdrlen(skb);
912 ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size;
913 }
914 } else {
915 if (skb->ip_summed == CHECKSUM_PARTIAL) {
916 /* For encap packets, skb_checksum_start_offset refers
917 * to inner L4 offset. Thus, below works for encap as
918 * well as non-encap case
919 */
920 ctx->l4_offset = skb_checksum_start_offset(skb);
921
922 if (VMXNET3_VERSION_GE_4(adapter) &&
923 skb->encapsulation) {
924 struct iphdr *iph = inner_ip_hdr(skb);
925
926 if (iph->version == 4) {
927 protocol = iph->protocol;
928 } else {
929 const struct ipv6hdr *ipv6h;
930
931 ipv6h = inner_ipv6_hdr(skb);
932 protocol = ipv6h->nexthdr;
933 }
934 } else {
935 if (ctx->ipv4) {
936 const struct iphdr *iph = ip_hdr(skb);
937
938 protocol = iph->protocol;
939 } else if (ctx->ipv6) {
940 const struct ipv6hdr *ipv6h;
941
942 ipv6h = ipv6_hdr(skb);
943 protocol = ipv6h->nexthdr;
944 }
945 }
946
947 switch (protocol) {
948 case IPPROTO_TCP:
949 ctx->l4_hdr_size = skb->encapsulation ? inner_tcp_hdrlen(skb) :
950 tcp_hdrlen(skb);
951 break;
952 case IPPROTO_UDP:
953 ctx->l4_hdr_size = sizeof(struct udphdr);
954 break;
955 default:
956 ctx->l4_hdr_size = 0;
957 break;
958 }
959
960 ctx->copy_size = min(ctx->l4_offset +
961 ctx->l4_hdr_size, skb->len);
962 } else {
963 ctx->l4_offset = 0;
964 ctx->l4_hdr_size = 0;
965 /* copy as much as allowed */
966 ctx->copy_size = min_t(unsigned int,
967 tq->txdata_desc_size,
968 skb_headlen(skb));
969 }
970
971 if (skb->len <= VMXNET3_HDR_COPY_SIZE)
972 ctx->copy_size = skb->len;
973
974 /* make sure headers are accessible directly */
975 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
976 goto err;
977 }
978
979 if (unlikely(ctx->copy_size > tq->txdata_desc_size)) {
980 tq->stats.oversized_hdr++;
981 ctx->copy_size = 0;
982 return 0;
983 }
984
985 return 1;
986err:
987 return -1;
988}
989
990/*
991 * copy relevant protocol headers to the transmit ring:
992 * For a tso pkt, relevant headers are L2/3/4 including options
993 * For a pkt requesting csum offloading, they are L2/3 and may include L4
994 * if it's a TCP/UDP pkt
995 *
996 *
997 * Note that this requires that vmxnet3_parse_hdr be called first to set the
998 * appropriate bits in ctx first
999 */
1000static void
1001vmxnet3_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
1002 struct vmxnet3_tx_ctx *ctx,
1003 struct vmxnet3_adapter *adapter)
1004{
1005 struct Vmxnet3_TxDataDesc *tdd;
1006
1007 tdd = (struct Vmxnet3_TxDataDesc *)((u8 *)tq->data_ring.base +
1008 tq->tx_ring.next2fill *
1009 tq->txdata_desc_size);
1010
1011 memcpy(tdd->data, skb->data, ctx->copy_size);
1012 netdev_dbg(adapter->netdev,
1013 "copy %u bytes to dataRing[%u]\n",
1014 ctx->copy_size, tq->tx_ring.next2fill);
1015}
1016
1017
1018static void
1019vmxnet3_prepare_inner_tso(struct sk_buff *skb,
1020 struct vmxnet3_tx_ctx *ctx)
1021{
1022 struct tcphdr *tcph = inner_tcp_hdr(skb);
1023 struct iphdr *iph = inner_ip_hdr(skb);
1024
1025 if (iph->version == 4) {
1026 iph->check = 0;
1027 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
1028 IPPROTO_TCP, 0);
1029 } else {
1030 struct ipv6hdr *iph = inner_ipv6_hdr(skb);
1031
1032 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
1033 IPPROTO_TCP, 0);
1034 }
1035}
1036
1037static void
1038vmxnet3_prepare_tso(struct sk_buff *skb,
1039 struct vmxnet3_tx_ctx *ctx)
1040{
1041 struct tcphdr *tcph = tcp_hdr(skb);
1042
1043 if (ctx->ipv4) {
1044 struct iphdr *iph = ip_hdr(skb);
1045
1046 iph->check = 0;
1047 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
1048 IPPROTO_TCP, 0);
1049 } else if (ctx->ipv6) {
1050 tcp_v6_gso_csum_prep(skb);
1051 }
1052}
1053
1054static int txd_estimate(const struct sk_buff *skb)
1055{
1056 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
1057 int i;
1058
1059 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1060 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1061
1062 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag));
1063 }
1064 return count;
1065}
1066
1067/*
1068 * Transmits a pkt thru a given tq
1069 * Returns:
1070 * NETDEV_TX_OK: descriptors are setup successfully
1071 * NETDEV_TX_OK: error occurred, the pkt is dropped
1072 * NETDEV_TX_BUSY: tx ring is full, queue is stopped
1073 *
1074 * Side-effects:
1075 * 1. tx ring may be changed
1076 * 2. tq stats may be updated accordingly
1077 * 3. shared->txNumDeferred may be updated
1078 */
1079
1080static int
1081vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
1082 struct vmxnet3_adapter *adapter, struct net_device *netdev)
1083{
1084 int ret;
1085 u32 count;
1086 int num_pkts;
1087 int tx_num_deferred;
1088 unsigned long flags;
1089 struct vmxnet3_tx_ctx ctx;
1090 union Vmxnet3_GenericDesc *gdesc;
1091#ifdef __BIG_ENDIAN_BITFIELD
1092 /* Use temporary descriptor to avoid touching bits multiple times */
1093 union Vmxnet3_GenericDesc tempTxDesc;
1094#endif
1095
1096 count = txd_estimate(skb);
1097
1098 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
1099 ctx.ipv6 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IPV6));
1100
1101 ctx.mss = skb_shinfo(skb)->gso_size;
1102 if (ctx.mss) {
1103 if (skb_header_cloned(skb)) {
1104 if (unlikely(pskb_expand_head(skb, 0, 0,
1105 GFP_ATOMIC) != 0)) {
1106 tq->stats.drop_tso++;
1107 goto drop_pkt;
1108 }
1109 tq->stats.copy_skb_header++;
1110 }
1111 if (unlikely(count > VMXNET3_MAX_TSO_TXD_PER_PKT)) {
1112 /* tso pkts must not use more than
1113 * VMXNET3_MAX_TSO_TXD_PER_PKT entries
1114 */
1115 if (skb_linearize(skb) != 0) {
1116 tq->stats.drop_too_many_frags++;
1117 goto drop_pkt;
1118 }
1119 tq->stats.linearized++;
1120
1121 /* recalculate the # of descriptors to use */
1122 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
1123 if (unlikely(count > VMXNET3_MAX_TSO_TXD_PER_PKT)) {
1124 tq->stats.drop_too_many_frags++;
1125 goto drop_pkt;
1126 }
1127 }
1128 if (skb->encapsulation) {
1129 vmxnet3_prepare_inner_tso(skb, &ctx);
1130 } else {
1131 vmxnet3_prepare_tso(skb, &ctx);
1132 }
1133 } else {
1134 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
1135
1136 /* non-tso pkts must not use more than
1137 * VMXNET3_MAX_TXD_PER_PKT entries
1138 */
1139 if (skb_linearize(skb) != 0) {
1140 tq->stats.drop_too_many_frags++;
1141 goto drop_pkt;
1142 }
1143 tq->stats.linearized++;
1144
1145 /* recalculate the # of descriptors to use */
1146 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
1147 }
1148 }
1149
1150 ret = vmxnet3_parse_hdr(skb, tq, &ctx, adapter);
1151 if (ret >= 0) {
1152 BUG_ON(ret <= 0 && ctx.copy_size != 0);
1153 /* hdrs parsed, check against other limits */
1154 if (ctx.mss) {
1155 if (unlikely(ctx.l4_offset + ctx.l4_hdr_size >
1156 VMXNET3_MAX_TX_BUF_SIZE)) {
1157 tq->stats.drop_oversized_hdr++;
1158 goto drop_pkt;
1159 }
1160 } else {
1161 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1162 if (unlikely(ctx.l4_offset +
1163 skb->csum_offset >
1164 VMXNET3_MAX_CSUM_OFFSET)) {
1165 tq->stats.drop_oversized_hdr++;
1166 goto drop_pkt;
1167 }
1168 }
1169 }
1170 } else {
1171 tq->stats.drop_hdr_inspect_err++;
1172 goto drop_pkt;
1173 }
1174
1175 spin_lock_irqsave(&tq->tx_lock, flags);
1176
1177 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
1178 tq->stats.tx_ring_full++;
1179 netdev_dbg(adapter->netdev,
1180 "tx queue stopped on %s, next2comp %u"
1181 " next2fill %u\n", adapter->netdev->name,
1182 tq->tx_ring.next2comp, tq->tx_ring.next2fill);
1183
1184 vmxnet3_tq_stop(tq, adapter);
1185 spin_unlock_irqrestore(&tq->tx_lock, flags);
1186 return NETDEV_TX_BUSY;
1187 }
1188
1189
1190 vmxnet3_copy_hdr(skb, tq, &ctx, adapter);
1191
1192 /* fill tx descs related to addr & len */
1193 if (vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter))
1194 goto unlock_drop_pkt;
1195
1196 /* setup the EOP desc */
1197 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
1198
1199 /* setup the SOP desc */
1200#ifdef __BIG_ENDIAN_BITFIELD
1201 gdesc = &tempTxDesc;
1202 gdesc->dword[2] = ctx.sop_txd->dword[2];
1203 gdesc->dword[3] = ctx.sop_txd->dword[3];
1204#else
1205 gdesc = ctx.sop_txd;
1206#endif
1207 tx_num_deferred = le32_to_cpu(tq->shared->txNumDeferred);
1208 if (ctx.mss) {
1209 if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) {
1210 gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
1211 if (VMXNET3_VERSION_GE_7(adapter)) {
1212 gdesc->txd.om = VMXNET3_OM_TSO;
1213 gdesc->txd.ext1 = 1;
1214 } else {
1215 gdesc->txd.om = VMXNET3_OM_ENCAP;
1216 }
1217 gdesc->txd.msscof = ctx.mss;
1218
1219 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1220 gdesc->txd.oco = 1;
1221 } else {
1222 gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
1223 gdesc->txd.om = VMXNET3_OM_TSO;
1224 gdesc->txd.msscof = ctx.mss;
1225 }
1226 num_pkts = (skb->len - gdesc->txd.hlen + ctx.mss - 1) / ctx.mss;
1227 } else {
1228 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1229 if (VMXNET3_VERSION_GE_4(adapter) &&
1230 skb->encapsulation) {
1231 gdesc->txd.hlen = ctx.l4_offset +
1232 ctx.l4_hdr_size;
1233 if (VMXNET3_VERSION_GE_7(adapter)) {
1234 gdesc->txd.om = VMXNET3_OM_CSUM;
1235 gdesc->txd.msscof = ctx.l4_offset +
1236 skb->csum_offset;
1237 gdesc->txd.ext1 = 1;
1238 } else {
1239 gdesc->txd.om = VMXNET3_OM_ENCAP;
1240 gdesc->txd.msscof = 0; /* Reserved */
1241 }
1242 } else {
1243 gdesc->txd.hlen = ctx.l4_offset;
1244 gdesc->txd.om = VMXNET3_OM_CSUM;
1245 gdesc->txd.msscof = ctx.l4_offset +
1246 skb->csum_offset;
1247 }
1248 } else {
1249 gdesc->txd.om = 0;
1250 gdesc->txd.msscof = 0;
1251 }
1252 num_pkts = 1;
1253 }
1254 le32_add_cpu(&tq->shared->txNumDeferred, num_pkts);
1255 tx_num_deferred += num_pkts;
1256
1257 if (skb_vlan_tag_present(skb)) {
1258 gdesc->txd.ti = 1;
1259 gdesc->txd.tci = skb_vlan_tag_get(skb);
1260 }
1261
1262 /* Ensure that the write to (&gdesc->txd)->gen will be observed after
1263 * all other writes to &gdesc->txd.
1264 */
1265 dma_wmb();
1266
1267 /* finally flips the GEN bit of the SOP desc. */
1268 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1269 VMXNET3_TXD_GEN);
1270#ifdef __BIG_ENDIAN_BITFIELD
1271 /* Finished updating in bitfields of Tx Desc, so write them in original
1272 * place.
1273 */
1274 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1275 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1276 gdesc = ctx.sop_txd;
1277#endif
1278 netdev_dbg(adapter->netdev,
1279 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
1280 (u32)(ctx.sop_txd -
1281 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1282 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
1283
1284 spin_unlock_irqrestore(&tq->tx_lock, flags);
1285
1286 if (tx_num_deferred >= le32_to_cpu(tq->shared->txThreshold)) {
1287 tq->shared->txNumDeferred = 0;
1288 VMXNET3_WRITE_BAR0_REG(adapter,
1289 adapter->tx_prod_offset + tq->qid * 8,
1290 tq->tx_ring.next2fill);
1291 }
1292
1293 return NETDEV_TX_OK;
1294
1295unlock_drop_pkt:
1296 spin_unlock_irqrestore(&tq->tx_lock, flags);
1297drop_pkt:
1298 tq->stats.drop_total++;
1299 dev_kfree_skb_any(skb);
1300 return NETDEV_TX_OK;
1301}
1302
1303static int
1304vmxnet3_create_pp(struct vmxnet3_adapter *adapter,
1305 struct vmxnet3_rx_queue *rq, int size)
1306{
1307 bool xdp_prog = vmxnet3_xdp_enabled(adapter);
1308 const struct page_pool_params pp_params = {
1309 .order = 0,
1310 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
1311 .pool_size = size,
1312 .nid = NUMA_NO_NODE,
1313 .dev = &adapter->pdev->dev,
1314 .offset = VMXNET3_XDP_RX_OFFSET,
1315 .max_len = VMXNET3_XDP_MAX_FRSIZE,
1316 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE,
1317 };
1318 struct page_pool *pp;
1319 int err;
1320
1321 pp = page_pool_create(&pp_params);
1322 if (IS_ERR(pp))
1323 return PTR_ERR(pp);
1324
1325 err = xdp_rxq_info_reg(&rq->xdp_rxq, adapter->netdev, rq->qid,
1326 rq->napi.napi_id);
1327 if (err < 0)
1328 goto err_free_pp;
1329
1330 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq, MEM_TYPE_PAGE_POOL, pp);
1331 if (err)
1332 goto err_unregister_rxq;
1333
1334 rq->page_pool = pp;
1335
1336 return 0;
1337
1338err_unregister_rxq:
1339 xdp_rxq_info_unreg(&rq->xdp_rxq);
1340err_free_pp:
1341 page_pool_destroy(pp);
1342
1343 return err;
1344}
1345
1346void *
1347vmxnet3_pp_get_buff(struct page_pool *pp, dma_addr_t *dma_addr,
1348 gfp_t gfp_mask)
1349{
1350 struct page *page;
1351
1352 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN);
1353 if (unlikely(!page))
1354 return NULL;
1355
1356 *dma_addr = page_pool_get_dma_addr(page) + pp->p.offset;
1357
1358 return page_address(page);
1359}
1360
1361static netdev_tx_t
1362vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1363{
1364 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1365
1366 BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1367 return vmxnet3_tq_xmit(skb,
1368 &adapter->tx_queue[skb->queue_mapping],
1369 adapter, netdev);
1370}
1371
1372
1373static void
1374vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1375 struct sk_buff *skb,
1376 union Vmxnet3_GenericDesc *gdesc)
1377{
1378 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
1379 if (gdesc->rcd.v4 &&
1380 (le32_to_cpu(gdesc->dword[3]) &
1381 VMXNET3_RCD_CSUM_OK) == VMXNET3_RCD_CSUM_OK) {
1382 skb->ip_summed = CHECKSUM_UNNECESSARY;
1383 if ((le32_to_cpu(gdesc->dword[0]) &
1384 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT))) {
1385 skb->csum_level = 1;
1386 }
1387 WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
1388 !(le32_to_cpu(gdesc->dword[0]) &
1389 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1390 WARN_ON_ONCE(gdesc->rcd.frg &&
1391 !(le32_to_cpu(gdesc->dword[0]) &
1392 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1393 } else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) &
1394 (1 << VMXNET3_RCD_TUC_SHIFT))) {
1395 skb->ip_summed = CHECKSUM_UNNECESSARY;
1396 if ((le32_to_cpu(gdesc->dword[0]) &
1397 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT))) {
1398 skb->csum_level = 1;
1399 }
1400 WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
1401 !(le32_to_cpu(gdesc->dword[0]) &
1402 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1403 WARN_ON_ONCE(gdesc->rcd.frg &&
1404 !(le32_to_cpu(gdesc->dword[0]) &
1405 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1406 } else {
1407 if (gdesc->rcd.csum) {
1408 skb->csum = htons(gdesc->rcd.csum);
1409 skb->ip_summed = CHECKSUM_PARTIAL;
1410 } else {
1411 skb_checksum_none_assert(skb);
1412 }
1413 }
1414 } else {
1415 skb_checksum_none_assert(skb);
1416 }
1417}
1418
1419
1420static void
1421vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1422 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
1423{
1424 rq->stats.drop_err++;
1425 if (!rcd->fcs)
1426 rq->stats.drop_fcs++;
1427
1428 rq->stats.drop_total++;
1429
1430 /*
1431 * We do not unmap and chain the rx buffer to the skb.
1432 * We basically pretend this buffer is not used and will be recycled
1433 * by vmxnet3_rq_alloc_rx_buf()
1434 */
1435
1436 /*
1437 * ctx->skb may be NULL if this is the first and the only one
1438 * desc for the pkt
1439 */
1440 if (ctx->skb)
1441 dev_kfree_skb_irq(ctx->skb);
1442
1443 ctx->skb = NULL;
1444}
1445
1446
1447static u32
1448vmxnet3_get_hdr_len(struct vmxnet3_adapter *adapter, struct sk_buff *skb,
1449 union Vmxnet3_GenericDesc *gdesc)
1450{
1451 u32 hlen, maplen;
1452 union {
1453 void *ptr;
1454 struct ethhdr *eth;
1455 struct vlan_ethhdr *veth;
1456 struct iphdr *ipv4;
1457 struct ipv6hdr *ipv6;
1458 struct tcphdr *tcp;
1459 } hdr;
1460 BUG_ON(gdesc->rcd.tcp == 0);
1461
1462 maplen = skb_headlen(skb);
1463 if (unlikely(sizeof(struct iphdr) + sizeof(struct tcphdr) > maplen))
1464 return 0;
1465
1466 if (skb->protocol == cpu_to_be16(ETH_P_8021Q) ||
1467 skb->protocol == cpu_to_be16(ETH_P_8021AD))
1468 hlen = sizeof(struct vlan_ethhdr);
1469 else
1470 hlen = sizeof(struct ethhdr);
1471
1472 hdr.eth = eth_hdr(skb);
1473 if (gdesc->rcd.v4) {
1474 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IP) &&
1475 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IP));
1476 hdr.ptr += hlen;
1477 BUG_ON(hdr.ipv4->protocol != IPPROTO_TCP);
1478 hlen = hdr.ipv4->ihl << 2;
1479 hdr.ptr += hdr.ipv4->ihl << 2;
1480 } else if (gdesc->rcd.v6) {
1481 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IPV6) &&
1482 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IPV6));
1483 hdr.ptr += hlen;
1484 /* Use an estimated value, since we also need to handle
1485 * TSO case.
1486 */
1487 if (hdr.ipv6->nexthdr != IPPROTO_TCP)
1488 return sizeof(struct ipv6hdr) + sizeof(struct tcphdr);
1489 hlen = sizeof(struct ipv6hdr);
1490 hdr.ptr += sizeof(struct ipv6hdr);
1491 } else {
1492 /* Non-IP pkt, dont estimate header length */
1493 return 0;
1494 }
1495
1496 if (hlen + sizeof(struct tcphdr) > maplen)
1497 return 0;
1498
1499 return (hlen + (hdr.tcp->doff << 2));
1500}
1501
1502static int
1503vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1504 struct vmxnet3_adapter *adapter, int quota)
1505{
1506 u32 rxprod_reg[2] = {
1507 adapter->rx_prod_offset, adapter->rx_prod2_offset
1508 };
1509 u32 num_pkts = 0;
1510 bool skip_page_frags = false;
1511 bool encap_lro = false;
1512 struct Vmxnet3_RxCompDesc *rcd;
1513 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
1514 u16 segCnt = 0, mss = 0;
1515 int comp_offset, fill_offset;
1516#ifdef __BIG_ENDIAN_BITFIELD
1517 struct Vmxnet3_RxDesc rxCmdDesc;
1518 struct Vmxnet3_RxCompDesc rxComp;
1519#endif
1520 bool need_flush = false;
1521
1522 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1523 &rxComp);
1524 while (rcd->gen == rq->comp_ring.gen) {
1525 struct vmxnet3_rx_buf_info *rbi;
1526 struct sk_buff *skb, *new_skb = NULL;
1527 struct page *new_page = NULL;
1528 dma_addr_t new_dma_addr;
1529 int num_to_alloc;
1530 struct Vmxnet3_RxDesc *rxd;
1531 u32 idx, ring_idx;
1532 struct vmxnet3_cmd_ring *ring = NULL;
1533 if (num_pkts >= quota) {
1534 /* we may stop even before we see the EOP desc of
1535 * the current pkt
1536 */
1537 break;
1538 }
1539
1540 /* Prevent any rcd field from being (speculatively) read before
1541 * rcd->gen is read.
1542 */
1543 dma_rmb();
1544
1545 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2 &&
1546 rcd->rqID != rq->dataRingQid);
1547 idx = rcd->rxdIdx;
1548 ring_idx = VMXNET3_GET_RING_IDX(adapter, rcd->rqID);
1549 ring = rq->rx_ring + ring_idx;
1550 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1551 &rxCmdDesc);
1552 rbi = rq->buf_info[ring_idx] + idx;
1553
1554 BUG_ON(rxd->addr != rbi->dma_addr ||
1555 rxd->len != rbi->len);
1556
1557 if (unlikely(rcd->eop && rcd->err)) {
1558 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1559 goto rcd_done;
1560 }
1561
1562 if (rcd->sop && rcd->eop && vmxnet3_xdp_enabled(adapter)) {
1563 struct sk_buff *skb_xdp_pass;
1564 int act;
1565
1566 if (VMXNET3_RX_DATA_RING(adapter, rcd->rqID)) {
1567 ctx->skb = NULL;
1568 goto skip_xdp; /* Handle it later. */
1569 }
1570
1571 if (rbi->buf_type != VMXNET3_RX_BUF_XDP)
1572 goto rcd_done;
1573
1574 act = vmxnet3_process_xdp(adapter, rq, rcd, rbi, rxd,
1575 &skb_xdp_pass);
1576 if (act == XDP_PASS) {
1577 ctx->skb = skb_xdp_pass;
1578 goto sop_done;
1579 }
1580 ctx->skb = NULL;
1581 need_flush |= act == XDP_REDIRECT;
1582
1583 goto rcd_done;
1584 }
1585skip_xdp:
1586
1587 if (rcd->sop) { /* first buf of the pkt */
1588 bool rxDataRingUsed;
1589 u16 len;
1590
1591 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
1592 (rcd->rqID != rq->qid &&
1593 rcd->rqID != rq->dataRingQid));
1594
1595 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB &&
1596 rbi->buf_type != VMXNET3_RX_BUF_XDP);
1597 BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1598
1599 if (unlikely(rcd->len == 0)) {
1600 /* Pretend the rx buffer is skipped. */
1601 BUG_ON(!(rcd->sop && rcd->eop));
1602 netdev_dbg(adapter->netdev,
1603 "rxRing[%u][%u] 0 length\n",
1604 ring_idx, idx);
1605 goto rcd_done;
1606 }
1607
1608 skip_page_frags = false;
1609 ctx->skb = rbi->skb;
1610
1611 rxDataRingUsed =
1612 VMXNET3_RX_DATA_RING(adapter, rcd->rqID);
1613 len = rxDataRingUsed ? rcd->len : rbi->len;
1614
1615 if (rxDataRingUsed && vmxnet3_xdp_enabled(adapter)) {
1616 struct sk_buff *skb_xdp_pass;
1617 size_t sz;
1618 int act;
1619
1620 sz = rcd->rxdIdx * rq->data_ring.desc_size;
1621 act = vmxnet3_process_xdp_small(adapter, rq,
1622 &rq->data_ring.base[sz],
1623 rcd->len,
1624 &skb_xdp_pass);
1625 if (act == XDP_PASS) {
1626 ctx->skb = skb_xdp_pass;
1627 goto sop_done;
1628 }
1629 need_flush |= act == XDP_REDIRECT;
1630
1631 goto rcd_done;
1632 }
1633 new_skb = netdev_alloc_skb_ip_align(adapter->netdev,
1634 len);
1635 if (new_skb == NULL) {
1636 /* Skb allocation failed, do not handover this
1637 * skb to stack. Reuse it. Drop the existing pkt
1638 */
1639 rq->stats.rx_buf_alloc_failure++;
1640 ctx->skb = NULL;
1641 rq->stats.drop_total++;
1642 skip_page_frags = true;
1643 goto rcd_done;
1644 }
1645
1646 if (rxDataRingUsed && adapter->rxdataring_enabled) {
1647 size_t sz;
1648
1649 BUG_ON(rcd->len > rq->data_ring.desc_size);
1650
1651 ctx->skb = new_skb;
1652 sz = rcd->rxdIdx * rq->data_ring.desc_size;
1653 memcpy(new_skb->data,
1654 &rq->data_ring.base[sz], rcd->len);
1655 } else {
1656 ctx->skb = rbi->skb;
1657
1658 new_dma_addr =
1659 dma_map_single(&adapter->pdev->dev,
1660 new_skb->data, rbi->len,
1661 DMA_FROM_DEVICE);
1662 if (dma_mapping_error(&adapter->pdev->dev,
1663 new_dma_addr)) {
1664 dev_kfree_skb(new_skb);
1665 /* Skb allocation failed, do not
1666 * handover this skb to stack. Reuse
1667 * it. Drop the existing pkt.
1668 */
1669 rq->stats.rx_buf_alloc_failure++;
1670 ctx->skb = NULL;
1671 rq->stats.drop_total++;
1672 skip_page_frags = true;
1673 goto rcd_done;
1674 }
1675
1676 dma_unmap_single(&adapter->pdev->dev,
1677 rbi->dma_addr,
1678 rbi->len,
1679 DMA_FROM_DEVICE);
1680
1681 /* Immediate refill */
1682 rbi->skb = new_skb;
1683 rbi->dma_addr = new_dma_addr;
1684 rxd->addr = cpu_to_le64(rbi->dma_addr);
1685 rxd->len = rbi->len;
1686 }
1687
1688 skb_record_rx_queue(ctx->skb, rq->qid);
1689 skb_put(ctx->skb, rcd->len);
1690
1691 if (VMXNET3_VERSION_GE_2(adapter) &&
1692 rcd->type == VMXNET3_CDTYPE_RXCOMP_LRO) {
1693 struct Vmxnet3_RxCompDescExt *rcdlro;
1694 union Vmxnet3_GenericDesc *gdesc;
1695
1696 rcdlro = (struct Vmxnet3_RxCompDescExt *)rcd;
1697 gdesc = (union Vmxnet3_GenericDesc *)rcd;
1698
1699 segCnt = rcdlro->segCnt;
1700 WARN_ON_ONCE(segCnt == 0);
1701 mss = rcdlro->mss;
1702 if (unlikely(segCnt <= 1))
1703 segCnt = 0;
1704 encap_lro = (le32_to_cpu(gdesc->dword[0]) &
1705 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT));
1706 } else {
1707 segCnt = 0;
1708 }
1709 } else {
1710 BUG_ON(ctx->skb == NULL && !skip_page_frags);
1711
1712 /* non SOP buffer must be type 1 in most cases */
1713 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
1714 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
1715
1716 /* If an sop buffer was dropped, skip all
1717 * following non-sop fragments. They will be reused.
1718 */
1719 if (skip_page_frags)
1720 goto rcd_done;
1721
1722 if (rcd->len) {
1723 new_page = alloc_page(GFP_ATOMIC);
1724 /* Replacement page frag could not be allocated.
1725 * Reuse this page. Drop the pkt and free the
1726 * skb which contained this page as a frag. Skip
1727 * processing all the following non-sop frags.
1728 */
1729 if (unlikely(!new_page)) {
1730 rq->stats.rx_buf_alloc_failure++;
1731 dev_kfree_skb(ctx->skb);
1732 ctx->skb = NULL;
1733 skip_page_frags = true;
1734 goto rcd_done;
1735 }
1736 new_dma_addr = dma_map_page(&adapter->pdev->dev,
1737 new_page,
1738 0, PAGE_SIZE,
1739 DMA_FROM_DEVICE);
1740 if (dma_mapping_error(&adapter->pdev->dev,
1741 new_dma_addr)) {
1742 put_page(new_page);
1743 rq->stats.rx_buf_alloc_failure++;
1744 dev_kfree_skb(ctx->skb);
1745 ctx->skb = NULL;
1746 skip_page_frags = true;
1747 goto rcd_done;
1748 }
1749
1750 dma_unmap_page(&adapter->pdev->dev,
1751 rbi->dma_addr, rbi->len,
1752 DMA_FROM_DEVICE);
1753
1754 vmxnet3_append_frag(ctx->skb, rcd, rbi);
1755
1756 /* Immediate refill */
1757 rbi->page = new_page;
1758 rbi->dma_addr = new_dma_addr;
1759 rxd->addr = cpu_to_le64(rbi->dma_addr);
1760 rxd->len = rbi->len;
1761 }
1762 }
1763
1764
1765sop_done:
1766 skb = ctx->skb;
1767 if (rcd->eop) {
1768 u32 mtu = adapter->netdev->mtu;
1769 skb->len += skb->data_len;
1770
1771#ifdef VMXNET3_RSS
1772 if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE &&
1773 (adapter->netdev->features & NETIF_F_RXHASH)) {
1774 enum pkt_hash_types hash_type;
1775
1776 switch (rcd->rssType) {
1777 case VMXNET3_RCD_RSS_TYPE_IPV4:
1778 case VMXNET3_RCD_RSS_TYPE_IPV6:
1779 hash_type = PKT_HASH_TYPE_L3;
1780 break;
1781 case VMXNET3_RCD_RSS_TYPE_TCPIPV4:
1782 case VMXNET3_RCD_RSS_TYPE_TCPIPV6:
1783 case VMXNET3_RCD_RSS_TYPE_UDPIPV4:
1784 case VMXNET3_RCD_RSS_TYPE_UDPIPV6:
1785 hash_type = PKT_HASH_TYPE_L4;
1786 break;
1787 default:
1788 hash_type = PKT_HASH_TYPE_L3;
1789 break;
1790 }
1791 skb_set_hash(skb,
1792 le32_to_cpu(rcd->rssHash),
1793 hash_type);
1794 }
1795#endif
1796 vmxnet3_rx_csum(adapter, skb,
1797 (union Vmxnet3_GenericDesc *)rcd);
1798 skb->protocol = eth_type_trans(skb, adapter->netdev);
1799 if ((!rcd->tcp && !encap_lro) ||
1800 !(adapter->netdev->features & NETIF_F_LRO))
1801 goto not_lro;
1802
1803 if (segCnt != 0 && mss != 0) {
1804 skb_shinfo(skb)->gso_type = rcd->v4 ?
1805 SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1806 skb_shinfo(skb)->gso_size = mss;
1807 skb_shinfo(skb)->gso_segs = segCnt;
1808 } else if ((segCnt != 0 || skb->len > mtu) && !encap_lro) {
1809 u32 hlen;
1810
1811 hlen = vmxnet3_get_hdr_len(adapter, skb,
1812 (union Vmxnet3_GenericDesc *)rcd);
1813 if (hlen == 0)
1814 goto not_lro;
1815
1816 skb_shinfo(skb)->gso_type =
1817 rcd->v4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1818 if (segCnt != 0) {
1819 skb_shinfo(skb)->gso_segs = segCnt;
1820 skb_shinfo(skb)->gso_size =
1821 DIV_ROUND_UP(skb->len -
1822 hlen, segCnt);
1823 } else {
1824 skb_shinfo(skb)->gso_size = mtu - hlen;
1825 }
1826 }
1827not_lro:
1828 if (unlikely(rcd->ts))
1829 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rcd->tci);
1830
1831 /* Use GRO callback if UPT is enabled */
1832 if ((adapter->netdev->features & NETIF_F_LRO) &&
1833 !rq->shared->updateRxProd)
1834 netif_receive_skb(skb);
1835 else
1836 napi_gro_receive(&rq->napi, skb);
1837
1838 ctx->skb = NULL;
1839 encap_lro = false;
1840 num_pkts++;
1841 }
1842
1843rcd_done:
1844 /* device may have skipped some rx descs */
1845 ring = rq->rx_ring + ring_idx;
1846 rbi->comp_state = VMXNET3_RXD_COMP_DONE;
1847
1848 comp_offset = vmxnet3_cmd_ring_desc_avail(ring);
1849 fill_offset = (idx > ring->next2fill ? 0 : ring->size) +
1850 idx - ring->next2fill - 1;
1851 if (!ring->isOutOfOrder || fill_offset >= comp_offset)
1852 ring->next2comp = idx;
1853 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
1854
1855 /* Ensure that the writes to rxd->gen bits will be observed
1856 * after all other writes to rxd objects.
1857 */
1858 dma_wmb();
1859
1860 while (num_to_alloc) {
1861 rbi = rq->buf_info[ring_idx] + ring->next2fill;
1862 if (!(adapter->dev_caps[0] & (1UL << VMXNET3_CAP_OOORX_COMP)))
1863 goto refill_buf;
1864 if (ring_idx == 0) {
1865 /* ring0 Type1 buffers can get skipped; re-fill them */
1866 if (rbi->buf_type != VMXNET3_RX_BUF_SKB)
1867 goto refill_buf;
1868 }
1869 if (rbi->comp_state == VMXNET3_RXD_COMP_DONE) {
1870refill_buf:
1871 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
1872 &rxCmdDesc);
1873 WARN_ON(!rxd->addr);
1874
1875 /* Recv desc is ready to be used by the device */
1876 rxd->gen = ring->gen;
1877 vmxnet3_cmd_ring_adv_next2fill(ring);
1878 rbi->comp_state = VMXNET3_RXD_COMP_PENDING;
1879 num_to_alloc--;
1880 } else {
1881 /* rx completion hasn't occurred */
1882 ring->isOutOfOrder = 1;
1883 break;
1884 }
1885 }
1886
1887 if (num_to_alloc == 0) {
1888 ring->isOutOfOrder = 0;
1889 }
1890
1891 /* if needed, update the register */
1892 if (unlikely(rq->shared->updateRxProd) && (ring->next2fill & 0xf) == 0) {
1893 VMXNET3_WRITE_BAR0_REG(adapter,
1894 rxprod_reg[ring_idx] + rq->qid * 8,
1895 ring->next2fill);
1896 }
1897
1898 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
1899 vmxnet3_getRxComp(rcd,
1900 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
1901 }
1902 if (need_flush)
1903 xdp_do_flush();
1904
1905 return num_pkts;
1906}
1907
1908
1909static void
1910vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1911 struct vmxnet3_adapter *adapter)
1912{
1913 u32 i, ring_idx;
1914 struct Vmxnet3_RxDesc *rxd;
1915
1916 /* ring has already been cleaned up */
1917 if (!rq->rx_ring[0].base)
1918 return;
1919
1920 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1921 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
1922 struct vmxnet3_rx_buf_info *rbi;
1923#ifdef __BIG_ENDIAN_BITFIELD
1924 struct Vmxnet3_RxDesc rxDesc;
1925#endif
1926
1927 rbi = &rq->buf_info[ring_idx][i];
1928 vmxnet3_getRxDesc(rxd,
1929 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
1930
1931 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1932 rbi->page && rbi->buf_type == VMXNET3_RX_BUF_XDP) {
1933 page_pool_recycle_direct(rq->page_pool,
1934 rbi->page);
1935 rbi->page = NULL;
1936 } else if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1937 rbi->skb) {
1938 dma_unmap_single(&adapter->pdev->dev, rxd->addr,
1939 rxd->len, DMA_FROM_DEVICE);
1940 dev_kfree_skb(rbi->skb);
1941 rbi->skb = NULL;
1942 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1943 rbi->page) {
1944 dma_unmap_page(&adapter->pdev->dev, rxd->addr,
1945 rxd->len, DMA_FROM_DEVICE);
1946 put_page(rbi->page);
1947 rbi->page = NULL;
1948 }
1949 }
1950
1951 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1952 rq->rx_ring[ring_idx].next2fill =
1953 rq->rx_ring[ring_idx].next2comp = 0;
1954 }
1955
1956 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1957 rq->comp_ring.next2proc = 0;
1958}
1959
1960
1961static void
1962vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1963{
1964 int i;
1965
1966 for (i = 0; i < adapter->num_rx_queues; i++)
1967 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1968 rcu_assign_pointer(adapter->xdp_bpf_prog, NULL);
1969}
1970
1971
1972static void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1973 struct vmxnet3_adapter *adapter)
1974{
1975 int i;
1976 int j;
1977
1978 /* all rx buffers must have already been freed */
1979 for (i = 0; i < 2; i++) {
1980 if (rq->buf_info[i]) {
1981 for (j = 0; j < rq->rx_ring[i].size; j++)
1982 BUG_ON(rq->buf_info[i][j].page != NULL);
1983 }
1984 }
1985
1986
1987 for (i = 0; i < 2; i++) {
1988 if (rq->rx_ring[i].base) {
1989 dma_free_coherent(&adapter->pdev->dev,
1990 rq->rx_ring[i].size
1991 * sizeof(struct Vmxnet3_RxDesc),
1992 rq->rx_ring[i].base,
1993 rq->rx_ring[i].basePA);
1994 rq->rx_ring[i].base = NULL;
1995 }
1996 }
1997
1998 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
1999 xdp_rxq_info_unreg(&rq->xdp_rxq);
2000 page_pool_destroy(rq->page_pool);
2001 rq->page_pool = NULL;
2002
2003 if (rq->data_ring.base) {
2004 dma_free_coherent(&adapter->pdev->dev,
2005 rq->rx_ring[0].size * rq->data_ring.desc_size,
2006 rq->data_ring.base, rq->data_ring.basePA);
2007 rq->data_ring.base = NULL;
2008 }
2009
2010 if (rq->comp_ring.base) {
2011 dma_free_coherent(&adapter->pdev->dev, rq->comp_ring.size
2012 * sizeof(struct Vmxnet3_RxCompDesc),
2013 rq->comp_ring.base, rq->comp_ring.basePA);
2014 rq->comp_ring.base = NULL;
2015 }
2016
2017 kfree(rq->buf_info[0]);
2018 rq->buf_info[0] = NULL;
2019 rq->buf_info[1] = NULL;
2020}
2021
2022static void
2023vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter *adapter)
2024{
2025 int i;
2026
2027 for (i = 0; i < adapter->num_rx_queues; i++) {
2028 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2029
2030 if (rq->data_ring.base) {
2031 dma_free_coherent(&adapter->pdev->dev,
2032 (rq->rx_ring[0].size *
2033 rq->data_ring.desc_size),
2034 rq->data_ring.base,
2035 rq->data_ring.basePA);
2036 rq->data_ring.base = NULL;
2037 rq->data_ring.desc_size = 0;
2038 }
2039 }
2040}
2041
2042static int
2043vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
2044 struct vmxnet3_adapter *adapter)
2045{
2046 int i, err;
2047
2048 /* initialize buf_info */
2049 for (i = 0; i < rq->rx_ring[0].size; i++) {
2050
2051 /* 1st buf for a pkt is skbuff or xdp page */
2052 if (i % adapter->rx_buf_per_pkt == 0) {
2053 rq->buf_info[0][i].buf_type = vmxnet3_xdp_enabled(adapter) ?
2054 VMXNET3_RX_BUF_XDP :
2055 VMXNET3_RX_BUF_SKB;
2056 rq->buf_info[0][i].len = adapter->skb_buf_size;
2057 } else { /* subsequent bufs for a pkt is frag */
2058 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
2059 rq->buf_info[0][i].len = PAGE_SIZE;
2060 }
2061 }
2062 for (i = 0; i < rq->rx_ring[1].size; i++) {
2063 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
2064 rq->buf_info[1][i].len = PAGE_SIZE;
2065 }
2066
2067 /* reset internal state and allocate buffers for both rings */
2068 for (i = 0; i < 2; i++) {
2069 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
2070
2071 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
2072 sizeof(struct Vmxnet3_RxDesc));
2073 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
2074 rq->rx_ring[i].isOutOfOrder = 0;
2075 }
2076
2077 err = vmxnet3_create_pp(adapter, rq,
2078 rq->rx_ring[0].size + rq->rx_ring[1].size);
2079 if (err)
2080 return err;
2081
2082 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
2083 adapter) == 0) {
2084 xdp_rxq_info_unreg(&rq->xdp_rxq);
2085 page_pool_destroy(rq->page_pool);
2086 rq->page_pool = NULL;
2087
2088 /* at least has 1 rx buffer for the 1st ring */
2089 return -ENOMEM;
2090 }
2091 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
2092
2093 /* reset the comp ring */
2094 rq->comp_ring.next2proc = 0;
2095 memset(rq->comp_ring.base, 0, rq->comp_ring.size *
2096 sizeof(struct Vmxnet3_RxCompDesc));
2097 rq->comp_ring.gen = VMXNET3_INIT_GEN;
2098
2099 /* reset rxctx */
2100 rq->rx_ctx.skb = NULL;
2101
2102 /* stats are not reset */
2103 return 0;
2104}
2105
2106
2107static int
2108vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
2109{
2110 int i, err = 0;
2111
2112 for (i = 0; i < adapter->num_rx_queues; i++) {
2113 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
2114 if (unlikely(err)) {
2115 dev_err(&adapter->netdev->dev, "%s: failed to "
2116 "initialize rx queue%i\n",
2117 adapter->netdev->name, i);
2118 break;
2119 }
2120 }
2121 return err;
2122
2123}
2124
2125
2126static int
2127vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
2128{
2129 int i;
2130 size_t sz;
2131 struct vmxnet3_rx_buf_info *bi;
2132
2133 for (i = 0; i < 2; i++) {
2134
2135 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
2136 rq->rx_ring[i].base = dma_alloc_coherent(
2137 &adapter->pdev->dev, sz,
2138 &rq->rx_ring[i].basePA,
2139 GFP_KERNEL);
2140 if (!rq->rx_ring[i].base) {
2141 netdev_err(adapter->netdev,
2142 "failed to allocate rx ring %d\n", i);
2143 goto err;
2144 }
2145 }
2146
2147 if ((adapter->rxdataring_enabled) && (rq->data_ring.desc_size != 0)) {
2148 sz = rq->rx_ring[0].size * rq->data_ring.desc_size;
2149 rq->data_ring.base =
2150 dma_alloc_coherent(&adapter->pdev->dev, sz,
2151 &rq->data_ring.basePA,
2152 GFP_KERNEL);
2153 if (!rq->data_ring.base) {
2154 netdev_err(adapter->netdev,
2155 "rx data ring will be disabled\n");
2156 adapter->rxdataring_enabled = false;
2157 }
2158 } else {
2159 rq->data_ring.base = NULL;
2160 rq->data_ring.desc_size = 0;
2161 }
2162
2163 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
2164 rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz,
2165 &rq->comp_ring.basePA,
2166 GFP_KERNEL);
2167 if (!rq->comp_ring.base) {
2168 netdev_err(adapter->netdev, "failed to allocate rx comp ring\n");
2169 goto err;
2170 }
2171
2172 bi = kcalloc_node(rq->rx_ring[0].size + rq->rx_ring[1].size,
2173 sizeof(rq->buf_info[0][0]), GFP_KERNEL,
2174 dev_to_node(&adapter->pdev->dev));
2175 if (!bi)
2176 goto err;
2177
2178 rq->buf_info[0] = bi;
2179 rq->buf_info[1] = bi + rq->rx_ring[0].size;
2180
2181 return 0;
2182
2183err:
2184 vmxnet3_rq_destroy(rq, adapter);
2185 return -ENOMEM;
2186}
2187
2188
2189int
2190vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
2191{
2192 int i, err = 0;
2193
2194 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
2195
2196 for (i = 0; i < adapter->num_rx_queues; i++) {
2197 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
2198 if (unlikely(err)) {
2199 dev_err(&adapter->netdev->dev,
2200 "%s: failed to create rx queue%i\n",
2201 adapter->netdev->name, i);
2202 goto err_out;
2203 }
2204 }
2205
2206 if (!adapter->rxdataring_enabled)
2207 vmxnet3_rq_destroy_all_rxdataring(adapter);
2208
2209 return err;
2210err_out:
2211 vmxnet3_rq_destroy_all(adapter);
2212 return err;
2213
2214}
2215
2216/* Multiple queue aware polling function for tx and rx */
2217
2218static int
2219vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
2220{
2221 int rcd_done = 0, i;
2222 if (unlikely(adapter->shared->ecr))
2223 vmxnet3_process_events(adapter);
2224 for (i = 0; i < adapter->num_tx_queues; i++)
2225 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
2226
2227 for (i = 0; i < adapter->num_rx_queues; i++)
2228 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
2229 adapter, budget);
2230 return rcd_done;
2231}
2232
2233
2234static int
2235vmxnet3_poll(struct napi_struct *napi, int budget)
2236{
2237 struct vmxnet3_rx_queue *rx_queue = container_of(napi,
2238 struct vmxnet3_rx_queue, napi);
2239 int rxd_done;
2240
2241 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
2242
2243 if (rxd_done < budget) {
2244 napi_complete_done(napi, rxd_done);
2245 vmxnet3_enable_all_intrs(rx_queue->adapter);
2246 }
2247 return rxd_done;
2248}
2249
2250/*
2251 * NAPI polling function for MSI-X mode with multiple Rx queues
2252 * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
2253 */
2254
2255static int
2256vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
2257{
2258 struct vmxnet3_rx_queue *rq = container_of(napi,
2259 struct vmxnet3_rx_queue, napi);
2260 struct vmxnet3_adapter *adapter = rq->adapter;
2261 int rxd_done;
2262
2263 /* When sharing interrupt with corresponding tx queue, process
2264 * tx completions in that queue as well
2265 */
2266 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
2267 struct vmxnet3_tx_queue *tq =
2268 &adapter->tx_queue[rq - adapter->rx_queue];
2269 vmxnet3_tq_tx_complete(tq, adapter);
2270 }
2271
2272 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
2273
2274 if (rxd_done < budget) {
2275 napi_complete_done(napi, rxd_done);
2276 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
2277 }
2278 return rxd_done;
2279}
2280
2281
2282#ifdef CONFIG_PCI_MSI
2283
2284/*
2285 * Handle completion interrupts on tx queues
2286 * Returns whether or not the intr is handled
2287 */
2288
2289static irqreturn_t
2290vmxnet3_msix_tx(int irq, void *data)
2291{
2292 struct vmxnet3_tx_queue *tq = data;
2293 struct vmxnet3_adapter *adapter = tq->adapter;
2294
2295 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2296 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
2297
2298 /* Handle the case where only one irq is allocate for all tx queues */
2299 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
2300 int i;
2301 for (i = 0; i < adapter->num_tx_queues; i++) {
2302 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
2303 vmxnet3_tq_tx_complete(txq, adapter);
2304 }
2305 } else {
2306 vmxnet3_tq_tx_complete(tq, adapter);
2307 }
2308 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
2309
2310 return IRQ_HANDLED;
2311}
2312
2313
2314/*
2315 * Handle completion interrupts on rx queues. Returns whether or not the
2316 * intr is handled
2317 */
2318
2319static irqreturn_t
2320vmxnet3_msix_rx(int irq, void *data)
2321{
2322 struct vmxnet3_rx_queue *rq = data;
2323 struct vmxnet3_adapter *adapter = rq->adapter;
2324
2325 /* disable intr if needed */
2326 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2327 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
2328 napi_schedule(&rq->napi);
2329
2330 return IRQ_HANDLED;
2331}
2332
2333/*
2334 *----------------------------------------------------------------------------
2335 *
2336 * vmxnet3_msix_event --
2337 *
2338 * vmxnet3 msix event intr handler
2339 *
2340 * Result:
2341 * whether or not the intr is handled
2342 *
2343 *----------------------------------------------------------------------------
2344 */
2345
2346static irqreturn_t
2347vmxnet3_msix_event(int irq, void *data)
2348{
2349 struct net_device *dev = data;
2350 struct vmxnet3_adapter *adapter = netdev_priv(dev);
2351
2352 /* disable intr if needed */
2353 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2354 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
2355
2356 if (adapter->shared->ecr)
2357 vmxnet3_process_events(adapter);
2358
2359 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
2360
2361 return IRQ_HANDLED;
2362}
2363
2364#endif /* CONFIG_PCI_MSI */
2365
2366
2367/* Interrupt handler for vmxnet3 */
2368static irqreturn_t
2369vmxnet3_intr(int irq, void *dev_id)
2370{
2371 struct net_device *dev = dev_id;
2372 struct vmxnet3_adapter *adapter = netdev_priv(dev);
2373
2374 if (adapter->intr.type == VMXNET3_IT_INTX) {
2375 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
2376 if (unlikely(icr == 0))
2377 /* not ours */
2378 return IRQ_NONE;
2379 }
2380
2381
2382 /* disable intr if needed */
2383 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2384 vmxnet3_disable_all_intrs(adapter);
2385
2386 napi_schedule(&adapter->rx_queue[0].napi);
2387
2388 return IRQ_HANDLED;
2389}
2390
2391#ifdef CONFIG_NET_POLL_CONTROLLER
2392
2393/* netpoll callback. */
2394static void
2395vmxnet3_netpoll(struct net_device *netdev)
2396{
2397 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2398
2399 switch (adapter->intr.type) {
2400#ifdef CONFIG_PCI_MSI
2401 case VMXNET3_IT_MSIX: {
2402 int i;
2403 for (i = 0; i < adapter->num_rx_queues; i++)
2404 vmxnet3_msix_rx(0, &adapter->rx_queue[i]);
2405 break;
2406 }
2407#endif
2408 case VMXNET3_IT_MSI:
2409 default:
2410 vmxnet3_intr(0, adapter->netdev);
2411 break;
2412 }
2413
2414}
2415#endif /* CONFIG_NET_POLL_CONTROLLER */
2416
2417static int
2418vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
2419{
2420 struct vmxnet3_intr *intr = &adapter->intr;
2421 int err = 0, i;
2422 int vector = 0;
2423
2424#ifdef CONFIG_PCI_MSI
2425 if (adapter->intr.type == VMXNET3_IT_MSIX) {
2426 for (i = 0; i < adapter->num_tx_queues; i++) {
2427 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2428 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
2429 adapter->netdev->name, vector);
2430 err = request_irq(
2431 intr->msix_entries[vector].vector,
2432 vmxnet3_msix_tx, 0,
2433 adapter->tx_queue[i].name,
2434 &adapter->tx_queue[i]);
2435 } else {
2436 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
2437 adapter->netdev->name, vector);
2438 }
2439 if (err) {
2440 dev_err(&adapter->netdev->dev,
2441 "Failed to request irq for MSIX, %s, "
2442 "error %d\n",
2443 adapter->tx_queue[i].name, err);
2444 return err;
2445 }
2446
2447 /* Handle the case where only 1 MSIx was allocated for
2448 * all tx queues */
2449 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
2450 for (; i < adapter->num_tx_queues; i++)
2451 adapter->tx_queue[i].comp_ring.intr_idx
2452 = vector;
2453 vector++;
2454 break;
2455 } else {
2456 adapter->tx_queue[i].comp_ring.intr_idx
2457 = vector++;
2458 }
2459 }
2460 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
2461 vector = 0;
2462
2463 for (i = 0; i < adapter->num_rx_queues; i++) {
2464 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
2465 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
2466 adapter->netdev->name, vector);
2467 else
2468 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
2469 adapter->netdev->name, vector);
2470 err = request_irq(intr->msix_entries[vector].vector,
2471 vmxnet3_msix_rx, 0,
2472 adapter->rx_queue[i].name,
2473 &(adapter->rx_queue[i]));
2474 if (err) {
2475 netdev_err(adapter->netdev,
2476 "Failed to request irq for MSIX, "
2477 "%s, error %d\n",
2478 adapter->rx_queue[i].name, err);
2479 return err;
2480 }
2481
2482 adapter->rx_queue[i].comp_ring.intr_idx = vector++;
2483 }
2484
2485 sprintf(intr->event_msi_vector_name, "%s-event-%d",
2486 adapter->netdev->name, vector);
2487 err = request_irq(intr->msix_entries[vector].vector,
2488 vmxnet3_msix_event, 0,
2489 intr->event_msi_vector_name, adapter->netdev);
2490 intr->event_intr_idx = vector;
2491
2492 } else if (intr->type == VMXNET3_IT_MSI) {
2493 adapter->num_rx_queues = 1;
2494 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
2495 adapter->netdev->name, adapter->netdev);
2496 } else {
2497#endif
2498 adapter->num_rx_queues = 1;
2499 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
2500 IRQF_SHARED, adapter->netdev->name,
2501 adapter->netdev);
2502#ifdef CONFIG_PCI_MSI
2503 }
2504#endif
2505 intr->num_intrs = vector + 1;
2506 if (err) {
2507 netdev_err(adapter->netdev,
2508 "Failed to request irq (intr type:%d), error %d\n",
2509 intr->type, err);
2510 } else {
2511 /* Number of rx queues will not change after this */
2512 for (i = 0; i < adapter->num_rx_queues; i++) {
2513 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2514 rq->qid = i;
2515 rq->qid2 = i + adapter->num_rx_queues;
2516 rq->dataRingQid = i + 2 * adapter->num_rx_queues;
2517 }
2518
2519 /* init our intr settings */
2520 for (i = 0; i < intr->num_intrs; i++)
2521 intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
2522 if (adapter->intr.type != VMXNET3_IT_MSIX) {
2523 adapter->intr.event_intr_idx = 0;
2524 for (i = 0; i < adapter->num_tx_queues; i++)
2525 adapter->tx_queue[i].comp_ring.intr_idx = 0;
2526 adapter->rx_queue[0].comp_ring.intr_idx = 0;
2527 }
2528
2529 netdev_info(adapter->netdev,
2530 "intr type %u, mode %u, %u vectors allocated\n",
2531 intr->type, intr->mask_mode, intr->num_intrs);
2532 }
2533
2534 return err;
2535}
2536
2537
2538static void
2539vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
2540{
2541 struct vmxnet3_intr *intr = &adapter->intr;
2542 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
2543
2544 switch (intr->type) {
2545#ifdef CONFIG_PCI_MSI
2546 case VMXNET3_IT_MSIX:
2547 {
2548 int i, vector = 0;
2549
2550 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2551 for (i = 0; i < adapter->num_tx_queues; i++) {
2552 free_irq(intr->msix_entries[vector++].vector,
2553 &(adapter->tx_queue[i]));
2554 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
2555 break;
2556 }
2557 }
2558
2559 for (i = 0; i < adapter->num_rx_queues; i++) {
2560 free_irq(intr->msix_entries[vector++].vector,
2561 &(adapter->rx_queue[i]));
2562 }
2563
2564 free_irq(intr->msix_entries[vector].vector,
2565 adapter->netdev);
2566 BUG_ON(vector >= intr->num_intrs);
2567 break;
2568 }
2569#endif
2570 case VMXNET3_IT_MSI:
2571 free_irq(adapter->pdev->irq, adapter->netdev);
2572 break;
2573 case VMXNET3_IT_INTX:
2574 free_irq(adapter->pdev->irq, adapter->netdev);
2575 break;
2576 default:
2577 BUG();
2578 }
2579}
2580
2581
2582static void
2583vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
2584{
2585 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2586 u16 vid;
2587
2588 /* allow untagged pkts */
2589 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
2590
2591 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2592 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2593}
2594
2595
2596static int
2597vmxnet3_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
2598{
2599 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2600
2601 if (!(netdev->flags & IFF_PROMISC)) {
2602 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2603 unsigned long flags;
2604
2605 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2606 spin_lock_irqsave(&adapter->cmd_lock, flags);
2607 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2608 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2609 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2610 }
2611
2612 set_bit(vid, adapter->active_vlans);
2613
2614 return 0;
2615}
2616
2617
2618static int
2619vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
2620{
2621 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2622
2623 if (!(netdev->flags & IFF_PROMISC)) {
2624 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2625 unsigned long flags;
2626
2627 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
2628 spin_lock_irqsave(&adapter->cmd_lock, flags);
2629 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2630 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2631 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2632 }
2633
2634 clear_bit(vid, adapter->active_vlans);
2635
2636 return 0;
2637}
2638
2639
2640static u8 *
2641vmxnet3_copy_mc(struct net_device *netdev)
2642{
2643 u8 *buf = NULL;
2644 u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
2645
2646 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
2647 if (sz <= 0xffff) {
2648 /* We may be called with BH disabled */
2649 buf = kmalloc(sz, GFP_ATOMIC);
2650 if (buf) {
2651 struct netdev_hw_addr *ha;
2652 int i = 0;
2653
2654 netdev_for_each_mc_addr(ha, netdev)
2655 memcpy(buf + i++ * ETH_ALEN, ha->addr,
2656 ETH_ALEN);
2657 }
2658 }
2659 return buf;
2660}
2661
2662
2663static void
2664vmxnet3_set_mc(struct net_device *netdev)
2665{
2666 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2667 unsigned long flags;
2668 struct Vmxnet3_RxFilterConf *rxConf =
2669 &adapter->shared->devRead.rxFilterConf;
2670 u8 *new_table = NULL;
2671 dma_addr_t new_table_pa = 0;
2672 bool new_table_pa_valid = false;
2673 u32 new_mode = VMXNET3_RXM_UCAST;
2674
2675 if (netdev->flags & IFF_PROMISC) {
2676 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2677 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
2678
2679 new_mode |= VMXNET3_RXM_PROMISC;
2680 } else {
2681 vmxnet3_restore_vlan(adapter);
2682 }
2683
2684 if (netdev->flags & IFF_BROADCAST)
2685 new_mode |= VMXNET3_RXM_BCAST;
2686
2687 if (netdev->flags & IFF_ALLMULTI)
2688 new_mode |= VMXNET3_RXM_ALL_MULTI;
2689 else
2690 if (!netdev_mc_empty(netdev)) {
2691 new_table = vmxnet3_copy_mc(netdev);
2692 if (new_table) {
2693 size_t sz = netdev_mc_count(netdev) * ETH_ALEN;
2694
2695 rxConf->mfTableLen = cpu_to_le16(sz);
2696 new_table_pa = dma_map_single(
2697 &adapter->pdev->dev,
2698 new_table,
2699 sz,
2700 DMA_TO_DEVICE);
2701 if (!dma_mapping_error(&adapter->pdev->dev,
2702 new_table_pa)) {
2703 new_mode |= VMXNET3_RXM_MCAST;
2704 new_table_pa_valid = true;
2705 rxConf->mfTablePA = cpu_to_le64(
2706 new_table_pa);
2707 }
2708 }
2709 if (!new_table_pa_valid) {
2710 netdev_info(netdev,
2711 "failed to copy mcast list, setting ALL_MULTI\n");
2712 new_mode |= VMXNET3_RXM_ALL_MULTI;
2713 }
2714 }
2715
2716 if (!(new_mode & VMXNET3_RXM_MCAST)) {
2717 rxConf->mfTableLen = 0;
2718 rxConf->mfTablePA = 0;
2719 }
2720
2721 spin_lock_irqsave(&adapter->cmd_lock, flags);
2722 if (new_mode != rxConf->rxMode) {
2723 rxConf->rxMode = cpu_to_le32(new_mode);
2724 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2725 VMXNET3_CMD_UPDATE_RX_MODE);
2726 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2727 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2728 }
2729
2730 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2731 VMXNET3_CMD_UPDATE_MAC_FILTERS);
2732 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2733
2734 if (new_table_pa_valid)
2735 dma_unmap_single(&adapter->pdev->dev, new_table_pa,
2736 rxConf->mfTableLen, DMA_TO_DEVICE);
2737 kfree(new_table);
2738}
2739
2740void
2741vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2742{
2743 int i;
2744
2745 for (i = 0; i < adapter->num_rx_queues; i++)
2746 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2747}
2748
2749
2750/*
2751 * Set up driver_shared based on settings in adapter.
2752 */
2753
2754static void
2755vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2756{
2757 struct Vmxnet3_DriverShared *shared = adapter->shared;
2758 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2759 struct Vmxnet3_DSDevReadExt *devReadExt = &shared->devReadExt;
2760 struct Vmxnet3_TxQueueConf *tqc;
2761 struct Vmxnet3_RxQueueConf *rqc;
2762 int i;
2763
2764 memset(shared, 0, sizeof(*shared));
2765
2766 /* driver settings */
2767 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2768 devRead->misc.driverInfo.version = cpu_to_le32(
2769 VMXNET3_DRIVER_VERSION_NUM);
2770 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2771 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2772 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
2773 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2774 *((u32 *)&devRead->misc.driverInfo.gos));
2775 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2776 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
2777
2778 devRead->misc.ddPA = cpu_to_le64(adapter->adapter_pa);
2779 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
2780
2781 /* set up feature flags */
2782 if (adapter->netdev->features & NETIF_F_RXCSUM)
2783 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
2784
2785 if (adapter->netdev->features & NETIF_F_LRO) {
2786 devRead->misc.uptFeatures |= UPT1_F_LRO;
2787 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
2788 }
2789 if (adapter->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2790 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
2791
2792 if (adapter->netdev->features & (NETIF_F_GSO_UDP_TUNNEL |
2793 NETIF_F_GSO_UDP_TUNNEL_CSUM))
2794 devRead->misc.uptFeatures |= UPT1_F_RXINNEROFLD;
2795
2796 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2797 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2798 devRead->misc.queueDescLen = cpu_to_le32(
2799 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2800 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
2801
2802 /* tx queue settings */
2803 devRead->misc.numTxQueues = adapter->num_tx_queues;
2804 for (i = 0; i < adapter->num_tx_queues; i++) {
2805 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2806 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2807 tqc = &adapter->tqd_start[i].conf;
2808 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
2809 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2810 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
2811 tqc->ddPA = cpu_to_le64(~0ULL);
2812 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
2813 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
2814 tqc->txDataRingDescSize = cpu_to_le32(tq->txdata_desc_size);
2815 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
2816 tqc->ddLen = cpu_to_le32(0);
2817 tqc->intrIdx = tq->comp_ring.intr_idx;
2818 }
2819
2820 /* rx queue settings */
2821 devRead->misc.numRxQueues = adapter->num_rx_queues;
2822 for (i = 0; i < adapter->num_rx_queues; i++) {
2823 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2824 rqc = &adapter->rqd_start[i].conf;
2825 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2826 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2827 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
2828 rqc->ddPA = cpu_to_le64(~0ULL);
2829 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
2830 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
2831 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
2832 rqc->ddLen = cpu_to_le32(0);
2833 rqc->intrIdx = rq->comp_ring.intr_idx;
2834 if (VMXNET3_VERSION_GE_3(adapter)) {
2835 rqc->rxDataRingBasePA =
2836 cpu_to_le64(rq->data_ring.basePA);
2837 rqc->rxDataRingDescSize =
2838 cpu_to_le16(rq->data_ring.desc_size);
2839 }
2840 }
2841
2842#ifdef VMXNET3_RSS
2843 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2844
2845 if (adapter->rss) {
2846 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
2847
2848 devRead->misc.uptFeatures |= UPT1_F_RSS;
2849 devRead->misc.numRxQueues = adapter->num_rx_queues;
2850 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2851 UPT1_RSS_HASH_TYPE_IPV4 |
2852 UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2853 UPT1_RSS_HASH_TYPE_IPV6;
2854 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2855 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2856 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
2857 netdev_rss_key_fill(rssConf->hashKey, sizeof(rssConf->hashKey));
2858
2859 for (i = 0; i < rssConf->indTableSize; i++)
2860 rssConf->indTable[i] = ethtool_rxfh_indir_default(
2861 i, adapter->num_rx_queues);
2862
2863 devRead->rssConfDesc.confVer = 1;
2864 devRead->rssConfDesc.confLen = cpu_to_le32(sizeof(*rssConf));
2865 devRead->rssConfDesc.confPA =
2866 cpu_to_le64(adapter->rss_conf_pa);
2867 }
2868
2869#endif /* VMXNET3_RSS */
2870
2871 /* intr settings */
2872 if (!VMXNET3_VERSION_GE_6(adapter) ||
2873 !adapter->queuesExtEnabled) {
2874 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2875 VMXNET3_IMM_AUTO;
2876 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2877 for (i = 0; i < adapter->intr.num_intrs; i++)
2878 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2879
2880 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
2881 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
2882 } else {
2883 devReadExt->intrConfExt.autoMask = adapter->intr.mask_mode ==
2884 VMXNET3_IMM_AUTO;
2885 devReadExt->intrConfExt.numIntrs = adapter->intr.num_intrs;
2886 for (i = 0; i < adapter->intr.num_intrs; i++)
2887 devReadExt->intrConfExt.modLevels[i] = adapter->intr.mod_levels[i];
2888
2889 devReadExt->intrConfExt.eventIntrIdx = adapter->intr.event_intr_idx;
2890 devReadExt->intrConfExt.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
2891 }
2892
2893 /* rx filter settings */
2894 devRead->rxFilterConf.rxMode = 0;
2895 vmxnet3_restore_vlan(adapter);
2896 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2897
2898 /* the rest are already zeroed */
2899}
2900
2901static void
2902vmxnet3_init_bufsize(struct vmxnet3_adapter *adapter)
2903{
2904 struct Vmxnet3_DriverShared *shared = adapter->shared;
2905 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
2906 unsigned long flags;
2907
2908 if (!VMXNET3_VERSION_GE_7(adapter))
2909 return;
2910
2911 cmdInfo->ringBufSize = adapter->ringBufSize;
2912 spin_lock_irqsave(&adapter->cmd_lock, flags);
2913 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2914 VMXNET3_CMD_SET_RING_BUFFER_SIZE);
2915 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2916}
2917
2918static void
2919vmxnet3_init_coalesce(struct vmxnet3_adapter *adapter)
2920{
2921 struct Vmxnet3_DriverShared *shared = adapter->shared;
2922 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
2923 unsigned long flags;
2924
2925 if (!VMXNET3_VERSION_GE_3(adapter))
2926 return;
2927
2928 spin_lock_irqsave(&adapter->cmd_lock, flags);
2929 cmdInfo->varConf.confVer = 1;
2930 cmdInfo->varConf.confLen =
2931 cpu_to_le32(sizeof(*adapter->coal_conf));
2932 cmdInfo->varConf.confPA = cpu_to_le64(adapter->coal_conf_pa);
2933
2934 if (adapter->default_coal_mode) {
2935 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2936 VMXNET3_CMD_GET_COALESCE);
2937 } else {
2938 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2939 VMXNET3_CMD_SET_COALESCE);
2940 }
2941
2942 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2943}
2944
2945static void
2946vmxnet3_init_rssfields(struct vmxnet3_adapter *adapter)
2947{
2948 struct Vmxnet3_DriverShared *shared = adapter->shared;
2949 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
2950 unsigned long flags;
2951
2952 if (!VMXNET3_VERSION_GE_4(adapter))
2953 return;
2954
2955 spin_lock_irqsave(&adapter->cmd_lock, flags);
2956
2957 if (adapter->default_rss_fields) {
2958 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2959 VMXNET3_CMD_GET_RSS_FIELDS);
2960 adapter->rss_fields =
2961 VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2962 } else {
2963 if (VMXNET3_VERSION_GE_7(adapter)) {
2964 if ((adapter->rss_fields & VMXNET3_RSS_FIELDS_UDPIP4 ||
2965 adapter->rss_fields & VMXNET3_RSS_FIELDS_UDPIP6) &&
2966 vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
2967 VMXNET3_CAP_UDP_RSS)) {
2968 adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_UDP_RSS;
2969 } else {
2970 adapter->dev_caps[0] &= ~(1UL << VMXNET3_CAP_UDP_RSS);
2971 }
2972
2973 if ((adapter->rss_fields & VMXNET3_RSS_FIELDS_ESPIP4) &&
2974 vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
2975 VMXNET3_CAP_ESP_RSS_IPV4)) {
2976 adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_ESP_RSS_IPV4;
2977 } else {
2978 adapter->dev_caps[0] &= ~(1UL << VMXNET3_CAP_ESP_RSS_IPV4);
2979 }
2980
2981 if ((adapter->rss_fields & VMXNET3_RSS_FIELDS_ESPIP6) &&
2982 vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
2983 VMXNET3_CAP_ESP_RSS_IPV6)) {
2984 adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_ESP_RSS_IPV6;
2985 } else {
2986 adapter->dev_caps[0] &= ~(1UL << VMXNET3_CAP_ESP_RSS_IPV6);
2987 }
2988
2989 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DCR, adapter->dev_caps[0]);
2990 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_DCR0_REG);
2991 adapter->dev_caps[0] = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2992 }
2993 cmdInfo->setRssFields = adapter->rss_fields;
2994 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2995 VMXNET3_CMD_SET_RSS_FIELDS);
2996 /* Not all requested RSS may get applied, so get and
2997 * cache what was actually applied.
2998 */
2999 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3000 VMXNET3_CMD_GET_RSS_FIELDS);
3001 adapter->rss_fields =
3002 VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
3003 }
3004
3005 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3006}
3007
3008int
3009vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
3010{
3011 int err, i;
3012 u32 ret;
3013 unsigned long flags;
3014
3015 netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
3016 " ring sizes %u %u %u\n", adapter->netdev->name,
3017 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
3018 adapter->tx_queue[0].tx_ring.size,
3019 adapter->rx_queue[0].rx_ring[0].size,
3020 adapter->rx_queue[0].rx_ring[1].size);
3021
3022 vmxnet3_tq_init_all(adapter);
3023 err = vmxnet3_rq_init_all(adapter);
3024 if (err) {
3025 netdev_err(adapter->netdev,
3026 "Failed to init rx queue error %d\n", err);
3027 goto rq_err;
3028 }
3029
3030 err = vmxnet3_request_irqs(adapter);
3031 if (err) {
3032 netdev_err(adapter->netdev,
3033 "Failed to setup irq for error %d\n", err);
3034 goto irq_err;
3035 }
3036
3037 vmxnet3_setup_driver_shared(adapter);
3038
3039 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
3040 adapter->shared_pa));
3041 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
3042 adapter->shared_pa));
3043 spin_lock_irqsave(&adapter->cmd_lock, flags);
3044 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3045 VMXNET3_CMD_ACTIVATE_DEV);
3046 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
3047 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3048
3049 if (ret != 0) {
3050 netdev_err(adapter->netdev,
3051 "Failed to activate dev: error %u\n", ret);
3052 err = -EINVAL;
3053 goto activate_err;
3054 }
3055
3056 vmxnet3_init_bufsize(adapter);
3057 vmxnet3_init_coalesce(adapter);
3058 vmxnet3_init_rssfields(adapter);
3059
3060 for (i = 0; i < adapter->num_rx_queues; i++) {
3061 VMXNET3_WRITE_BAR0_REG(adapter,
3062 adapter->rx_prod_offset + i * VMXNET3_REG_ALIGN,
3063 adapter->rx_queue[i].rx_ring[0].next2fill);
3064 VMXNET3_WRITE_BAR0_REG(adapter, (adapter->rx_prod2_offset +
3065 (i * VMXNET3_REG_ALIGN)),
3066 adapter->rx_queue[i].rx_ring[1].next2fill);
3067 }
3068
3069 /* Apply the rx filter settins last. */
3070 vmxnet3_set_mc(adapter->netdev);
3071
3072 /*
3073 * Check link state when first activating device. It will start the
3074 * tx queue if the link is up.
3075 */
3076 vmxnet3_check_link(adapter, true);
3077 netif_tx_wake_all_queues(adapter->netdev);
3078 for (i = 0; i < adapter->num_rx_queues; i++)
3079 napi_enable(&adapter->rx_queue[i].napi);
3080 vmxnet3_enable_all_intrs(adapter);
3081 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
3082 return 0;
3083
3084activate_err:
3085 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
3086 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
3087 vmxnet3_free_irqs(adapter);
3088irq_err:
3089rq_err:
3090 /* free up buffers we allocated */
3091 vmxnet3_rq_cleanup_all(adapter);
3092 return err;
3093}
3094
3095
3096void
3097vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
3098{
3099 unsigned long flags;
3100 spin_lock_irqsave(&adapter->cmd_lock, flags);
3101 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
3102 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3103}
3104
3105
3106int
3107vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
3108{
3109 int i;
3110 unsigned long flags;
3111 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
3112 return 0;
3113
3114
3115 spin_lock_irqsave(&adapter->cmd_lock, flags);
3116 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3117 VMXNET3_CMD_QUIESCE_DEV);
3118 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3119 vmxnet3_disable_all_intrs(adapter);
3120
3121 for (i = 0; i < adapter->num_rx_queues; i++)
3122 napi_disable(&adapter->rx_queue[i].napi);
3123 netif_tx_disable(adapter->netdev);
3124 adapter->link_speed = 0;
3125 netif_carrier_off(adapter->netdev);
3126
3127 vmxnet3_tq_cleanup_all(adapter);
3128 vmxnet3_rq_cleanup_all(adapter);
3129 vmxnet3_free_irqs(adapter);
3130 return 0;
3131}
3132
3133
3134static void
3135vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, const u8 *mac)
3136{
3137 u32 tmp;
3138
3139 tmp = *(u32 *)mac;
3140 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
3141
3142 tmp = (mac[5] << 8) | mac[4];
3143 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
3144}
3145
3146
3147static int
3148vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
3149{
3150 struct sockaddr *addr = p;
3151 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3152
3153 dev_addr_set(netdev, addr->sa_data);
3154 vmxnet3_write_mac_addr(adapter, addr->sa_data);
3155
3156 return 0;
3157}
3158
3159
3160/* ==================== initialization and cleanup routines ============ */
3161
3162static int
3163vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter)
3164{
3165 int err;
3166 unsigned long mmio_start, mmio_len;
3167 struct pci_dev *pdev = adapter->pdev;
3168
3169 err = pci_enable_device(pdev);
3170 if (err) {
3171 dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err);
3172 return err;
3173 }
3174
3175 err = pci_request_selected_regions(pdev, (1 << 2) - 1,
3176 vmxnet3_driver_name);
3177 if (err) {
3178 dev_err(&pdev->dev,
3179 "Failed to request region for adapter: error %d\n", err);
3180 goto err_enable_device;
3181 }
3182
3183 pci_set_master(pdev);
3184
3185 mmio_start = pci_resource_start(pdev, 0);
3186 mmio_len = pci_resource_len(pdev, 0);
3187 adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
3188 if (!adapter->hw_addr0) {
3189 dev_err(&pdev->dev, "Failed to map bar0\n");
3190 err = -EIO;
3191 goto err_ioremap;
3192 }
3193
3194 mmio_start = pci_resource_start(pdev, 1);
3195 mmio_len = pci_resource_len(pdev, 1);
3196 adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
3197 if (!adapter->hw_addr1) {
3198 dev_err(&pdev->dev, "Failed to map bar1\n");
3199 err = -EIO;
3200 goto err_bar1;
3201 }
3202 return 0;
3203
3204err_bar1:
3205 iounmap(adapter->hw_addr0);
3206err_ioremap:
3207 pci_release_selected_regions(pdev, (1 << 2) - 1);
3208err_enable_device:
3209 pci_disable_device(pdev);
3210 return err;
3211}
3212
3213
3214static void
3215vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
3216{
3217 BUG_ON(!adapter->pdev);
3218
3219 iounmap(adapter->hw_addr0);
3220 iounmap(adapter->hw_addr1);
3221 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
3222 pci_disable_device(adapter->pdev);
3223}
3224
3225
3226void
3227vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
3228{
3229 size_t sz, i, ring0_size, ring1_size, comp_size;
3230 /* With version7 ring1 will have only T0 buffers */
3231 if (!VMXNET3_VERSION_GE_7(adapter)) {
3232 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
3233 VMXNET3_MAX_ETH_HDR_SIZE) {
3234 adapter->skb_buf_size = adapter->netdev->mtu +
3235 VMXNET3_MAX_ETH_HDR_SIZE;
3236 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
3237 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
3238
3239 adapter->rx_buf_per_pkt = 1;
3240 } else {
3241 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
3242 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
3243 VMXNET3_MAX_ETH_HDR_SIZE;
3244 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
3245 }
3246 } else {
3247 adapter->skb_buf_size = min((int)adapter->netdev->mtu + VMXNET3_MAX_ETH_HDR_SIZE,
3248 VMXNET3_MAX_SKB_BUF_SIZE);
3249 adapter->rx_buf_per_pkt = 1;
3250 adapter->ringBufSize.ring1BufSizeType0 = cpu_to_le16(adapter->skb_buf_size);
3251 adapter->ringBufSize.ring1BufSizeType1 = 0;
3252 adapter->ringBufSize.ring2BufSizeType1 = cpu_to_le16(PAGE_SIZE);
3253 }
3254
3255 /*
3256 * for simplicity, force the ring0 size to be a multiple of
3257 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
3258 */
3259 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
3260 ring0_size = adapter->rx_queue[0].rx_ring[0].size;
3261 ring0_size = (ring0_size + sz - 1) / sz * sz;
3262 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
3263 sz * sz);
3264 ring1_size = adapter->rx_queue[0].rx_ring[1].size;
3265 ring1_size = (ring1_size + sz - 1) / sz * sz;
3266 ring1_size = min_t(u32, ring1_size, VMXNET3_RX_RING2_MAX_SIZE /
3267 sz * sz);
3268 /* For v7 and later, keep ring size power of 2 for UPT */
3269 if (VMXNET3_VERSION_GE_7(adapter)) {
3270 ring0_size = rounddown_pow_of_two(ring0_size);
3271 ring1_size = rounddown_pow_of_two(ring1_size);
3272 }
3273 comp_size = ring0_size + ring1_size;
3274
3275 for (i = 0; i < adapter->num_rx_queues; i++) {
3276 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
3277
3278 rq->rx_ring[0].size = ring0_size;
3279 rq->rx_ring[1].size = ring1_size;
3280 rq->comp_ring.size = comp_size;
3281 }
3282}
3283
3284
3285int
3286vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
3287 u32 rx_ring_size, u32 rx_ring2_size,
3288 u16 txdata_desc_size, u16 rxdata_desc_size)
3289{
3290 int err = 0, i;
3291
3292 for (i = 0; i < adapter->num_tx_queues; i++) {
3293 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
3294 tq->tx_ring.size = tx_ring_size;
3295 tq->data_ring.size = tx_ring_size;
3296 tq->comp_ring.size = tx_ring_size;
3297 tq->txdata_desc_size = txdata_desc_size;
3298 tq->shared = &adapter->tqd_start[i].ctrl;
3299 tq->stopped = true;
3300 tq->adapter = adapter;
3301 tq->qid = i;
3302 err = vmxnet3_tq_create(tq, adapter);
3303 /*
3304 * Too late to change num_tx_queues. We cannot do away with
3305 * lesser number of queues than what we asked for
3306 */
3307 if (err)
3308 goto queue_err;
3309 }
3310
3311 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
3312 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
3313 vmxnet3_adjust_rx_ring_size(adapter);
3314
3315 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
3316 for (i = 0; i < adapter->num_rx_queues; i++) {
3317 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
3318 /* qid and qid2 for rx queues will be assigned later when num
3319 * of rx queues is finalized after allocating intrs */
3320 rq->shared = &adapter->rqd_start[i].ctrl;
3321 rq->adapter = adapter;
3322 rq->data_ring.desc_size = rxdata_desc_size;
3323 err = vmxnet3_rq_create(rq, adapter);
3324 if (err) {
3325 if (i == 0) {
3326 netdev_err(adapter->netdev,
3327 "Could not allocate any rx queues. "
3328 "Aborting.\n");
3329 goto queue_err;
3330 } else {
3331 netdev_info(adapter->netdev,
3332 "Number of rx queues changed "
3333 "to : %d.\n", i);
3334 adapter->num_rx_queues = i;
3335 err = 0;
3336 break;
3337 }
3338 }
3339 }
3340
3341 if (!adapter->rxdataring_enabled)
3342 vmxnet3_rq_destroy_all_rxdataring(adapter);
3343
3344 return err;
3345queue_err:
3346 vmxnet3_tq_destroy_all(adapter);
3347 return err;
3348}
3349
3350static int
3351vmxnet3_open(struct net_device *netdev)
3352{
3353 struct vmxnet3_adapter *adapter;
3354 int err, i;
3355
3356 adapter = netdev_priv(netdev);
3357
3358 for (i = 0; i < adapter->num_tx_queues; i++)
3359 spin_lock_init(&adapter->tx_queue[i].tx_lock);
3360
3361 if (VMXNET3_VERSION_GE_3(adapter)) {
3362 unsigned long flags;
3363 u16 txdata_desc_size;
3364
3365 spin_lock_irqsave(&adapter->cmd_lock, flags);
3366 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3367 VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
3368 txdata_desc_size = VMXNET3_READ_BAR1_REG(adapter,
3369 VMXNET3_REG_CMD);
3370 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3371
3372 if ((txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE) ||
3373 (txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE) ||
3374 (txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK)) {
3375 adapter->txdata_desc_size =
3376 sizeof(struct Vmxnet3_TxDataDesc);
3377 } else {
3378 adapter->txdata_desc_size = txdata_desc_size;
3379 }
3380 } else {
3381 adapter->txdata_desc_size = sizeof(struct Vmxnet3_TxDataDesc);
3382 }
3383
3384 err = vmxnet3_create_queues(adapter,
3385 adapter->tx_ring_size,
3386 adapter->rx_ring_size,
3387 adapter->rx_ring2_size,
3388 adapter->txdata_desc_size,
3389 adapter->rxdata_desc_size);
3390 if (err)
3391 goto queue_err;
3392
3393 err = vmxnet3_activate_dev(adapter);
3394 if (err)
3395 goto activate_err;
3396
3397 return 0;
3398
3399activate_err:
3400 vmxnet3_rq_destroy_all(adapter);
3401 vmxnet3_tq_destroy_all(adapter);
3402queue_err:
3403 return err;
3404}
3405
3406
3407static int
3408vmxnet3_close(struct net_device *netdev)
3409{
3410 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3411
3412 /*
3413 * Reset_work may be in the middle of resetting the device, wait for its
3414 * completion.
3415 */
3416 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3417 usleep_range(1000, 2000);
3418
3419 vmxnet3_quiesce_dev(adapter);
3420
3421 vmxnet3_rq_destroy_all(adapter);
3422 vmxnet3_tq_destroy_all(adapter);
3423
3424 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3425
3426
3427 return 0;
3428}
3429
3430
3431void
3432vmxnet3_force_close(struct vmxnet3_adapter *adapter)
3433{
3434 int i;
3435
3436 /*
3437 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
3438 * vmxnet3_close() will deadlock.
3439 */
3440 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
3441
3442 /* we need to enable NAPI, otherwise dev_close will deadlock */
3443 for (i = 0; i < adapter->num_rx_queues; i++)
3444 napi_enable(&adapter->rx_queue[i].napi);
3445 /*
3446 * Need to clear the quiesce bit to ensure that vmxnet3_close
3447 * can quiesce the device properly
3448 */
3449 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
3450 dev_close(adapter->netdev);
3451}
3452
3453
3454static int
3455vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
3456{
3457 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3458 int err = 0;
3459
3460 netdev->mtu = new_mtu;
3461
3462 /*
3463 * Reset_work may be in the middle of resetting the device, wait for its
3464 * completion.
3465 */
3466 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3467 usleep_range(1000, 2000);
3468
3469 if (netif_running(netdev)) {
3470 vmxnet3_quiesce_dev(adapter);
3471 vmxnet3_reset_dev(adapter);
3472
3473 /* we need to re-create the rx queue based on the new mtu */
3474 vmxnet3_rq_destroy_all(adapter);
3475 vmxnet3_adjust_rx_ring_size(adapter);
3476 err = vmxnet3_rq_create_all(adapter);
3477 if (err) {
3478 netdev_err(netdev,
3479 "failed to re-create rx queues, "
3480 " error %d. Closing it.\n", err);
3481 goto out;
3482 }
3483
3484 err = vmxnet3_activate_dev(adapter);
3485 if (err) {
3486 netdev_err(netdev,
3487 "failed to re-activate, error %d. "
3488 "Closing it\n", err);
3489 goto out;
3490 }
3491 }
3492
3493out:
3494 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3495 if (err)
3496 vmxnet3_force_close(adapter);
3497
3498 return err;
3499}
3500
3501
3502static void
3503vmxnet3_declare_features(struct vmxnet3_adapter *adapter)
3504{
3505 struct net_device *netdev = adapter->netdev;
3506
3507 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
3508 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
3509 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
3510 NETIF_F_LRO | NETIF_F_HIGHDMA;
3511
3512 if (VMXNET3_VERSION_GE_4(adapter)) {
3513 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3514 NETIF_F_GSO_UDP_TUNNEL_CSUM;
3515
3516 netdev->hw_enc_features = NETIF_F_SG | NETIF_F_RXCSUM |
3517 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
3518 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
3519 NETIF_F_LRO | NETIF_F_GSO_UDP_TUNNEL |
3520 NETIF_F_GSO_UDP_TUNNEL_CSUM;
3521 }
3522
3523 if (VMXNET3_VERSION_GE_7(adapter)) {
3524 unsigned long flags;
3525
3526 if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
3527 VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD)) {
3528 adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD;
3529 }
3530 if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
3531 VMXNET3_CAP_VXLAN_CHECKSUM_OFFLOAD)) {
3532 adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_VXLAN_CHECKSUM_OFFLOAD;
3533 }
3534 if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
3535 VMXNET3_CAP_GENEVE_TSO)) {
3536 adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_GENEVE_TSO;
3537 }
3538 if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
3539 VMXNET3_CAP_VXLAN_TSO)) {
3540 adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_VXLAN_TSO;
3541 }
3542 if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
3543 VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD)) {
3544 adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD;
3545 }
3546 if (vmxnet3_check_ptcapability(adapter->ptcap_supported[0],
3547 VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD)) {
3548 adapter->dev_caps[0] |= 1UL << VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD;
3549 }
3550
3551 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DCR, adapter->dev_caps[0]);
3552 spin_lock_irqsave(&adapter->cmd_lock, flags);
3553 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_DCR0_REG);
3554 adapter->dev_caps[0] = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
3555 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3556
3557 if (!(adapter->dev_caps[0] & (1UL << VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD)) &&
3558 !(adapter->dev_caps[0] & (1UL << VMXNET3_CAP_VXLAN_CHECKSUM_OFFLOAD)) &&
3559 !(adapter->dev_caps[0] & (1UL << VMXNET3_CAP_GENEVE_TSO)) &&
3560 !(adapter->dev_caps[0] & (1UL << VMXNET3_CAP_VXLAN_TSO))) {
3561 netdev->hw_enc_features &= ~NETIF_F_GSO_UDP_TUNNEL;
3562 netdev->hw_features &= ~NETIF_F_GSO_UDP_TUNNEL;
3563 }
3564 if (!(adapter->dev_caps[0] & (1UL << VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD)) &&
3565 !(adapter->dev_caps[0] & (1UL << VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD))) {
3566 netdev->hw_enc_features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
3567 netdev->hw_features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
3568 }
3569 }
3570
3571 netdev->vlan_features = netdev->hw_features &
3572 ~(NETIF_F_HW_VLAN_CTAG_TX |
3573 NETIF_F_HW_VLAN_CTAG_RX);
3574 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
3575}
3576
3577
3578static void
3579vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
3580{
3581 u32 tmp;
3582
3583 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
3584 *(u32 *)mac = tmp;
3585
3586 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
3587 mac[4] = tmp & 0xff;
3588 mac[5] = (tmp >> 8) & 0xff;
3589}
3590
3591#ifdef CONFIG_PCI_MSI
3592
3593/*
3594 * Enable MSIx vectors.
3595 * Returns :
3596 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
3597 * were enabled.
3598 * number of vectors which were enabled otherwise (this number is greater
3599 * than VMXNET3_LINUX_MIN_MSIX_VECT)
3600 */
3601
3602static int
3603vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, int nvec)
3604{
3605 int ret = pci_enable_msix_range(adapter->pdev,
3606 adapter->intr.msix_entries, nvec, nvec);
3607
3608 if (ret == -ENOSPC && nvec > VMXNET3_LINUX_MIN_MSIX_VECT) {
3609 dev_err(&adapter->netdev->dev,
3610 "Failed to enable %d MSI-X, trying %d\n",
3611 nvec, VMXNET3_LINUX_MIN_MSIX_VECT);
3612
3613 ret = pci_enable_msix_range(adapter->pdev,
3614 adapter->intr.msix_entries,
3615 VMXNET3_LINUX_MIN_MSIX_VECT,
3616 VMXNET3_LINUX_MIN_MSIX_VECT);
3617 }
3618
3619 if (ret < 0) {
3620 dev_err(&adapter->netdev->dev,
3621 "Failed to enable MSI-X, error: %d\n", ret);
3622 }
3623
3624 return ret;
3625}
3626
3627
3628#endif /* CONFIG_PCI_MSI */
3629
3630static void
3631vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
3632{
3633 u32 cfg;
3634 unsigned long flags;
3635
3636 /* intr settings */
3637 spin_lock_irqsave(&adapter->cmd_lock, flags);
3638 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3639 VMXNET3_CMD_GET_CONF_INTR);
3640 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
3641 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3642 adapter->intr.type = cfg & 0x3;
3643 adapter->intr.mask_mode = (cfg >> 2) & 0x3;
3644
3645 if (adapter->intr.type == VMXNET3_IT_AUTO) {
3646 adapter->intr.type = VMXNET3_IT_MSIX;
3647 }
3648
3649#ifdef CONFIG_PCI_MSI
3650 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3651 int i, nvec, nvec_allocated;
3652
3653 nvec = adapter->share_intr == VMXNET3_INTR_TXSHARE ?
3654 1 : adapter->num_tx_queues;
3655 nvec += adapter->share_intr == VMXNET3_INTR_BUDDYSHARE ?
3656 0 : adapter->num_rx_queues;
3657 nvec += 1; /* for link event */
3658 nvec = nvec > VMXNET3_LINUX_MIN_MSIX_VECT ?
3659 nvec : VMXNET3_LINUX_MIN_MSIX_VECT;
3660
3661 for (i = 0; i < nvec; i++)
3662 adapter->intr.msix_entries[i].entry = i;
3663
3664 nvec_allocated = vmxnet3_acquire_msix_vectors(adapter, nvec);
3665 if (nvec_allocated < 0)
3666 goto msix_err;
3667
3668 /* If we cannot allocate one MSIx vector per queue
3669 * then limit the number of rx queues to 1
3670 */
3671 if (nvec_allocated == VMXNET3_LINUX_MIN_MSIX_VECT &&
3672 nvec != VMXNET3_LINUX_MIN_MSIX_VECT) {
3673 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
3674 || adapter->num_rx_queues != 1) {
3675 adapter->share_intr = VMXNET3_INTR_TXSHARE;
3676 netdev_err(adapter->netdev,
3677 "Number of rx queues : 1\n");
3678 adapter->num_rx_queues = 1;
3679 }
3680 }
3681
3682 adapter->intr.num_intrs = nvec_allocated;
3683 return;
3684
3685msix_err:
3686 /* If we cannot allocate MSIx vectors use only one rx queue */
3687 dev_info(&adapter->pdev->dev,
3688 "Failed to enable MSI-X, error %d. "
3689 "Limiting #rx queues to 1, try MSI.\n", nvec_allocated);
3690
3691 adapter->intr.type = VMXNET3_IT_MSI;
3692 }
3693
3694 if (adapter->intr.type == VMXNET3_IT_MSI) {
3695 if (!pci_enable_msi(adapter->pdev)) {
3696 adapter->num_rx_queues = 1;
3697 adapter->intr.num_intrs = 1;
3698 return;
3699 }
3700 }
3701#endif /* CONFIG_PCI_MSI */
3702
3703 adapter->num_rx_queues = 1;
3704 dev_info(&adapter->netdev->dev,
3705 "Using INTx interrupt, #Rx queues: 1.\n");
3706 adapter->intr.type = VMXNET3_IT_INTX;
3707
3708 /* INT-X related setting */
3709 adapter->intr.num_intrs = 1;
3710}
3711
3712
3713static void
3714vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
3715{
3716 if (adapter->intr.type == VMXNET3_IT_MSIX)
3717 pci_disable_msix(adapter->pdev);
3718 else if (adapter->intr.type == VMXNET3_IT_MSI)
3719 pci_disable_msi(adapter->pdev);
3720 else
3721 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
3722}
3723
3724
3725static void
3726vmxnet3_tx_timeout(struct net_device *netdev, unsigned int txqueue)
3727{
3728 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3729 adapter->tx_timeout_count++;
3730
3731 netdev_err(adapter->netdev, "tx hang\n");
3732 schedule_work(&adapter->work);
3733}
3734
3735
3736static void
3737vmxnet3_reset_work(struct work_struct *data)
3738{
3739 struct vmxnet3_adapter *adapter;
3740
3741 adapter = container_of(data, struct vmxnet3_adapter, work);
3742
3743 /* if another thread is resetting the device, no need to proceed */
3744 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3745 return;
3746
3747 /* if the device is closed, we must leave it alone */
3748 rtnl_lock();
3749 if (netif_running(adapter->netdev)) {
3750 netdev_notice(adapter->netdev, "resetting\n");
3751 vmxnet3_quiesce_dev(adapter);
3752 vmxnet3_reset_dev(adapter);
3753 vmxnet3_activate_dev(adapter);
3754 } else {
3755 netdev_info(adapter->netdev, "already closed\n");
3756 }
3757 rtnl_unlock();
3758
3759 netif_wake_queue(adapter->netdev);
3760 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3761}
3762
3763
3764static int
3765vmxnet3_probe_device(struct pci_dev *pdev,
3766 const struct pci_device_id *id)
3767{
3768 static const struct net_device_ops vmxnet3_netdev_ops = {
3769 .ndo_open = vmxnet3_open,
3770 .ndo_stop = vmxnet3_close,
3771 .ndo_start_xmit = vmxnet3_xmit_frame,
3772 .ndo_set_mac_address = vmxnet3_set_mac_addr,
3773 .ndo_change_mtu = vmxnet3_change_mtu,
3774 .ndo_fix_features = vmxnet3_fix_features,
3775 .ndo_set_features = vmxnet3_set_features,
3776 .ndo_features_check = vmxnet3_features_check,
3777 .ndo_get_stats64 = vmxnet3_get_stats64,
3778 .ndo_tx_timeout = vmxnet3_tx_timeout,
3779 .ndo_set_rx_mode = vmxnet3_set_mc,
3780 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
3781 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
3782#ifdef CONFIG_NET_POLL_CONTROLLER
3783 .ndo_poll_controller = vmxnet3_netpoll,
3784#endif
3785 .ndo_bpf = vmxnet3_xdp,
3786 .ndo_xdp_xmit = vmxnet3_xdp_xmit,
3787 };
3788 int err;
3789 u32 ver;
3790 struct net_device *netdev;
3791 struct vmxnet3_adapter *adapter;
3792 u8 mac[ETH_ALEN];
3793 int size;
3794 int num_tx_queues;
3795 int num_rx_queues;
3796 int queues;
3797 unsigned long flags;
3798
3799 if (!pci_msi_enabled())
3800 enable_mq = 0;
3801
3802#ifdef VMXNET3_RSS
3803 if (enable_mq)
3804 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3805 (int)num_online_cpus());
3806 else
3807#endif
3808 num_rx_queues = 1;
3809
3810 if (enable_mq)
3811 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
3812 (int)num_online_cpus());
3813 else
3814 num_tx_queues = 1;
3815
3816 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
3817 max(num_tx_queues, num_rx_queues));
3818 if (!netdev)
3819 return -ENOMEM;
3820
3821 pci_set_drvdata(pdev, netdev);
3822 adapter = netdev_priv(netdev);
3823 adapter->netdev = netdev;
3824 adapter->pdev = pdev;
3825
3826 adapter->tx_ring_size = VMXNET3_DEF_TX_RING_SIZE;
3827 adapter->rx_ring_size = VMXNET3_DEF_RX_RING_SIZE;
3828 adapter->rx_ring2_size = VMXNET3_DEF_RX_RING2_SIZE;
3829
3830 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3831 if (err) {
3832 dev_err(&pdev->dev, "dma_set_mask failed\n");
3833 goto err_set_mask;
3834 }
3835
3836 spin_lock_init(&adapter->cmd_lock);
3837 adapter->adapter_pa = dma_map_single(&adapter->pdev->dev, adapter,
3838 sizeof(struct vmxnet3_adapter),
3839 DMA_TO_DEVICE);
3840 if (dma_mapping_error(&adapter->pdev->dev, adapter->adapter_pa)) {
3841 dev_err(&pdev->dev, "Failed to map dma\n");
3842 err = -EFAULT;
3843 goto err_set_mask;
3844 }
3845 adapter->shared = dma_alloc_coherent(
3846 &adapter->pdev->dev,
3847 sizeof(struct Vmxnet3_DriverShared),
3848 &adapter->shared_pa, GFP_KERNEL);
3849 if (!adapter->shared) {
3850 dev_err(&pdev->dev, "Failed to allocate memory\n");
3851 err = -ENOMEM;
3852 goto err_alloc_shared;
3853 }
3854
3855 err = vmxnet3_alloc_pci_resources(adapter);
3856 if (err < 0)
3857 goto err_alloc_pci;
3858
3859 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
3860 if (ver & (1 << VMXNET3_REV_7)) {
3861 VMXNET3_WRITE_BAR1_REG(adapter,
3862 VMXNET3_REG_VRRS,
3863 1 << VMXNET3_REV_7);
3864 adapter->version = VMXNET3_REV_7 + 1;
3865 } else if (ver & (1 << VMXNET3_REV_6)) {
3866 VMXNET3_WRITE_BAR1_REG(adapter,
3867 VMXNET3_REG_VRRS,
3868 1 << VMXNET3_REV_6);
3869 adapter->version = VMXNET3_REV_6 + 1;
3870 } else if (ver & (1 << VMXNET3_REV_5)) {
3871 VMXNET3_WRITE_BAR1_REG(adapter,
3872 VMXNET3_REG_VRRS,
3873 1 << VMXNET3_REV_5);
3874 adapter->version = VMXNET3_REV_5 + 1;
3875 } else if (ver & (1 << VMXNET3_REV_4)) {
3876 VMXNET3_WRITE_BAR1_REG(adapter,
3877 VMXNET3_REG_VRRS,
3878 1 << VMXNET3_REV_4);
3879 adapter->version = VMXNET3_REV_4 + 1;
3880 } else if (ver & (1 << VMXNET3_REV_3)) {
3881 VMXNET3_WRITE_BAR1_REG(adapter,
3882 VMXNET3_REG_VRRS,
3883 1 << VMXNET3_REV_3);
3884 adapter->version = VMXNET3_REV_3 + 1;
3885 } else if (ver & (1 << VMXNET3_REV_2)) {
3886 VMXNET3_WRITE_BAR1_REG(adapter,
3887 VMXNET3_REG_VRRS,
3888 1 << VMXNET3_REV_2);
3889 adapter->version = VMXNET3_REV_2 + 1;
3890 } else if (ver & (1 << VMXNET3_REV_1)) {
3891 VMXNET3_WRITE_BAR1_REG(adapter,
3892 VMXNET3_REG_VRRS,
3893 1 << VMXNET3_REV_1);
3894 adapter->version = VMXNET3_REV_1 + 1;
3895 } else {
3896 dev_err(&pdev->dev,
3897 "Incompatible h/w version (0x%x) for adapter\n", ver);
3898 err = -EBUSY;
3899 goto err_ver;
3900 }
3901 dev_dbg(&pdev->dev, "Using device version %d\n", adapter->version);
3902
3903 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
3904 if (ver & 1) {
3905 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
3906 } else {
3907 dev_err(&pdev->dev,
3908 "Incompatible upt version (0x%x) for adapter\n", ver);
3909 err = -EBUSY;
3910 goto err_ver;
3911 }
3912
3913 if (VMXNET3_VERSION_GE_7(adapter)) {
3914 adapter->devcap_supported[0] = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_DCR);
3915 adapter->ptcap_supported[0] = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_PTCR);
3916 if (adapter->devcap_supported[0] & (1UL << VMXNET3_CAP_LARGE_BAR)) {
3917 adapter->dev_caps[0] = adapter->devcap_supported[0] &
3918 (1UL << VMXNET3_CAP_LARGE_BAR);
3919 }
3920 if (!(adapter->ptcap_supported[0] & (1UL << VMXNET3_DCR_ERROR)) &&
3921 adapter->ptcap_supported[0] & (1UL << VMXNET3_CAP_OOORX_COMP) &&
3922 adapter->devcap_supported[0] & (1UL << VMXNET3_CAP_OOORX_COMP)) {
3923 adapter->dev_caps[0] |= adapter->devcap_supported[0] &
3924 (1UL << VMXNET3_CAP_OOORX_COMP);
3925 }
3926 if (adapter->dev_caps[0])
3927 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DCR, adapter->dev_caps[0]);
3928
3929 spin_lock_irqsave(&adapter->cmd_lock, flags);
3930 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_DCR0_REG);
3931 adapter->dev_caps[0] = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
3932 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3933 }
3934
3935 if (VMXNET3_VERSION_GE_7(adapter) &&
3936 adapter->dev_caps[0] & (1UL << VMXNET3_CAP_LARGE_BAR)) {
3937 adapter->tx_prod_offset = VMXNET3_REG_LB_TXPROD;
3938 adapter->rx_prod_offset = VMXNET3_REG_LB_RXPROD;
3939 adapter->rx_prod2_offset = VMXNET3_REG_LB_RXPROD2;
3940 } else {
3941 adapter->tx_prod_offset = VMXNET3_REG_TXPROD;
3942 adapter->rx_prod_offset = VMXNET3_REG_RXPROD;
3943 adapter->rx_prod2_offset = VMXNET3_REG_RXPROD2;
3944 }
3945
3946 if (VMXNET3_VERSION_GE_6(adapter)) {
3947 spin_lock_irqsave(&adapter->cmd_lock, flags);
3948 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3949 VMXNET3_CMD_GET_MAX_QUEUES_CONF);
3950 queues = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
3951 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3952 if (queues > 0) {
3953 adapter->num_rx_queues = min(num_rx_queues, ((queues >> 8) & 0xff));
3954 adapter->num_tx_queues = min(num_tx_queues, (queues & 0xff));
3955 } else {
3956 adapter->num_rx_queues = min(num_rx_queues,
3957 VMXNET3_DEVICE_DEFAULT_RX_QUEUES);
3958 adapter->num_tx_queues = min(num_tx_queues,
3959 VMXNET3_DEVICE_DEFAULT_TX_QUEUES);
3960 }
3961 if (adapter->num_rx_queues > VMXNET3_MAX_RX_QUEUES ||
3962 adapter->num_tx_queues > VMXNET3_MAX_TX_QUEUES) {
3963 adapter->queuesExtEnabled = true;
3964 } else {
3965 adapter->queuesExtEnabled = false;
3966 }
3967 } else {
3968 adapter->queuesExtEnabled = false;
3969 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
3970 num_tx_queues = rounddown_pow_of_two(num_tx_queues);
3971 adapter->num_rx_queues = min(num_rx_queues,
3972 VMXNET3_DEVICE_DEFAULT_RX_QUEUES);
3973 adapter->num_tx_queues = min(num_tx_queues,
3974 VMXNET3_DEVICE_DEFAULT_TX_QUEUES);
3975 }
3976 dev_info(&pdev->dev,
3977 "# of Tx queues : %d, # of Rx queues : %d\n",
3978 adapter->num_tx_queues, adapter->num_rx_queues);
3979
3980 adapter->rx_buf_per_pkt = 1;
3981
3982 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3983 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
3984 adapter->tqd_start = dma_alloc_coherent(&adapter->pdev->dev, size,
3985 &adapter->queue_desc_pa,
3986 GFP_KERNEL);
3987
3988 if (!adapter->tqd_start) {
3989 dev_err(&pdev->dev, "Failed to allocate memory\n");
3990 err = -ENOMEM;
3991 goto err_ver;
3992 }
3993 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
3994 adapter->num_tx_queues);
3995
3996 adapter->pm_conf = dma_alloc_coherent(&adapter->pdev->dev,
3997 sizeof(struct Vmxnet3_PMConf),
3998 &adapter->pm_conf_pa,
3999 GFP_KERNEL);
4000 if (adapter->pm_conf == NULL) {
4001 err = -ENOMEM;
4002 goto err_alloc_pm;
4003 }
4004
4005#ifdef VMXNET3_RSS
4006
4007 adapter->rss_conf = dma_alloc_coherent(&adapter->pdev->dev,
4008 sizeof(struct UPT1_RSSConf),
4009 &adapter->rss_conf_pa,
4010 GFP_KERNEL);
4011 if (adapter->rss_conf == NULL) {
4012 err = -ENOMEM;
4013 goto err_alloc_rss;
4014 }
4015#endif /* VMXNET3_RSS */
4016
4017 if (VMXNET3_VERSION_GE_3(adapter)) {
4018 adapter->coal_conf =
4019 dma_alloc_coherent(&adapter->pdev->dev,
4020 sizeof(struct Vmxnet3_CoalesceScheme)
4021 ,
4022 &adapter->coal_conf_pa,
4023 GFP_KERNEL);
4024 if (!adapter->coal_conf) {
4025 err = -ENOMEM;
4026 goto err_coal_conf;
4027 }
4028 adapter->coal_conf->coalMode = VMXNET3_COALESCE_DISABLED;
4029 adapter->default_coal_mode = true;
4030 }
4031
4032 if (VMXNET3_VERSION_GE_4(adapter)) {
4033 adapter->default_rss_fields = true;
4034 adapter->rss_fields = VMXNET3_RSS_FIELDS_DEFAULT;
4035 }
4036
4037 SET_NETDEV_DEV(netdev, &pdev->dev);
4038 vmxnet3_declare_features(adapter);
4039 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
4040 NETDEV_XDP_ACT_NDO_XMIT;
4041
4042 adapter->rxdata_desc_size = VMXNET3_VERSION_GE_3(adapter) ?
4043 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
4044
4045 if (adapter->num_tx_queues == adapter->num_rx_queues)
4046 adapter->share_intr = VMXNET3_INTR_BUDDYSHARE;
4047 else
4048 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
4049
4050 vmxnet3_alloc_intr_resources(adapter);
4051
4052#ifdef VMXNET3_RSS
4053 if (adapter->num_rx_queues > 1 &&
4054 adapter->intr.type == VMXNET3_IT_MSIX) {
4055 adapter->rss = true;
4056 netdev->hw_features |= NETIF_F_RXHASH;
4057 netdev->features |= NETIF_F_RXHASH;
4058 dev_dbg(&pdev->dev, "RSS is enabled.\n");
4059 } else {
4060 adapter->rss = false;
4061 }
4062#endif
4063
4064 vmxnet3_read_mac_addr(adapter, mac);
4065 dev_addr_set(netdev, mac);
4066
4067 netdev->netdev_ops = &vmxnet3_netdev_ops;
4068 vmxnet3_set_ethtool_ops(netdev);
4069 netdev->watchdog_timeo = 5 * HZ;
4070
4071 /* MTU range: 60 - 9190 */
4072 netdev->min_mtu = VMXNET3_MIN_MTU;
4073 if (VMXNET3_VERSION_GE_6(adapter))
4074 netdev->max_mtu = VMXNET3_V6_MAX_MTU;
4075 else
4076 netdev->max_mtu = VMXNET3_MAX_MTU;
4077
4078 INIT_WORK(&adapter->work, vmxnet3_reset_work);
4079 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
4080
4081 if (adapter->intr.type == VMXNET3_IT_MSIX) {
4082 int i;
4083 for (i = 0; i < adapter->num_rx_queues; i++) {
4084 netif_napi_add(adapter->netdev,
4085 &adapter->rx_queue[i].napi,
4086 vmxnet3_poll_rx_only);
4087 }
4088 } else {
4089 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
4090 vmxnet3_poll);
4091 }
4092
4093 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4094 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
4095
4096 netif_carrier_off(netdev);
4097 err = register_netdev(netdev);
4098
4099 if (err) {
4100 dev_err(&pdev->dev, "Failed to register adapter\n");
4101 goto err_register;
4102 }
4103
4104 vmxnet3_check_link(adapter, false);
4105 return 0;
4106
4107err_register:
4108 if (VMXNET3_VERSION_GE_3(adapter)) {
4109 dma_free_coherent(&adapter->pdev->dev,
4110 sizeof(struct Vmxnet3_CoalesceScheme),
4111 adapter->coal_conf, adapter->coal_conf_pa);
4112 }
4113 vmxnet3_free_intr_resources(adapter);
4114err_coal_conf:
4115#ifdef VMXNET3_RSS
4116 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
4117 adapter->rss_conf, adapter->rss_conf_pa);
4118err_alloc_rss:
4119#endif
4120 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
4121 adapter->pm_conf, adapter->pm_conf_pa);
4122err_alloc_pm:
4123 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
4124 adapter->queue_desc_pa);
4125err_ver:
4126 vmxnet3_free_pci_resources(adapter);
4127err_alloc_pci:
4128 dma_free_coherent(&adapter->pdev->dev,
4129 sizeof(struct Vmxnet3_DriverShared),
4130 adapter->shared, adapter->shared_pa);
4131err_alloc_shared:
4132 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
4133 sizeof(struct vmxnet3_adapter), DMA_TO_DEVICE);
4134err_set_mask:
4135 free_netdev(netdev);
4136 return err;
4137}
4138
4139
4140static void
4141vmxnet3_remove_device(struct pci_dev *pdev)
4142{
4143 struct net_device *netdev = pci_get_drvdata(pdev);
4144 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
4145 int size = 0;
4146 int num_rx_queues, rx_queues;
4147 unsigned long flags;
4148
4149#ifdef VMXNET3_RSS
4150 if (enable_mq)
4151 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
4152 (int)num_online_cpus());
4153 else
4154#endif
4155 num_rx_queues = 1;
4156 if (!VMXNET3_VERSION_GE_6(adapter)) {
4157 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
4158 }
4159 if (VMXNET3_VERSION_GE_6(adapter)) {
4160 spin_lock_irqsave(&adapter->cmd_lock, flags);
4161 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
4162 VMXNET3_CMD_GET_MAX_QUEUES_CONF);
4163 rx_queues = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
4164 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
4165 if (rx_queues > 0)
4166 rx_queues = (rx_queues >> 8) & 0xff;
4167 else
4168 rx_queues = min(num_rx_queues, VMXNET3_DEVICE_DEFAULT_RX_QUEUES);
4169 num_rx_queues = min(num_rx_queues, rx_queues);
4170 } else {
4171 num_rx_queues = min(num_rx_queues,
4172 VMXNET3_DEVICE_DEFAULT_RX_QUEUES);
4173 }
4174
4175 cancel_work_sync(&adapter->work);
4176
4177 unregister_netdev(netdev);
4178
4179 vmxnet3_free_intr_resources(adapter);
4180 vmxnet3_free_pci_resources(adapter);
4181 if (VMXNET3_VERSION_GE_3(adapter)) {
4182 dma_free_coherent(&adapter->pdev->dev,
4183 sizeof(struct Vmxnet3_CoalesceScheme),
4184 adapter->coal_conf, adapter->coal_conf_pa);
4185 }
4186#ifdef VMXNET3_RSS
4187 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
4188 adapter->rss_conf, adapter->rss_conf_pa);
4189#endif
4190 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
4191 adapter->pm_conf, adapter->pm_conf_pa);
4192
4193 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
4194 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
4195 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
4196 adapter->queue_desc_pa);
4197 dma_free_coherent(&adapter->pdev->dev,
4198 sizeof(struct Vmxnet3_DriverShared),
4199 adapter->shared, adapter->shared_pa);
4200 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
4201 sizeof(struct vmxnet3_adapter), DMA_TO_DEVICE);
4202 free_netdev(netdev);
4203}
4204
4205static void vmxnet3_shutdown_device(struct pci_dev *pdev)
4206{
4207 struct net_device *netdev = pci_get_drvdata(pdev);
4208 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
4209 unsigned long flags;
4210
4211 /* Reset_work may be in the middle of resetting the device, wait for its
4212 * completion.
4213 */
4214 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
4215 usleep_range(1000, 2000);
4216
4217 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED,
4218 &adapter->state)) {
4219 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
4220 return;
4221 }
4222 spin_lock_irqsave(&adapter->cmd_lock, flags);
4223 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
4224 VMXNET3_CMD_QUIESCE_DEV);
4225 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
4226 vmxnet3_disable_all_intrs(adapter);
4227
4228 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
4229}
4230
4231
4232#ifdef CONFIG_PM
4233
4234static int
4235vmxnet3_suspend(struct device *device)
4236{
4237 struct pci_dev *pdev = to_pci_dev(device);
4238 struct net_device *netdev = pci_get_drvdata(pdev);
4239 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
4240 struct Vmxnet3_PMConf *pmConf;
4241 struct ethhdr *ehdr;
4242 struct arphdr *ahdr;
4243 u8 *arpreq;
4244 struct in_device *in_dev;
4245 struct in_ifaddr *ifa;
4246 unsigned long flags;
4247 int i = 0;
4248
4249 if (!netif_running(netdev))
4250 return 0;
4251
4252 for (i = 0; i < adapter->num_rx_queues; i++)
4253 napi_disable(&adapter->rx_queue[i].napi);
4254
4255 vmxnet3_disable_all_intrs(adapter);
4256 vmxnet3_free_irqs(adapter);
4257 vmxnet3_free_intr_resources(adapter);
4258
4259 netif_device_detach(netdev);
4260
4261 /* Create wake-up filters. */
4262 pmConf = adapter->pm_conf;
4263 memset(pmConf, 0, sizeof(*pmConf));
4264
4265 if (adapter->wol & WAKE_UCAST) {
4266 pmConf->filters[i].patternSize = ETH_ALEN;
4267 pmConf->filters[i].maskSize = 1;
4268 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
4269 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
4270
4271 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
4272 i++;
4273 }
4274
4275 if (adapter->wol & WAKE_ARP) {
4276 rcu_read_lock();
4277
4278 in_dev = __in_dev_get_rcu(netdev);
4279 if (!in_dev) {
4280 rcu_read_unlock();
4281 goto skip_arp;
4282 }
4283
4284 ifa = rcu_dereference(in_dev->ifa_list);
4285 if (!ifa) {
4286 rcu_read_unlock();
4287 goto skip_arp;
4288 }
4289
4290 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
4291 sizeof(struct arphdr) + /* ARP header */
4292 2 * ETH_ALEN + /* 2 Ethernet addresses*/
4293 2 * sizeof(u32); /*2 IPv4 addresses */
4294 pmConf->filters[i].maskSize =
4295 (pmConf->filters[i].patternSize - 1) / 8 + 1;
4296
4297 /* ETH_P_ARP in Ethernet header. */
4298 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
4299 ehdr->h_proto = htons(ETH_P_ARP);
4300
4301 /* ARPOP_REQUEST in ARP header. */
4302 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
4303 ahdr->ar_op = htons(ARPOP_REQUEST);
4304 arpreq = (u8 *)(ahdr + 1);
4305
4306 /* The Unicast IPv4 address in 'tip' field. */
4307 arpreq += 2 * ETH_ALEN + sizeof(u32);
4308 *(__be32 *)arpreq = ifa->ifa_address;
4309
4310 rcu_read_unlock();
4311
4312 /* The mask for the relevant bits. */
4313 pmConf->filters[i].mask[0] = 0x00;
4314 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
4315 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
4316 pmConf->filters[i].mask[3] = 0x00;
4317 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
4318 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
4319
4320 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
4321 i++;
4322 }
4323
4324skip_arp:
4325 if (adapter->wol & WAKE_MAGIC)
4326 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
4327
4328 pmConf->numFilters = i;
4329
4330 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
4331 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
4332 *pmConf));
4333 adapter->shared->devRead.pmConfDesc.confPA =
4334 cpu_to_le64(adapter->pm_conf_pa);
4335
4336 spin_lock_irqsave(&adapter->cmd_lock, flags);
4337 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
4338 VMXNET3_CMD_UPDATE_PMCFG);
4339 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
4340
4341 pci_save_state(pdev);
4342 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
4343 adapter->wol);
4344 pci_disable_device(pdev);
4345 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
4346
4347 return 0;
4348}
4349
4350
4351static int
4352vmxnet3_resume(struct device *device)
4353{
4354 int err;
4355 unsigned long flags;
4356 struct pci_dev *pdev = to_pci_dev(device);
4357 struct net_device *netdev = pci_get_drvdata(pdev);
4358 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
4359
4360 if (!netif_running(netdev))
4361 return 0;
4362
4363 pci_set_power_state(pdev, PCI_D0);
4364 pci_restore_state(pdev);
4365 err = pci_enable_device_mem(pdev);
4366 if (err != 0)
4367 return err;
4368
4369 pci_enable_wake(pdev, PCI_D0, 0);
4370
4371 vmxnet3_alloc_intr_resources(adapter);
4372
4373 /* During hibernate and suspend, device has to be reinitialized as the
4374 * device state need not be preserved.
4375 */
4376
4377 /* Need not check adapter state as other reset tasks cannot run during
4378 * device resume.
4379 */
4380 spin_lock_irqsave(&adapter->cmd_lock, flags);
4381 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
4382 VMXNET3_CMD_QUIESCE_DEV);
4383 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
4384 vmxnet3_tq_cleanup_all(adapter);
4385 vmxnet3_rq_cleanup_all(adapter);
4386
4387 vmxnet3_reset_dev(adapter);
4388 err = vmxnet3_activate_dev(adapter);
4389 if (err != 0) {
4390 netdev_err(netdev,
4391 "failed to re-activate on resume, error: %d", err);
4392 vmxnet3_force_close(adapter);
4393 return err;
4394 }
4395 netif_device_attach(netdev);
4396
4397 return 0;
4398}
4399
4400static const struct dev_pm_ops vmxnet3_pm_ops = {
4401 .suspend = vmxnet3_suspend,
4402 .resume = vmxnet3_resume,
4403 .freeze = vmxnet3_suspend,
4404 .restore = vmxnet3_resume,
4405};
4406#endif
4407
4408static struct pci_driver vmxnet3_driver = {
4409 .name = vmxnet3_driver_name,
4410 .id_table = vmxnet3_pciid_table,
4411 .probe = vmxnet3_probe_device,
4412 .remove = vmxnet3_remove_device,
4413 .shutdown = vmxnet3_shutdown_device,
4414#ifdef CONFIG_PM
4415 .driver.pm = &vmxnet3_pm_ops,
4416#endif
4417};
4418
4419
4420static int __init
4421vmxnet3_init_module(void)
4422{
4423 pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC,
4424 VMXNET3_DRIVER_VERSION_REPORT);
4425 return pci_register_driver(&vmxnet3_driver);
4426}
4427
4428module_init(vmxnet3_init_module);
4429
4430
4431static void
4432vmxnet3_exit_module(void)
4433{
4434 pci_unregister_driver(&vmxnet3_driver);
4435}
4436
4437module_exit(vmxnet3_exit_module);
4438
4439MODULE_AUTHOR("VMware, Inc.");
4440MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
4441MODULE_LICENSE("GPL v2");
4442MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);
1/*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
4 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
23 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
24 *
25 */
26
27#include <net/ip6_checksum.h>
28
29#include "vmxnet3_int.h"
30
31char vmxnet3_driver_name[] = "vmxnet3";
32#define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
33
34/*
35 * PCI Device ID Table
36 * Last entry must be all 0s
37 */
38static DEFINE_PCI_DEVICE_TABLE(vmxnet3_pciid_table) = {
39 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
40 {0}
41};
42
43MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
44
45static atomic_t devices_found;
46
47#define VMXNET3_MAX_DEVICES 10
48static int enable_mq = 1;
49static int irq_share_mode;
50
51static void
52vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
53
54/*
55 * Enable/Disable the given intr
56 */
57static void
58vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
59{
60 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
61}
62
63
64static void
65vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
66{
67 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
68}
69
70
71/*
72 * Enable/Disable all intrs used by the device
73 */
74static void
75vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
76{
77 int i;
78
79 for (i = 0; i < adapter->intr.num_intrs; i++)
80 vmxnet3_enable_intr(adapter, i);
81 adapter->shared->devRead.intrConf.intrCtrl &=
82 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
83}
84
85
86static void
87vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
88{
89 int i;
90
91 adapter->shared->devRead.intrConf.intrCtrl |=
92 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
93 for (i = 0; i < adapter->intr.num_intrs; i++)
94 vmxnet3_disable_intr(adapter, i);
95}
96
97
98static void
99vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
100{
101 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
102}
103
104
105static bool
106vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
107{
108 return tq->stopped;
109}
110
111
112static void
113vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
114{
115 tq->stopped = false;
116 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
117}
118
119
120static void
121vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
122{
123 tq->stopped = false;
124 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
125}
126
127
128static void
129vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
130{
131 tq->stopped = true;
132 tq->num_stop++;
133 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
134}
135
136
137/*
138 * Check the link state. This may start or stop the tx queue.
139 */
140static void
141vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
142{
143 u32 ret;
144 int i;
145 unsigned long flags;
146
147 spin_lock_irqsave(&adapter->cmd_lock, flags);
148 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
149 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
150 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
151
152 adapter->link_speed = ret >> 16;
153 if (ret & 1) { /* Link is up. */
154 printk(KERN_INFO "%s: NIC Link is Up %d Mbps\n",
155 adapter->netdev->name, adapter->link_speed);
156 if (!netif_carrier_ok(adapter->netdev))
157 netif_carrier_on(adapter->netdev);
158
159 if (affectTxQueue) {
160 for (i = 0; i < adapter->num_tx_queues; i++)
161 vmxnet3_tq_start(&adapter->tx_queue[i],
162 adapter);
163 }
164 } else {
165 printk(KERN_INFO "%s: NIC Link is Down\n",
166 adapter->netdev->name);
167 if (netif_carrier_ok(adapter->netdev))
168 netif_carrier_off(adapter->netdev);
169
170 if (affectTxQueue) {
171 for (i = 0; i < adapter->num_tx_queues; i++)
172 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
173 }
174 }
175}
176
177static void
178vmxnet3_process_events(struct vmxnet3_adapter *adapter)
179{
180 int i;
181 unsigned long flags;
182 u32 events = le32_to_cpu(adapter->shared->ecr);
183 if (!events)
184 return;
185
186 vmxnet3_ack_events(adapter, events);
187
188 /* Check if link state has changed */
189 if (events & VMXNET3_ECR_LINK)
190 vmxnet3_check_link(adapter, true);
191
192 /* Check if there is an error on xmit/recv queues */
193 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
194 spin_lock_irqsave(&adapter->cmd_lock, flags);
195 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
196 VMXNET3_CMD_GET_QUEUE_STATUS);
197 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
198
199 for (i = 0; i < adapter->num_tx_queues; i++)
200 if (adapter->tqd_start[i].status.stopped)
201 dev_err(&adapter->netdev->dev,
202 "%s: tq[%d] error 0x%x\n",
203 adapter->netdev->name, i, le32_to_cpu(
204 adapter->tqd_start[i].status.error));
205 for (i = 0; i < adapter->num_rx_queues; i++)
206 if (adapter->rqd_start[i].status.stopped)
207 dev_err(&adapter->netdev->dev,
208 "%s: rq[%d] error 0x%x\n",
209 adapter->netdev->name, i,
210 adapter->rqd_start[i].status.error);
211
212 schedule_work(&adapter->work);
213 }
214}
215
216#ifdef __BIG_ENDIAN_BITFIELD
217/*
218 * The device expects the bitfields in shared structures to be written in
219 * little endian. When CPU is big endian, the following routines are used to
220 * correctly read and write into ABI.
221 * The general technique used here is : double word bitfields are defined in
222 * opposite order for big endian architecture. Then before reading them in
223 * driver the complete double word is translated using le32_to_cpu. Similarly
224 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
225 * double words into required format.
226 * In order to avoid touching bits in shared structure more than once, temporary
227 * descriptors are used. These are passed as srcDesc to following functions.
228 */
229static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
230 struct Vmxnet3_RxDesc *dstDesc)
231{
232 u32 *src = (u32 *)srcDesc + 2;
233 u32 *dst = (u32 *)dstDesc + 2;
234 dstDesc->addr = le64_to_cpu(srcDesc->addr);
235 *dst = le32_to_cpu(*src);
236 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
237}
238
239static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
240 struct Vmxnet3_TxDesc *dstDesc)
241{
242 int i;
243 u32 *src = (u32 *)(srcDesc + 1);
244 u32 *dst = (u32 *)(dstDesc + 1);
245
246 /* Working backwards so that the gen bit is set at the end. */
247 for (i = 2; i > 0; i--) {
248 src--;
249 dst--;
250 *dst = cpu_to_le32(*src);
251 }
252}
253
254
255static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
256 struct Vmxnet3_RxCompDesc *dstDesc)
257{
258 int i = 0;
259 u32 *src = (u32 *)srcDesc;
260 u32 *dst = (u32 *)dstDesc;
261 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
262 *dst = le32_to_cpu(*src);
263 src++;
264 dst++;
265 }
266}
267
268
269/* Used to read bitfield values from double words. */
270static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
271{
272 u32 temp = le32_to_cpu(*bitfield);
273 u32 mask = ((1 << size) - 1) << pos;
274 temp &= mask;
275 temp >>= pos;
276 return temp;
277}
278
279
280
281#endif /* __BIG_ENDIAN_BITFIELD */
282
283#ifdef __BIG_ENDIAN_BITFIELD
284
285# define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
286 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
287 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
288# define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
289 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
290 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
291# define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
292 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
293 VMXNET3_TCD_GEN_SIZE)
294# define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
295 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
296# define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
297 (dstrcd) = (tmp); \
298 vmxnet3_RxCompToCPU((rcd), (tmp)); \
299 } while (0)
300# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
301 (dstrxd) = (tmp); \
302 vmxnet3_RxDescToCPU((rxd), (tmp)); \
303 } while (0)
304
305#else
306
307# define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
308# define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
309# define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
310# define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
311# define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
312# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
313
314#endif /* __BIG_ENDIAN_BITFIELD */
315
316
317static void
318vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
319 struct pci_dev *pdev)
320{
321 if (tbi->map_type == VMXNET3_MAP_SINGLE)
322 pci_unmap_single(pdev, tbi->dma_addr, tbi->len,
323 PCI_DMA_TODEVICE);
324 else if (tbi->map_type == VMXNET3_MAP_PAGE)
325 pci_unmap_page(pdev, tbi->dma_addr, tbi->len,
326 PCI_DMA_TODEVICE);
327 else
328 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
329
330 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
331}
332
333
334static int
335vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
336 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
337{
338 struct sk_buff *skb;
339 int entries = 0;
340
341 /* no out of order completion */
342 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
343 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
344
345 skb = tq->buf_info[eop_idx].skb;
346 BUG_ON(skb == NULL);
347 tq->buf_info[eop_idx].skb = NULL;
348
349 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
350
351 while (tq->tx_ring.next2comp != eop_idx) {
352 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
353 pdev);
354
355 /* update next2comp w/o tx_lock. Since we are marking more,
356 * instead of less, tx ring entries avail, the worst case is
357 * that the tx routine incorrectly re-queues a pkt due to
358 * insufficient tx ring entries.
359 */
360 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
361 entries++;
362 }
363
364 dev_kfree_skb_any(skb);
365 return entries;
366}
367
368
369static int
370vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
371 struct vmxnet3_adapter *adapter)
372{
373 int completed = 0;
374 union Vmxnet3_GenericDesc *gdesc;
375
376 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
377 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
378 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
379 &gdesc->tcd), tq, adapter->pdev,
380 adapter);
381
382 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
383 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
384 }
385
386 if (completed) {
387 spin_lock(&tq->tx_lock);
388 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
389 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
390 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
391 netif_carrier_ok(adapter->netdev))) {
392 vmxnet3_tq_wake(tq, adapter);
393 }
394 spin_unlock(&tq->tx_lock);
395 }
396 return completed;
397}
398
399
400static void
401vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
402 struct vmxnet3_adapter *adapter)
403{
404 int i;
405
406 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
407 struct vmxnet3_tx_buf_info *tbi;
408
409 tbi = tq->buf_info + tq->tx_ring.next2comp;
410
411 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
412 if (tbi->skb) {
413 dev_kfree_skb_any(tbi->skb);
414 tbi->skb = NULL;
415 }
416 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
417 }
418
419 /* sanity check, verify all buffers are indeed unmapped and freed */
420 for (i = 0; i < tq->tx_ring.size; i++) {
421 BUG_ON(tq->buf_info[i].skb != NULL ||
422 tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
423 }
424
425 tq->tx_ring.gen = VMXNET3_INIT_GEN;
426 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
427
428 tq->comp_ring.gen = VMXNET3_INIT_GEN;
429 tq->comp_ring.next2proc = 0;
430}
431
432
433static void
434vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
435 struct vmxnet3_adapter *adapter)
436{
437 if (tq->tx_ring.base) {
438 pci_free_consistent(adapter->pdev, tq->tx_ring.size *
439 sizeof(struct Vmxnet3_TxDesc),
440 tq->tx_ring.base, tq->tx_ring.basePA);
441 tq->tx_ring.base = NULL;
442 }
443 if (tq->data_ring.base) {
444 pci_free_consistent(adapter->pdev, tq->data_ring.size *
445 sizeof(struct Vmxnet3_TxDataDesc),
446 tq->data_ring.base, tq->data_ring.basePA);
447 tq->data_ring.base = NULL;
448 }
449 if (tq->comp_ring.base) {
450 pci_free_consistent(adapter->pdev, tq->comp_ring.size *
451 sizeof(struct Vmxnet3_TxCompDesc),
452 tq->comp_ring.base, tq->comp_ring.basePA);
453 tq->comp_ring.base = NULL;
454 }
455 kfree(tq->buf_info);
456 tq->buf_info = NULL;
457}
458
459
460/* Destroy all tx queues */
461void
462vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
463{
464 int i;
465
466 for (i = 0; i < adapter->num_tx_queues; i++)
467 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
468}
469
470
471static void
472vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
473 struct vmxnet3_adapter *adapter)
474{
475 int i;
476
477 /* reset the tx ring contents to 0 and reset the tx ring states */
478 memset(tq->tx_ring.base, 0, tq->tx_ring.size *
479 sizeof(struct Vmxnet3_TxDesc));
480 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
481 tq->tx_ring.gen = VMXNET3_INIT_GEN;
482
483 memset(tq->data_ring.base, 0, tq->data_ring.size *
484 sizeof(struct Vmxnet3_TxDataDesc));
485
486 /* reset the tx comp ring contents to 0 and reset comp ring states */
487 memset(tq->comp_ring.base, 0, tq->comp_ring.size *
488 sizeof(struct Vmxnet3_TxCompDesc));
489 tq->comp_ring.next2proc = 0;
490 tq->comp_ring.gen = VMXNET3_INIT_GEN;
491
492 /* reset the bookkeeping data */
493 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
494 for (i = 0; i < tq->tx_ring.size; i++)
495 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
496
497 /* stats are not reset */
498}
499
500
501static int
502vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
503 struct vmxnet3_adapter *adapter)
504{
505 BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
506 tq->comp_ring.base || tq->buf_info);
507
508 tq->tx_ring.base = pci_alloc_consistent(adapter->pdev, tq->tx_ring.size
509 * sizeof(struct Vmxnet3_TxDesc),
510 &tq->tx_ring.basePA);
511 if (!tq->tx_ring.base) {
512 printk(KERN_ERR "%s: failed to allocate tx ring\n",
513 adapter->netdev->name);
514 goto err;
515 }
516
517 tq->data_ring.base = pci_alloc_consistent(adapter->pdev,
518 tq->data_ring.size *
519 sizeof(struct Vmxnet3_TxDataDesc),
520 &tq->data_ring.basePA);
521 if (!tq->data_ring.base) {
522 printk(KERN_ERR "%s: failed to allocate data ring\n",
523 adapter->netdev->name);
524 goto err;
525 }
526
527 tq->comp_ring.base = pci_alloc_consistent(adapter->pdev,
528 tq->comp_ring.size *
529 sizeof(struct Vmxnet3_TxCompDesc),
530 &tq->comp_ring.basePA);
531 if (!tq->comp_ring.base) {
532 printk(KERN_ERR "%s: failed to allocate tx comp ring\n",
533 adapter->netdev->name);
534 goto err;
535 }
536
537 tq->buf_info = kcalloc(tq->tx_ring.size, sizeof(tq->buf_info[0]),
538 GFP_KERNEL);
539 if (!tq->buf_info) {
540 printk(KERN_ERR "%s: failed to allocate tx bufinfo\n",
541 adapter->netdev->name);
542 goto err;
543 }
544
545 return 0;
546
547err:
548 vmxnet3_tq_destroy(tq, adapter);
549 return -ENOMEM;
550}
551
552static void
553vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
554{
555 int i;
556
557 for (i = 0; i < adapter->num_tx_queues; i++)
558 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
559}
560
561/*
562 * starting from ring->next2fill, allocate rx buffers for the given ring
563 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
564 * are allocated or allocation fails
565 */
566
567static int
568vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
569 int num_to_alloc, struct vmxnet3_adapter *adapter)
570{
571 int num_allocated = 0;
572 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
573 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
574 u32 val;
575
576 while (num_allocated <= num_to_alloc) {
577 struct vmxnet3_rx_buf_info *rbi;
578 union Vmxnet3_GenericDesc *gd;
579
580 rbi = rbi_base + ring->next2fill;
581 gd = ring->base + ring->next2fill;
582
583 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
584 if (rbi->skb == NULL) {
585 rbi->skb = dev_alloc_skb(rbi->len +
586 NET_IP_ALIGN);
587 if (unlikely(rbi->skb == NULL)) {
588 rq->stats.rx_buf_alloc_failure++;
589 break;
590 }
591 rbi->skb->dev = adapter->netdev;
592
593 skb_reserve(rbi->skb, NET_IP_ALIGN);
594 rbi->dma_addr = pci_map_single(adapter->pdev,
595 rbi->skb->data, rbi->len,
596 PCI_DMA_FROMDEVICE);
597 } else {
598 /* rx buffer skipped by the device */
599 }
600 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
601 } else {
602 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
603 rbi->len != PAGE_SIZE);
604
605 if (rbi->page == NULL) {
606 rbi->page = alloc_page(GFP_ATOMIC);
607 if (unlikely(rbi->page == NULL)) {
608 rq->stats.rx_buf_alloc_failure++;
609 break;
610 }
611 rbi->dma_addr = pci_map_page(adapter->pdev,
612 rbi->page, 0, PAGE_SIZE,
613 PCI_DMA_FROMDEVICE);
614 } else {
615 /* rx buffers skipped by the device */
616 }
617 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
618 }
619
620 BUG_ON(rbi->dma_addr == 0);
621 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
622 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
623 | val | rbi->len);
624
625 /* Fill the last buffer but dont mark it ready, or else the
626 * device will think that the queue is full */
627 if (num_allocated == num_to_alloc)
628 break;
629
630 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
631 num_allocated++;
632 vmxnet3_cmd_ring_adv_next2fill(ring);
633 }
634 rq->uncommitted[ring_idx] += num_allocated;
635
636 dev_dbg(&adapter->netdev->dev,
637 "alloc_rx_buf: %d allocated, next2fill %u, next2comp "
638 "%u, uncommited %u\n", num_allocated, ring->next2fill,
639 ring->next2comp, rq->uncommitted[ring_idx]);
640
641 /* so that the device can distinguish a full ring and an empty ring */
642 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
643
644 return num_allocated;
645}
646
647
648static void
649vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
650 struct vmxnet3_rx_buf_info *rbi)
651{
652 struct skb_frag_struct *frag = skb_shinfo(skb)->frags +
653 skb_shinfo(skb)->nr_frags;
654
655 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
656
657 frag->page = rbi->page;
658 frag->page_offset = 0;
659 frag->size = rcd->len;
660 skb->data_len += frag->size;
661 skb_shinfo(skb)->nr_frags++;
662}
663
664
665static void
666vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
667 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
668 struct vmxnet3_adapter *adapter)
669{
670 u32 dw2, len;
671 unsigned long buf_offset;
672 int i;
673 union Vmxnet3_GenericDesc *gdesc;
674 struct vmxnet3_tx_buf_info *tbi = NULL;
675
676 BUG_ON(ctx->copy_size > skb_headlen(skb));
677
678 /* use the previous gen bit for the SOP desc */
679 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
680
681 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
682 gdesc = ctx->sop_txd; /* both loops below can be skipped */
683
684 /* no need to map the buffer if headers are copied */
685 if (ctx->copy_size) {
686 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
687 tq->tx_ring.next2fill *
688 sizeof(struct Vmxnet3_TxDataDesc));
689 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
690 ctx->sop_txd->dword[3] = 0;
691
692 tbi = tq->buf_info + tq->tx_ring.next2fill;
693 tbi->map_type = VMXNET3_MAP_NONE;
694
695 dev_dbg(&adapter->netdev->dev,
696 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
697 tq->tx_ring.next2fill,
698 le64_to_cpu(ctx->sop_txd->txd.addr),
699 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
700 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
701
702 /* use the right gen for non-SOP desc */
703 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
704 }
705
706 /* linear part can use multiple tx desc if it's big */
707 len = skb_headlen(skb) - ctx->copy_size;
708 buf_offset = ctx->copy_size;
709 while (len) {
710 u32 buf_size;
711
712 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
713 buf_size = len;
714 dw2 |= len;
715 } else {
716 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
717 /* spec says that for TxDesc.len, 0 == 2^14 */
718 }
719
720 tbi = tq->buf_info + tq->tx_ring.next2fill;
721 tbi->map_type = VMXNET3_MAP_SINGLE;
722 tbi->dma_addr = pci_map_single(adapter->pdev,
723 skb->data + buf_offset, buf_size,
724 PCI_DMA_TODEVICE);
725
726 tbi->len = buf_size;
727
728 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
729 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
730
731 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
732 gdesc->dword[2] = cpu_to_le32(dw2);
733 gdesc->dword[3] = 0;
734
735 dev_dbg(&adapter->netdev->dev,
736 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
737 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
738 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
739 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
740 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
741
742 len -= buf_size;
743 buf_offset += buf_size;
744 }
745
746 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
747 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
748
749 tbi = tq->buf_info + tq->tx_ring.next2fill;
750 tbi->map_type = VMXNET3_MAP_PAGE;
751 tbi->dma_addr = pci_map_page(adapter->pdev, frag->page,
752 frag->page_offset, frag->size,
753 PCI_DMA_TODEVICE);
754
755 tbi->len = frag->size;
756
757 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
758 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
759
760 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
761 gdesc->dword[2] = cpu_to_le32(dw2 | frag->size);
762 gdesc->dword[3] = 0;
763
764 dev_dbg(&adapter->netdev->dev,
765 "txd[%u]: 0x%llu %u %u\n",
766 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
767 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
768 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
769 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
770 }
771
772 ctx->eop_txd = gdesc;
773
774 /* set the last buf_info for the pkt */
775 tbi->skb = skb;
776 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
777}
778
779
780/* Init all tx queues */
781static void
782vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
783{
784 int i;
785
786 for (i = 0; i < adapter->num_tx_queues; i++)
787 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
788}
789
790
791/*
792 * parse and copy relevant protocol headers:
793 * For a tso pkt, relevant headers are L2/3/4 including options
794 * For a pkt requesting csum offloading, they are L2/3 and may include L4
795 * if it's a TCP/UDP pkt
796 *
797 * Returns:
798 * -1: error happens during parsing
799 * 0: protocol headers parsed, but too big to be copied
800 * 1: protocol headers parsed and copied
801 *
802 * Other effects:
803 * 1. related *ctx fields are updated.
804 * 2. ctx->copy_size is # of bytes copied
805 * 3. the portion copied is guaranteed to be in the linear part
806 *
807 */
808static int
809vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
810 struct vmxnet3_tx_ctx *ctx,
811 struct vmxnet3_adapter *adapter)
812{
813 struct Vmxnet3_TxDataDesc *tdd;
814
815 if (ctx->mss) { /* TSO */
816 ctx->eth_ip_hdr_size = skb_transport_offset(skb);
817 ctx->l4_hdr_size = ((struct tcphdr *)
818 skb_transport_header(skb))->doff * 4;
819 ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size;
820 } else {
821 if (skb->ip_summed == CHECKSUM_PARTIAL) {
822 ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb);
823
824 if (ctx->ipv4) {
825 struct iphdr *iph = (struct iphdr *)
826 skb_network_header(skb);
827 if (iph->protocol == IPPROTO_TCP)
828 ctx->l4_hdr_size = ((struct tcphdr *)
829 skb_transport_header(skb))->doff * 4;
830 else if (iph->protocol == IPPROTO_UDP)
831 /*
832 * Use tcp header size so that bytes to
833 * be copied are more than required by
834 * the device.
835 */
836 ctx->l4_hdr_size =
837 sizeof(struct tcphdr);
838 else
839 ctx->l4_hdr_size = 0;
840 } else {
841 /* for simplicity, don't copy L4 headers */
842 ctx->l4_hdr_size = 0;
843 }
844 ctx->copy_size = ctx->eth_ip_hdr_size +
845 ctx->l4_hdr_size;
846 } else {
847 ctx->eth_ip_hdr_size = 0;
848 ctx->l4_hdr_size = 0;
849 /* copy as much as allowed */
850 ctx->copy_size = min((unsigned int)VMXNET3_HDR_COPY_SIZE
851 , skb_headlen(skb));
852 }
853
854 /* make sure headers are accessible directly */
855 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
856 goto err;
857 }
858
859 if (unlikely(ctx->copy_size > VMXNET3_HDR_COPY_SIZE)) {
860 tq->stats.oversized_hdr++;
861 ctx->copy_size = 0;
862 return 0;
863 }
864
865 tdd = tq->data_ring.base + tq->tx_ring.next2fill;
866
867 memcpy(tdd->data, skb->data, ctx->copy_size);
868 dev_dbg(&adapter->netdev->dev,
869 "copy %u bytes to dataRing[%u]\n",
870 ctx->copy_size, tq->tx_ring.next2fill);
871 return 1;
872
873err:
874 return -1;
875}
876
877
878static void
879vmxnet3_prepare_tso(struct sk_buff *skb,
880 struct vmxnet3_tx_ctx *ctx)
881{
882 struct tcphdr *tcph = (struct tcphdr *)skb_transport_header(skb);
883 if (ctx->ipv4) {
884 struct iphdr *iph = (struct iphdr *)skb_network_header(skb);
885 iph->check = 0;
886 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
887 IPPROTO_TCP, 0);
888 } else {
889 struct ipv6hdr *iph = (struct ipv6hdr *)skb_network_header(skb);
890 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
891 IPPROTO_TCP, 0);
892 }
893}
894
895
896/*
897 * Transmits a pkt thru a given tq
898 * Returns:
899 * NETDEV_TX_OK: descriptors are setup successfully
900 * NETDEV_TX_OK: error occurred, the pkt is dropped
901 * NETDEV_TX_BUSY: tx ring is full, queue is stopped
902 *
903 * Side-effects:
904 * 1. tx ring may be changed
905 * 2. tq stats may be updated accordingly
906 * 3. shared->txNumDeferred may be updated
907 */
908
909static int
910vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
911 struct vmxnet3_adapter *adapter, struct net_device *netdev)
912{
913 int ret;
914 u32 count;
915 unsigned long flags;
916 struct vmxnet3_tx_ctx ctx;
917 union Vmxnet3_GenericDesc *gdesc;
918#ifdef __BIG_ENDIAN_BITFIELD
919 /* Use temporary descriptor to avoid touching bits multiple times */
920 union Vmxnet3_GenericDesc tempTxDesc;
921#endif
922
923 /* conservatively estimate # of descriptors to use */
924 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) +
925 skb_shinfo(skb)->nr_frags + 1;
926
927 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
928
929 ctx.mss = skb_shinfo(skb)->gso_size;
930 if (ctx.mss) {
931 if (skb_header_cloned(skb)) {
932 if (unlikely(pskb_expand_head(skb, 0, 0,
933 GFP_ATOMIC) != 0)) {
934 tq->stats.drop_tso++;
935 goto drop_pkt;
936 }
937 tq->stats.copy_skb_header++;
938 }
939 vmxnet3_prepare_tso(skb, &ctx);
940 } else {
941 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
942
943 /* non-tso pkts must not use more than
944 * VMXNET3_MAX_TXD_PER_PKT entries
945 */
946 if (skb_linearize(skb) != 0) {
947 tq->stats.drop_too_many_frags++;
948 goto drop_pkt;
949 }
950 tq->stats.linearized++;
951
952 /* recalculate the # of descriptors to use */
953 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
954 }
955 }
956
957 spin_lock_irqsave(&tq->tx_lock, flags);
958
959 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
960 tq->stats.tx_ring_full++;
961 dev_dbg(&adapter->netdev->dev,
962 "tx queue stopped on %s, next2comp %u"
963 " next2fill %u\n", adapter->netdev->name,
964 tq->tx_ring.next2comp, tq->tx_ring.next2fill);
965
966 vmxnet3_tq_stop(tq, adapter);
967 spin_unlock_irqrestore(&tq->tx_lock, flags);
968 return NETDEV_TX_BUSY;
969 }
970
971
972 ret = vmxnet3_parse_and_copy_hdr(skb, tq, &ctx, adapter);
973 if (ret >= 0) {
974 BUG_ON(ret <= 0 && ctx.copy_size != 0);
975 /* hdrs parsed, check against other limits */
976 if (ctx.mss) {
977 if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size >
978 VMXNET3_MAX_TX_BUF_SIZE)) {
979 goto hdr_too_big;
980 }
981 } else {
982 if (skb->ip_summed == CHECKSUM_PARTIAL) {
983 if (unlikely(ctx.eth_ip_hdr_size +
984 skb->csum_offset >
985 VMXNET3_MAX_CSUM_OFFSET)) {
986 goto hdr_too_big;
987 }
988 }
989 }
990 } else {
991 tq->stats.drop_hdr_inspect_err++;
992 goto unlock_drop_pkt;
993 }
994
995 /* fill tx descs related to addr & len */
996 vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter);
997
998 /* setup the EOP desc */
999 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
1000
1001 /* setup the SOP desc */
1002#ifdef __BIG_ENDIAN_BITFIELD
1003 gdesc = &tempTxDesc;
1004 gdesc->dword[2] = ctx.sop_txd->dword[2];
1005 gdesc->dword[3] = ctx.sop_txd->dword[3];
1006#else
1007 gdesc = ctx.sop_txd;
1008#endif
1009 if (ctx.mss) {
1010 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size;
1011 gdesc->txd.om = VMXNET3_OM_TSO;
1012 gdesc->txd.msscof = ctx.mss;
1013 le32_add_cpu(&tq->shared->txNumDeferred, (skb->len -
1014 gdesc->txd.hlen + ctx.mss - 1) / ctx.mss);
1015 } else {
1016 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1017 gdesc->txd.hlen = ctx.eth_ip_hdr_size;
1018 gdesc->txd.om = VMXNET3_OM_CSUM;
1019 gdesc->txd.msscof = ctx.eth_ip_hdr_size +
1020 skb->csum_offset;
1021 } else {
1022 gdesc->txd.om = 0;
1023 gdesc->txd.msscof = 0;
1024 }
1025 le32_add_cpu(&tq->shared->txNumDeferred, 1);
1026 }
1027
1028 if (vlan_tx_tag_present(skb)) {
1029 gdesc->txd.ti = 1;
1030 gdesc->txd.tci = vlan_tx_tag_get(skb);
1031 }
1032
1033 /* finally flips the GEN bit of the SOP desc. */
1034 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1035 VMXNET3_TXD_GEN);
1036#ifdef __BIG_ENDIAN_BITFIELD
1037 /* Finished updating in bitfields of Tx Desc, so write them in original
1038 * place.
1039 */
1040 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1041 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1042 gdesc = ctx.sop_txd;
1043#endif
1044 dev_dbg(&adapter->netdev->dev,
1045 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
1046 (u32)((union Vmxnet3_GenericDesc *)ctx.sop_txd -
1047 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1048 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
1049
1050 spin_unlock_irqrestore(&tq->tx_lock, flags);
1051
1052 if (le32_to_cpu(tq->shared->txNumDeferred) >=
1053 le32_to_cpu(tq->shared->txThreshold)) {
1054 tq->shared->txNumDeferred = 0;
1055 VMXNET3_WRITE_BAR0_REG(adapter,
1056 VMXNET3_REG_TXPROD + tq->qid * 8,
1057 tq->tx_ring.next2fill);
1058 }
1059
1060 return NETDEV_TX_OK;
1061
1062hdr_too_big:
1063 tq->stats.drop_oversized_hdr++;
1064unlock_drop_pkt:
1065 spin_unlock_irqrestore(&tq->tx_lock, flags);
1066drop_pkt:
1067 tq->stats.drop_total++;
1068 dev_kfree_skb(skb);
1069 return NETDEV_TX_OK;
1070}
1071
1072
1073static netdev_tx_t
1074vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1075{
1076 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1077
1078 BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1079 return vmxnet3_tq_xmit(skb,
1080 &adapter->tx_queue[skb->queue_mapping],
1081 adapter, netdev);
1082}
1083
1084
1085static void
1086vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1087 struct sk_buff *skb,
1088 union Vmxnet3_GenericDesc *gdesc)
1089{
1090 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
1091 /* typical case: TCP/UDP over IP and both csums are correct */
1092 if ((le32_to_cpu(gdesc->dword[3]) & VMXNET3_RCD_CSUM_OK) ==
1093 VMXNET3_RCD_CSUM_OK) {
1094 skb->ip_summed = CHECKSUM_UNNECESSARY;
1095 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
1096 BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6));
1097 BUG_ON(gdesc->rcd.frg);
1098 } else {
1099 if (gdesc->rcd.csum) {
1100 skb->csum = htons(gdesc->rcd.csum);
1101 skb->ip_summed = CHECKSUM_PARTIAL;
1102 } else {
1103 skb_checksum_none_assert(skb);
1104 }
1105 }
1106 } else {
1107 skb_checksum_none_assert(skb);
1108 }
1109}
1110
1111
1112static void
1113vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1114 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
1115{
1116 rq->stats.drop_err++;
1117 if (!rcd->fcs)
1118 rq->stats.drop_fcs++;
1119
1120 rq->stats.drop_total++;
1121
1122 /*
1123 * We do not unmap and chain the rx buffer to the skb.
1124 * We basically pretend this buffer is not used and will be recycled
1125 * by vmxnet3_rq_alloc_rx_buf()
1126 */
1127
1128 /*
1129 * ctx->skb may be NULL if this is the first and the only one
1130 * desc for the pkt
1131 */
1132 if (ctx->skb)
1133 dev_kfree_skb_irq(ctx->skb);
1134
1135 ctx->skb = NULL;
1136}
1137
1138
1139static int
1140vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1141 struct vmxnet3_adapter *adapter, int quota)
1142{
1143 static const u32 rxprod_reg[2] = {
1144 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
1145 };
1146 u32 num_rxd = 0;
1147 bool skip_page_frags = false;
1148 struct Vmxnet3_RxCompDesc *rcd;
1149 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
1150#ifdef __BIG_ENDIAN_BITFIELD
1151 struct Vmxnet3_RxDesc rxCmdDesc;
1152 struct Vmxnet3_RxCompDesc rxComp;
1153#endif
1154 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1155 &rxComp);
1156 while (rcd->gen == rq->comp_ring.gen) {
1157 struct vmxnet3_rx_buf_info *rbi;
1158 struct sk_buff *skb, *new_skb = NULL;
1159 struct page *new_page = NULL;
1160 int num_to_alloc;
1161 struct Vmxnet3_RxDesc *rxd;
1162 u32 idx, ring_idx;
1163 struct vmxnet3_cmd_ring *ring = NULL;
1164 if (num_rxd >= quota) {
1165 /* we may stop even before we see the EOP desc of
1166 * the current pkt
1167 */
1168 break;
1169 }
1170 num_rxd++;
1171 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2);
1172 idx = rcd->rxdIdx;
1173 ring_idx = rcd->rqID < adapter->num_rx_queues ? 0 : 1;
1174 ring = rq->rx_ring + ring_idx;
1175 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1176 &rxCmdDesc);
1177 rbi = rq->buf_info[ring_idx] + idx;
1178
1179 BUG_ON(rxd->addr != rbi->dma_addr ||
1180 rxd->len != rbi->len);
1181
1182 if (unlikely(rcd->eop && rcd->err)) {
1183 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1184 goto rcd_done;
1185 }
1186
1187 if (rcd->sop) { /* first buf of the pkt */
1188 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
1189 rcd->rqID != rq->qid);
1190
1191 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
1192 BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1193
1194 if (unlikely(rcd->len == 0)) {
1195 /* Pretend the rx buffer is skipped. */
1196 BUG_ON(!(rcd->sop && rcd->eop));
1197 dev_dbg(&adapter->netdev->dev,
1198 "rxRing[%u][%u] 0 length\n",
1199 ring_idx, idx);
1200 goto rcd_done;
1201 }
1202
1203 skip_page_frags = false;
1204 ctx->skb = rbi->skb;
1205 new_skb = dev_alloc_skb(rbi->len + NET_IP_ALIGN);
1206 if (new_skb == NULL) {
1207 /* Skb allocation failed, do not handover this
1208 * skb to stack. Reuse it. Drop the existing pkt
1209 */
1210 rq->stats.rx_buf_alloc_failure++;
1211 ctx->skb = NULL;
1212 rq->stats.drop_total++;
1213 skip_page_frags = true;
1214 goto rcd_done;
1215 }
1216
1217 pci_unmap_single(adapter->pdev, rbi->dma_addr, rbi->len,
1218 PCI_DMA_FROMDEVICE);
1219
1220 skb_put(ctx->skb, rcd->len);
1221
1222 /* Immediate refill */
1223 new_skb->dev = adapter->netdev;
1224 skb_reserve(new_skb, NET_IP_ALIGN);
1225 rbi->skb = new_skb;
1226 rbi->dma_addr = pci_map_single(adapter->pdev,
1227 rbi->skb->data, rbi->len,
1228 PCI_DMA_FROMDEVICE);
1229 rxd->addr = cpu_to_le64(rbi->dma_addr);
1230 rxd->len = rbi->len;
1231
1232 } else {
1233 BUG_ON(ctx->skb == NULL && !skip_page_frags);
1234
1235 /* non SOP buffer must be type 1 in most cases */
1236 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
1237 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
1238
1239 /* If an sop buffer was dropped, skip all
1240 * following non-sop fragments. They will be reused.
1241 */
1242 if (skip_page_frags)
1243 goto rcd_done;
1244
1245 new_page = alloc_page(GFP_ATOMIC);
1246 if (unlikely(new_page == NULL)) {
1247 /* Replacement page frag could not be allocated.
1248 * Reuse this page. Drop the pkt and free the
1249 * skb which contained this page as a frag. Skip
1250 * processing all the following non-sop frags.
1251 */
1252 rq->stats.rx_buf_alloc_failure++;
1253 dev_kfree_skb(ctx->skb);
1254 ctx->skb = NULL;
1255 skip_page_frags = true;
1256 goto rcd_done;
1257 }
1258
1259 if (rcd->len) {
1260 pci_unmap_page(adapter->pdev,
1261 rbi->dma_addr, rbi->len,
1262 PCI_DMA_FROMDEVICE);
1263
1264 vmxnet3_append_frag(ctx->skb, rcd, rbi);
1265 }
1266
1267 /* Immediate refill */
1268 rbi->page = new_page;
1269 rbi->dma_addr = pci_map_page(adapter->pdev, rbi->page,
1270 0, PAGE_SIZE,
1271 PCI_DMA_FROMDEVICE);
1272 rxd->addr = cpu_to_le64(rbi->dma_addr);
1273 rxd->len = rbi->len;
1274 }
1275
1276
1277 skb = ctx->skb;
1278 if (rcd->eop) {
1279 skb->len += skb->data_len;
1280 skb->truesize += skb->data_len;
1281
1282 vmxnet3_rx_csum(adapter, skb,
1283 (union Vmxnet3_GenericDesc *)rcd);
1284 skb->protocol = eth_type_trans(skb, adapter->netdev);
1285
1286 if (unlikely(rcd->ts))
1287 __vlan_hwaccel_put_tag(skb, rcd->tci);
1288
1289 if (adapter->netdev->features & NETIF_F_LRO)
1290 netif_receive_skb(skb);
1291 else
1292 napi_gro_receive(&rq->napi, skb);
1293
1294 ctx->skb = NULL;
1295 }
1296
1297rcd_done:
1298 /* device may have skipped some rx descs */
1299 ring->next2comp = idx;
1300 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
1301 ring = rq->rx_ring + ring_idx;
1302 while (num_to_alloc) {
1303 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
1304 &rxCmdDesc);
1305 BUG_ON(!rxd->addr);
1306
1307 /* Recv desc is ready to be used by the device */
1308 rxd->gen = ring->gen;
1309 vmxnet3_cmd_ring_adv_next2fill(ring);
1310 num_to_alloc--;
1311 }
1312
1313 /* if needed, update the register */
1314 if (unlikely(rq->shared->updateRxProd)) {
1315 VMXNET3_WRITE_BAR0_REG(adapter,
1316 rxprod_reg[ring_idx] + rq->qid * 8,
1317 ring->next2fill);
1318 rq->uncommitted[ring_idx] = 0;
1319 }
1320
1321 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
1322 vmxnet3_getRxComp(rcd,
1323 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
1324 }
1325
1326 return num_rxd;
1327}
1328
1329
1330static void
1331vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1332 struct vmxnet3_adapter *adapter)
1333{
1334 u32 i, ring_idx;
1335 struct Vmxnet3_RxDesc *rxd;
1336
1337 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1338 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
1339#ifdef __BIG_ENDIAN_BITFIELD
1340 struct Vmxnet3_RxDesc rxDesc;
1341#endif
1342 vmxnet3_getRxDesc(rxd,
1343 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
1344
1345 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1346 rq->buf_info[ring_idx][i].skb) {
1347 pci_unmap_single(adapter->pdev, rxd->addr,
1348 rxd->len, PCI_DMA_FROMDEVICE);
1349 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1350 rq->buf_info[ring_idx][i].skb = NULL;
1351 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1352 rq->buf_info[ring_idx][i].page) {
1353 pci_unmap_page(adapter->pdev, rxd->addr,
1354 rxd->len, PCI_DMA_FROMDEVICE);
1355 put_page(rq->buf_info[ring_idx][i].page);
1356 rq->buf_info[ring_idx][i].page = NULL;
1357 }
1358 }
1359
1360 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1361 rq->rx_ring[ring_idx].next2fill =
1362 rq->rx_ring[ring_idx].next2comp = 0;
1363 rq->uncommitted[ring_idx] = 0;
1364 }
1365
1366 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1367 rq->comp_ring.next2proc = 0;
1368}
1369
1370
1371static void
1372vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1373{
1374 int i;
1375
1376 for (i = 0; i < adapter->num_rx_queues; i++)
1377 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1378}
1379
1380
1381void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1382 struct vmxnet3_adapter *adapter)
1383{
1384 int i;
1385 int j;
1386
1387 /* all rx buffers must have already been freed */
1388 for (i = 0; i < 2; i++) {
1389 if (rq->buf_info[i]) {
1390 for (j = 0; j < rq->rx_ring[i].size; j++)
1391 BUG_ON(rq->buf_info[i][j].page != NULL);
1392 }
1393 }
1394
1395
1396 kfree(rq->buf_info[0]);
1397
1398 for (i = 0; i < 2; i++) {
1399 if (rq->rx_ring[i].base) {
1400 pci_free_consistent(adapter->pdev, rq->rx_ring[i].size
1401 * sizeof(struct Vmxnet3_RxDesc),
1402 rq->rx_ring[i].base,
1403 rq->rx_ring[i].basePA);
1404 rq->rx_ring[i].base = NULL;
1405 }
1406 rq->buf_info[i] = NULL;
1407 }
1408
1409 if (rq->comp_ring.base) {
1410 pci_free_consistent(adapter->pdev, rq->comp_ring.size *
1411 sizeof(struct Vmxnet3_RxCompDesc),
1412 rq->comp_ring.base, rq->comp_ring.basePA);
1413 rq->comp_ring.base = NULL;
1414 }
1415}
1416
1417
1418static int
1419vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
1420 struct vmxnet3_adapter *adapter)
1421{
1422 int i;
1423
1424 /* initialize buf_info */
1425 for (i = 0; i < rq->rx_ring[0].size; i++) {
1426
1427 /* 1st buf for a pkt is skbuff */
1428 if (i % adapter->rx_buf_per_pkt == 0) {
1429 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
1430 rq->buf_info[0][i].len = adapter->skb_buf_size;
1431 } else { /* subsequent bufs for a pkt is frag */
1432 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
1433 rq->buf_info[0][i].len = PAGE_SIZE;
1434 }
1435 }
1436 for (i = 0; i < rq->rx_ring[1].size; i++) {
1437 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
1438 rq->buf_info[1][i].len = PAGE_SIZE;
1439 }
1440
1441 /* reset internal state and allocate buffers for both rings */
1442 for (i = 0; i < 2; i++) {
1443 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
1444 rq->uncommitted[i] = 0;
1445
1446 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
1447 sizeof(struct Vmxnet3_RxDesc));
1448 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
1449 }
1450 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
1451 adapter) == 0) {
1452 /* at least has 1 rx buffer for the 1st ring */
1453 return -ENOMEM;
1454 }
1455 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
1456
1457 /* reset the comp ring */
1458 rq->comp_ring.next2proc = 0;
1459 memset(rq->comp_ring.base, 0, rq->comp_ring.size *
1460 sizeof(struct Vmxnet3_RxCompDesc));
1461 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1462
1463 /* reset rxctx */
1464 rq->rx_ctx.skb = NULL;
1465
1466 /* stats are not reset */
1467 return 0;
1468}
1469
1470
1471static int
1472vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
1473{
1474 int i, err = 0;
1475
1476 for (i = 0; i < adapter->num_rx_queues; i++) {
1477 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
1478 if (unlikely(err)) {
1479 dev_err(&adapter->netdev->dev, "%s: failed to "
1480 "initialize rx queue%i\n",
1481 adapter->netdev->name, i);
1482 break;
1483 }
1484 }
1485 return err;
1486
1487}
1488
1489
1490static int
1491vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
1492{
1493 int i;
1494 size_t sz;
1495 struct vmxnet3_rx_buf_info *bi;
1496
1497 for (i = 0; i < 2; i++) {
1498
1499 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
1500 rq->rx_ring[i].base = pci_alloc_consistent(adapter->pdev, sz,
1501 &rq->rx_ring[i].basePA);
1502 if (!rq->rx_ring[i].base) {
1503 printk(KERN_ERR "%s: failed to allocate rx ring %d\n",
1504 adapter->netdev->name, i);
1505 goto err;
1506 }
1507 }
1508
1509 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
1510 rq->comp_ring.base = pci_alloc_consistent(adapter->pdev, sz,
1511 &rq->comp_ring.basePA);
1512 if (!rq->comp_ring.base) {
1513 printk(KERN_ERR "%s: failed to allocate rx comp ring\n",
1514 adapter->netdev->name);
1515 goto err;
1516 }
1517
1518 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
1519 rq->rx_ring[1].size);
1520 bi = kzalloc(sz, GFP_KERNEL);
1521 if (!bi) {
1522 printk(KERN_ERR "%s: failed to allocate rx bufinfo\n",
1523 adapter->netdev->name);
1524 goto err;
1525 }
1526 rq->buf_info[0] = bi;
1527 rq->buf_info[1] = bi + rq->rx_ring[0].size;
1528
1529 return 0;
1530
1531err:
1532 vmxnet3_rq_destroy(rq, adapter);
1533 return -ENOMEM;
1534}
1535
1536
1537static int
1538vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
1539{
1540 int i, err = 0;
1541
1542 for (i = 0; i < adapter->num_rx_queues; i++) {
1543 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
1544 if (unlikely(err)) {
1545 dev_err(&adapter->netdev->dev,
1546 "%s: failed to create rx queue%i\n",
1547 adapter->netdev->name, i);
1548 goto err_out;
1549 }
1550 }
1551 return err;
1552err_out:
1553 vmxnet3_rq_destroy_all(adapter);
1554 return err;
1555
1556}
1557
1558/* Multiple queue aware polling function for tx and rx */
1559
1560static int
1561vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
1562{
1563 int rcd_done = 0, i;
1564 if (unlikely(adapter->shared->ecr))
1565 vmxnet3_process_events(adapter);
1566 for (i = 0; i < adapter->num_tx_queues; i++)
1567 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
1568
1569 for (i = 0; i < adapter->num_rx_queues; i++)
1570 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
1571 adapter, budget);
1572 return rcd_done;
1573}
1574
1575
1576static int
1577vmxnet3_poll(struct napi_struct *napi, int budget)
1578{
1579 struct vmxnet3_rx_queue *rx_queue = container_of(napi,
1580 struct vmxnet3_rx_queue, napi);
1581 int rxd_done;
1582
1583 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
1584
1585 if (rxd_done < budget) {
1586 napi_complete(napi);
1587 vmxnet3_enable_all_intrs(rx_queue->adapter);
1588 }
1589 return rxd_done;
1590}
1591
1592/*
1593 * NAPI polling function for MSI-X mode with multiple Rx queues
1594 * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
1595 */
1596
1597static int
1598vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
1599{
1600 struct vmxnet3_rx_queue *rq = container_of(napi,
1601 struct vmxnet3_rx_queue, napi);
1602 struct vmxnet3_adapter *adapter = rq->adapter;
1603 int rxd_done;
1604
1605 /* When sharing interrupt with corresponding tx queue, process
1606 * tx completions in that queue as well
1607 */
1608 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
1609 struct vmxnet3_tx_queue *tq =
1610 &adapter->tx_queue[rq - adapter->rx_queue];
1611 vmxnet3_tq_tx_complete(tq, adapter);
1612 }
1613
1614 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
1615
1616 if (rxd_done < budget) {
1617 napi_complete(napi);
1618 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
1619 }
1620 return rxd_done;
1621}
1622
1623
1624#ifdef CONFIG_PCI_MSI
1625
1626/*
1627 * Handle completion interrupts on tx queues
1628 * Returns whether or not the intr is handled
1629 */
1630
1631static irqreturn_t
1632vmxnet3_msix_tx(int irq, void *data)
1633{
1634 struct vmxnet3_tx_queue *tq = data;
1635 struct vmxnet3_adapter *adapter = tq->adapter;
1636
1637 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1638 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
1639
1640 /* Handle the case where only one irq is allocate for all tx queues */
1641 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1642 int i;
1643 for (i = 0; i < adapter->num_tx_queues; i++) {
1644 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
1645 vmxnet3_tq_tx_complete(txq, adapter);
1646 }
1647 } else {
1648 vmxnet3_tq_tx_complete(tq, adapter);
1649 }
1650 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
1651
1652 return IRQ_HANDLED;
1653}
1654
1655
1656/*
1657 * Handle completion interrupts on rx queues. Returns whether or not the
1658 * intr is handled
1659 */
1660
1661static irqreturn_t
1662vmxnet3_msix_rx(int irq, void *data)
1663{
1664 struct vmxnet3_rx_queue *rq = data;
1665 struct vmxnet3_adapter *adapter = rq->adapter;
1666
1667 /* disable intr if needed */
1668 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1669 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
1670 napi_schedule(&rq->napi);
1671
1672 return IRQ_HANDLED;
1673}
1674
1675/*
1676 *----------------------------------------------------------------------------
1677 *
1678 * vmxnet3_msix_event --
1679 *
1680 * vmxnet3 msix event intr handler
1681 *
1682 * Result:
1683 * whether or not the intr is handled
1684 *
1685 *----------------------------------------------------------------------------
1686 */
1687
1688static irqreturn_t
1689vmxnet3_msix_event(int irq, void *data)
1690{
1691 struct net_device *dev = data;
1692 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1693
1694 /* disable intr if needed */
1695 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1696 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
1697
1698 if (adapter->shared->ecr)
1699 vmxnet3_process_events(adapter);
1700
1701 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
1702
1703 return IRQ_HANDLED;
1704}
1705
1706#endif /* CONFIG_PCI_MSI */
1707
1708
1709/* Interrupt handler for vmxnet3 */
1710static irqreturn_t
1711vmxnet3_intr(int irq, void *dev_id)
1712{
1713 struct net_device *dev = dev_id;
1714 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1715
1716 if (adapter->intr.type == VMXNET3_IT_INTX) {
1717 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
1718 if (unlikely(icr == 0))
1719 /* not ours */
1720 return IRQ_NONE;
1721 }
1722
1723
1724 /* disable intr if needed */
1725 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1726 vmxnet3_disable_all_intrs(adapter);
1727
1728 napi_schedule(&adapter->rx_queue[0].napi);
1729
1730 return IRQ_HANDLED;
1731}
1732
1733#ifdef CONFIG_NET_POLL_CONTROLLER
1734
1735/* netpoll callback. */
1736static void
1737vmxnet3_netpoll(struct net_device *netdev)
1738{
1739 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1740
1741 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1742 vmxnet3_disable_all_intrs(adapter);
1743
1744 vmxnet3_do_poll(adapter, adapter->rx_queue[0].rx_ring[0].size);
1745 vmxnet3_enable_all_intrs(adapter);
1746
1747}
1748#endif /* CONFIG_NET_POLL_CONTROLLER */
1749
1750static int
1751vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
1752{
1753 struct vmxnet3_intr *intr = &adapter->intr;
1754 int err = 0, i;
1755 int vector = 0;
1756
1757#ifdef CONFIG_PCI_MSI
1758 if (adapter->intr.type == VMXNET3_IT_MSIX) {
1759 for (i = 0; i < adapter->num_tx_queues; i++) {
1760 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
1761 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
1762 adapter->netdev->name, vector);
1763 err = request_irq(
1764 intr->msix_entries[vector].vector,
1765 vmxnet3_msix_tx, 0,
1766 adapter->tx_queue[i].name,
1767 &adapter->tx_queue[i]);
1768 } else {
1769 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
1770 adapter->netdev->name, vector);
1771 }
1772 if (err) {
1773 dev_err(&adapter->netdev->dev,
1774 "Failed to request irq for MSIX, %s, "
1775 "error %d\n",
1776 adapter->tx_queue[i].name, err);
1777 return err;
1778 }
1779
1780 /* Handle the case where only 1 MSIx was allocated for
1781 * all tx queues */
1782 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1783 for (; i < adapter->num_tx_queues; i++)
1784 adapter->tx_queue[i].comp_ring.intr_idx
1785 = vector;
1786 vector++;
1787 break;
1788 } else {
1789 adapter->tx_queue[i].comp_ring.intr_idx
1790 = vector++;
1791 }
1792 }
1793 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
1794 vector = 0;
1795
1796 for (i = 0; i < adapter->num_rx_queues; i++) {
1797 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
1798 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
1799 adapter->netdev->name, vector);
1800 else
1801 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
1802 adapter->netdev->name, vector);
1803 err = request_irq(intr->msix_entries[vector].vector,
1804 vmxnet3_msix_rx, 0,
1805 adapter->rx_queue[i].name,
1806 &(adapter->rx_queue[i]));
1807 if (err) {
1808 printk(KERN_ERR "Failed to request irq for MSIX"
1809 ", %s, error %d\n",
1810 adapter->rx_queue[i].name, err);
1811 return err;
1812 }
1813
1814 adapter->rx_queue[i].comp_ring.intr_idx = vector++;
1815 }
1816
1817 sprintf(intr->event_msi_vector_name, "%s-event-%d",
1818 adapter->netdev->name, vector);
1819 err = request_irq(intr->msix_entries[vector].vector,
1820 vmxnet3_msix_event, 0,
1821 intr->event_msi_vector_name, adapter->netdev);
1822 intr->event_intr_idx = vector;
1823
1824 } else if (intr->type == VMXNET3_IT_MSI) {
1825 adapter->num_rx_queues = 1;
1826 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
1827 adapter->netdev->name, adapter->netdev);
1828 } else {
1829#endif
1830 adapter->num_rx_queues = 1;
1831 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
1832 IRQF_SHARED, adapter->netdev->name,
1833 adapter->netdev);
1834#ifdef CONFIG_PCI_MSI
1835 }
1836#endif
1837 intr->num_intrs = vector + 1;
1838 if (err) {
1839 printk(KERN_ERR "Failed to request irq %s (intr type:%d), error"
1840 ":%d\n", adapter->netdev->name, intr->type, err);
1841 } else {
1842 /* Number of rx queues will not change after this */
1843 for (i = 0; i < adapter->num_rx_queues; i++) {
1844 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
1845 rq->qid = i;
1846 rq->qid2 = i + adapter->num_rx_queues;
1847 }
1848
1849
1850
1851 /* init our intr settings */
1852 for (i = 0; i < intr->num_intrs; i++)
1853 intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
1854 if (adapter->intr.type != VMXNET3_IT_MSIX) {
1855 adapter->intr.event_intr_idx = 0;
1856 for (i = 0; i < adapter->num_tx_queues; i++)
1857 adapter->tx_queue[i].comp_ring.intr_idx = 0;
1858 adapter->rx_queue[0].comp_ring.intr_idx = 0;
1859 }
1860
1861 printk(KERN_INFO "%s: intr type %u, mode %u, %u vectors "
1862 "allocated\n", adapter->netdev->name, intr->type,
1863 intr->mask_mode, intr->num_intrs);
1864 }
1865
1866 return err;
1867}
1868
1869
1870static void
1871vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
1872{
1873 struct vmxnet3_intr *intr = &adapter->intr;
1874 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
1875
1876 switch (intr->type) {
1877#ifdef CONFIG_PCI_MSI
1878 case VMXNET3_IT_MSIX:
1879 {
1880 int i, vector = 0;
1881
1882 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
1883 for (i = 0; i < adapter->num_tx_queues; i++) {
1884 free_irq(intr->msix_entries[vector++].vector,
1885 &(adapter->tx_queue[i]));
1886 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
1887 break;
1888 }
1889 }
1890
1891 for (i = 0; i < adapter->num_rx_queues; i++) {
1892 free_irq(intr->msix_entries[vector++].vector,
1893 &(adapter->rx_queue[i]));
1894 }
1895
1896 free_irq(intr->msix_entries[vector].vector,
1897 adapter->netdev);
1898 BUG_ON(vector >= intr->num_intrs);
1899 break;
1900 }
1901#endif
1902 case VMXNET3_IT_MSI:
1903 free_irq(adapter->pdev->irq, adapter->netdev);
1904 break;
1905 case VMXNET3_IT_INTX:
1906 free_irq(adapter->pdev->irq, adapter->netdev);
1907 break;
1908 default:
1909 BUG_ON(true);
1910 }
1911}
1912
1913
1914static void
1915vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
1916{
1917 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1918 u16 vid;
1919
1920 /* allow untagged pkts */
1921 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
1922
1923 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
1924 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
1925}
1926
1927
1928static void
1929vmxnet3_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1930{
1931 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1932
1933 if (!(netdev->flags & IFF_PROMISC)) {
1934 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1935 unsigned long flags;
1936
1937 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
1938 spin_lock_irqsave(&adapter->cmd_lock, flags);
1939 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1940 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1941 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
1942 }
1943
1944 set_bit(vid, adapter->active_vlans);
1945}
1946
1947
1948static void
1949vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1950{
1951 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1952
1953 if (!(netdev->flags & IFF_PROMISC)) {
1954 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1955 unsigned long flags;
1956
1957 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
1958 spin_lock_irqsave(&adapter->cmd_lock, flags);
1959 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1960 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1961 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
1962 }
1963
1964 clear_bit(vid, adapter->active_vlans);
1965}
1966
1967
1968static u8 *
1969vmxnet3_copy_mc(struct net_device *netdev)
1970{
1971 u8 *buf = NULL;
1972 u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
1973
1974 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
1975 if (sz <= 0xffff) {
1976 /* We may be called with BH disabled */
1977 buf = kmalloc(sz, GFP_ATOMIC);
1978 if (buf) {
1979 struct netdev_hw_addr *ha;
1980 int i = 0;
1981
1982 netdev_for_each_mc_addr(ha, netdev)
1983 memcpy(buf + i++ * ETH_ALEN, ha->addr,
1984 ETH_ALEN);
1985 }
1986 }
1987 return buf;
1988}
1989
1990
1991static void
1992vmxnet3_set_mc(struct net_device *netdev)
1993{
1994 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1995 unsigned long flags;
1996 struct Vmxnet3_RxFilterConf *rxConf =
1997 &adapter->shared->devRead.rxFilterConf;
1998 u8 *new_table = NULL;
1999 u32 new_mode = VMXNET3_RXM_UCAST;
2000
2001 if (netdev->flags & IFF_PROMISC) {
2002 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2003 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
2004
2005 new_mode |= VMXNET3_RXM_PROMISC;
2006 } else {
2007 vmxnet3_restore_vlan(adapter);
2008 }
2009
2010 if (netdev->flags & IFF_BROADCAST)
2011 new_mode |= VMXNET3_RXM_BCAST;
2012
2013 if (netdev->flags & IFF_ALLMULTI)
2014 new_mode |= VMXNET3_RXM_ALL_MULTI;
2015 else
2016 if (!netdev_mc_empty(netdev)) {
2017 new_table = vmxnet3_copy_mc(netdev);
2018 if (new_table) {
2019 new_mode |= VMXNET3_RXM_MCAST;
2020 rxConf->mfTableLen = cpu_to_le16(
2021 netdev_mc_count(netdev) * ETH_ALEN);
2022 rxConf->mfTablePA = cpu_to_le64(virt_to_phys(
2023 new_table));
2024 } else {
2025 printk(KERN_INFO "%s: failed to copy mcast list"
2026 ", setting ALL_MULTI\n", netdev->name);
2027 new_mode |= VMXNET3_RXM_ALL_MULTI;
2028 }
2029 }
2030
2031
2032 if (!(new_mode & VMXNET3_RXM_MCAST)) {
2033 rxConf->mfTableLen = 0;
2034 rxConf->mfTablePA = 0;
2035 }
2036
2037 spin_lock_irqsave(&adapter->cmd_lock, flags);
2038 if (new_mode != rxConf->rxMode) {
2039 rxConf->rxMode = cpu_to_le32(new_mode);
2040 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2041 VMXNET3_CMD_UPDATE_RX_MODE);
2042 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2043 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2044 }
2045
2046 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2047 VMXNET3_CMD_UPDATE_MAC_FILTERS);
2048 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2049
2050 kfree(new_table);
2051}
2052
2053void
2054vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2055{
2056 int i;
2057
2058 for (i = 0; i < adapter->num_rx_queues; i++)
2059 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2060}
2061
2062
2063/*
2064 * Set up driver_shared based on settings in adapter.
2065 */
2066
2067static void
2068vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2069{
2070 struct Vmxnet3_DriverShared *shared = adapter->shared;
2071 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2072 struct Vmxnet3_TxQueueConf *tqc;
2073 struct Vmxnet3_RxQueueConf *rqc;
2074 int i;
2075
2076 memset(shared, 0, sizeof(*shared));
2077
2078 /* driver settings */
2079 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2080 devRead->misc.driverInfo.version = cpu_to_le32(
2081 VMXNET3_DRIVER_VERSION_NUM);
2082 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2083 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2084 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
2085 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2086 *((u32 *)&devRead->misc.driverInfo.gos));
2087 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2088 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
2089
2090 devRead->misc.ddPA = cpu_to_le64(virt_to_phys(adapter));
2091 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
2092
2093 /* set up feature flags */
2094 if (adapter->netdev->features & NETIF_F_RXCSUM)
2095 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
2096
2097 if (adapter->netdev->features & NETIF_F_LRO) {
2098 devRead->misc.uptFeatures |= UPT1_F_LRO;
2099 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
2100 }
2101 if (adapter->netdev->features & NETIF_F_HW_VLAN_RX)
2102 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
2103
2104 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2105 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2106 devRead->misc.queueDescLen = cpu_to_le32(
2107 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2108 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
2109
2110 /* tx queue settings */
2111 devRead->misc.numTxQueues = adapter->num_tx_queues;
2112 for (i = 0; i < adapter->num_tx_queues; i++) {
2113 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2114 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2115 tqc = &adapter->tqd_start[i].conf;
2116 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
2117 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2118 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
2119 tqc->ddPA = cpu_to_le64(virt_to_phys(tq->buf_info));
2120 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
2121 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
2122 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
2123 tqc->ddLen = cpu_to_le32(
2124 sizeof(struct vmxnet3_tx_buf_info) *
2125 tqc->txRingSize);
2126 tqc->intrIdx = tq->comp_ring.intr_idx;
2127 }
2128
2129 /* rx queue settings */
2130 devRead->misc.numRxQueues = adapter->num_rx_queues;
2131 for (i = 0; i < adapter->num_rx_queues; i++) {
2132 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2133 rqc = &adapter->rqd_start[i].conf;
2134 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2135 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2136 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
2137 rqc->ddPA = cpu_to_le64(virt_to_phys(
2138 rq->buf_info));
2139 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
2140 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
2141 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
2142 rqc->ddLen = cpu_to_le32(
2143 sizeof(struct vmxnet3_rx_buf_info) *
2144 (rqc->rxRingSize[0] +
2145 rqc->rxRingSize[1]));
2146 rqc->intrIdx = rq->comp_ring.intr_idx;
2147 }
2148
2149#ifdef VMXNET3_RSS
2150 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2151
2152 if (adapter->rss) {
2153 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
2154 devRead->misc.uptFeatures |= UPT1_F_RSS;
2155 devRead->misc.numRxQueues = adapter->num_rx_queues;
2156 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2157 UPT1_RSS_HASH_TYPE_IPV4 |
2158 UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2159 UPT1_RSS_HASH_TYPE_IPV6;
2160 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2161 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2162 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
2163 get_random_bytes(&rssConf->hashKey[0], rssConf->hashKeySize);
2164 for (i = 0; i < rssConf->indTableSize; i++)
2165 rssConf->indTable[i] = i % adapter->num_rx_queues;
2166
2167 devRead->rssConfDesc.confVer = 1;
2168 devRead->rssConfDesc.confLen = sizeof(*rssConf);
2169 devRead->rssConfDesc.confPA = virt_to_phys(rssConf);
2170 }
2171
2172#endif /* VMXNET3_RSS */
2173
2174 /* intr settings */
2175 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2176 VMXNET3_IMM_AUTO;
2177 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2178 for (i = 0; i < adapter->intr.num_intrs; i++)
2179 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2180
2181 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
2182 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
2183
2184 /* rx filter settings */
2185 devRead->rxFilterConf.rxMode = 0;
2186 vmxnet3_restore_vlan(adapter);
2187 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2188
2189 /* the rest are already zeroed */
2190}
2191
2192
2193int
2194vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
2195{
2196 int err, i;
2197 u32 ret;
2198 unsigned long flags;
2199
2200 dev_dbg(&adapter->netdev->dev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
2201 " ring sizes %u %u %u\n", adapter->netdev->name,
2202 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
2203 adapter->tx_queue[0].tx_ring.size,
2204 adapter->rx_queue[0].rx_ring[0].size,
2205 adapter->rx_queue[0].rx_ring[1].size);
2206
2207 vmxnet3_tq_init_all(adapter);
2208 err = vmxnet3_rq_init_all(adapter);
2209 if (err) {
2210 printk(KERN_ERR "Failed to init rx queue for %s: error %d\n",
2211 adapter->netdev->name, err);
2212 goto rq_err;
2213 }
2214
2215 err = vmxnet3_request_irqs(adapter);
2216 if (err) {
2217 printk(KERN_ERR "Failed to setup irq for %s: error %d\n",
2218 adapter->netdev->name, err);
2219 goto irq_err;
2220 }
2221
2222 vmxnet3_setup_driver_shared(adapter);
2223
2224 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
2225 adapter->shared_pa));
2226 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
2227 adapter->shared_pa));
2228 spin_lock_irqsave(&adapter->cmd_lock, flags);
2229 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2230 VMXNET3_CMD_ACTIVATE_DEV);
2231 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2232 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2233
2234 if (ret != 0) {
2235 printk(KERN_ERR "Failed to activate dev %s: error %u\n",
2236 adapter->netdev->name, ret);
2237 err = -EINVAL;
2238 goto activate_err;
2239 }
2240
2241 for (i = 0; i < adapter->num_rx_queues; i++) {
2242 VMXNET3_WRITE_BAR0_REG(adapter,
2243 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
2244 adapter->rx_queue[i].rx_ring[0].next2fill);
2245 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
2246 (i * VMXNET3_REG_ALIGN)),
2247 adapter->rx_queue[i].rx_ring[1].next2fill);
2248 }
2249
2250 /* Apply the rx filter settins last. */
2251 vmxnet3_set_mc(adapter->netdev);
2252
2253 /*
2254 * Check link state when first activating device. It will start the
2255 * tx queue if the link is up.
2256 */
2257 vmxnet3_check_link(adapter, true);
2258 for (i = 0; i < adapter->num_rx_queues; i++)
2259 napi_enable(&adapter->rx_queue[i].napi);
2260 vmxnet3_enable_all_intrs(adapter);
2261 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
2262 return 0;
2263
2264activate_err:
2265 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
2266 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
2267 vmxnet3_free_irqs(adapter);
2268irq_err:
2269rq_err:
2270 /* free up buffers we allocated */
2271 vmxnet3_rq_cleanup_all(adapter);
2272 return err;
2273}
2274
2275
2276void
2277vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
2278{
2279 unsigned long flags;
2280 spin_lock_irqsave(&adapter->cmd_lock, flags);
2281 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
2282 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2283}
2284
2285
2286int
2287vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
2288{
2289 int i;
2290 unsigned long flags;
2291 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
2292 return 0;
2293
2294
2295 spin_lock_irqsave(&adapter->cmd_lock, flags);
2296 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2297 VMXNET3_CMD_QUIESCE_DEV);
2298 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2299 vmxnet3_disable_all_intrs(adapter);
2300
2301 for (i = 0; i < adapter->num_rx_queues; i++)
2302 napi_disable(&adapter->rx_queue[i].napi);
2303 netif_tx_disable(adapter->netdev);
2304 adapter->link_speed = 0;
2305 netif_carrier_off(adapter->netdev);
2306
2307 vmxnet3_tq_cleanup_all(adapter);
2308 vmxnet3_rq_cleanup_all(adapter);
2309 vmxnet3_free_irqs(adapter);
2310 return 0;
2311}
2312
2313
2314static void
2315vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2316{
2317 u32 tmp;
2318
2319 tmp = *(u32 *)mac;
2320 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
2321
2322 tmp = (mac[5] << 8) | mac[4];
2323 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
2324}
2325
2326
2327static int
2328vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
2329{
2330 struct sockaddr *addr = p;
2331 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2332
2333 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2334 vmxnet3_write_mac_addr(adapter, addr->sa_data);
2335
2336 return 0;
2337}
2338
2339
2340/* ==================== initialization and cleanup routines ============ */
2341
2342static int
2343vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64)
2344{
2345 int err;
2346 unsigned long mmio_start, mmio_len;
2347 struct pci_dev *pdev = adapter->pdev;
2348
2349 err = pci_enable_device(pdev);
2350 if (err) {
2351 printk(KERN_ERR "Failed to enable adapter %s: error %d\n",
2352 pci_name(pdev), err);
2353 return err;
2354 }
2355
2356 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
2357 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
2358 printk(KERN_ERR "pci_set_consistent_dma_mask failed "
2359 "for adapter %s\n", pci_name(pdev));
2360 err = -EIO;
2361 goto err_set_mask;
2362 }
2363 *dma64 = true;
2364 } else {
2365 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
2366 printk(KERN_ERR "pci_set_dma_mask failed for adapter "
2367 "%s\n", pci_name(pdev));
2368 err = -EIO;
2369 goto err_set_mask;
2370 }
2371 *dma64 = false;
2372 }
2373
2374 err = pci_request_selected_regions(pdev, (1 << 2) - 1,
2375 vmxnet3_driver_name);
2376 if (err) {
2377 printk(KERN_ERR "Failed to request region for adapter %s: "
2378 "error %d\n", pci_name(pdev), err);
2379 goto err_set_mask;
2380 }
2381
2382 pci_set_master(pdev);
2383
2384 mmio_start = pci_resource_start(pdev, 0);
2385 mmio_len = pci_resource_len(pdev, 0);
2386 adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
2387 if (!adapter->hw_addr0) {
2388 printk(KERN_ERR "Failed to map bar0 for adapter %s\n",
2389 pci_name(pdev));
2390 err = -EIO;
2391 goto err_ioremap;
2392 }
2393
2394 mmio_start = pci_resource_start(pdev, 1);
2395 mmio_len = pci_resource_len(pdev, 1);
2396 adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
2397 if (!adapter->hw_addr1) {
2398 printk(KERN_ERR "Failed to map bar1 for adapter %s\n",
2399 pci_name(pdev));
2400 err = -EIO;
2401 goto err_bar1;
2402 }
2403 return 0;
2404
2405err_bar1:
2406 iounmap(adapter->hw_addr0);
2407err_ioremap:
2408 pci_release_selected_regions(pdev, (1 << 2) - 1);
2409err_set_mask:
2410 pci_disable_device(pdev);
2411 return err;
2412}
2413
2414
2415static void
2416vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
2417{
2418 BUG_ON(!adapter->pdev);
2419
2420 iounmap(adapter->hw_addr0);
2421 iounmap(adapter->hw_addr1);
2422 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
2423 pci_disable_device(adapter->pdev);
2424}
2425
2426
2427static void
2428vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
2429{
2430 size_t sz, i, ring0_size, ring1_size, comp_size;
2431 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[0];
2432
2433
2434 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
2435 VMXNET3_MAX_ETH_HDR_SIZE) {
2436 adapter->skb_buf_size = adapter->netdev->mtu +
2437 VMXNET3_MAX_ETH_HDR_SIZE;
2438 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
2439 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
2440
2441 adapter->rx_buf_per_pkt = 1;
2442 } else {
2443 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
2444 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
2445 VMXNET3_MAX_ETH_HDR_SIZE;
2446 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
2447 }
2448
2449 /*
2450 * for simplicity, force the ring0 size to be a multiple of
2451 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
2452 */
2453 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
2454 ring0_size = adapter->rx_queue[0].rx_ring[0].size;
2455 ring0_size = (ring0_size + sz - 1) / sz * sz;
2456 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
2457 sz * sz);
2458 ring1_size = adapter->rx_queue[0].rx_ring[1].size;
2459 comp_size = ring0_size + ring1_size;
2460
2461 for (i = 0; i < adapter->num_rx_queues; i++) {
2462 rq = &adapter->rx_queue[i];
2463 rq->rx_ring[0].size = ring0_size;
2464 rq->rx_ring[1].size = ring1_size;
2465 rq->comp_ring.size = comp_size;
2466 }
2467}
2468
2469
2470int
2471vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
2472 u32 rx_ring_size, u32 rx_ring2_size)
2473{
2474 int err = 0, i;
2475
2476 for (i = 0; i < adapter->num_tx_queues; i++) {
2477 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2478 tq->tx_ring.size = tx_ring_size;
2479 tq->data_ring.size = tx_ring_size;
2480 tq->comp_ring.size = tx_ring_size;
2481 tq->shared = &adapter->tqd_start[i].ctrl;
2482 tq->stopped = true;
2483 tq->adapter = adapter;
2484 tq->qid = i;
2485 err = vmxnet3_tq_create(tq, adapter);
2486 /*
2487 * Too late to change num_tx_queues. We cannot do away with
2488 * lesser number of queues than what we asked for
2489 */
2490 if (err)
2491 goto queue_err;
2492 }
2493
2494 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
2495 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
2496 vmxnet3_adjust_rx_ring_size(adapter);
2497 for (i = 0; i < adapter->num_rx_queues; i++) {
2498 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2499 /* qid and qid2 for rx queues will be assigned later when num
2500 * of rx queues is finalized after allocating intrs */
2501 rq->shared = &adapter->rqd_start[i].ctrl;
2502 rq->adapter = adapter;
2503 err = vmxnet3_rq_create(rq, adapter);
2504 if (err) {
2505 if (i == 0) {
2506 printk(KERN_ERR "Could not allocate any rx"
2507 "queues. Aborting.\n");
2508 goto queue_err;
2509 } else {
2510 printk(KERN_INFO "Number of rx queues changed "
2511 "to : %d.\n", i);
2512 adapter->num_rx_queues = i;
2513 err = 0;
2514 break;
2515 }
2516 }
2517 }
2518 return err;
2519queue_err:
2520 vmxnet3_tq_destroy_all(adapter);
2521 return err;
2522}
2523
2524static int
2525vmxnet3_open(struct net_device *netdev)
2526{
2527 struct vmxnet3_adapter *adapter;
2528 int err, i;
2529
2530 adapter = netdev_priv(netdev);
2531
2532 for (i = 0; i < adapter->num_tx_queues; i++)
2533 spin_lock_init(&adapter->tx_queue[i].tx_lock);
2534
2535 err = vmxnet3_create_queues(adapter, VMXNET3_DEF_TX_RING_SIZE,
2536 VMXNET3_DEF_RX_RING_SIZE,
2537 VMXNET3_DEF_RX_RING_SIZE);
2538 if (err)
2539 goto queue_err;
2540
2541 err = vmxnet3_activate_dev(adapter);
2542 if (err)
2543 goto activate_err;
2544
2545 return 0;
2546
2547activate_err:
2548 vmxnet3_rq_destroy_all(adapter);
2549 vmxnet3_tq_destroy_all(adapter);
2550queue_err:
2551 return err;
2552}
2553
2554
2555static int
2556vmxnet3_close(struct net_device *netdev)
2557{
2558 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2559
2560 /*
2561 * Reset_work may be in the middle of resetting the device, wait for its
2562 * completion.
2563 */
2564 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2565 msleep(1);
2566
2567 vmxnet3_quiesce_dev(adapter);
2568
2569 vmxnet3_rq_destroy_all(adapter);
2570 vmxnet3_tq_destroy_all(adapter);
2571
2572 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2573
2574
2575 return 0;
2576}
2577
2578
2579void
2580vmxnet3_force_close(struct vmxnet3_adapter *adapter)
2581{
2582 int i;
2583
2584 /*
2585 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
2586 * vmxnet3_close() will deadlock.
2587 */
2588 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
2589
2590 /* we need to enable NAPI, otherwise dev_close will deadlock */
2591 for (i = 0; i < adapter->num_rx_queues; i++)
2592 napi_enable(&adapter->rx_queue[i].napi);
2593 dev_close(adapter->netdev);
2594}
2595
2596
2597static int
2598vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
2599{
2600 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2601 int err = 0;
2602
2603 if (new_mtu < VMXNET3_MIN_MTU || new_mtu > VMXNET3_MAX_MTU)
2604 return -EINVAL;
2605
2606 netdev->mtu = new_mtu;
2607
2608 /*
2609 * Reset_work may be in the middle of resetting the device, wait for its
2610 * completion.
2611 */
2612 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2613 msleep(1);
2614
2615 if (netif_running(netdev)) {
2616 vmxnet3_quiesce_dev(adapter);
2617 vmxnet3_reset_dev(adapter);
2618
2619 /* we need to re-create the rx queue based on the new mtu */
2620 vmxnet3_rq_destroy_all(adapter);
2621 vmxnet3_adjust_rx_ring_size(adapter);
2622 err = vmxnet3_rq_create_all(adapter);
2623 if (err) {
2624 printk(KERN_ERR "%s: failed to re-create rx queues,"
2625 " error %d. Closing it.\n", netdev->name, err);
2626 goto out;
2627 }
2628
2629 err = vmxnet3_activate_dev(adapter);
2630 if (err) {
2631 printk(KERN_ERR "%s: failed to re-activate, error %d. "
2632 "Closing it\n", netdev->name, err);
2633 goto out;
2634 }
2635 }
2636
2637out:
2638 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2639 if (err)
2640 vmxnet3_force_close(adapter);
2641
2642 return err;
2643}
2644
2645
2646static void
2647vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
2648{
2649 struct net_device *netdev = adapter->netdev;
2650
2651 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
2652 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_TX |
2653 NETIF_F_HW_VLAN_RX | NETIF_F_TSO | NETIF_F_TSO6 |
2654 NETIF_F_LRO;
2655 if (dma64)
2656 netdev->hw_features |= NETIF_F_HIGHDMA;
2657 netdev->vlan_features = netdev->hw_features &
2658 ~(NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
2659 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_FILTER;
2660
2661 netdev_info(adapter->netdev,
2662 "features: sg csum vlan jf tso tsoIPv6 lro%s\n",
2663 dma64 ? " highDMA" : "");
2664}
2665
2666
2667static void
2668vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2669{
2670 u32 tmp;
2671
2672 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
2673 *(u32 *)mac = tmp;
2674
2675 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
2676 mac[4] = tmp & 0xff;
2677 mac[5] = (tmp >> 8) & 0xff;
2678}
2679
2680#ifdef CONFIG_PCI_MSI
2681
2682/*
2683 * Enable MSIx vectors.
2684 * Returns :
2685 * 0 on successful enabling of required vectors,
2686 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
2687 * could be enabled.
2688 * number of vectors which can be enabled otherwise (this number is smaller
2689 * than VMXNET3_LINUX_MIN_MSIX_VECT)
2690 */
2691
2692static int
2693vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter,
2694 int vectors)
2695{
2696 int err = 0, vector_threshold;
2697 vector_threshold = VMXNET3_LINUX_MIN_MSIX_VECT;
2698
2699 while (vectors >= vector_threshold) {
2700 err = pci_enable_msix(adapter->pdev, adapter->intr.msix_entries,
2701 vectors);
2702 if (!err) {
2703 adapter->intr.num_intrs = vectors;
2704 return 0;
2705 } else if (err < 0) {
2706 printk(KERN_ERR "Failed to enable MSI-X for %s, error"
2707 " %d\n", adapter->netdev->name, err);
2708 vectors = 0;
2709 } else if (err < vector_threshold) {
2710 break;
2711 } else {
2712 /* If fails to enable required number of MSI-x vectors
2713 * try enabling minimum number of vectors required.
2714 */
2715 vectors = vector_threshold;
2716 printk(KERN_ERR "Failed to enable %d MSI-X for %s, try"
2717 " %d instead\n", vectors, adapter->netdev->name,
2718 vector_threshold);
2719 }
2720 }
2721
2722 printk(KERN_INFO "Number of MSI-X interrupts which can be allocatedi"
2723 " are lower than min threshold required.\n");
2724 return err;
2725}
2726
2727
2728#endif /* CONFIG_PCI_MSI */
2729
2730static void
2731vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
2732{
2733 u32 cfg;
2734 unsigned long flags;
2735
2736 /* intr settings */
2737 spin_lock_irqsave(&adapter->cmd_lock, flags);
2738 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2739 VMXNET3_CMD_GET_CONF_INTR);
2740 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2741 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2742 adapter->intr.type = cfg & 0x3;
2743 adapter->intr.mask_mode = (cfg >> 2) & 0x3;
2744
2745 if (adapter->intr.type == VMXNET3_IT_AUTO) {
2746 adapter->intr.type = VMXNET3_IT_MSIX;
2747 }
2748
2749#ifdef CONFIG_PCI_MSI
2750 if (adapter->intr.type == VMXNET3_IT_MSIX) {
2751 int vector, err = 0;
2752
2753 adapter->intr.num_intrs = (adapter->share_intr ==
2754 VMXNET3_INTR_TXSHARE) ? 1 :
2755 adapter->num_tx_queues;
2756 adapter->intr.num_intrs += (adapter->share_intr ==
2757 VMXNET3_INTR_BUDDYSHARE) ? 0 :
2758 adapter->num_rx_queues;
2759 adapter->intr.num_intrs += 1; /* for link event */
2760
2761 adapter->intr.num_intrs = (adapter->intr.num_intrs >
2762 VMXNET3_LINUX_MIN_MSIX_VECT
2763 ? adapter->intr.num_intrs :
2764 VMXNET3_LINUX_MIN_MSIX_VECT);
2765
2766 for (vector = 0; vector < adapter->intr.num_intrs; vector++)
2767 adapter->intr.msix_entries[vector].entry = vector;
2768
2769 err = vmxnet3_acquire_msix_vectors(adapter,
2770 adapter->intr.num_intrs);
2771 /* If we cannot allocate one MSIx vector per queue
2772 * then limit the number of rx queues to 1
2773 */
2774 if (err == VMXNET3_LINUX_MIN_MSIX_VECT) {
2775 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
2776 || adapter->num_rx_queues != 1) {
2777 adapter->share_intr = VMXNET3_INTR_TXSHARE;
2778 printk(KERN_ERR "Number of rx queues : 1\n");
2779 adapter->num_rx_queues = 1;
2780 adapter->intr.num_intrs =
2781 VMXNET3_LINUX_MIN_MSIX_VECT;
2782 }
2783 return;
2784 }
2785 if (!err)
2786 return;
2787
2788 /* If we cannot allocate MSIx vectors use only one rx queue */
2789 printk(KERN_INFO "Failed to enable MSI-X for %s, error %d."
2790 "#rx queues : 1, try MSI\n", adapter->netdev->name, err);
2791
2792 adapter->intr.type = VMXNET3_IT_MSI;
2793 }
2794
2795 if (adapter->intr.type == VMXNET3_IT_MSI) {
2796 int err;
2797 err = pci_enable_msi(adapter->pdev);
2798 if (!err) {
2799 adapter->num_rx_queues = 1;
2800 adapter->intr.num_intrs = 1;
2801 return;
2802 }
2803 }
2804#endif /* CONFIG_PCI_MSI */
2805
2806 adapter->num_rx_queues = 1;
2807 printk(KERN_INFO "Using INTx interrupt, #Rx queues: 1.\n");
2808 adapter->intr.type = VMXNET3_IT_INTX;
2809
2810 /* INT-X related setting */
2811 adapter->intr.num_intrs = 1;
2812}
2813
2814
2815static void
2816vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
2817{
2818 if (adapter->intr.type == VMXNET3_IT_MSIX)
2819 pci_disable_msix(adapter->pdev);
2820 else if (adapter->intr.type == VMXNET3_IT_MSI)
2821 pci_disable_msi(adapter->pdev);
2822 else
2823 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
2824}
2825
2826
2827static void
2828vmxnet3_tx_timeout(struct net_device *netdev)
2829{
2830 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2831 adapter->tx_timeout_count++;
2832
2833 printk(KERN_ERR "%s: tx hang\n", adapter->netdev->name);
2834 schedule_work(&adapter->work);
2835 netif_wake_queue(adapter->netdev);
2836}
2837
2838
2839static void
2840vmxnet3_reset_work(struct work_struct *data)
2841{
2842 struct vmxnet3_adapter *adapter;
2843
2844 adapter = container_of(data, struct vmxnet3_adapter, work);
2845
2846 /* if another thread is resetting the device, no need to proceed */
2847 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2848 return;
2849
2850 /* if the device is closed, we must leave it alone */
2851 rtnl_lock();
2852 if (netif_running(adapter->netdev)) {
2853 printk(KERN_INFO "%s: resetting\n", adapter->netdev->name);
2854 vmxnet3_quiesce_dev(adapter);
2855 vmxnet3_reset_dev(adapter);
2856 vmxnet3_activate_dev(adapter);
2857 } else {
2858 printk(KERN_INFO "%s: already closed\n", adapter->netdev->name);
2859 }
2860 rtnl_unlock();
2861
2862 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2863}
2864
2865
2866static int __devinit
2867vmxnet3_probe_device(struct pci_dev *pdev,
2868 const struct pci_device_id *id)
2869{
2870 static const struct net_device_ops vmxnet3_netdev_ops = {
2871 .ndo_open = vmxnet3_open,
2872 .ndo_stop = vmxnet3_close,
2873 .ndo_start_xmit = vmxnet3_xmit_frame,
2874 .ndo_set_mac_address = vmxnet3_set_mac_addr,
2875 .ndo_change_mtu = vmxnet3_change_mtu,
2876 .ndo_set_features = vmxnet3_set_features,
2877 .ndo_get_stats64 = vmxnet3_get_stats64,
2878 .ndo_tx_timeout = vmxnet3_tx_timeout,
2879 .ndo_set_multicast_list = vmxnet3_set_mc,
2880 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
2881 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
2882#ifdef CONFIG_NET_POLL_CONTROLLER
2883 .ndo_poll_controller = vmxnet3_netpoll,
2884#endif
2885 };
2886 int err;
2887 bool dma64 = false; /* stupid gcc */
2888 u32 ver;
2889 struct net_device *netdev;
2890 struct vmxnet3_adapter *adapter;
2891 u8 mac[ETH_ALEN];
2892 int size;
2893 int num_tx_queues;
2894 int num_rx_queues;
2895
2896 if (!pci_msi_enabled())
2897 enable_mq = 0;
2898
2899#ifdef VMXNET3_RSS
2900 if (enable_mq)
2901 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
2902 (int)num_online_cpus());
2903 else
2904#endif
2905 num_rx_queues = 1;
2906 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
2907
2908 if (enable_mq)
2909 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
2910 (int)num_online_cpus());
2911 else
2912 num_tx_queues = 1;
2913
2914 num_tx_queues = rounddown_pow_of_two(num_tx_queues);
2915 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
2916 max(num_tx_queues, num_rx_queues));
2917 printk(KERN_INFO "# of Tx queues : %d, # of Rx queues : %d\n",
2918 num_tx_queues, num_rx_queues);
2919
2920 if (!netdev) {
2921 printk(KERN_ERR "Failed to alloc ethernet device for adapter "
2922 "%s\n", pci_name(pdev));
2923 return -ENOMEM;
2924 }
2925
2926 pci_set_drvdata(pdev, netdev);
2927 adapter = netdev_priv(netdev);
2928 adapter->netdev = netdev;
2929 adapter->pdev = pdev;
2930
2931 spin_lock_init(&adapter->cmd_lock);
2932 adapter->shared = pci_alloc_consistent(adapter->pdev,
2933 sizeof(struct Vmxnet3_DriverShared),
2934 &adapter->shared_pa);
2935 if (!adapter->shared) {
2936 printk(KERN_ERR "Failed to allocate memory for %s\n",
2937 pci_name(pdev));
2938 err = -ENOMEM;
2939 goto err_alloc_shared;
2940 }
2941
2942 adapter->num_rx_queues = num_rx_queues;
2943 adapter->num_tx_queues = num_tx_queues;
2944
2945 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
2946 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
2947 adapter->tqd_start = pci_alloc_consistent(adapter->pdev, size,
2948 &adapter->queue_desc_pa);
2949
2950 if (!adapter->tqd_start) {
2951 printk(KERN_ERR "Failed to allocate memory for %s\n",
2952 pci_name(pdev));
2953 err = -ENOMEM;
2954 goto err_alloc_queue_desc;
2955 }
2956 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
2957 adapter->num_tx_queues);
2958
2959 adapter->pm_conf = kmalloc(sizeof(struct Vmxnet3_PMConf), GFP_KERNEL);
2960 if (adapter->pm_conf == NULL) {
2961 printk(KERN_ERR "Failed to allocate memory for %s\n",
2962 pci_name(pdev));
2963 err = -ENOMEM;
2964 goto err_alloc_pm;
2965 }
2966
2967#ifdef VMXNET3_RSS
2968
2969 adapter->rss_conf = kmalloc(sizeof(struct UPT1_RSSConf), GFP_KERNEL);
2970 if (adapter->rss_conf == NULL) {
2971 printk(KERN_ERR "Failed to allocate memory for %s\n",
2972 pci_name(pdev));
2973 err = -ENOMEM;
2974 goto err_alloc_rss;
2975 }
2976#endif /* VMXNET3_RSS */
2977
2978 err = vmxnet3_alloc_pci_resources(adapter, &dma64);
2979 if (err < 0)
2980 goto err_alloc_pci;
2981
2982 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
2983 if (ver & 1) {
2984 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_VRRS, 1);
2985 } else {
2986 printk(KERN_ERR "Incompatible h/w version (0x%x) for adapter"
2987 " %s\n", ver, pci_name(pdev));
2988 err = -EBUSY;
2989 goto err_ver;
2990 }
2991
2992 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
2993 if (ver & 1) {
2994 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
2995 } else {
2996 printk(KERN_ERR "Incompatible upt version (0x%x) for "
2997 "adapter %s\n", ver, pci_name(pdev));
2998 err = -EBUSY;
2999 goto err_ver;
3000 }
3001
3002 SET_NETDEV_DEV(netdev, &pdev->dev);
3003 vmxnet3_declare_features(adapter, dma64);
3004
3005 adapter->dev_number = atomic_read(&devices_found);
3006
3007 adapter->share_intr = irq_share_mode;
3008 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE &&
3009 adapter->num_tx_queues != adapter->num_rx_queues)
3010 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
3011
3012 vmxnet3_alloc_intr_resources(adapter);
3013
3014#ifdef VMXNET3_RSS
3015 if (adapter->num_rx_queues > 1 &&
3016 adapter->intr.type == VMXNET3_IT_MSIX) {
3017 adapter->rss = true;
3018 printk(KERN_INFO "RSS is enabled.\n");
3019 } else {
3020 adapter->rss = false;
3021 }
3022#endif
3023
3024 vmxnet3_read_mac_addr(adapter, mac);
3025 memcpy(netdev->dev_addr, mac, netdev->addr_len);
3026
3027 netdev->netdev_ops = &vmxnet3_netdev_ops;
3028 vmxnet3_set_ethtool_ops(netdev);
3029 netdev->watchdog_timeo = 5 * HZ;
3030
3031 INIT_WORK(&adapter->work, vmxnet3_reset_work);
3032
3033 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3034 int i;
3035 for (i = 0; i < adapter->num_rx_queues; i++) {
3036 netif_napi_add(adapter->netdev,
3037 &adapter->rx_queue[i].napi,
3038 vmxnet3_poll_rx_only, 64);
3039 }
3040 } else {
3041 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
3042 vmxnet3_poll, 64);
3043 }
3044
3045 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
3046 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
3047
3048 err = register_netdev(netdev);
3049
3050 if (err) {
3051 printk(KERN_ERR "Failed to register adapter %s\n",
3052 pci_name(pdev));
3053 goto err_register;
3054 }
3055
3056 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
3057 vmxnet3_check_link(adapter, false);
3058 atomic_inc(&devices_found);
3059 return 0;
3060
3061err_register:
3062 vmxnet3_free_intr_resources(adapter);
3063err_ver:
3064 vmxnet3_free_pci_resources(adapter);
3065err_alloc_pci:
3066#ifdef VMXNET3_RSS
3067 kfree(adapter->rss_conf);
3068err_alloc_rss:
3069#endif
3070 kfree(adapter->pm_conf);
3071err_alloc_pm:
3072 pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
3073 adapter->queue_desc_pa);
3074err_alloc_queue_desc:
3075 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
3076 adapter->shared, adapter->shared_pa);
3077err_alloc_shared:
3078 pci_set_drvdata(pdev, NULL);
3079 free_netdev(netdev);
3080 return err;
3081}
3082
3083
3084static void __devexit
3085vmxnet3_remove_device(struct pci_dev *pdev)
3086{
3087 struct net_device *netdev = pci_get_drvdata(pdev);
3088 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3089 int size = 0;
3090 int num_rx_queues;
3091
3092#ifdef VMXNET3_RSS
3093 if (enable_mq)
3094 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3095 (int)num_online_cpus());
3096 else
3097#endif
3098 num_rx_queues = 1;
3099 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
3100
3101 cancel_work_sync(&adapter->work);
3102
3103 unregister_netdev(netdev);
3104
3105 vmxnet3_free_intr_resources(adapter);
3106 vmxnet3_free_pci_resources(adapter);
3107#ifdef VMXNET3_RSS
3108 kfree(adapter->rss_conf);
3109#endif
3110 kfree(adapter->pm_conf);
3111
3112 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3113 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
3114 pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
3115 adapter->queue_desc_pa);
3116 pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
3117 adapter->shared, adapter->shared_pa);
3118 free_netdev(netdev);
3119}
3120
3121
3122#ifdef CONFIG_PM
3123
3124static int
3125vmxnet3_suspend(struct device *device)
3126{
3127 struct pci_dev *pdev = to_pci_dev(device);
3128 struct net_device *netdev = pci_get_drvdata(pdev);
3129 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3130 struct Vmxnet3_PMConf *pmConf;
3131 struct ethhdr *ehdr;
3132 struct arphdr *ahdr;
3133 u8 *arpreq;
3134 struct in_device *in_dev;
3135 struct in_ifaddr *ifa;
3136 unsigned long flags;
3137 int i = 0;
3138
3139 if (!netif_running(netdev))
3140 return 0;
3141
3142 for (i = 0; i < adapter->num_rx_queues; i++)
3143 napi_disable(&adapter->rx_queue[i].napi);
3144
3145 vmxnet3_disable_all_intrs(adapter);
3146 vmxnet3_free_irqs(adapter);
3147 vmxnet3_free_intr_resources(adapter);
3148
3149 netif_device_detach(netdev);
3150 netif_tx_stop_all_queues(netdev);
3151
3152 /* Create wake-up filters. */
3153 pmConf = adapter->pm_conf;
3154 memset(pmConf, 0, sizeof(*pmConf));
3155
3156 if (adapter->wol & WAKE_UCAST) {
3157 pmConf->filters[i].patternSize = ETH_ALEN;
3158 pmConf->filters[i].maskSize = 1;
3159 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
3160 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
3161
3162 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
3163 i++;
3164 }
3165
3166 if (adapter->wol & WAKE_ARP) {
3167 in_dev = in_dev_get(netdev);
3168 if (!in_dev)
3169 goto skip_arp;
3170
3171 ifa = (struct in_ifaddr *)in_dev->ifa_list;
3172 if (!ifa)
3173 goto skip_arp;
3174
3175 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
3176 sizeof(struct arphdr) + /* ARP header */
3177 2 * ETH_ALEN + /* 2 Ethernet addresses*/
3178 2 * sizeof(u32); /*2 IPv4 addresses */
3179 pmConf->filters[i].maskSize =
3180 (pmConf->filters[i].patternSize - 1) / 8 + 1;
3181
3182 /* ETH_P_ARP in Ethernet header. */
3183 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
3184 ehdr->h_proto = htons(ETH_P_ARP);
3185
3186 /* ARPOP_REQUEST in ARP header. */
3187 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
3188 ahdr->ar_op = htons(ARPOP_REQUEST);
3189 arpreq = (u8 *)(ahdr + 1);
3190
3191 /* The Unicast IPv4 address in 'tip' field. */
3192 arpreq += 2 * ETH_ALEN + sizeof(u32);
3193 *(u32 *)arpreq = ifa->ifa_address;
3194
3195 /* The mask for the relevant bits. */
3196 pmConf->filters[i].mask[0] = 0x00;
3197 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
3198 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
3199 pmConf->filters[i].mask[3] = 0x00;
3200 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
3201 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
3202 in_dev_put(in_dev);
3203
3204 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
3205 i++;
3206 }
3207
3208skip_arp:
3209 if (adapter->wol & WAKE_MAGIC)
3210 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
3211
3212 pmConf->numFilters = i;
3213
3214 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3215 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3216 *pmConf));
3217 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
3218 pmConf));
3219
3220 spin_lock_irqsave(&adapter->cmd_lock, flags);
3221 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3222 VMXNET3_CMD_UPDATE_PMCFG);
3223 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3224
3225 pci_save_state(pdev);
3226 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
3227 adapter->wol);
3228 pci_disable_device(pdev);
3229 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
3230
3231 return 0;
3232}
3233
3234
3235static int
3236vmxnet3_resume(struct device *device)
3237{
3238 int err, i = 0;
3239 unsigned long flags;
3240 struct pci_dev *pdev = to_pci_dev(device);
3241 struct net_device *netdev = pci_get_drvdata(pdev);
3242 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3243 struct Vmxnet3_PMConf *pmConf;
3244
3245 if (!netif_running(netdev))
3246 return 0;
3247
3248 /* Destroy wake-up filters. */
3249 pmConf = adapter->pm_conf;
3250 memset(pmConf, 0, sizeof(*pmConf));
3251
3252 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3253 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3254 *pmConf));
3255 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
3256 pmConf));
3257
3258 netif_device_attach(netdev);
3259 pci_set_power_state(pdev, PCI_D0);
3260 pci_restore_state(pdev);
3261 err = pci_enable_device_mem(pdev);
3262 if (err != 0)
3263 return err;
3264
3265 pci_enable_wake(pdev, PCI_D0, 0);
3266
3267 spin_lock_irqsave(&adapter->cmd_lock, flags);
3268 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3269 VMXNET3_CMD_UPDATE_PMCFG);
3270 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3271 vmxnet3_alloc_intr_resources(adapter);
3272 vmxnet3_request_irqs(adapter);
3273 for (i = 0; i < adapter->num_rx_queues; i++)
3274 napi_enable(&adapter->rx_queue[i].napi);
3275 vmxnet3_enable_all_intrs(adapter);
3276
3277 return 0;
3278}
3279
3280static const struct dev_pm_ops vmxnet3_pm_ops = {
3281 .suspend = vmxnet3_suspend,
3282 .resume = vmxnet3_resume,
3283};
3284#endif
3285
3286static struct pci_driver vmxnet3_driver = {
3287 .name = vmxnet3_driver_name,
3288 .id_table = vmxnet3_pciid_table,
3289 .probe = vmxnet3_probe_device,
3290 .remove = __devexit_p(vmxnet3_remove_device),
3291#ifdef CONFIG_PM
3292 .driver.pm = &vmxnet3_pm_ops,
3293#endif
3294};
3295
3296
3297static int __init
3298vmxnet3_init_module(void)
3299{
3300 printk(KERN_INFO "%s - version %s\n", VMXNET3_DRIVER_DESC,
3301 VMXNET3_DRIVER_VERSION_REPORT);
3302 return pci_register_driver(&vmxnet3_driver);
3303}
3304
3305module_init(vmxnet3_init_module);
3306
3307
3308static void
3309vmxnet3_exit_module(void)
3310{
3311 pci_unregister_driver(&vmxnet3_driver);
3312}
3313
3314module_exit(vmxnet3_exit_module);
3315
3316MODULE_AUTHOR("VMware, Inc.");
3317MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
3318MODULE_LICENSE("GPL v2");
3319MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);