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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) STMicroelectronics 2009
4 * Copyright (C) ST-Ericsson SA 2010
5 *
6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
8 *
9 * PRCM Unit registers
10 */
11
12#ifndef __DB8500_PRCMU_REGS_H
13#define __DB8500_PRCMU_REGS_H
14
15#define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
16
17#define PRCM_ACLK_MGT (0x004)
18#define PRCM_SVAMMCSPCLK_MGT (0x008)
19#define PRCM_SIAMMDSPCLK_MGT (0x00C)
20#define PRCM_SGACLK_MGT (0x014)
21#define PRCM_UARTCLK_MGT (0x018)
22#define PRCM_MSP02CLK_MGT (0x01C)
23#define PRCM_I2CCLK_MGT (0x020)
24#define PRCM_SDMMCCLK_MGT (0x024)
25#define PRCM_SLIMCLK_MGT (0x028)
26#define PRCM_PER1CLK_MGT (0x02C)
27#define PRCM_PER2CLK_MGT (0x030)
28#define PRCM_PER3CLK_MGT (0x034)
29#define PRCM_PER5CLK_MGT (0x038)
30#define PRCM_PER6CLK_MGT (0x03C)
31#define PRCM_PER7CLK_MGT (0x040)
32#define PRCM_LCDCLK_MGT (0x044)
33#define PRCM_BMLCLK_MGT (0x04C)
34#define PRCM_HSITXCLK_MGT (0x050)
35#define PRCM_HSIRXCLK_MGT (0x054)
36#define PRCM_HDMICLK_MGT (0x058)
37#define PRCM_APEATCLK_MGT (0x05C)
38#define PRCM_APETRACECLK_MGT (0x060)
39#define PRCM_MCDECLK_MGT (0x064)
40#define PRCM_IPI2CCLK_MGT (0x068)
41#define PRCM_DSIALTCLK_MGT (0x06C)
42#define PRCM_DMACLK_MGT (0x074)
43#define PRCM_B2R2CLK_MGT (0x078)
44#define PRCM_TVCLK_MGT (0x07C)
45#define PRCM_UNIPROCLK_MGT (0x278)
46#define PRCM_SSPCLK_MGT (0x280)
47#define PRCM_RNGCLK_MGT (0x284)
48#define PRCM_UICCCLK_MGT (0x27C)
49#define PRCM_MSP1CLK_MGT (0x288)
50
51#define PRCM_ARM_PLLDIVPS (prcmu_base + 0x118)
52#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f
53#define PRCM_ARM_PLLDIVPS_MAX_MASK 0xf
54
55#define PRCM_PLLARM_LOCKP (prcmu_base + 0x0a8)
56#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2
57
58#define PRCM_ARM_CHGCLKREQ (prcmu_base + 0x114)
59#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0)
60#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL BIT(16)
61
62#define PRCM_PLLARM_ENABLE (prcmu_base + 0x98)
63#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1
64#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON 0x100
65
66#define PRCM_ARMCLKFIX_MGT (prcmu_base + 0x0)
67#define PRCM_A9PL_FORCE_CLKEN (prcmu_base + 0x19C)
68#define PRCM_A9_RESETN_CLR (prcmu_base + 0x1f4)
69#define PRCM_A9_RESETN_SET (prcmu_base + 0x1f0)
70#define PRCM_ARM_LS_CLAMP (prcmu_base + 0x30c)
71#define PRCM_SRAM_A9 (prcmu_base + 0x308)
72
73#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0)
74#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1)
75
76/* CPU mailbox registers */
77#define PRCM_MBOX_CPU_VAL (prcmu_base + 0x0fc)
78#define PRCM_MBOX_CPU_SET (prcmu_base + 0x100)
79#define PRCM_MBOX_CPU_CLR (prcmu_base + 0x104)
80
81#define PRCM_HOSTACCESS_REQ (prcmu_base + 0x334)
82#define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1
83#define PRCM_HOSTACCESS_REQ_WAKE_REQ BIT(16)
84#define ARM_WAKEUP_MODEM 0x1
85
86#define PRCM_ARM_IT1_CLR (prcmu_base + 0x48C)
87#define PRCM_ARM_IT1_VAL (prcmu_base + 0x494)
88#define PRCM_HOLD_EVT (prcmu_base + 0x174)
89
90#define PRCM_MOD_AWAKE_STATUS (prcmu_base + 0x4A0)
91#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE BIT(0)
92#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE BIT(1)
93#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO BIT(2)
94
95#define PRCM_ITSTATUS0 (prcmu_base + 0x148)
96#define PRCM_ITSTATUS1 (prcmu_base + 0x150)
97#define PRCM_ITSTATUS2 (prcmu_base + 0x158)
98#define PRCM_ITSTATUS3 (prcmu_base + 0x160)
99#define PRCM_ITSTATUS4 (prcmu_base + 0x168)
100#define PRCM_ITSTATUS5 (prcmu_base + 0x484)
101#define PRCM_ITCLEAR5 (prcmu_base + 0x488)
102#define PRCM_ARMIT_MASKXP70_IT (prcmu_base + 0x1018)
103
104/* System reset register */
105#define PRCM_APE_SOFTRST (prcmu_base + 0x228)
106
107/* Level shifter and clamp control registers */
108#define PRCM_MMIP_LS_CLAMP_SET (prcmu_base + 0x420)
109#define PRCM_MMIP_LS_CLAMP_CLR (prcmu_base + 0x424)
110
111#define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP BIT(11)
112#define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI BIT(22)
113
114/* PRCMU clock/PLL/reset registers */
115#define PRCM_PLLSOC0_FREQ (prcmu_base + 0x080)
116#define PRCM_PLLSOC1_FREQ (prcmu_base + 0x084)
117#define PRCM_PLLARM_FREQ (prcmu_base + 0x088)
118#define PRCM_PLLDDR_FREQ (prcmu_base + 0x08C)
119#define PRCM_PLL_FREQ_D_SHIFT 0
120#define PRCM_PLL_FREQ_D_MASK BITS(0, 7)
121#define PRCM_PLL_FREQ_N_SHIFT 8
122#define PRCM_PLL_FREQ_N_MASK BITS(8, 13)
123#define PRCM_PLL_FREQ_R_SHIFT 16
124#define PRCM_PLL_FREQ_R_MASK BITS(16, 18)
125#define PRCM_PLL_FREQ_SELDIV2 BIT(24)
126#define PRCM_PLL_FREQ_DIV2EN BIT(25)
127
128#define PRCM_PLLDSI_FREQ (prcmu_base + 0x500)
129#define PRCM_PLLDSI_ENABLE (prcmu_base + 0x504)
130#define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508)
131#define PRCM_DSI_PLLOUT_SEL (prcmu_base + 0x530)
132#define PRCM_DSITVCLK_DIV (prcmu_base + 0x52C)
133#define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508)
134#define PRCM_APE_RESETN_SET (prcmu_base + 0x1E4)
135#define PRCM_APE_RESETN_CLR (prcmu_base + 0x1E8)
136
137#define PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE BIT(0)
138
139#define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 BIT(0)
140#define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3 BIT(1)
141
142#define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT 0
143#define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK BITS(0, 2)
144#define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT 8
145#define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK BITS(8, 10)
146
147#define PRCM_DSI_PLLOUT_SEL_OFF 0
148#define PRCM_DSI_PLLOUT_SEL_PHI 1
149#define PRCM_DSI_PLLOUT_SEL_PHI_2 2
150#define PRCM_DSI_PLLOUT_SEL_PHI_4 3
151
152#define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT 0
153#define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK BITS(0, 7)
154#define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT 8
155#define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK BITS(8, 15)
156#define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT 16
157#define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK BITS(16, 23)
158#define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN BIT(24)
159#define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN BIT(25)
160#define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN BIT(26)
161
162#define PRCM_APE_RESETN_DSIPLL_RESETN BIT(14)
163
164#define PRCM_CLKOCR (prcmu_base + 0x1CC)
165#define PRCM_CLKOCR_CLKOUT0_REF_CLK (1 << 0)
166#define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13)
167#define PRCM_CLKOCR_CLKOUT1_REF_CLK (1 << 16)
168#define PRCM_CLKOCR_CLKOUT1_MASK BITS(16, 29)
169
170/* ePOD and memory power signal control registers */
171#define PRCM_EPOD_C_SET (prcmu_base + 0x410)
172#define PRCM_SRAM_LS_SLEEP (prcmu_base + 0x304)
173
174/* Debug power control unit registers */
175#define PRCM_POWER_STATE_SET (prcmu_base + 0x254)
176
177/* Miscellaneous unit registers */
178#define PRCM_DSI_SW_RESET (prcmu_base + 0x324)
179#define PRCM_GPIOCR (prcmu_base + 0x138)
180#define PRCM_GPIOCR_DBG_STM_MOD_CMD1 0x800
181#define PRCM_GPIOCR_DBG_UARTMOD_CMD0 0x1
182
183/* PRCMU HW semaphore */
184#define PRCM_SEM (prcmu_base + 0x400)
185#define PRCM_SEM_PRCM_SEM BIT(0)
186
187#define PRCM_TCR (prcmu_base + 0x1C8)
188#define PRCM_TCR_TENSEL_MASK BITS(0, 7)
189#define PRCM_TCR_STOP_TIMERS BIT(16)
190#define PRCM_TCR_DOZE_MODE BIT(17)
191
192#define PRCM_CLKOCR_CLKODIV0_SHIFT 0
193#define PRCM_CLKOCR_CLKODIV0_MASK BITS(0, 5)
194#define PRCM_CLKOCR_CLKOSEL0_SHIFT 6
195#define PRCM_CLKOCR_CLKOSEL0_MASK BITS(6, 8)
196#define PRCM_CLKOCR_CLKODIV1_SHIFT 16
197#define PRCM_CLKOCR_CLKODIV1_MASK BITS(16, 21)
198#define PRCM_CLKOCR_CLKOSEL1_SHIFT 22
199#define PRCM_CLKOCR_CLKOSEL1_MASK BITS(22, 24)
200#define PRCM_CLKOCR_CLK1TYPE BIT(28)
201
202#define PRCM_CLK_MGT_CLKPLLDIV_MASK BITS(0, 4)
203#define PRCM_CLK_MGT_CLKPLLSW_SOC0 BIT(5)
204#define PRCM_CLK_MGT_CLKPLLSW_SOC1 BIT(6)
205#define PRCM_CLK_MGT_CLKPLLSW_DDR BIT(7)
206#define PRCM_CLK_MGT_CLKPLLSW_MASK BITS(5, 7)
207#define PRCM_CLK_MGT_CLKEN BIT(8)
208#define PRCM_CLK_MGT_CLK38 BIT(9)
209#define PRCM_CLK_MGT_CLK38DIV BIT(11)
210#define PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN BIT(12)
211
212/* GPIOCR register */
213#define PRCM_GPIOCR_SPI2_SELECT BIT(23)
214
215#define PRCM_DDR_SUBSYS_APE_MINBW (prcmu_base + 0x438)
216#define PRCM_CGATING_BYPASS (prcmu_base + 0x134)
217#define PRCM_CGATING_BYPASS_ICN2 BIT(6)
218
219/* Miscellaneous unit registers */
220#define PRCM_RESOUTN_SET (prcmu_base + 0x214)
221#define PRCM_RESOUTN_CLR (prcmu_base + 0x218)
222
223/* System reset register */
224#define PRCM_APE_SOFTRST (prcmu_base + 0x228)
225
226#endif /* __DB8500_PRCMU_REGS_H */
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
6 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
7 *
8 * License Terms: GNU General Public License v2
9 *
10 * PRCM Unit registers
11 */
12#ifndef __DB8500_PRCMU_REGS_H
13#define __DB8500_PRCMU_REGS_H
14
15#include <linux/bitops.h>
16#include <mach/hardware.h>
17
18#define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
19
20#define PRCM_ARM_PLLDIVPS 0x118
21#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE BITS(0, 5)
22#define PRCM_ARM_PLLDIVPS_MAX_MASK 0xF
23
24#define PRCM_PLLARM_LOCKP 0x0A8
25#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 BIT(1)
26
27#define PRCM_ARM_CHGCLKREQ 0x114
28#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0)
29
30#define PRCM_PLLARM_ENABLE 0x98
31#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE BIT(0)
32#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON BIT(8)
33
34#define PRCM_ARMCLKFIX_MGT 0x0
35#define PRCM_A9_RESETN_CLR 0x1f4
36#define PRCM_A9_RESETN_SET 0x1f0
37#define PRCM_ARM_LS_CLAMP 0x30C
38#define PRCM_SRAM_A9 0x308
39
40/* ARM WFI Standby signal register */
41#define PRCM_ARM_WFI_STANDBY 0x130
42#define PRCM_IOCR 0x310
43#define PRCM_IOCR_IOFORCE BIT(0)
44
45/* CPU mailbox registers */
46#define PRCM_MBOX_CPU_VAL 0x0FC
47#define PRCM_MBOX_CPU_SET 0x100
48
49/* Dual A9 core interrupt management unit registers */
50#define PRCM_A9_MASK_REQ 0x328
51#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ BIT(0)
52
53#define PRCM_A9_MASK_ACK 0x32C
54#define PRCM_ARMITMSK31TO0 0x11C
55#define PRCM_ARMITMSK63TO32 0x120
56#define PRCM_ARMITMSK95TO64 0x124
57#define PRCM_ARMITMSK127TO96 0x128
58#define PRCM_POWER_STATE_VAL 0x25C
59#define PRCM_ARMITVAL31TO0 0x260
60#define PRCM_ARMITVAL63TO32 0x264
61#define PRCM_ARMITVAL95TO64 0x268
62#define PRCM_ARMITVAL127TO96 0x26C
63
64#define PRCM_HOSTACCESS_REQ 0x334
65#define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ BIT(0)
66
67#define PRCM_ARM_IT1_CLR 0x48C
68#define PRCM_ARM_IT1_VAL 0x494
69
70#define PRCM_ITSTATUS0 0x148
71#define PRCM_ITSTATUS1 0x150
72#define PRCM_ITSTATUS2 0x158
73#define PRCM_ITSTATUS3 0x160
74#define PRCM_ITSTATUS4 0x168
75#define PRCM_ITSTATUS5 0x484
76#define PRCM_ITCLEAR5 0x488
77#define PRCM_ARMIT_MASKXP70_IT 0x1018
78
79/* System reset register */
80#define PRCM_APE_SOFTRST 0x228
81
82/* Level shifter and clamp control registers */
83#define PRCM_MMIP_LS_CLAMP_SET 0x420
84#define PRCM_MMIP_LS_CLAMP_CLR 0x424
85
86/* PRCMU HW semaphore */
87#define PRCM_SEM 0x400
88#define PRCM_SEM_PRCM_SEM BIT(0)
89
90/* PRCMU clock/PLL/reset registers */
91#define PRCM_PLLDSI_FREQ 0x500
92#define PRCM_PLLDSI_ENABLE 0x504
93#define PRCM_PLLDSI_LOCKP 0x508
94#define PRCM_DSI_PLLOUT_SEL 0x530
95#define PRCM_DSITVCLK_DIV 0x52C
96#define PRCM_APE_RESETN_SET 0x1E4
97#define PRCM_APE_RESETN_CLR 0x1E8
98
99#define PRCM_TCR 0x1C8
100#define PRCM_TCR_TENSEL_MASK BITS(0, 7)
101#define PRCM_TCR_STOP_TIMERS BIT(16)
102#define PRCM_TCR_DOZE_MODE BIT(17)
103
104#define PRCM_CLKOCR 0x1CC
105#define PRCM_CLKOCR_CLKODIV0_SHIFT 0
106#define PRCM_CLKOCR_CLKODIV0_MASK BITS(0, 5)
107#define PRCM_CLKOCR_CLKOSEL0_SHIFT 6
108#define PRCM_CLKOCR_CLKOSEL0_MASK BITS(6, 8)
109#define PRCM_CLKOCR_CLKODIV1_SHIFT 16
110#define PRCM_CLKOCR_CLKODIV1_MASK BITS(16, 21)
111#define PRCM_CLKOCR_CLKOSEL1_SHIFT 22
112#define PRCM_CLKOCR_CLKOSEL1_MASK BITS(22, 24)
113#define PRCM_CLKOCR_CLK1TYPE BIT(28)
114
115#define PRCM_SGACLK_MGT 0x014
116#define PRCM_UARTCLK_MGT 0x018
117#define PRCM_MSP02CLK_MGT 0x01C
118#define PRCM_MSP1CLK_MGT 0x288
119#define PRCM_I2CCLK_MGT 0x020
120#define PRCM_SDMMCCLK_MGT 0x024
121#define PRCM_SLIMCLK_MGT 0x028
122#define PRCM_PER1CLK_MGT 0x02C
123#define PRCM_PER2CLK_MGT 0x030
124#define PRCM_PER3CLK_MGT 0x034
125#define PRCM_PER5CLK_MGT 0x038
126#define PRCM_PER6CLK_MGT 0x03C
127#define PRCM_PER7CLK_MGT 0x040
128#define PRCM_LCDCLK_MGT 0x044
129#define PRCM_BMLCLK_MGT 0x04C
130#define PRCM_HSITXCLK_MGT 0x050
131#define PRCM_HSIRXCLK_MGT 0x054
132#define PRCM_HDMICLK_MGT 0x058
133#define PRCM_APEATCLK_MGT 0x05C
134#define PRCM_APETRACECLK_MGT 0x060
135#define PRCM_MCDECLK_MGT 0x064
136#define PRCM_IPI2CCLK_MGT 0x068
137#define PRCM_DSIALTCLK_MGT 0x06C
138#define PRCM_DMACLK_MGT 0x074
139#define PRCM_B2R2CLK_MGT 0x078
140#define PRCM_TVCLK_MGT 0x07C
141#define PRCM_UNIPROCLK_MGT 0x278
142#define PRCM_SSPCLK_MGT 0x280
143#define PRCM_RNGCLK_MGT 0x284
144#define PRCM_UICCCLK_MGT 0x27C
145
146#define PRCM_CLK_MGT_CLKPLLDIV_MASK BITS(0, 4)
147#define PRCM_CLK_MGT_CLKPLLSW_MASK BITS(5, 7)
148#define PRCM_CLK_MGT_CLKEN BIT(8)
149
150/* ePOD and memory power signal control registers */
151#define PRCM_EPOD_C_SET 0x410
152#define PRCM_SRAM_LS_SLEEP 0x304
153
154/* Debug power control unit registers */
155#define PRCM_POWER_STATE_SET 0x254
156
157/* Miscellaneous unit registers */
158#define PRCM_DSI_SW_RESET 0x324
159#define PRCM_GPIOCR 0x138
160
161/* GPIOCR register */
162#define PRCM_GPIOCR_SPI2_SELECT BIT(23)
163
164#define PRCM_DDR_SUBSYS_APE_MINBW 0x438
165
166#endif /* __DB8500_PRCMU_REGS_H */