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1// SPDX-License-Identifier: GPL-2.0
2// Copyright 2017 NXP
3
4/* INTMUX Block Diagram
5 *
6 * ________________
7 * interrupt source # 0 +---->| |
8 * | | |
9 * interrupt source # 1 +++-->| |
10 * ... | | | channel # 0 |--------->interrupt out # 0
11 * ... | | | |
12 * ... | | | |
13 * interrupt source # X-1 +++-->|________________|
14 * | | |
15 * | | |
16 * | | | ________________
17 * +---->| |
18 * | | | | |
19 * | +-->| |
20 * | | | | channel # 1 |--------->interrupt out # 1
21 * | | +>| |
22 * | | | | |
23 * | | | |________________|
24 * | | |
25 * | | |
26 * | | | ...
27 * | | | ...
28 * | | |
29 * | | | ________________
30 * +---->| |
31 * | | | |
32 * +-->| |
33 * | | channel # N |--------->interrupt out # N
34 * +>| |
35 * | |
36 * |________________|
37 *
38 *
39 * N: Interrupt Channel Instance Number (N=7)
40 * X: Interrupt Source Number for each channel (X=32)
41 *
42 * The INTMUX interrupt multiplexer has 8 channels, each channel receives 32
43 * interrupt sources and generates 1 interrupt output.
44 *
45 */
46
47#include <linux/clk.h>
48#include <linux/interrupt.h>
49#include <linux/irq.h>
50#include <linux/irqchip/chained_irq.h>
51#include <linux/irqdomain.h>
52#include <linux/kernel.h>
53#include <linux/mod_devicetable.h>
54#include <linux/of_irq.h>
55#include <linux/platform_device.h>
56#include <linux/spinlock.h>
57#include <linux/pm_runtime.h>
58
59#define CHANIER(n) (0x10 + (0x40 * n))
60#define CHANIPR(n) (0x20 + (0x40 * n))
61
62#define CHAN_MAX_NUM 0x8
63
64struct intmux_irqchip_data {
65 u32 saved_reg;
66 int chanidx;
67 int irq;
68 struct irq_domain *domain;
69};
70
71struct intmux_data {
72 raw_spinlock_t lock;
73 void __iomem *regs;
74 struct clk *ipg_clk;
75 int channum;
76 struct intmux_irqchip_data irqchip_data[] __counted_by(channum);
77};
78
79static void imx_intmux_irq_mask(struct irq_data *d)
80{
81 struct intmux_irqchip_data *irqchip_data = d->chip_data;
82 int idx = irqchip_data->chanidx;
83 struct intmux_data *data = container_of(irqchip_data, struct intmux_data,
84 irqchip_data[idx]);
85 unsigned long flags;
86 void __iomem *reg;
87 u32 val;
88
89 raw_spin_lock_irqsave(&data->lock, flags);
90 reg = data->regs + CHANIER(idx);
91 val = readl_relaxed(reg);
92 /* disable the interrupt source of this channel */
93 val &= ~BIT(d->hwirq);
94 writel_relaxed(val, reg);
95 raw_spin_unlock_irqrestore(&data->lock, flags);
96}
97
98static void imx_intmux_irq_unmask(struct irq_data *d)
99{
100 struct intmux_irqchip_data *irqchip_data = d->chip_data;
101 int idx = irqchip_data->chanidx;
102 struct intmux_data *data = container_of(irqchip_data, struct intmux_data,
103 irqchip_data[idx]);
104 unsigned long flags;
105 void __iomem *reg;
106 u32 val;
107
108 raw_spin_lock_irqsave(&data->lock, flags);
109 reg = data->regs + CHANIER(idx);
110 val = readl_relaxed(reg);
111 /* enable the interrupt source of this channel */
112 val |= BIT(d->hwirq);
113 writel_relaxed(val, reg);
114 raw_spin_unlock_irqrestore(&data->lock, flags);
115}
116
117static struct irq_chip imx_intmux_irq_chip __ro_after_init = {
118 .name = "intmux",
119 .irq_mask = imx_intmux_irq_mask,
120 .irq_unmask = imx_intmux_irq_unmask,
121};
122
123static int imx_intmux_irq_map(struct irq_domain *h, unsigned int irq,
124 irq_hw_number_t hwirq)
125{
126 struct intmux_irqchip_data *data = h->host_data;
127
128 irq_set_chip_data(irq, data);
129 irq_set_chip_and_handler(irq, &imx_intmux_irq_chip, handle_level_irq);
130
131 return 0;
132}
133
134static int imx_intmux_irq_xlate(struct irq_domain *d, struct device_node *node,
135 const u32 *intspec, unsigned int intsize,
136 unsigned long *out_hwirq, unsigned int *out_type)
137{
138 struct intmux_irqchip_data *irqchip_data = d->host_data;
139 int idx = irqchip_data->chanidx;
140 struct intmux_data *data = container_of(irqchip_data, struct intmux_data,
141 irqchip_data[idx]);
142
143 /*
144 * two cells needed in interrupt specifier:
145 * the 1st cell: hw interrupt number
146 * the 2nd cell: channel index
147 */
148 if (WARN_ON(intsize != 2))
149 return -EINVAL;
150
151 if (WARN_ON(intspec[1] >= data->channum))
152 return -EINVAL;
153
154 *out_hwirq = intspec[0];
155 *out_type = IRQ_TYPE_LEVEL_HIGH;
156
157 return 0;
158}
159
160static int imx_intmux_irq_select(struct irq_domain *d, struct irq_fwspec *fwspec,
161 enum irq_domain_bus_token bus_token)
162{
163 struct intmux_irqchip_data *irqchip_data = d->host_data;
164
165 /* Not for us */
166 if (fwspec->fwnode != d->fwnode)
167 return false;
168
169 return irqchip_data->chanidx == fwspec->param[1];
170}
171
172static const struct irq_domain_ops imx_intmux_domain_ops = {
173 .map = imx_intmux_irq_map,
174 .xlate = imx_intmux_irq_xlate,
175 .select = imx_intmux_irq_select,
176};
177
178static void imx_intmux_irq_handler(struct irq_desc *desc)
179{
180 struct intmux_irqchip_data *irqchip_data = irq_desc_get_handler_data(desc);
181 int idx = irqchip_data->chanidx;
182 struct intmux_data *data = container_of(irqchip_data, struct intmux_data,
183 irqchip_data[idx]);
184 unsigned long irqstat;
185 int pos;
186
187 chained_irq_enter(irq_desc_get_chip(desc), desc);
188
189 /* read the interrupt source pending status of this channel */
190 irqstat = readl_relaxed(data->regs + CHANIPR(idx));
191
192 for_each_set_bit(pos, &irqstat, 32)
193 generic_handle_domain_irq(irqchip_data->domain, pos);
194
195 chained_irq_exit(irq_desc_get_chip(desc), desc);
196}
197
198static int imx_intmux_probe(struct platform_device *pdev)
199{
200 struct device_node *np = pdev->dev.of_node;
201 struct irq_domain *domain;
202 struct intmux_data *data;
203 int channum;
204 int i, ret;
205
206 channum = platform_irq_count(pdev);
207 if (channum == -EPROBE_DEFER) {
208 return -EPROBE_DEFER;
209 } else if (channum > CHAN_MAX_NUM) {
210 dev_err(&pdev->dev, "supports up to %d multiplex channels\n",
211 CHAN_MAX_NUM);
212 return -EINVAL;
213 }
214
215 data = devm_kzalloc(&pdev->dev, struct_size(data, irqchip_data, channum), GFP_KERNEL);
216 if (!data)
217 return -ENOMEM;
218
219 data->regs = devm_platform_ioremap_resource(pdev, 0);
220 if (IS_ERR(data->regs)) {
221 dev_err(&pdev->dev, "failed to initialize reg\n");
222 return PTR_ERR(data->regs);
223 }
224
225 data->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
226 if (IS_ERR(data->ipg_clk))
227 return dev_err_probe(&pdev->dev, PTR_ERR(data->ipg_clk),
228 "failed to get ipg clk\n");
229
230 data->channum = channum;
231 raw_spin_lock_init(&data->lock);
232
233 pm_runtime_get_noresume(&pdev->dev);
234 pm_runtime_set_active(&pdev->dev);
235 pm_runtime_enable(&pdev->dev);
236
237 ret = clk_prepare_enable(data->ipg_clk);
238 if (ret) {
239 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
240 return ret;
241 }
242
243 for (i = 0; i < channum; i++) {
244 data->irqchip_data[i].chanidx = i;
245
246 data->irqchip_data[i].irq = irq_of_parse_and_map(np, i);
247 if (data->irqchip_data[i].irq <= 0) {
248 ret = -EINVAL;
249 dev_err(&pdev->dev, "failed to get irq\n");
250 goto out;
251 }
252
253 domain = irq_domain_add_linear(np, 32, &imx_intmux_domain_ops,
254 &data->irqchip_data[i]);
255 if (!domain) {
256 ret = -ENOMEM;
257 dev_err(&pdev->dev, "failed to create IRQ domain\n");
258 goto out;
259 }
260 data->irqchip_data[i].domain = domain;
261 irq_domain_set_pm_device(domain, &pdev->dev);
262
263 /* disable all interrupt sources of this channel firstly */
264 writel_relaxed(0, data->regs + CHANIER(i));
265
266 irq_set_chained_handler_and_data(data->irqchip_data[i].irq,
267 imx_intmux_irq_handler,
268 &data->irqchip_data[i]);
269 }
270
271 platform_set_drvdata(pdev, data);
272
273 /*
274 * Let pm_runtime_put() disable clock.
275 * If CONFIG_PM is not enabled, the clock will stay powered.
276 */
277 pm_runtime_put(&pdev->dev);
278
279 return 0;
280out:
281 clk_disable_unprepare(data->ipg_clk);
282 return ret;
283}
284
285static int imx_intmux_remove(struct platform_device *pdev)
286{
287 struct intmux_data *data = platform_get_drvdata(pdev);
288 int i;
289
290 for (i = 0; i < data->channum; i++) {
291 /* disable all interrupt sources of this channel */
292 writel_relaxed(0, data->regs + CHANIER(i));
293
294 irq_set_chained_handler_and_data(data->irqchip_data[i].irq,
295 NULL, NULL);
296
297 irq_domain_remove(data->irqchip_data[i].domain);
298 }
299
300 pm_runtime_disable(&pdev->dev);
301
302 return 0;
303}
304
305#ifdef CONFIG_PM
306static int imx_intmux_runtime_suspend(struct device *dev)
307{
308 struct intmux_data *data = dev_get_drvdata(dev);
309 struct intmux_irqchip_data *irqchip_data;
310 int i;
311
312 for (i = 0; i < data->channum; i++) {
313 irqchip_data = &data->irqchip_data[i];
314 irqchip_data->saved_reg = readl_relaxed(data->regs + CHANIER(i));
315 }
316
317 clk_disable_unprepare(data->ipg_clk);
318
319 return 0;
320}
321
322static int imx_intmux_runtime_resume(struct device *dev)
323{
324 struct intmux_data *data = dev_get_drvdata(dev);
325 struct intmux_irqchip_data *irqchip_data;
326 int ret, i;
327
328 ret = clk_prepare_enable(data->ipg_clk);
329 if (ret) {
330 dev_err(dev, "failed to enable ipg clk: %d\n", ret);
331 return ret;
332 }
333
334 for (i = 0; i < data->channum; i++) {
335 irqchip_data = &data->irqchip_data[i];
336 writel_relaxed(irqchip_data->saved_reg, data->regs + CHANIER(i));
337 }
338
339 return 0;
340}
341#endif
342
343static const struct dev_pm_ops imx_intmux_pm_ops = {
344 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
345 pm_runtime_force_resume)
346 SET_RUNTIME_PM_OPS(imx_intmux_runtime_suspend,
347 imx_intmux_runtime_resume, NULL)
348};
349
350static const struct of_device_id imx_intmux_id[] = {
351 { .compatible = "fsl,imx-intmux", },
352 { /* sentinel */ },
353};
354
355static struct platform_driver imx_intmux_driver = {
356 .driver = {
357 .name = "imx-intmux",
358 .of_match_table = imx_intmux_id,
359 .pm = &imx_intmux_pm_ops,
360 },
361 .probe = imx_intmux_probe,
362 .remove = imx_intmux_remove,
363};
364builtin_platform_driver(imx_intmux_driver);