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1/*
2 * Copyright (c) 2010 - 2017 Intel Corporation. All rights reserved.
3 * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#include <linux/pci.h>
35#include <linux/io.h>
36#include <linux/delay.h>
37#include <linux/vmalloc.h>
38#include <linux/module.h>
39
40#include "qib.h"
41
42/*
43 * This file contains PCIe utility routines that are common to the
44 * various QLogic InfiniPath adapters
45 */
46
47/*
48 * Code to adjust PCIe capabilities.
49 * To minimize the change footprint, we call it
50 * from qib_pcie_params, which every chip-specific
51 * file calls, even though this violates some
52 * expectations of harmlessness.
53 */
54static void qib_tune_pcie_caps(struct qib_devdata *);
55static void qib_tune_pcie_coalesce(struct qib_devdata *);
56
57/*
58 * Do all the common PCIe setup and initialization.
59 * devdata is not yet allocated, and is not allocated until after this
60 * routine returns success. Therefore qib_dev_err() can't be used for error
61 * printing.
62 */
63int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent)
64{
65 int ret;
66
67 ret = pci_enable_device(pdev);
68 if (ret) {
69 /*
70 * This can happen (in theory) iff:
71 * We did a chip reset, and then failed to reprogram the
72 * BAR, or the chip reset due to an internal error. We then
73 * unloaded the driver and reloaded it.
74 *
75 * Both reset cases set the BAR back to initial state. For
76 * the latter case, the AER sticky error bit at offset 0x718
77 * should be set, but the Linux kernel doesn't yet know
78 * about that, it appears. If the original BAR was retained
79 * in the kernel data structures, this may be OK.
80 */
81 qib_early_err(&pdev->dev, "pci enable failed: error %d\n",
82 -ret);
83 goto done;
84 }
85
86 ret = pci_request_regions(pdev, QIB_DRV_NAME);
87 if (ret) {
88 qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret);
89 goto bail;
90 }
91
92 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
93 if (ret) {
94 /*
95 * If the 64 bit setup fails, try 32 bit. Some systems
96 * do not setup 64 bit maps on systems with 2GB or less
97 * memory installed.
98 */
99 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
100 if (ret) {
101 qib_devinfo(pdev, "Unable to set DMA mask: %d\n", ret);
102 goto bail;
103 }
104 }
105
106 pci_set_master(pdev);
107 goto done;
108
109bail:
110 pci_disable_device(pdev);
111 pci_release_regions(pdev);
112done:
113 return ret;
114}
115
116/*
117 * Do remaining PCIe setup, once dd is allocated, and save away
118 * fields required to re-initialize after a chip reset, or for
119 * various other purposes
120 */
121int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev,
122 const struct pci_device_id *ent)
123{
124 unsigned long len;
125 resource_size_t addr;
126
127 dd->pcidev = pdev;
128 pci_set_drvdata(pdev, dd);
129
130 addr = pci_resource_start(pdev, 0);
131 len = pci_resource_len(pdev, 0);
132
133 dd->kregbase = ioremap(addr, len);
134 if (!dd->kregbase)
135 return -ENOMEM;
136
137 dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len);
138 dd->physaddr = addr; /* used for io_remap, etc. */
139
140 /*
141 * Save BARs to rewrite after device reset. Save all 64 bits of
142 * BAR, just in case.
143 */
144 dd->pcibar0 = addr;
145 dd->pcibar1 = addr >> 32;
146 dd->deviceid = ent->device; /* save for later use */
147 dd->vendorid = ent->vendor;
148
149 return 0;
150}
151
152/*
153 * Do PCIe cleanup, after chip-specific cleanup, etc. Just prior
154 * to releasing the dd memory.
155 * void because none of the core pcie cleanup returns are void
156 */
157void qib_pcie_ddcleanup(struct qib_devdata *dd)
158{
159 u64 __iomem *base = (void __iomem *) dd->kregbase;
160
161 dd->kregbase = NULL;
162 iounmap(base);
163 if (dd->piobase)
164 iounmap(dd->piobase);
165 if (dd->userbase)
166 iounmap(dd->userbase);
167 if (dd->piovl15base)
168 iounmap(dd->piovl15base);
169
170 pci_disable_device(dd->pcidev);
171 pci_release_regions(dd->pcidev);
172
173 pci_set_drvdata(dd->pcidev, NULL);
174}
175
176/*
177 * We save the msi lo and hi values, so we can restore them after
178 * chip reset (the kernel PCI infrastructure doesn't yet handle that
179 * correctly.
180 */
181static void qib_cache_msi_info(struct qib_devdata *dd, int pos)
182{
183 struct pci_dev *pdev = dd->pcidev;
184 u16 control;
185
186 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO, &dd->msi_lo);
187 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI, &dd->msi_hi);
188 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
189
190 /* now save the data (vector) info */
191 pci_read_config_word(pdev,
192 pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
193 &dd->msi_data);
194}
195
196int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent)
197{
198 u16 linkstat, speed;
199 int nvec;
200 int maxvec;
201 unsigned int flags = PCI_IRQ_MSIX | PCI_IRQ_MSI;
202
203 if (!pci_is_pcie(dd->pcidev)) {
204 qib_dev_err(dd, "Can't find PCI Express capability!\n");
205 /* set up something... */
206 dd->lbus_width = 1;
207 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
208 nvec = -1;
209 goto bail;
210 }
211
212 if (dd->flags & QIB_HAS_INTX)
213 flags |= PCI_IRQ_LEGACY;
214 maxvec = (nent && *nent) ? *nent : 1;
215 nvec = pci_alloc_irq_vectors(dd->pcidev, 1, maxvec, flags);
216 if (nvec < 0)
217 goto bail;
218
219 /*
220 * If nent exists, make sure to record how many vectors were allocated.
221 * If msix_enabled is false, return 0 so the fallback code works
222 * correctly.
223 */
224 if (nent)
225 *nent = !dd->pcidev->msix_enabled ? 0 : nvec;
226
227 if (dd->pcidev->msi_enabled)
228 qib_cache_msi_info(dd, dd->pcidev->msi_cap);
229
230 pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
231 /*
232 * speed is bits 0-3, linkwidth is bits 4-8
233 * no defines for them in headers
234 */
235 speed = linkstat & 0xf;
236 linkstat >>= 4;
237 linkstat &= 0x1f;
238 dd->lbus_width = linkstat;
239
240 switch (speed) {
241 case 1:
242 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
243 break;
244 case 2:
245 dd->lbus_speed = 5000; /* Gen1, 5GHz */
246 break;
247 default: /* not defined, assume gen1 */
248 dd->lbus_speed = 2500;
249 break;
250 }
251
252 /*
253 * Check against expected pcie width and complain if "wrong"
254 * on first initialization, not afterwards (i.e., reset).
255 */
256 if (minw && linkstat < minw)
257 qib_dev_err(dd,
258 "PCIe width %u (x%u HCA), performance reduced\n",
259 linkstat, minw);
260
261 qib_tune_pcie_caps(dd);
262
263 qib_tune_pcie_coalesce(dd);
264
265bail:
266 /* fill in string, even on errors */
267 snprintf(dd->lbus_info, sizeof(dd->lbus_info),
268 "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width);
269 return nvec < 0 ? nvec : 0;
270}
271
272/**
273 * qib_free_irq - Cleanup INTx and MSI interrupts
274 * @dd: valid pointer to qib dev data
275 *
276 * Since cleanup for INTx and MSI interrupts is trivial, have a common
277 * routine.
278 *
279 */
280void qib_free_irq(struct qib_devdata *dd)
281{
282 pci_free_irq(dd->pcidev, 0, dd);
283 pci_free_irq_vectors(dd->pcidev);
284}
285
286/*
287 * Setup pcie interrupt stuff again after a reset. I'd like to just call
288 * pci_enable_msi() again for msi, but when I do that,
289 * the MSI enable bit doesn't get set in the command word, and
290 * we switch to a different interrupt vector, which is confusing,
291 * so I instead just do it all inline. Perhaps somehow can tie this
292 * into the PCIe hotplug support at some point
293 */
294int qib_reinit_intr(struct qib_devdata *dd)
295{
296 int pos;
297 u16 control;
298 int ret = 0;
299
300 /* If we aren't using MSI, don't restore it */
301 if (!dd->msi_lo)
302 goto bail;
303
304 pos = dd->pcidev->msi_cap;
305 if (!pos) {
306 qib_dev_err(dd,
307 "Can't find MSI capability, can't restore MSI settings\n");
308 ret = 0;
309 /* nothing special for MSIx, just MSI */
310 goto bail;
311 }
312 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
313 dd->msi_lo);
314 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
315 dd->msi_hi);
316 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
317 if (!(control & PCI_MSI_FLAGS_ENABLE)) {
318 control |= PCI_MSI_FLAGS_ENABLE;
319 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
320 control);
321 }
322 /* now rewrite the data (vector) info */
323 pci_write_config_word(dd->pcidev, pos +
324 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
325 dd->msi_data);
326 ret = 1;
327bail:
328 qib_free_irq(dd);
329
330 if (!ret && (dd->flags & QIB_HAS_INTX))
331 ret = 1;
332
333 /* and now set the pci master bit again */
334 pci_set_master(dd->pcidev);
335
336 return ret;
337}
338
339/*
340 * These two routines are helper routines for the device reset code
341 * to move all the pcie code out of the chip-specific driver code.
342 */
343void qib_pcie_getcmd(struct qib_devdata *dd, u16 *cmd, u8 *iline, u8 *cline)
344{
345 pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd);
346 pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
347 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
348}
349
350void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline)
351{
352 int r;
353
354 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
355 dd->pcibar0);
356 if (r)
357 qib_dev_err(dd, "rewrite of BAR0 failed: %d\n", r);
358 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
359 dd->pcibar1);
360 if (r)
361 qib_dev_err(dd, "rewrite of BAR1 failed: %d\n", r);
362 /* now re-enable memory access, and restore cosmetic settings */
363 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd);
364 pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
365 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
366 r = pci_enable_device(dd->pcidev);
367 if (r)
368 qib_dev_err(dd,
369 "pci_enable_device failed after reset: %d\n", r);
370}
371
372
373static int qib_pcie_coalesce;
374module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO);
375MODULE_PARM_DESC(pcie_coalesce, "tune PCIe coalescing on some Intel chipsets");
376
377/*
378 * Enable PCIe completion and data coalescing, on Intel 5x00 and 7300
379 * chipsets. This is known to be unsafe for some revisions of some
380 * of these chipsets, with some BIOS settings, and enabling it on those
381 * systems may result in the system crashing, and/or data corruption.
382 */
383static void qib_tune_pcie_coalesce(struct qib_devdata *dd)
384{
385 struct pci_dev *parent;
386 u16 devid;
387 u32 mask, bits, val;
388
389 if (!qib_pcie_coalesce)
390 return;
391
392 /* Find out supported and configured values for parent (root) */
393 parent = dd->pcidev->bus->self;
394 if (parent->bus->parent) {
395 qib_devinfo(dd->pcidev, "Parent not root\n");
396 return;
397 }
398 if (!pci_is_pcie(parent))
399 return;
400 if (parent->vendor != 0x8086)
401 return;
402
403 /*
404 * - bit 12: Max_rdcmp_Imt_EN: need to set to 1
405 * - bit 11: COALESCE_FORCE: need to set to 0
406 * - bit 10: COALESCE_EN: need to set to 1
407 * (but limitations on some on some chipsets)
408 *
409 * On the Intel 5000, 5100, and 7300 chipsets, there is
410 * also: - bit 25:24: COALESCE_MODE, need to set to 0
411 */
412 devid = parent->device;
413 if (devid >= 0x25e2 && devid <= 0x25fa) {
414 /* 5000 P/V/X/Z */
415 if (parent->revision <= 0xb2)
416 bits = 1U << 10;
417 else
418 bits = 7U << 10;
419 mask = (3U << 24) | (7U << 10);
420 } else if (devid >= 0x65e2 && devid <= 0x65fa) {
421 /* 5100 */
422 bits = 1U << 10;
423 mask = (3U << 24) | (7U << 10);
424 } else if (devid >= 0x4021 && devid <= 0x402e) {
425 /* 5400 */
426 bits = 7U << 10;
427 mask = 7U << 10;
428 } else if (devid >= 0x3604 && devid <= 0x360a) {
429 /* 7300 */
430 bits = 7U << 10;
431 mask = (3U << 24) | (7U << 10);
432 } else {
433 /* not one of the chipsets that we know about */
434 return;
435 }
436 pci_read_config_dword(parent, 0x48, &val);
437 val &= ~mask;
438 val |= bits;
439 pci_write_config_dword(parent, 0x48, val);
440}
441
442/*
443 * BIOS may not set PCIe bus-utilization parameters for best performance.
444 * Check and optionally adjust them to maximize our throughput.
445 */
446static int qib_pcie_caps;
447module_param_named(pcie_caps, qib_pcie_caps, int, S_IRUGO);
448MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)");
449
450static void qib_tune_pcie_caps(struct qib_devdata *dd)
451{
452 struct pci_dev *parent;
453 u16 rc_mpss, rc_mps, ep_mpss, ep_mps;
454 u16 rc_mrrs, ep_mrrs, max_mrrs;
455
456 /* Find out supported and configured values for parent (root) */
457 parent = dd->pcidev->bus->self;
458 if (!pci_is_root_bus(parent->bus)) {
459 qib_devinfo(dd->pcidev, "Parent not root\n");
460 return;
461 }
462
463 if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))
464 return;
465
466 rc_mpss = parent->pcie_mpss;
467 rc_mps = ffs(pcie_get_mps(parent)) - 8;
468 /* Find out supported and configured values for endpoint (us) */
469 ep_mpss = dd->pcidev->pcie_mpss;
470 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;
471
472 /* Find max payload supported by root, endpoint */
473 if (rc_mpss > ep_mpss)
474 rc_mpss = ep_mpss;
475
476 /* If Supported greater than limit in module param, limit it */
477 if (rc_mpss > (qib_pcie_caps & 7))
478 rc_mpss = qib_pcie_caps & 7;
479 /* If less than (allowed, supported), bump root payload */
480 if (rc_mpss > rc_mps) {
481 rc_mps = rc_mpss;
482 pcie_set_mps(parent, 128 << rc_mps);
483 }
484 /* If less than (allowed, supported), bump endpoint payload */
485 if (rc_mpss > ep_mps) {
486 ep_mps = rc_mpss;
487 pcie_set_mps(dd->pcidev, 128 << ep_mps);
488 }
489
490 /*
491 * Now the Read Request size.
492 * No field for max supported, but PCIe spec limits it to 4096,
493 * which is code '5' (log2(4096) - 7)
494 */
495 max_mrrs = 5;
496 if (max_mrrs > ((qib_pcie_caps >> 4) & 7))
497 max_mrrs = (qib_pcie_caps >> 4) & 7;
498
499 max_mrrs = 128 << max_mrrs;
500 rc_mrrs = pcie_get_readrq(parent);
501 ep_mrrs = pcie_get_readrq(dd->pcidev);
502
503 if (max_mrrs > rc_mrrs) {
504 rc_mrrs = max_mrrs;
505 pcie_set_readrq(parent, rc_mrrs);
506 }
507 if (max_mrrs > ep_mrrs) {
508 ep_mrrs = max_mrrs;
509 pcie_set_readrq(dd->pcidev, ep_mrrs);
510 }
511}
512/* End of PCIe capability tuning */
513
514/*
515 * From here through qib_pci_err_handler definition is invoked via
516 * PCI error infrastructure, registered via pci
517 */
518static pci_ers_result_t
519qib_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
520{
521 struct qib_devdata *dd = pci_get_drvdata(pdev);
522 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
523
524 switch (state) {
525 case pci_channel_io_normal:
526 qib_devinfo(pdev, "State Normal, ignoring\n");
527 break;
528
529 case pci_channel_io_frozen:
530 qib_devinfo(pdev, "State Frozen, requesting reset\n");
531 pci_disable_device(pdev);
532 ret = PCI_ERS_RESULT_NEED_RESET;
533 break;
534
535 case pci_channel_io_perm_failure:
536 qib_devinfo(pdev, "State Permanent Failure, disabling\n");
537 if (dd) {
538 /* no more register accesses! */
539 dd->flags &= ~QIB_PRESENT;
540 qib_disable_after_error(dd);
541 }
542 /* else early, or other problem */
543 ret = PCI_ERS_RESULT_DISCONNECT;
544 break;
545
546 default: /* shouldn't happen */
547 qib_devinfo(pdev, "QIB PCI errors detected (state %d)\n",
548 state);
549 break;
550 }
551 return ret;
552}
553
554static pci_ers_result_t
555qib_pci_mmio_enabled(struct pci_dev *pdev)
556{
557 u64 words = 0U;
558 struct qib_devdata *dd = pci_get_drvdata(pdev);
559 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
560
561 if (dd && dd->pport) {
562 words = dd->f_portcntr(dd->pport, QIBPORTCNTR_WORDRCV);
563 if (words == ~0ULL)
564 ret = PCI_ERS_RESULT_NEED_RESET;
565 }
566 qib_devinfo(pdev,
567 "QIB mmio_enabled function called, read wordscntr %Lx, returning %d\n",
568 words, ret);
569 return ret;
570}
571
572static pci_ers_result_t
573qib_pci_slot_reset(struct pci_dev *pdev)
574{
575 qib_devinfo(pdev, "QIB slot_reset function called, ignored\n");
576 return PCI_ERS_RESULT_CAN_RECOVER;
577}
578
579static void
580qib_pci_resume(struct pci_dev *pdev)
581{
582 struct qib_devdata *dd = pci_get_drvdata(pdev);
583
584 qib_devinfo(pdev, "QIB resume function called\n");
585 /*
586 * Running jobs will fail, since it's asynchronous
587 * unlike sysfs-requested reset. Better than
588 * doing nothing.
589 */
590 qib_init(dd, 1); /* same as re-init after reset */
591}
592
593const struct pci_error_handlers qib_pci_err_handler = {
594 .error_detected = qib_pci_error_detected,
595 .mmio_enabled = qib_pci_mmio_enabled,
596 .slot_reset = qib_pci_slot_reset,
597 .resume = qib_pci_resume,
598};
1/*
2 * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/pci.h>
34#include <linux/io.h>
35#include <linux/delay.h>
36#include <linux/vmalloc.h>
37#include <linux/aer.h>
38
39#include "qib.h"
40
41/*
42 * This file contains PCIe utility routines that are common to the
43 * various QLogic InfiniPath adapters
44 */
45
46/*
47 * Code to adjust PCIe capabilities.
48 * To minimize the change footprint, we call it
49 * from qib_pcie_params, which every chip-specific
50 * file calls, even though this violates some
51 * expectations of harmlessness.
52 */
53static int qib_tune_pcie_caps(struct qib_devdata *);
54static int qib_tune_pcie_coalesce(struct qib_devdata *);
55
56/*
57 * Do all the common PCIe setup and initialization.
58 * devdata is not yet allocated, and is not allocated until after this
59 * routine returns success. Therefore qib_dev_err() can't be used for error
60 * printing.
61 */
62int qib_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent)
63{
64 int ret;
65
66 ret = pci_enable_device(pdev);
67 if (ret) {
68 /*
69 * This can happen (in theory) iff:
70 * We did a chip reset, and then failed to reprogram the
71 * BAR, or the chip reset due to an internal error. We then
72 * unloaded the driver and reloaded it.
73 *
74 * Both reset cases set the BAR back to initial state. For
75 * the latter case, the AER sticky error bit at offset 0x718
76 * should be set, but the Linux kernel doesn't yet know
77 * about that, it appears. If the original BAR was retained
78 * in the kernel data structures, this may be OK.
79 */
80 qib_early_err(&pdev->dev, "pci enable failed: error %d\n",
81 -ret);
82 goto done;
83 }
84
85 ret = pci_request_regions(pdev, QIB_DRV_NAME);
86 if (ret) {
87 qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret);
88 goto bail;
89 }
90
91 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
92 if (ret) {
93 /*
94 * If the 64 bit setup fails, try 32 bit. Some systems
95 * do not setup 64 bit maps on systems with 2GB or less
96 * memory installed.
97 */
98 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
99 if (ret) {
100 qib_devinfo(pdev, "Unable to set DMA mask: %d\n", ret);
101 goto bail;
102 }
103 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
104 } else
105 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
106 if (ret) {
107 qib_early_err(&pdev->dev,
108 "Unable to set DMA consistent mask: %d\n", ret);
109 goto bail;
110 }
111
112 pci_set_master(pdev);
113 ret = pci_enable_pcie_error_reporting(pdev);
114 if (ret) {
115 qib_early_err(&pdev->dev,
116 "Unable to enable pcie error reporting: %d\n",
117 ret);
118 ret = 0;
119 }
120 goto done;
121
122bail:
123 pci_disable_device(pdev);
124 pci_release_regions(pdev);
125done:
126 return ret;
127}
128
129/*
130 * Do remaining PCIe setup, once dd is allocated, and save away
131 * fields required to re-initialize after a chip reset, or for
132 * various other purposes
133 */
134int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev,
135 const struct pci_device_id *ent)
136{
137 unsigned long len;
138 resource_size_t addr;
139
140 dd->pcidev = pdev;
141 pci_set_drvdata(pdev, dd);
142
143 addr = pci_resource_start(pdev, 0);
144 len = pci_resource_len(pdev, 0);
145
146#if defined(__powerpc__)
147 /* There isn't a generic way to specify writethrough mappings */
148 dd->kregbase = __ioremap(addr, len, _PAGE_NO_CACHE | _PAGE_WRITETHRU);
149#else
150 dd->kregbase = ioremap_nocache(addr, len);
151#endif
152
153 if (!dd->kregbase)
154 return -ENOMEM;
155
156 dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len);
157 dd->physaddr = addr; /* used for io_remap, etc. */
158
159 /*
160 * Save BARs to rewrite after device reset. Save all 64 bits of
161 * BAR, just in case.
162 */
163 dd->pcibar0 = addr;
164 dd->pcibar1 = addr >> 32;
165 dd->deviceid = ent->device; /* save for later use */
166 dd->vendorid = ent->vendor;
167
168 return 0;
169}
170
171/*
172 * Do PCIe cleanup, after chip-specific cleanup, etc. Just prior
173 * to releasing the dd memory.
174 * void because none of the core pcie cleanup returns are void
175 */
176void qib_pcie_ddcleanup(struct qib_devdata *dd)
177{
178 u64 __iomem *base = (void __iomem *) dd->kregbase;
179
180 dd->kregbase = NULL;
181 iounmap(base);
182 if (dd->piobase)
183 iounmap(dd->piobase);
184 if (dd->userbase)
185 iounmap(dd->userbase);
186 if (dd->piovl15base)
187 iounmap(dd->piovl15base);
188
189 pci_disable_device(dd->pcidev);
190 pci_release_regions(dd->pcidev);
191
192 pci_set_drvdata(dd->pcidev, NULL);
193}
194
195static void qib_msix_setup(struct qib_devdata *dd, int pos, u32 *msixcnt,
196 struct msix_entry *msix_entry)
197{
198 int ret;
199 u32 tabsize = 0;
200 u16 msix_flags;
201
202 pci_read_config_word(dd->pcidev, pos + PCI_MSIX_FLAGS, &msix_flags);
203 tabsize = 1 + (msix_flags & PCI_MSIX_FLAGS_QSIZE);
204 if (tabsize > *msixcnt)
205 tabsize = *msixcnt;
206 ret = pci_enable_msix(dd->pcidev, msix_entry, tabsize);
207 if (ret > 0) {
208 tabsize = ret;
209 ret = pci_enable_msix(dd->pcidev, msix_entry, tabsize);
210 }
211 if (ret) {
212 qib_dev_err(dd, "pci_enable_msix %d vectors failed: %d, "
213 "falling back to INTx\n", tabsize, ret);
214 tabsize = 0;
215 }
216 *msixcnt = tabsize;
217
218 if (ret)
219 qib_enable_intx(dd->pcidev);
220
221}
222
223/**
224 * We save the msi lo and hi values, so we can restore them after
225 * chip reset (the kernel PCI infrastructure doesn't yet handle that
226 * correctly.
227 */
228static int qib_msi_setup(struct qib_devdata *dd, int pos)
229{
230 struct pci_dev *pdev = dd->pcidev;
231 u16 control;
232 int ret;
233
234 ret = pci_enable_msi(pdev);
235 if (ret)
236 qib_dev_err(dd, "pci_enable_msi failed: %d, "
237 "interrupts may not work\n", ret);
238 /* continue even if it fails, we may still be OK... */
239
240 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO,
241 &dd->msi_lo);
242 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI,
243 &dd->msi_hi);
244 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
245 /* now save the data (vector) info */
246 pci_read_config_word(pdev, pos + ((control & PCI_MSI_FLAGS_64BIT)
247 ? 12 : 8),
248 &dd->msi_data);
249 return ret;
250}
251
252int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent,
253 struct msix_entry *entry)
254{
255 u16 linkstat, speed;
256 int pos = 0, pose, ret = 1;
257
258 pose = pci_pcie_cap(dd->pcidev);
259 if (!pose) {
260 qib_dev_err(dd, "Can't find PCI Express capability!\n");
261 /* set up something... */
262 dd->lbus_width = 1;
263 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
264 goto bail;
265 }
266
267 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSIX);
268 if (nent && *nent && pos) {
269 qib_msix_setup(dd, pos, nent, entry);
270 ret = 0; /* did it, either MSIx or INTx */
271 } else {
272 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI);
273 if (pos)
274 ret = qib_msi_setup(dd, pos);
275 else
276 qib_dev_err(dd, "No PCI MSI or MSIx capability!\n");
277 }
278 if (!pos)
279 qib_enable_intx(dd->pcidev);
280
281 pci_read_config_word(dd->pcidev, pose + PCI_EXP_LNKSTA, &linkstat);
282 /*
283 * speed is bits 0-3, linkwidth is bits 4-8
284 * no defines for them in headers
285 */
286 speed = linkstat & 0xf;
287 linkstat >>= 4;
288 linkstat &= 0x1f;
289 dd->lbus_width = linkstat;
290
291 switch (speed) {
292 case 1:
293 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */
294 break;
295 case 2:
296 dd->lbus_speed = 5000; /* Gen1, 5GHz */
297 break;
298 default: /* not defined, assume gen1 */
299 dd->lbus_speed = 2500;
300 break;
301 }
302
303 /*
304 * Check against expected pcie width and complain if "wrong"
305 * on first initialization, not afterwards (i.e., reset).
306 */
307 if (minw && linkstat < minw)
308 qib_dev_err(dd,
309 "PCIe width %u (x%u HCA), performance reduced\n",
310 linkstat, minw);
311
312 qib_tune_pcie_caps(dd);
313
314 qib_tune_pcie_coalesce(dd);
315
316bail:
317 /* fill in string, even on errors */
318 snprintf(dd->lbus_info, sizeof(dd->lbus_info),
319 "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width);
320 return ret;
321}
322
323/*
324 * Setup pcie interrupt stuff again after a reset. I'd like to just call
325 * pci_enable_msi() again for msi, but when I do that,
326 * the MSI enable bit doesn't get set in the command word, and
327 * we switch to to a different interrupt vector, which is confusing,
328 * so I instead just do it all inline. Perhaps somehow can tie this
329 * into the PCIe hotplug support at some point
330 */
331int qib_reinit_intr(struct qib_devdata *dd)
332{
333 int pos;
334 u16 control;
335 int ret = 0;
336
337 /* If we aren't using MSI, don't restore it */
338 if (!dd->msi_lo)
339 goto bail;
340
341 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI);
342 if (!pos) {
343 qib_dev_err(dd, "Can't find MSI capability, "
344 "can't restore MSI settings\n");
345 ret = 0;
346 /* nothing special for MSIx, just MSI */
347 goto bail;
348 }
349 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
350 dd->msi_lo);
351 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
352 dd->msi_hi);
353 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
354 if (!(control & PCI_MSI_FLAGS_ENABLE)) {
355 control |= PCI_MSI_FLAGS_ENABLE;
356 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
357 control);
358 }
359 /* now rewrite the data (vector) info */
360 pci_write_config_word(dd->pcidev, pos +
361 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
362 dd->msi_data);
363 ret = 1;
364bail:
365 if (!ret && (dd->flags & QIB_HAS_INTX)) {
366 qib_enable_intx(dd->pcidev);
367 ret = 1;
368 }
369
370 /* and now set the pci master bit again */
371 pci_set_master(dd->pcidev);
372
373 return ret;
374}
375
376/*
377 * Disable msi interrupt if enabled, and clear msi_lo.
378 * This is used primarily for the fallback to INTx, but
379 * is also used in reinit after reset, and during cleanup.
380 */
381void qib_nomsi(struct qib_devdata *dd)
382{
383 dd->msi_lo = 0;
384 pci_disable_msi(dd->pcidev);
385}
386
387/*
388 * Same as qib_nosmi, but for MSIx.
389 */
390void qib_nomsix(struct qib_devdata *dd)
391{
392 pci_disable_msix(dd->pcidev);
393}
394
395/*
396 * Similar to pci_intx(pdev, 1), except that we make sure
397 * msi(x) is off.
398 */
399void qib_enable_intx(struct pci_dev *pdev)
400{
401 u16 cw, new;
402 int pos;
403
404 /* first, turn on INTx */
405 pci_read_config_word(pdev, PCI_COMMAND, &cw);
406 new = cw & ~PCI_COMMAND_INTX_DISABLE;
407 if (new != cw)
408 pci_write_config_word(pdev, PCI_COMMAND, new);
409
410 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
411 if (pos) {
412 /* then turn off MSI */
413 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw);
414 new = cw & ~PCI_MSI_FLAGS_ENABLE;
415 if (new != cw)
416 pci_write_config_word(pdev, pos + PCI_MSI_FLAGS, new);
417 }
418 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
419 if (pos) {
420 /* then turn off MSIx */
421 pci_read_config_word(pdev, pos + PCI_MSIX_FLAGS, &cw);
422 new = cw & ~PCI_MSIX_FLAGS_ENABLE;
423 if (new != cw)
424 pci_write_config_word(pdev, pos + PCI_MSIX_FLAGS, new);
425 }
426}
427
428/*
429 * These two routines are helper routines for the device reset code
430 * to move all the pcie code out of the chip-specific driver code.
431 */
432void qib_pcie_getcmd(struct qib_devdata *dd, u16 *cmd, u8 *iline, u8 *cline)
433{
434 pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd);
435 pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
436 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
437}
438
439void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline)
440{
441 int r;
442 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
443 dd->pcibar0);
444 if (r)
445 qib_dev_err(dd, "rewrite of BAR0 failed: %d\n", r);
446 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
447 dd->pcibar1);
448 if (r)
449 qib_dev_err(dd, "rewrite of BAR1 failed: %d\n", r);
450 /* now re-enable memory access, and restore cosmetic settings */
451 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd);
452 pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline);
453 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
454 r = pci_enable_device(dd->pcidev);
455 if (r)
456 qib_dev_err(dd, "pci_enable_device failed after "
457 "reset: %d\n", r);
458}
459
460/* code to adjust PCIe capabilities. */
461
462static int fld2val(int wd, int mask)
463{
464 int lsbmask;
465
466 if (!mask)
467 return 0;
468 wd &= mask;
469 lsbmask = mask ^ (mask & (mask - 1));
470 wd /= lsbmask;
471 return wd;
472}
473
474static int val2fld(int wd, int mask)
475{
476 int lsbmask;
477
478 if (!mask)
479 return 0;
480 lsbmask = mask ^ (mask & (mask - 1));
481 wd *= lsbmask;
482 return wd;
483}
484
485static int qib_pcie_coalesce;
486module_param_named(pcie_coalesce, qib_pcie_coalesce, int, S_IRUGO);
487MODULE_PARM_DESC(pcie_coalesce, "tune PCIe colescing on some Intel chipsets");
488
489/*
490 * Enable PCIe completion and data coalescing, on Intel 5x00 and 7300
491 * chipsets. This is known to be unsafe for some revisions of some
492 * of these chipsets, with some BIOS settings, and enabling it on those
493 * systems may result in the system crashing, and/or data corruption.
494 */
495static int qib_tune_pcie_coalesce(struct qib_devdata *dd)
496{
497 int r;
498 struct pci_dev *parent;
499 int ppos;
500 u16 devid;
501 u32 mask, bits, val;
502
503 if (!qib_pcie_coalesce)
504 return 0;
505
506 /* Find out supported and configured values for parent (root) */
507 parent = dd->pcidev->bus->self;
508 if (parent->bus->parent) {
509 qib_devinfo(dd->pcidev, "Parent not root\n");
510 return 1;
511 }
512 ppos = pci_pcie_cap(parent);
513 if (!ppos)
514 return 1;
515 if (parent->vendor != 0x8086)
516 return 1;
517
518 /*
519 * - bit 12: Max_rdcmp_Imt_EN: need to set to 1
520 * - bit 11: COALESCE_FORCE: need to set to 0
521 * - bit 10: COALESCE_EN: need to set to 1
522 * (but limitations on some on some chipsets)
523 *
524 * On the Intel 5000, 5100, and 7300 chipsets, there is
525 * also: - bit 25:24: COALESCE_MODE, need to set to 0
526 */
527 devid = parent->device;
528 if (devid >= 0x25e2 && devid <= 0x25fa) {
529 /* 5000 P/V/X/Z */
530 if (parent->revision <= 0xb2)
531 bits = 1U << 10;
532 else
533 bits = 7U << 10;
534 mask = (3U << 24) | (7U << 10);
535 } else if (devid >= 0x65e2 && devid <= 0x65fa) {
536 /* 5100 */
537 bits = 1U << 10;
538 mask = (3U << 24) | (7U << 10);
539 } else if (devid >= 0x4021 && devid <= 0x402e) {
540 /* 5400 */
541 bits = 7U << 10;
542 mask = 7U << 10;
543 } else if (devid >= 0x3604 && devid <= 0x360a) {
544 /* 7300 */
545 bits = 7U << 10;
546 mask = (3U << 24) | (7U << 10);
547 } else {
548 /* not one of the chipsets that we know about */
549 return 1;
550 }
551 pci_read_config_dword(parent, 0x48, &val);
552 val &= ~mask;
553 val |= bits;
554 r = pci_write_config_dword(parent, 0x48, val);
555 return 0;
556}
557
558/*
559 * BIOS may not set PCIe bus-utilization parameters for best performance.
560 * Check and optionally adjust them to maximize our throughput.
561 */
562static int qib_pcie_caps;
563module_param_named(pcie_caps, qib_pcie_caps, int, S_IRUGO);
564MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (4lsb), ReadReq (D4..7)");
565
566static int qib_tune_pcie_caps(struct qib_devdata *dd)
567{
568 int ret = 1; /* Assume the worst */
569 struct pci_dev *parent;
570 int ppos, epos;
571 u16 pcaps, pctl, ecaps, ectl;
572 int rc_sup, ep_sup;
573 int rc_cur, ep_cur;
574
575 /* Find out supported and configured values for parent (root) */
576 parent = dd->pcidev->bus->self;
577 if (parent->bus->parent) {
578 qib_devinfo(dd->pcidev, "Parent not root\n");
579 goto bail;
580 }
581 ppos = pci_pcie_cap(parent);
582 if (ppos) {
583 pci_read_config_word(parent, ppos + PCI_EXP_DEVCAP, &pcaps);
584 pci_read_config_word(parent, ppos + PCI_EXP_DEVCTL, &pctl);
585 } else
586 goto bail;
587 /* Find out supported and configured values for endpoint (us) */
588 epos = pci_pcie_cap(dd->pcidev);
589 if (epos) {
590 pci_read_config_word(dd->pcidev, epos + PCI_EXP_DEVCAP, &ecaps);
591 pci_read_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, &ectl);
592 } else
593 goto bail;
594 ret = 0;
595 /* Find max payload supported by root, endpoint */
596 rc_sup = fld2val(pcaps, PCI_EXP_DEVCAP_PAYLOAD);
597 ep_sup = fld2val(ecaps, PCI_EXP_DEVCAP_PAYLOAD);
598 if (rc_sup > ep_sup)
599 rc_sup = ep_sup;
600
601 rc_cur = fld2val(pctl, PCI_EXP_DEVCTL_PAYLOAD);
602 ep_cur = fld2val(ectl, PCI_EXP_DEVCTL_PAYLOAD);
603
604 /* If Supported greater than limit in module param, limit it */
605 if (rc_sup > (qib_pcie_caps & 7))
606 rc_sup = qib_pcie_caps & 7;
607 /* If less than (allowed, supported), bump root payload */
608 if (rc_sup > rc_cur) {
609 rc_cur = rc_sup;
610 pctl = (pctl & ~PCI_EXP_DEVCTL_PAYLOAD) |
611 val2fld(rc_cur, PCI_EXP_DEVCTL_PAYLOAD);
612 pci_write_config_word(parent, ppos + PCI_EXP_DEVCTL, pctl);
613 }
614 /* If less than (allowed, supported), bump endpoint payload */
615 if (rc_sup > ep_cur) {
616 ep_cur = rc_sup;
617 ectl = (ectl & ~PCI_EXP_DEVCTL_PAYLOAD) |
618 val2fld(ep_cur, PCI_EXP_DEVCTL_PAYLOAD);
619 pci_write_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, ectl);
620 }
621
622 /*
623 * Now the Read Request size.
624 * No field for max supported, but PCIe spec limits it to 4096,
625 * which is code '5' (log2(4096) - 7)
626 */
627 rc_sup = 5;
628 if (rc_sup > ((qib_pcie_caps >> 4) & 7))
629 rc_sup = (qib_pcie_caps >> 4) & 7;
630 rc_cur = fld2val(pctl, PCI_EXP_DEVCTL_READRQ);
631 ep_cur = fld2val(ectl, PCI_EXP_DEVCTL_READRQ);
632
633 if (rc_sup > rc_cur) {
634 rc_cur = rc_sup;
635 pctl = (pctl & ~PCI_EXP_DEVCTL_READRQ) |
636 val2fld(rc_cur, PCI_EXP_DEVCTL_READRQ);
637 pci_write_config_word(parent, ppos + PCI_EXP_DEVCTL, pctl);
638 }
639 if (rc_sup > ep_cur) {
640 ep_cur = rc_sup;
641 ectl = (ectl & ~PCI_EXP_DEVCTL_READRQ) |
642 val2fld(ep_cur, PCI_EXP_DEVCTL_READRQ);
643 pci_write_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, ectl);
644 }
645bail:
646 return ret;
647}
648/* End of PCIe capability tuning */
649
650/*
651 * From here through qib_pci_err_handler definition is invoked via
652 * PCI error infrastructure, registered via pci
653 */
654static pci_ers_result_t
655qib_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
656{
657 struct qib_devdata *dd = pci_get_drvdata(pdev);
658 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
659
660 switch (state) {
661 case pci_channel_io_normal:
662 qib_devinfo(pdev, "State Normal, ignoring\n");
663 break;
664
665 case pci_channel_io_frozen:
666 qib_devinfo(pdev, "State Frozen, requesting reset\n");
667 pci_disable_device(pdev);
668 ret = PCI_ERS_RESULT_NEED_RESET;
669 break;
670
671 case pci_channel_io_perm_failure:
672 qib_devinfo(pdev, "State Permanent Failure, disabling\n");
673 if (dd) {
674 /* no more register accesses! */
675 dd->flags &= ~QIB_PRESENT;
676 qib_disable_after_error(dd);
677 }
678 /* else early, or other problem */
679 ret = PCI_ERS_RESULT_DISCONNECT;
680 break;
681
682 default: /* shouldn't happen */
683 qib_devinfo(pdev, "QIB PCI errors detected (state %d)\n",
684 state);
685 break;
686 }
687 return ret;
688}
689
690static pci_ers_result_t
691qib_pci_mmio_enabled(struct pci_dev *pdev)
692{
693 u64 words = 0U;
694 struct qib_devdata *dd = pci_get_drvdata(pdev);
695 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
696
697 if (dd && dd->pport) {
698 words = dd->f_portcntr(dd->pport, QIBPORTCNTR_WORDRCV);
699 if (words == ~0ULL)
700 ret = PCI_ERS_RESULT_NEED_RESET;
701 }
702 qib_devinfo(pdev, "QIB mmio_enabled function called, "
703 "read wordscntr %Lx, returning %d\n", words, ret);
704 return ret;
705}
706
707static pci_ers_result_t
708qib_pci_slot_reset(struct pci_dev *pdev)
709{
710 qib_devinfo(pdev, "QIB link_reset function called, ignored\n");
711 return PCI_ERS_RESULT_CAN_RECOVER;
712}
713
714static pci_ers_result_t
715qib_pci_link_reset(struct pci_dev *pdev)
716{
717 qib_devinfo(pdev, "QIB link_reset function called, ignored\n");
718 return PCI_ERS_RESULT_CAN_RECOVER;
719}
720
721static void
722qib_pci_resume(struct pci_dev *pdev)
723{
724 struct qib_devdata *dd = pci_get_drvdata(pdev);
725 qib_devinfo(pdev, "QIB resume function called\n");
726 pci_cleanup_aer_uncorrect_error_status(pdev);
727 /*
728 * Running jobs will fail, since it's asynchronous
729 * unlike sysfs-requested reset. Better than
730 * doing nothing.
731 */
732 qib_init(dd, 1); /* same as re-init after reset */
733}
734
735struct pci_error_handlers qib_pci_err_handler = {
736 .error_detected = qib_pci_error_detected,
737 .mmio_enabled = qib_pci_mmio_enabled,
738 .link_reset = qib_pci_link_reset,
739 .slot_reset = qib_pci_slot_reset,
740 .resume = qib_pci_resume,
741};