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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * AMCC SoC PPC4xx Crypto Driver
4 *
5 * Copyright (c) 2008 Applied Micro Circuits Corporation.
6 * All rights reserved. James Hsiao <jhsiao@amcc.com>
7 *
8 * This file implements AMCC crypto offload Linux device driver for use with
9 * Linux CryptoAPI.
10 */
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/spinlock_types.h>
15#include <linux/random.h>
16#include <linux/scatterlist.h>
17#include <linux/crypto.h>
18#include <linux/dma-mapping.h>
19#include <linux/platform_device.h>
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
24#include <linux/of_platform.h>
25#include <linux/slab.h>
26#include <asm/dcr.h>
27#include <asm/dcr-regs.h>
28#include <asm/cacheflush.h>
29#include <crypto/aead.h>
30#include <crypto/aes.h>
31#include <crypto/ctr.h>
32#include <crypto/gcm.h>
33#include <crypto/sha1.h>
34#include <crypto/rng.h>
35#include <crypto/scatterwalk.h>
36#include <crypto/skcipher.h>
37#include <crypto/internal/aead.h>
38#include <crypto/internal/rng.h>
39#include <crypto/internal/skcipher.h>
40#include "crypto4xx_reg_def.h"
41#include "crypto4xx_core.h"
42#include "crypto4xx_sa.h"
43#include "crypto4xx_trng.h"
44
45#define PPC4XX_SEC_VERSION_STR "0.5"
46
47/*
48 * PPC4xx Crypto Engine Initialization Routine
49 */
50static void crypto4xx_hw_init(struct crypto4xx_device *dev)
51{
52 union ce_ring_size ring_size;
53 union ce_ring_control ring_ctrl;
54 union ce_part_ring_size part_ring_size;
55 union ce_io_threshold io_threshold;
56 u32 rand_num;
57 union ce_pe_dma_cfg pe_dma_cfg;
58 u32 device_ctrl;
59
60 writel(PPC4XX_BYTE_ORDER, dev->ce_base + CRYPTO4XX_BYTE_ORDER_CFG);
61 /* setup pe dma, include reset sg, pdr and pe, then release reset */
62 pe_dma_cfg.w = 0;
63 pe_dma_cfg.bf.bo_sgpd_en = 1;
64 pe_dma_cfg.bf.bo_data_en = 0;
65 pe_dma_cfg.bf.bo_sa_en = 1;
66 pe_dma_cfg.bf.bo_pd_en = 1;
67 pe_dma_cfg.bf.dynamic_sa_en = 1;
68 pe_dma_cfg.bf.reset_sg = 1;
69 pe_dma_cfg.bf.reset_pdr = 1;
70 pe_dma_cfg.bf.reset_pe = 1;
71 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
72 /* un reset pe,sg and pdr */
73 pe_dma_cfg.bf.pe_mode = 0;
74 pe_dma_cfg.bf.reset_sg = 0;
75 pe_dma_cfg.bf.reset_pdr = 0;
76 pe_dma_cfg.bf.reset_pe = 0;
77 pe_dma_cfg.bf.bo_td_en = 0;
78 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
79 writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_PDR_BASE);
80 writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_RDR_BASE);
81 writel(PPC4XX_PRNG_CTRL_AUTO_EN, dev->ce_base + CRYPTO4XX_PRNG_CTRL);
82 get_random_bytes(&rand_num, sizeof(rand_num));
83 writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_L);
84 get_random_bytes(&rand_num, sizeof(rand_num));
85 writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_H);
86 ring_size.w = 0;
87 ring_size.bf.ring_offset = PPC4XX_PD_SIZE;
88 ring_size.bf.ring_size = PPC4XX_NUM_PD;
89 writel(ring_size.w, dev->ce_base + CRYPTO4XX_RING_SIZE);
90 ring_ctrl.w = 0;
91 writel(ring_ctrl.w, dev->ce_base + CRYPTO4XX_RING_CTRL);
92 device_ctrl = readl(dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
93 device_ctrl |= PPC4XX_DC_3DES_EN;
94 writel(device_ctrl, dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
95 writel(dev->gdr_pa, dev->ce_base + CRYPTO4XX_GATH_RING_BASE);
96 writel(dev->sdr_pa, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE);
97 part_ring_size.w = 0;
98 part_ring_size.bf.sdr_size = PPC4XX_SDR_SIZE;
99 part_ring_size.bf.gdr_size = PPC4XX_GDR_SIZE;
100 writel(part_ring_size.w, dev->ce_base + CRYPTO4XX_PART_RING_SIZE);
101 writel(PPC4XX_SD_BUFFER_SIZE, dev->ce_base + CRYPTO4XX_PART_RING_CFG);
102 io_threshold.w = 0;
103 io_threshold.bf.output_threshold = PPC4XX_OUTPUT_THRESHOLD;
104 io_threshold.bf.input_threshold = PPC4XX_INPUT_THRESHOLD;
105 writel(io_threshold.w, dev->ce_base + CRYPTO4XX_IO_THRESHOLD);
106 writel(0, dev->ce_base + CRYPTO4XX_PDR_BASE_UADDR);
107 writel(0, dev->ce_base + CRYPTO4XX_RDR_BASE_UADDR);
108 writel(0, dev->ce_base + CRYPTO4XX_PKT_SRC_UADDR);
109 writel(0, dev->ce_base + CRYPTO4XX_PKT_DEST_UADDR);
110 writel(0, dev->ce_base + CRYPTO4XX_SA_UADDR);
111 writel(0, dev->ce_base + CRYPTO4XX_GATH_RING_BASE_UADDR);
112 writel(0, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE_UADDR);
113 /* un reset pe,sg and pdr */
114 pe_dma_cfg.bf.pe_mode = 1;
115 pe_dma_cfg.bf.reset_sg = 0;
116 pe_dma_cfg.bf.reset_pdr = 0;
117 pe_dma_cfg.bf.reset_pe = 0;
118 pe_dma_cfg.bf.bo_td_en = 0;
119 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
120 /*clear all pending interrupt*/
121 writel(PPC4XX_INTERRUPT_CLR, dev->ce_base + CRYPTO4XX_INT_CLR);
122 writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
123 writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
124 writel(PPC4XX_INT_CFG, dev->ce_base + CRYPTO4XX_INT_CFG);
125 if (dev->is_revb) {
126 writel(PPC4XX_INT_TIMEOUT_CNT_REVB << 10,
127 dev->ce_base + CRYPTO4XX_INT_TIMEOUT_CNT);
128 writel(PPC4XX_PD_DONE_INT | PPC4XX_TMO_ERR_INT,
129 dev->ce_base + CRYPTO4XX_INT_EN);
130 } else {
131 writel(PPC4XX_PD_DONE_INT, dev->ce_base + CRYPTO4XX_INT_EN);
132 }
133}
134
135int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size)
136{
137 ctx->sa_in = kcalloc(size, 4, GFP_ATOMIC);
138 if (ctx->sa_in == NULL)
139 return -ENOMEM;
140
141 ctx->sa_out = kcalloc(size, 4, GFP_ATOMIC);
142 if (ctx->sa_out == NULL) {
143 kfree(ctx->sa_in);
144 ctx->sa_in = NULL;
145 return -ENOMEM;
146 }
147
148 ctx->sa_len = size;
149
150 return 0;
151}
152
153void crypto4xx_free_sa(struct crypto4xx_ctx *ctx)
154{
155 kfree(ctx->sa_in);
156 ctx->sa_in = NULL;
157 kfree(ctx->sa_out);
158 ctx->sa_out = NULL;
159 ctx->sa_len = 0;
160}
161
162/*
163 * alloc memory for the gather ring
164 * no need to alloc buf for the ring
165 * gdr_tail, gdr_head and gdr_count are initialized by this function
166 */
167static u32 crypto4xx_build_pdr(struct crypto4xx_device *dev)
168{
169 int i;
170 dev->pdr = dma_alloc_coherent(dev->core_dev->device,
171 sizeof(struct ce_pd) * PPC4XX_NUM_PD,
172 &dev->pdr_pa, GFP_KERNEL);
173 if (!dev->pdr)
174 return -ENOMEM;
175
176 dev->pdr_uinfo = kcalloc(PPC4XX_NUM_PD, sizeof(struct pd_uinfo),
177 GFP_KERNEL);
178 if (!dev->pdr_uinfo) {
179 dma_free_coherent(dev->core_dev->device,
180 sizeof(struct ce_pd) * PPC4XX_NUM_PD,
181 dev->pdr,
182 dev->pdr_pa);
183 return -ENOMEM;
184 }
185 dev->shadow_sa_pool = dma_alloc_coherent(dev->core_dev->device,
186 sizeof(union shadow_sa_buf) * PPC4XX_NUM_PD,
187 &dev->shadow_sa_pool_pa,
188 GFP_KERNEL);
189 if (!dev->shadow_sa_pool)
190 return -ENOMEM;
191
192 dev->shadow_sr_pool = dma_alloc_coherent(dev->core_dev->device,
193 sizeof(struct sa_state_record) * PPC4XX_NUM_PD,
194 &dev->shadow_sr_pool_pa, GFP_KERNEL);
195 if (!dev->shadow_sr_pool)
196 return -ENOMEM;
197 for (i = 0; i < PPC4XX_NUM_PD; i++) {
198 struct ce_pd *pd = &dev->pdr[i];
199 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[i];
200
201 pd->sa = dev->shadow_sa_pool_pa +
202 sizeof(union shadow_sa_buf) * i;
203
204 /* alloc 256 bytes which is enough for any kind of dynamic sa */
205 pd_uinfo->sa_va = &dev->shadow_sa_pool[i].sa;
206
207 /* alloc state record */
208 pd_uinfo->sr_va = &dev->shadow_sr_pool[i];
209 pd_uinfo->sr_pa = dev->shadow_sr_pool_pa +
210 sizeof(struct sa_state_record) * i;
211 }
212
213 return 0;
214}
215
216static void crypto4xx_destroy_pdr(struct crypto4xx_device *dev)
217{
218 if (dev->pdr)
219 dma_free_coherent(dev->core_dev->device,
220 sizeof(struct ce_pd) * PPC4XX_NUM_PD,
221 dev->pdr, dev->pdr_pa);
222
223 if (dev->shadow_sa_pool)
224 dma_free_coherent(dev->core_dev->device,
225 sizeof(union shadow_sa_buf) * PPC4XX_NUM_PD,
226 dev->shadow_sa_pool, dev->shadow_sa_pool_pa);
227
228 if (dev->shadow_sr_pool)
229 dma_free_coherent(dev->core_dev->device,
230 sizeof(struct sa_state_record) * PPC4XX_NUM_PD,
231 dev->shadow_sr_pool, dev->shadow_sr_pool_pa);
232
233 kfree(dev->pdr_uinfo);
234}
235
236static u32 crypto4xx_get_pd_from_pdr_nolock(struct crypto4xx_device *dev)
237{
238 u32 retval;
239 u32 tmp;
240
241 retval = dev->pdr_head;
242 tmp = (dev->pdr_head + 1) % PPC4XX_NUM_PD;
243
244 if (tmp == dev->pdr_tail)
245 return ERING_WAS_FULL;
246
247 dev->pdr_head = tmp;
248
249 return retval;
250}
251
252static u32 crypto4xx_put_pd_to_pdr(struct crypto4xx_device *dev, u32 idx)
253{
254 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[idx];
255 u32 tail;
256 unsigned long flags;
257
258 spin_lock_irqsave(&dev->core_dev->lock, flags);
259 pd_uinfo->state = PD_ENTRY_FREE;
260
261 if (dev->pdr_tail != PPC4XX_LAST_PD)
262 dev->pdr_tail++;
263 else
264 dev->pdr_tail = 0;
265 tail = dev->pdr_tail;
266 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
267
268 return tail;
269}
270
271/*
272 * alloc memory for the gather ring
273 * no need to alloc buf for the ring
274 * gdr_tail, gdr_head and gdr_count are initialized by this function
275 */
276static u32 crypto4xx_build_gdr(struct crypto4xx_device *dev)
277{
278 dev->gdr = dma_alloc_coherent(dev->core_dev->device,
279 sizeof(struct ce_gd) * PPC4XX_NUM_GD,
280 &dev->gdr_pa, GFP_KERNEL);
281 if (!dev->gdr)
282 return -ENOMEM;
283
284 return 0;
285}
286
287static inline void crypto4xx_destroy_gdr(struct crypto4xx_device *dev)
288{
289 if (dev->gdr)
290 dma_free_coherent(dev->core_dev->device,
291 sizeof(struct ce_gd) * PPC4XX_NUM_GD,
292 dev->gdr, dev->gdr_pa);
293}
294
295/*
296 * when this function is called.
297 * preemption or interrupt must be disabled
298 */
299static u32 crypto4xx_get_n_gd(struct crypto4xx_device *dev, int n)
300{
301 u32 retval;
302 u32 tmp;
303
304 if (n >= PPC4XX_NUM_GD)
305 return ERING_WAS_FULL;
306
307 retval = dev->gdr_head;
308 tmp = (dev->gdr_head + n) % PPC4XX_NUM_GD;
309 if (dev->gdr_head > dev->gdr_tail) {
310 if (tmp < dev->gdr_head && tmp >= dev->gdr_tail)
311 return ERING_WAS_FULL;
312 } else if (dev->gdr_head < dev->gdr_tail) {
313 if (tmp < dev->gdr_head || tmp >= dev->gdr_tail)
314 return ERING_WAS_FULL;
315 }
316 dev->gdr_head = tmp;
317
318 return retval;
319}
320
321static u32 crypto4xx_put_gd_to_gdr(struct crypto4xx_device *dev)
322{
323 unsigned long flags;
324
325 spin_lock_irqsave(&dev->core_dev->lock, flags);
326 if (dev->gdr_tail == dev->gdr_head) {
327 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
328 return 0;
329 }
330
331 if (dev->gdr_tail != PPC4XX_LAST_GD)
332 dev->gdr_tail++;
333 else
334 dev->gdr_tail = 0;
335
336 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
337
338 return 0;
339}
340
341static inline struct ce_gd *crypto4xx_get_gdp(struct crypto4xx_device *dev,
342 dma_addr_t *gd_dma, u32 idx)
343{
344 *gd_dma = dev->gdr_pa + sizeof(struct ce_gd) * idx;
345
346 return &dev->gdr[idx];
347}
348
349/*
350 * alloc memory for the scatter ring
351 * need to alloc buf for the ring
352 * sdr_tail, sdr_head and sdr_count are initialized by this function
353 */
354static u32 crypto4xx_build_sdr(struct crypto4xx_device *dev)
355{
356 int i;
357
358 dev->scatter_buffer_va =
359 dma_alloc_coherent(dev->core_dev->device,
360 PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD,
361 &dev->scatter_buffer_pa, GFP_KERNEL);
362 if (!dev->scatter_buffer_va)
363 return -ENOMEM;
364
365 /* alloc memory for scatter descriptor ring */
366 dev->sdr = dma_alloc_coherent(dev->core_dev->device,
367 sizeof(struct ce_sd) * PPC4XX_NUM_SD,
368 &dev->sdr_pa, GFP_KERNEL);
369 if (!dev->sdr)
370 return -ENOMEM;
371
372 for (i = 0; i < PPC4XX_NUM_SD; i++) {
373 dev->sdr[i].ptr = dev->scatter_buffer_pa +
374 PPC4XX_SD_BUFFER_SIZE * i;
375 }
376
377 return 0;
378}
379
380static void crypto4xx_destroy_sdr(struct crypto4xx_device *dev)
381{
382 if (dev->sdr)
383 dma_free_coherent(dev->core_dev->device,
384 sizeof(struct ce_sd) * PPC4XX_NUM_SD,
385 dev->sdr, dev->sdr_pa);
386
387 if (dev->scatter_buffer_va)
388 dma_free_coherent(dev->core_dev->device,
389 PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD,
390 dev->scatter_buffer_va,
391 dev->scatter_buffer_pa);
392}
393
394/*
395 * when this function is called.
396 * preemption or interrupt must be disabled
397 */
398static u32 crypto4xx_get_n_sd(struct crypto4xx_device *dev, int n)
399{
400 u32 retval;
401 u32 tmp;
402
403 if (n >= PPC4XX_NUM_SD)
404 return ERING_WAS_FULL;
405
406 retval = dev->sdr_head;
407 tmp = (dev->sdr_head + n) % PPC4XX_NUM_SD;
408 if (dev->sdr_head > dev->gdr_tail) {
409 if (tmp < dev->sdr_head && tmp >= dev->sdr_tail)
410 return ERING_WAS_FULL;
411 } else if (dev->sdr_head < dev->sdr_tail) {
412 if (tmp < dev->sdr_head || tmp >= dev->sdr_tail)
413 return ERING_WAS_FULL;
414 } /* the head = tail, or empty case is already take cared */
415 dev->sdr_head = tmp;
416
417 return retval;
418}
419
420static u32 crypto4xx_put_sd_to_sdr(struct crypto4xx_device *dev)
421{
422 unsigned long flags;
423
424 spin_lock_irqsave(&dev->core_dev->lock, flags);
425 if (dev->sdr_tail == dev->sdr_head) {
426 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
427 return 0;
428 }
429 if (dev->sdr_tail != PPC4XX_LAST_SD)
430 dev->sdr_tail++;
431 else
432 dev->sdr_tail = 0;
433 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
434
435 return 0;
436}
437
438static inline struct ce_sd *crypto4xx_get_sdp(struct crypto4xx_device *dev,
439 dma_addr_t *sd_dma, u32 idx)
440{
441 *sd_dma = dev->sdr_pa + sizeof(struct ce_sd) * idx;
442
443 return &dev->sdr[idx];
444}
445
446static void crypto4xx_copy_pkt_to_dst(struct crypto4xx_device *dev,
447 struct ce_pd *pd,
448 struct pd_uinfo *pd_uinfo,
449 u32 nbytes,
450 struct scatterlist *dst)
451{
452 unsigned int first_sd = pd_uinfo->first_sd;
453 unsigned int last_sd;
454 unsigned int overflow = 0;
455 unsigned int to_copy;
456 unsigned int dst_start = 0;
457
458 /*
459 * Because the scatter buffers are all neatly organized in one
460 * big continuous ringbuffer; scatterwalk_map_and_copy() can
461 * be instructed to copy a range of buffers in one go.
462 */
463
464 last_sd = (first_sd + pd_uinfo->num_sd);
465 if (last_sd > PPC4XX_LAST_SD) {
466 last_sd = PPC4XX_LAST_SD;
467 overflow = last_sd % PPC4XX_NUM_SD;
468 }
469
470 while (nbytes) {
471 void *buf = dev->scatter_buffer_va +
472 first_sd * PPC4XX_SD_BUFFER_SIZE;
473
474 to_copy = min(nbytes, PPC4XX_SD_BUFFER_SIZE *
475 (1 + last_sd - first_sd));
476 scatterwalk_map_and_copy(buf, dst, dst_start, to_copy, 1);
477 nbytes -= to_copy;
478
479 if (overflow) {
480 first_sd = 0;
481 last_sd = overflow;
482 dst_start += to_copy;
483 overflow = 0;
484 }
485 }
486}
487
488static void crypto4xx_copy_digest_to_dst(void *dst,
489 struct pd_uinfo *pd_uinfo,
490 struct crypto4xx_ctx *ctx)
491{
492 struct dynamic_sa_ctl *sa = (struct dynamic_sa_ctl *) ctx->sa_in;
493
494 if (sa->sa_command_0.bf.hash_alg == SA_HASH_ALG_SHA1) {
495 memcpy(dst, pd_uinfo->sr_va->save_digest,
496 SA_HASH_ALG_SHA1_DIGEST_SIZE);
497 }
498}
499
500static void crypto4xx_ret_sg_desc(struct crypto4xx_device *dev,
501 struct pd_uinfo *pd_uinfo)
502{
503 int i;
504 if (pd_uinfo->num_gd) {
505 for (i = 0; i < pd_uinfo->num_gd; i++)
506 crypto4xx_put_gd_to_gdr(dev);
507 pd_uinfo->first_gd = 0xffffffff;
508 pd_uinfo->num_gd = 0;
509 }
510 if (pd_uinfo->num_sd) {
511 for (i = 0; i < pd_uinfo->num_sd; i++)
512 crypto4xx_put_sd_to_sdr(dev);
513
514 pd_uinfo->first_sd = 0xffffffff;
515 pd_uinfo->num_sd = 0;
516 }
517}
518
519static void crypto4xx_cipher_done(struct crypto4xx_device *dev,
520 struct pd_uinfo *pd_uinfo,
521 struct ce_pd *pd)
522{
523 struct skcipher_request *req;
524 struct scatterlist *dst;
525
526 req = skcipher_request_cast(pd_uinfo->async_req);
527
528 if (pd_uinfo->sa_va->sa_command_0.bf.scatter) {
529 crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo,
530 req->cryptlen, req->dst);
531 } else {
532 dst = pd_uinfo->dest_va;
533 dma_unmap_page(dev->core_dev->device, pd->dest, dst->length,
534 DMA_FROM_DEVICE);
535 }
536
537 if (pd_uinfo->sa_va->sa_command_0.bf.save_iv == SA_SAVE_IV) {
538 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
539
540 crypto4xx_memcpy_from_le32((u32 *)req->iv,
541 pd_uinfo->sr_va->save_iv,
542 crypto_skcipher_ivsize(skcipher));
543 }
544
545 crypto4xx_ret_sg_desc(dev, pd_uinfo);
546
547 if (pd_uinfo->state & PD_ENTRY_BUSY)
548 skcipher_request_complete(req, -EINPROGRESS);
549 skcipher_request_complete(req, 0);
550}
551
552static void crypto4xx_ahash_done(struct crypto4xx_device *dev,
553 struct pd_uinfo *pd_uinfo)
554{
555 struct crypto4xx_ctx *ctx;
556 struct ahash_request *ahash_req;
557
558 ahash_req = ahash_request_cast(pd_uinfo->async_req);
559 ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(ahash_req));
560
561 crypto4xx_copy_digest_to_dst(ahash_req->result, pd_uinfo, ctx);
562 crypto4xx_ret_sg_desc(dev, pd_uinfo);
563
564 if (pd_uinfo->state & PD_ENTRY_BUSY)
565 ahash_request_complete(ahash_req, -EINPROGRESS);
566 ahash_request_complete(ahash_req, 0);
567}
568
569static void crypto4xx_aead_done(struct crypto4xx_device *dev,
570 struct pd_uinfo *pd_uinfo,
571 struct ce_pd *pd)
572{
573 struct aead_request *aead_req = container_of(pd_uinfo->async_req,
574 struct aead_request, base);
575 struct scatterlist *dst = pd_uinfo->dest_va;
576 size_t cp_len = crypto_aead_authsize(
577 crypto_aead_reqtfm(aead_req));
578 u32 icv[AES_BLOCK_SIZE];
579 int err = 0;
580
581 if (pd_uinfo->sa_va->sa_command_0.bf.scatter) {
582 crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo,
583 pd->pd_ctl_len.bf.pkt_len,
584 dst);
585 } else {
586 dma_unmap_page(dev->core_dev->device, pd->dest, dst->length,
587 DMA_FROM_DEVICE);
588 }
589
590 if (pd_uinfo->sa_va->sa_command_0.bf.dir == DIR_OUTBOUND) {
591 /* append icv at the end */
592 crypto4xx_memcpy_from_le32(icv, pd_uinfo->sr_va->save_digest,
593 sizeof(icv));
594
595 scatterwalk_map_and_copy(icv, dst, aead_req->cryptlen,
596 cp_len, 1);
597 } else {
598 /* check icv at the end */
599 scatterwalk_map_and_copy(icv, aead_req->src,
600 aead_req->assoclen + aead_req->cryptlen -
601 cp_len, cp_len, 0);
602
603 crypto4xx_memcpy_from_le32(icv, icv, sizeof(icv));
604
605 if (crypto_memneq(icv, pd_uinfo->sr_va->save_digest, cp_len))
606 err = -EBADMSG;
607 }
608
609 crypto4xx_ret_sg_desc(dev, pd_uinfo);
610
611 if (pd->pd_ctl.bf.status & 0xff) {
612 if (!__ratelimit(&dev->aead_ratelimit)) {
613 if (pd->pd_ctl.bf.status & 2)
614 pr_err("pad fail error\n");
615 if (pd->pd_ctl.bf.status & 4)
616 pr_err("seqnum fail\n");
617 if (pd->pd_ctl.bf.status & 8)
618 pr_err("error _notify\n");
619 pr_err("aead return err status = 0x%02x\n",
620 pd->pd_ctl.bf.status & 0xff);
621 pr_err("pd pad_ctl = 0x%08x\n",
622 pd->pd_ctl.bf.pd_pad_ctl);
623 }
624 err = -EINVAL;
625 }
626
627 if (pd_uinfo->state & PD_ENTRY_BUSY)
628 aead_request_complete(aead_req, -EINPROGRESS);
629
630 aead_request_complete(aead_req, err);
631}
632
633static void crypto4xx_pd_done(struct crypto4xx_device *dev, u32 idx)
634{
635 struct ce_pd *pd = &dev->pdr[idx];
636 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[idx];
637
638 switch (crypto_tfm_alg_type(pd_uinfo->async_req->tfm)) {
639 case CRYPTO_ALG_TYPE_SKCIPHER:
640 crypto4xx_cipher_done(dev, pd_uinfo, pd);
641 break;
642 case CRYPTO_ALG_TYPE_AEAD:
643 crypto4xx_aead_done(dev, pd_uinfo, pd);
644 break;
645 case CRYPTO_ALG_TYPE_AHASH:
646 crypto4xx_ahash_done(dev, pd_uinfo);
647 break;
648 }
649}
650
651static void crypto4xx_stop_all(struct crypto4xx_core_device *core_dev)
652{
653 crypto4xx_destroy_pdr(core_dev->dev);
654 crypto4xx_destroy_gdr(core_dev->dev);
655 crypto4xx_destroy_sdr(core_dev->dev);
656 iounmap(core_dev->dev->ce_base);
657 kfree(core_dev->dev);
658 kfree(core_dev);
659}
660
661static u32 get_next_gd(u32 current)
662{
663 if (current != PPC4XX_LAST_GD)
664 return current + 1;
665 else
666 return 0;
667}
668
669static u32 get_next_sd(u32 current)
670{
671 if (current != PPC4XX_LAST_SD)
672 return current + 1;
673 else
674 return 0;
675}
676
677int crypto4xx_build_pd(struct crypto_async_request *req,
678 struct crypto4xx_ctx *ctx,
679 struct scatterlist *src,
680 struct scatterlist *dst,
681 const unsigned int datalen,
682 const __le32 *iv, const u32 iv_len,
683 const struct dynamic_sa_ctl *req_sa,
684 const unsigned int sa_len,
685 const unsigned int assoclen,
686 struct scatterlist *_dst)
687{
688 struct crypto4xx_device *dev = ctx->dev;
689 struct dynamic_sa_ctl *sa;
690 struct ce_gd *gd;
691 struct ce_pd *pd;
692 u32 num_gd, num_sd;
693 u32 fst_gd = 0xffffffff;
694 u32 fst_sd = 0xffffffff;
695 u32 pd_entry;
696 unsigned long flags;
697 struct pd_uinfo *pd_uinfo;
698 unsigned int nbytes = datalen;
699 size_t offset_to_sr_ptr;
700 u32 gd_idx = 0;
701 int tmp;
702 bool is_busy, force_sd;
703
704 /*
705 * There's a very subtile/disguised "bug" in the hardware that
706 * gets indirectly mentioned in 18.1.3.5 Encryption/Decryption
707 * of the hardware spec:
708 * *drum roll* the AES/(T)DES OFB and CFB modes are listed as
709 * operation modes for >>> "Block ciphers" <<<.
710 *
711 * To workaround this issue and stop the hardware from causing
712 * "overran dst buffer" on crypttexts that are not a multiple
713 * of 16 (AES_BLOCK_SIZE), we force the driver to use the
714 * scatter buffers.
715 */
716 force_sd = (req_sa->sa_command_1.bf.crypto_mode9_8 == CRYPTO_MODE_CFB
717 || req_sa->sa_command_1.bf.crypto_mode9_8 == CRYPTO_MODE_OFB)
718 && (datalen % AES_BLOCK_SIZE);
719
720 /* figure how many gd are needed */
721 tmp = sg_nents_for_len(src, assoclen + datalen);
722 if (tmp < 0) {
723 dev_err(dev->core_dev->device, "Invalid number of src SG.\n");
724 return tmp;
725 }
726 if (tmp == 1)
727 tmp = 0;
728 num_gd = tmp;
729
730 if (assoclen) {
731 nbytes += assoclen;
732 dst = scatterwalk_ffwd(_dst, dst, assoclen);
733 }
734
735 /* figure how many sd are needed */
736 if (sg_is_last(dst) && force_sd == false) {
737 num_sd = 0;
738 } else {
739 if (datalen > PPC4XX_SD_BUFFER_SIZE) {
740 num_sd = datalen / PPC4XX_SD_BUFFER_SIZE;
741 if (datalen % PPC4XX_SD_BUFFER_SIZE)
742 num_sd++;
743 } else {
744 num_sd = 1;
745 }
746 }
747
748 /*
749 * The follow section of code needs to be protected
750 * The gather ring and scatter ring needs to be consecutive
751 * In case of run out of any kind of descriptor, the descriptor
752 * already got must be return the original place.
753 */
754 spin_lock_irqsave(&dev->core_dev->lock, flags);
755 /*
756 * Let the caller know to slow down, once more than 13/16ths = 81%
757 * of the available data contexts are being used simultaneously.
758 *
759 * With PPC4XX_NUM_PD = 256, this will leave a "backlog queue" for
760 * 31 more contexts. Before new requests have to be rejected.
761 */
762 if (req->flags & CRYPTO_TFM_REQ_MAY_BACKLOG) {
763 is_busy = ((dev->pdr_head - dev->pdr_tail) % PPC4XX_NUM_PD) >=
764 ((PPC4XX_NUM_PD * 13) / 16);
765 } else {
766 /*
767 * To fix contention issues between ipsec (no blacklog) and
768 * dm-crypto (backlog) reserve 32 entries for "no backlog"
769 * data contexts.
770 */
771 is_busy = ((dev->pdr_head - dev->pdr_tail) % PPC4XX_NUM_PD) >=
772 ((PPC4XX_NUM_PD * 15) / 16);
773
774 if (is_busy) {
775 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
776 return -EBUSY;
777 }
778 }
779
780 if (num_gd) {
781 fst_gd = crypto4xx_get_n_gd(dev, num_gd);
782 if (fst_gd == ERING_WAS_FULL) {
783 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
784 return -EAGAIN;
785 }
786 }
787 if (num_sd) {
788 fst_sd = crypto4xx_get_n_sd(dev, num_sd);
789 if (fst_sd == ERING_WAS_FULL) {
790 if (num_gd)
791 dev->gdr_head = fst_gd;
792 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
793 return -EAGAIN;
794 }
795 }
796 pd_entry = crypto4xx_get_pd_from_pdr_nolock(dev);
797 if (pd_entry == ERING_WAS_FULL) {
798 if (num_gd)
799 dev->gdr_head = fst_gd;
800 if (num_sd)
801 dev->sdr_head = fst_sd;
802 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
803 return -EAGAIN;
804 }
805 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
806
807 pd = &dev->pdr[pd_entry];
808 pd->sa_len = sa_len;
809
810 pd_uinfo = &dev->pdr_uinfo[pd_entry];
811 pd_uinfo->num_gd = num_gd;
812 pd_uinfo->num_sd = num_sd;
813 pd_uinfo->dest_va = dst;
814 pd_uinfo->async_req = req;
815
816 if (iv_len)
817 memcpy(pd_uinfo->sr_va->save_iv, iv, iv_len);
818
819 sa = pd_uinfo->sa_va;
820 memcpy(sa, req_sa, sa_len * 4);
821
822 sa->sa_command_1.bf.hash_crypto_offset = (assoclen >> 2);
823 offset_to_sr_ptr = get_dynamic_sa_offset_state_ptr_field(sa);
824 *(u32 *)((unsigned long)sa + offset_to_sr_ptr) = pd_uinfo->sr_pa;
825
826 if (num_gd) {
827 dma_addr_t gd_dma;
828 struct scatterlist *sg;
829
830 /* get first gd we are going to use */
831 gd_idx = fst_gd;
832 pd_uinfo->first_gd = fst_gd;
833 gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
834 pd->src = gd_dma;
835 /* enable gather */
836 sa->sa_command_0.bf.gather = 1;
837 /* walk the sg, and setup gather array */
838
839 sg = src;
840 while (nbytes) {
841 size_t len;
842
843 len = min(sg->length, nbytes);
844 gd->ptr = dma_map_page(dev->core_dev->device,
845 sg_page(sg), sg->offset, len, DMA_TO_DEVICE);
846 gd->ctl_len.len = len;
847 gd->ctl_len.done = 0;
848 gd->ctl_len.ready = 1;
849 if (len >= nbytes)
850 break;
851
852 nbytes -= sg->length;
853 gd_idx = get_next_gd(gd_idx);
854 gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
855 sg = sg_next(sg);
856 }
857 } else {
858 pd->src = (u32)dma_map_page(dev->core_dev->device, sg_page(src),
859 src->offset, min(nbytes, src->length),
860 DMA_TO_DEVICE);
861 /*
862 * Disable gather in sa command
863 */
864 sa->sa_command_0.bf.gather = 0;
865 /*
866 * Indicate gather array is not used
867 */
868 pd_uinfo->first_gd = 0xffffffff;
869 }
870 if (!num_sd) {
871 /*
872 * we know application give us dst a whole piece of memory
873 * no need to use scatter ring.
874 */
875 pd_uinfo->first_sd = 0xffffffff;
876 sa->sa_command_0.bf.scatter = 0;
877 pd->dest = (u32)dma_map_page(dev->core_dev->device,
878 sg_page(dst), dst->offset,
879 min(datalen, dst->length),
880 DMA_TO_DEVICE);
881 } else {
882 dma_addr_t sd_dma;
883 struct ce_sd *sd = NULL;
884
885 u32 sd_idx = fst_sd;
886 nbytes = datalen;
887 sa->sa_command_0.bf.scatter = 1;
888 pd_uinfo->first_sd = fst_sd;
889 sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
890 pd->dest = sd_dma;
891 /* setup scatter descriptor */
892 sd->ctl.done = 0;
893 sd->ctl.rdy = 1;
894 /* sd->ptr should be setup by sd_init routine*/
895 if (nbytes >= PPC4XX_SD_BUFFER_SIZE)
896 nbytes -= PPC4XX_SD_BUFFER_SIZE;
897 else
898 nbytes = 0;
899 while (nbytes) {
900 sd_idx = get_next_sd(sd_idx);
901 sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
902 /* setup scatter descriptor */
903 sd->ctl.done = 0;
904 sd->ctl.rdy = 1;
905 if (nbytes >= PPC4XX_SD_BUFFER_SIZE) {
906 nbytes -= PPC4XX_SD_BUFFER_SIZE;
907 } else {
908 /*
909 * SD entry can hold PPC4XX_SD_BUFFER_SIZE,
910 * which is more than nbytes, so done.
911 */
912 nbytes = 0;
913 }
914 }
915 }
916
917 pd->pd_ctl.w = PD_CTL_HOST_READY |
918 ((crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AHASH) ||
919 (crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AEAD) ?
920 PD_CTL_HASH_FINAL : 0);
921 pd->pd_ctl_len.w = 0x00400000 | (assoclen + datalen);
922 pd_uinfo->state = PD_ENTRY_INUSE | (is_busy ? PD_ENTRY_BUSY : 0);
923
924 wmb();
925 /* write any value to push engine to read a pd */
926 writel(0, dev->ce_base + CRYPTO4XX_INT_DESCR_RD);
927 writel(1, dev->ce_base + CRYPTO4XX_INT_DESCR_RD);
928 return is_busy ? -EBUSY : -EINPROGRESS;
929}
930
931/*
932 * Algorithm Registration Functions
933 */
934static void crypto4xx_ctx_init(struct crypto4xx_alg *amcc_alg,
935 struct crypto4xx_ctx *ctx)
936{
937 ctx->dev = amcc_alg->dev;
938 ctx->sa_in = NULL;
939 ctx->sa_out = NULL;
940 ctx->sa_len = 0;
941}
942
943static int crypto4xx_sk_init(struct crypto_skcipher *sk)
944{
945 struct skcipher_alg *alg = crypto_skcipher_alg(sk);
946 struct crypto4xx_alg *amcc_alg;
947 struct crypto4xx_ctx *ctx = crypto_skcipher_ctx(sk);
948
949 if (alg->base.cra_flags & CRYPTO_ALG_NEED_FALLBACK) {
950 ctx->sw_cipher.cipher =
951 crypto_alloc_sync_skcipher(alg->base.cra_name, 0,
952 CRYPTO_ALG_NEED_FALLBACK);
953 if (IS_ERR(ctx->sw_cipher.cipher))
954 return PTR_ERR(ctx->sw_cipher.cipher);
955 }
956
957 amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.cipher);
958 crypto4xx_ctx_init(amcc_alg, ctx);
959 return 0;
960}
961
962static void crypto4xx_common_exit(struct crypto4xx_ctx *ctx)
963{
964 crypto4xx_free_sa(ctx);
965}
966
967static void crypto4xx_sk_exit(struct crypto_skcipher *sk)
968{
969 struct crypto4xx_ctx *ctx = crypto_skcipher_ctx(sk);
970
971 crypto4xx_common_exit(ctx);
972 if (ctx->sw_cipher.cipher)
973 crypto_free_sync_skcipher(ctx->sw_cipher.cipher);
974}
975
976static int crypto4xx_aead_init(struct crypto_aead *tfm)
977{
978 struct aead_alg *alg = crypto_aead_alg(tfm);
979 struct crypto4xx_ctx *ctx = crypto_aead_ctx(tfm);
980 struct crypto4xx_alg *amcc_alg;
981
982 ctx->sw_cipher.aead = crypto_alloc_aead(alg->base.cra_name, 0,
983 CRYPTO_ALG_NEED_FALLBACK |
984 CRYPTO_ALG_ASYNC);
985 if (IS_ERR(ctx->sw_cipher.aead))
986 return PTR_ERR(ctx->sw_cipher.aead);
987
988 amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.aead);
989 crypto4xx_ctx_init(amcc_alg, ctx);
990 crypto_aead_set_reqsize(tfm, max(sizeof(struct aead_request) + 32 +
991 crypto_aead_reqsize(ctx->sw_cipher.aead),
992 sizeof(struct crypto4xx_aead_reqctx)));
993 return 0;
994}
995
996static void crypto4xx_aead_exit(struct crypto_aead *tfm)
997{
998 struct crypto4xx_ctx *ctx = crypto_aead_ctx(tfm);
999
1000 crypto4xx_common_exit(ctx);
1001 crypto_free_aead(ctx->sw_cipher.aead);
1002}
1003
1004static int crypto4xx_register_alg(struct crypto4xx_device *sec_dev,
1005 struct crypto4xx_alg_common *crypto_alg,
1006 int array_size)
1007{
1008 struct crypto4xx_alg *alg;
1009 int i;
1010 int rc = 0;
1011
1012 for (i = 0; i < array_size; i++) {
1013 alg = kzalloc(sizeof(struct crypto4xx_alg), GFP_KERNEL);
1014 if (!alg)
1015 return -ENOMEM;
1016
1017 alg->alg = crypto_alg[i];
1018 alg->dev = sec_dev;
1019
1020 switch (alg->alg.type) {
1021 case CRYPTO_ALG_TYPE_AEAD:
1022 rc = crypto_register_aead(&alg->alg.u.aead);
1023 break;
1024
1025 case CRYPTO_ALG_TYPE_AHASH:
1026 rc = crypto_register_ahash(&alg->alg.u.hash);
1027 break;
1028
1029 case CRYPTO_ALG_TYPE_RNG:
1030 rc = crypto_register_rng(&alg->alg.u.rng);
1031 break;
1032
1033 default:
1034 rc = crypto_register_skcipher(&alg->alg.u.cipher);
1035 break;
1036 }
1037
1038 if (rc)
1039 kfree(alg);
1040 else
1041 list_add_tail(&alg->entry, &sec_dev->alg_list);
1042 }
1043
1044 return 0;
1045}
1046
1047static void crypto4xx_unregister_alg(struct crypto4xx_device *sec_dev)
1048{
1049 struct crypto4xx_alg *alg, *tmp;
1050
1051 list_for_each_entry_safe(alg, tmp, &sec_dev->alg_list, entry) {
1052 list_del(&alg->entry);
1053 switch (alg->alg.type) {
1054 case CRYPTO_ALG_TYPE_AHASH:
1055 crypto_unregister_ahash(&alg->alg.u.hash);
1056 break;
1057
1058 case CRYPTO_ALG_TYPE_AEAD:
1059 crypto_unregister_aead(&alg->alg.u.aead);
1060 break;
1061
1062 case CRYPTO_ALG_TYPE_RNG:
1063 crypto_unregister_rng(&alg->alg.u.rng);
1064 break;
1065
1066 default:
1067 crypto_unregister_skcipher(&alg->alg.u.cipher);
1068 }
1069 kfree(alg);
1070 }
1071}
1072
1073static void crypto4xx_bh_tasklet_cb(unsigned long data)
1074{
1075 struct device *dev = (struct device *)data;
1076 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1077 struct pd_uinfo *pd_uinfo;
1078 struct ce_pd *pd;
1079 u32 tail = core_dev->dev->pdr_tail;
1080 u32 head = core_dev->dev->pdr_head;
1081
1082 do {
1083 pd_uinfo = &core_dev->dev->pdr_uinfo[tail];
1084 pd = &core_dev->dev->pdr[tail];
1085 if ((pd_uinfo->state & PD_ENTRY_INUSE) &&
1086 ((READ_ONCE(pd->pd_ctl.w) &
1087 (PD_CTL_PE_DONE | PD_CTL_HOST_READY)) ==
1088 PD_CTL_PE_DONE)) {
1089 crypto4xx_pd_done(core_dev->dev, tail);
1090 tail = crypto4xx_put_pd_to_pdr(core_dev->dev, tail);
1091 } else {
1092 /* if tail not done, break */
1093 break;
1094 }
1095 } while (head != tail);
1096}
1097
1098/*
1099 * Top Half of isr.
1100 */
1101static inline irqreturn_t crypto4xx_interrupt_handler(int irq, void *data,
1102 u32 clr_val)
1103{
1104 struct device *dev = data;
1105 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1106
1107 writel(clr_val, core_dev->dev->ce_base + CRYPTO4XX_INT_CLR);
1108 tasklet_schedule(&core_dev->tasklet);
1109
1110 return IRQ_HANDLED;
1111}
1112
1113static irqreturn_t crypto4xx_ce_interrupt_handler(int irq, void *data)
1114{
1115 return crypto4xx_interrupt_handler(irq, data, PPC4XX_INTERRUPT_CLR);
1116}
1117
1118static irqreturn_t crypto4xx_ce_interrupt_handler_revb(int irq, void *data)
1119{
1120 return crypto4xx_interrupt_handler(irq, data, PPC4XX_INTERRUPT_CLR |
1121 PPC4XX_TMO_ERR_INT);
1122}
1123
1124static int ppc4xx_prng_data_read(struct crypto4xx_device *dev,
1125 u8 *data, unsigned int max)
1126{
1127 unsigned int i, curr = 0;
1128 u32 val[2];
1129
1130 do {
1131 /* trigger PRN generation */
1132 writel(PPC4XX_PRNG_CTRL_AUTO_EN,
1133 dev->ce_base + CRYPTO4XX_PRNG_CTRL);
1134
1135 for (i = 0; i < 1024; i++) {
1136 /* usually 19 iterations are enough */
1137 if ((readl(dev->ce_base + CRYPTO4XX_PRNG_STAT) &
1138 CRYPTO4XX_PRNG_STAT_BUSY))
1139 continue;
1140
1141 val[0] = readl_be(dev->ce_base + CRYPTO4XX_PRNG_RES_0);
1142 val[1] = readl_be(dev->ce_base + CRYPTO4XX_PRNG_RES_1);
1143 break;
1144 }
1145 if (i == 1024)
1146 return -ETIMEDOUT;
1147
1148 if ((max - curr) >= 8) {
1149 memcpy(data, &val, 8);
1150 data += 8;
1151 curr += 8;
1152 } else {
1153 /* copy only remaining bytes */
1154 memcpy(data, &val, max - curr);
1155 break;
1156 }
1157 } while (curr < max);
1158
1159 return curr;
1160}
1161
1162static int crypto4xx_prng_generate(struct crypto_rng *tfm,
1163 const u8 *src, unsigned int slen,
1164 u8 *dstn, unsigned int dlen)
1165{
1166 struct rng_alg *alg = crypto_rng_alg(tfm);
1167 struct crypto4xx_alg *amcc_alg;
1168 struct crypto4xx_device *dev;
1169 int ret;
1170
1171 amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.rng);
1172 dev = amcc_alg->dev;
1173
1174 mutex_lock(&dev->core_dev->rng_lock);
1175 ret = ppc4xx_prng_data_read(dev, dstn, dlen);
1176 mutex_unlock(&dev->core_dev->rng_lock);
1177 return ret;
1178}
1179
1180
1181static int crypto4xx_prng_seed(struct crypto_rng *tfm, const u8 *seed,
1182 unsigned int slen)
1183{
1184 return 0;
1185}
1186
1187/*
1188 * Supported Crypto Algorithms
1189 */
1190static struct crypto4xx_alg_common crypto4xx_alg[] = {
1191 /* Crypto AES modes */
1192 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1193 .base = {
1194 .cra_name = "cbc(aes)",
1195 .cra_driver_name = "cbc-aes-ppc4xx",
1196 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1197 .cra_flags = CRYPTO_ALG_ASYNC |
1198 CRYPTO_ALG_KERN_DRIVER_ONLY,
1199 .cra_blocksize = AES_BLOCK_SIZE,
1200 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1201 .cra_module = THIS_MODULE,
1202 },
1203 .min_keysize = AES_MIN_KEY_SIZE,
1204 .max_keysize = AES_MAX_KEY_SIZE,
1205 .ivsize = AES_IV_SIZE,
1206 .setkey = crypto4xx_setkey_aes_cbc,
1207 .encrypt = crypto4xx_encrypt_iv_block,
1208 .decrypt = crypto4xx_decrypt_iv_block,
1209 .init = crypto4xx_sk_init,
1210 .exit = crypto4xx_sk_exit,
1211 } },
1212 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1213 .base = {
1214 .cra_name = "ctr(aes)",
1215 .cra_driver_name = "ctr-aes-ppc4xx",
1216 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1217 .cra_flags = CRYPTO_ALG_NEED_FALLBACK |
1218 CRYPTO_ALG_ASYNC |
1219 CRYPTO_ALG_KERN_DRIVER_ONLY,
1220 .cra_blocksize = 1,
1221 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1222 .cra_module = THIS_MODULE,
1223 },
1224 .min_keysize = AES_MIN_KEY_SIZE,
1225 .max_keysize = AES_MAX_KEY_SIZE,
1226 .ivsize = AES_IV_SIZE,
1227 .setkey = crypto4xx_setkey_aes_ctr,
1228 .encrypt = crypto4xx_encrypt_ctr,
1229 .decrypt = crypto4xx_decrypt_ctr,
1230 .init = crypto4xx_sk_init,
1231 .exit = crypto4xx_sk_exit,
1232 } },
1233 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1234 .base = {
1235 .cra_name = "rfc3686(ctr(aes))",
1236 .cra_driver_name = "rfc3686-ctr-aes-ppc4xx",
1237 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1238 .cra_flags = CRYPTO_ALG_ASYNC |
1239 CRYPTO_ALG_KERN_DRIVER_ONLY,
1240 .cra_blocksize = 1,
1241 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1242 .cra_module = THIS_MODULE,
1243 },
1244 .min_keysize = AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE,
1245 .max_keysize = AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE,
1246 .ivsize = CTR_RFC3686_IV_SIZE,
1247 .setkey = crypto4xx_setkey_rfc3686,
1248 .encrypt = crypto4xx_rfc3686_encrypt,
1249 .decrypt = crypto4xx_rfc3686_decrypt,
1250 .init = crypto4xx_sk_init,
1251 .exit = crypto4xx_sk_exit,
1252 } },
1253 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1254 .base = {
1255 .cra_name = "ecb(aes)",
1256 .cra_driver_name = "ecb-aes-ppc4xx",
1257 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1258 .cra_flags = CRYPTO_ALG_ASYNC |
1259 CRYPTO_ALG_KERN_DRIVER_ONLY,
1260 .cra_blocksize = AES_BLOCK_SIZE,
1261 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1262 .cra_module = THIS_MODULE,
1263 },
1264 .min_keysize = AES_MIN_KEY_SIZE,
1265 .max_keysize = AES_MAX_KEY_SIZE,
1266 .setkey = crypto4xx_setkey_aes_ecb,
1267 .encrypt = crypto4xx_encrypt_noiv_block,
1268 .decrypt = crypto4xx_decrypt_noiv_block,
1269 .init = crypto4xx_sk_init,
1270 .exit = crypto4xx_sk_exit,
1271 } },
1272
1273 /* AEAD */
1274 { .type = CRYPTO_ALG_TYPE_AEAD, .u.aead = {
1275 .setkey = crypto4xx_setkey_aes_ccm,
1276 .setauthsize = crypto4xx_setauthsize_aead,
1277 .encrypt = crypto4xx_encrypt_aes_ccm,
1278 .decrypt = crypto4xx_decrypt_aes_ccm,
1279 .init = crypto4xx_aead_init,
1280 .exit = crypto4xx_aead_exit,
1281 .ivsize = AES_BLOCK_SIZE,
1282 .maxauthsize = 16,
1283 .base = {
1284 .cra_name = "ccm(aes)",
1285 .cra_driver_name = "ccm-aes-ppc4xx",
1286 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1287 .cra_flags = CRYPTO_ALG_ASYNC |
1288 CRYPTO_ALG_NEED_FALLBACK |
1289 CRYPTO_ALG_KERN_DRIVER_ONLY,
1290 .cra_blocksize = 1,
1291 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1292 .cra_module = THIS_MODULE,
1293 },
1294 } },
1295 { .type = CRYPTO_ALG_TYPE_AEAD, .u.aead = {
1296 .setkey = crypto4xx_setkey_aes_gcm,
1297 .setauthsize = crypto4xx_setauthsize_aead,
1298 .encrypt = crypto4xx_encrypt_aes_gcm,
1299 .decrypt = crypto4xx_decrypt_aes_gcm,
1300 .init = crypto4xx_aead_init,
1301 .exit = crypto4xx_aead_exit,
1302 .ivsize = GCM_AES_IV_SIZE,
1303 .maxauthsize = 16,
1304 .base = {
1305 .cra_name = "gcm(aes)",
1306 .cra_driver_name = "gcm-aes-ppc4xx",
1307 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1308 .cra_flags = CRYPTO_ALG_ASYNC |
1309 CRYPTO_ALG_NEED_FALLBACK |
1310 CRYPTO_ALG_KERN_DRIVER_ONLY,
1311 .cra_blocksize = 1,
1312 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1313 .cra_module = THIS_MODULE,
1314 },
1315 } },
1316 { .type = CRYPTO_ALG_TYPE_RNG, .u.rng = {
1317 .base = {
1318 .cra_name = "stdrng",
1319 .cra_driver_name = "crypto4xx_rng",
1320 .cra_priority = 300,
1321 .cra_ctxsize = 0,
1322 .cra_module = THIS_MODULE,
1323 },
1324 .generate = crypto4xx_prng_generate,
1325 .seed = crypto4xx_prng_seed,
1326 .seedsize = 0,
1327 } },
1328};
1329
1330/*
1331 * Module Initialization Routine
1332 */
1333static int crypto4xx_probe(struct platform_device *ofdev)
1334{
1335 int rc;
1336 struct resource res;
1337 struct device *dev = &ofdev->dev;
1338 struct crypto4xx_core_device *core_dev;
1339 struct device_node *np;
1340 u32 pvr;
1341 bool is_revb = true;
1342
1343 rc = of_address_to_resource(ofdev->dev.of_node, 0, &res);
1344 if (rc)
1345 return -ENODEV;
1346
1347 np = of_find_compatible_node(NULL, NULL, "amcc,ppc460ex-crypto");
1348 if (np) {
1349 mtdcri(SDR0, PPC460EX_SDR0_SRST,
1350 mfdcri(SDR0, PPC460EX_SDR0_SRST) | PPC460EX_CE_RESET);
1351 mtdcri(SDR0, PPC460EX_SDR0_SRST,
1352 mfdcri(SDR0, PPC460EX_SDR0_SRST) & ~PPC460EX_CE_RESET);
1353 } else {
1354 np = of_find_compatible_node(NULL, NULL, "amcc,ppc405ex-crypto");
1355 if (np) {
1356 mtdcri(SDR0, PPC405EX_SDR0_SRST,
1357 mfdcri(SDR0, PPC405EX_SDR0_SRST) | PPC405EX_CE_RESET);
1358 mtdcri(SDR0, PPC405EX_SDR0_SRST,
1359 mfdcri(SDR0, PPC405EX_SDR0_SRST) & ~PPC405EX_CE_RESET);
1360 is_revb = false;
1361 } else {
1362 np = of_find_compatible_node(NULL, NULL, "amcc,ppc460sx-crypto");
1363 if (np) {
1364 mtdcri(SDR0, PPC460SX_SDR0_SRST,
1365 mfdcri(SDR0, PPC460SX_SDR0_SRST) | PPC460SX_CE_RESET);
1366 mtdcri(SDR0, PPC460SX_SDR0_SRST,
1367 mfdcri(SDR0, PPC460SX_SDR0_SRST) & ~PPC460SX_CE_RESET);
1368 } else {
1369 printk(KERN_ERR "Crypto Function Not supported!\n");
1370 return -EINVAL;
1371 }
1372 }
1373 }
1374
1375 of_node_put(np);
1376
1377 core_dev = kzalloc(sizeof(struct crypto4xx_core_device), GFP_KERNEL);
1378 if (!core_dev)
1379 return -ENOMEM;
1380
1381 dev_set_drvdata(dev, core_dev);
1382 core_dev->ofdev = ofdev;
1383 core_dev->dev = kzalloc(sizeof(struct crypto4xx_device), GFP_KERNEL);
1384 rc = -ENOMEM;
1385 if (!core_dev->dev)
1386 goto err_alloc_dev;
1387
1388 /*
1389 * Older version of 460EX/GT have a hardware bug.
1390 * Hence they do not support H/W based security intr coalescing
1391 */
1392 pvr = mfspr(SPRN_PVR);
1393 if (is_revb && ((pvr >> 4) == 0x130218A)) {
1394 u32 min = PVR_MIN(pvr);
1395
1396 if (min < 4) {
1397 dev_info(dev, "RevA detected - disable interrupt coalescing\n");
1398 is_revb = false;
1399 }
1400 }
1401
1402 core_dev->dev->core_dev = core_dev;
1403 core_dev->dev->is_revb = is_revb;
1404 core_dev->device = dev;
1405 mutex_init(&core_dev->rng_lock);
1406 spin_lock_init(&core_dev->lock);
1407 INIT_LIST_HEAD(&core_dev->dev->alg_list);
1408 ratelimit_default_init(&core_dev->dev->aead_ratelimit);
1409 rc = crypto4xx_build_sdr(core_dev->dev);
1410 if (rc)
1411 goto err_build_sdr;
1412 rc = crypto4xx_build_pdr(core_dev->dev);
1413 if (rc)
1414 goto err_build_sdr;
1415
1416 rc = crypto4xx_build_gdr(core_dev->dev);
1417 if (rc)
1418 goto err_build_sdr;
1419
1420 /* Init tasklet for bottom half processing */
1421 tasklet_init(&core_dev->tasklet, crypto4xx_bh_tasklet_cb,
1422 (unsigned long) dev);
1423
1424 core_dev->dev->ce_base = of_iomap(ofdev->dev.of_node, 0);
1425 if (!core_dev->dev->ce_base) {
1426 dev_err(dev, "failed to of_iomap\n");
1427 rc = -ENOMEM;
1428 goto err_iomap;
1429 }
1430
1431 /* Register for Crypto isr, Crypto Engine IRQ */
1432 core_dev->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1433 rc = request_irq(core_dev->irq, is_revb ?
1434 crypto4xx_ce_interrupt_handler_revb :
1435 crypto4xx_ce_interrupt_handler, 0,
1436 KBUILD_MODNAME, dev);
1437 if (rc)
1438 goto err_request_irq;
1439
1440 /* need to setup pdr, rdr, gdr and sdr before this */
1441 crypto4xx_hw_init(core_dev->dev);
1442
1443 /* Register security algorithms with Linux CryptoAPI */
1444 rc = crypto4xx_register_alg(core_dev->dev, crypto4xx_alg,
1445 ARRAY_SIZE(crypto4xx_alg));
1446 if (rc)
1447 goto err_start_dev;
1448
1449 ppc4xx_trng_probe(core_dev);
1450 return 0;
1451
1452err_start_dev:
1453 free_irq(core_dev->irq, dev);
1454err_request_irq:
1455 irq_dispose_mapping(core_dev->irq);
1456 iounmap(core_dev->dev->ce_base);
1457err_iomap:
1458 tasklet_kill(&core_dev->tasklet);
1459err_build_sdr:
1460 crypto4xx_destroy_sdr(core_dev->dev);
1461 crypto4xx_destroy_gdr(core_dev->dev);
1462 crypto4xx_destroy_pdr(core_dev->dev);
1463 kfree(core_dev->dev);
1464err_alloc_dev:
1465 kfree(core_dev);
1466
1467 return rc;
1468}
1469
1470static void crypto4xx_remove(struct platform_device *ofdev)
1471{
1472 struct device *dev = &ofdev->dev;
1473 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1474
1475 ppc4xx_trng_remove(core_dev);
1476
1477 free_irq(core_dev->irq, dev);
1478 irq_dispose_mapping(core_dev->irq);
1479
1480 tasklet_kill(&core_dev->tasklet);
1481 /* Un-register with Linux CryptoAPI */
1482 crypto4xx_unregister_alg(core_dev->dev);
1483 mutex_destroy(&core_dev->rng_lock);
1484 /* Free all allocated memory */
1485 crypto4xx_stop_all(core_dev);
1486}
1487
1488static const struct of_device_id crypto4xx_match[] = {
1489 { .compatible = "amcc,ppc4xx-crypto",},
1490 { },
1491};
1492MODULE_DEVICE_TABLE(of, crypto4xx_match);
1493
1494static struct platform_driver crypto4xx_driver = {
1495 .driver = {
1496 .name = KBUILD_MODNAME,
1497 .of_match_table = crypto4xx_match,
1498 },
1499 .probe = crypto4xx_probe,
1500 .remove_new = crypto4xx_remove,
1501};
1502
1503module_platform_driver(crypto4xx_driver);
1504
1505MODULE_LICENSE("GPL");
1506MODULE_AUTHOR("James Hsiao <jhsiao@amcc.com>");
1507MODULE_DESCRIPTION("Driver for AMCC PPC4xx crypto accelerator");
1/**
2 * AMCC SoC PPC4xx Crypto Driver
3 *
4 * Copyright (c) 2008 Applied Micro Circuits Corporation.
5 * All rights reserved. James Hsiao <jhsiao@amcc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * This file implements AMCC crypto offload Linux device driver for use with
18 * Linux CryptoAPI.
19 */
20
21#include <linux/kernel.h>
22#include <linux/interrupt.h>
23#include <linux/spinlock_types.h>
24#include <linux/random.h>
25#include <linux/scatterlist.h>
26#include <linux/crypto.h>
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
29#include <linux/init.h>
30#include <linux/of_platform.h>
31#include <linux/slab.h>
32#include <asm/dcr.h>
33#include <asm/dcr-regs.h>
34#include <asm/cacheflush.h>
35#include <crypto/aes.h>
36#include <crypto/sha.h>
37#include "crypto4xx_reg_def.h"
38#include "crypto4xx_core.h"
39#include "crypto4xx_sa.h"
40
41#define PPC4XX_SEC_VERSION_STR "0.5"
42
43/**
44 * PPC4xx Crypto Engine Initialization Routine
45 */
46static void crypto4xx_hw_init(struct crypto4xx_device *dev)
47{
48 union ce_ring_size ring_size;
49 union ce_ring_contol ring_ctrl;
50 union ce_part_ring_size part_ring_size;
51 union ce_io_threshold io_threshold;
52 u32 rand_num;
53 union ce_pe_dma_cfg pe_dma_cfg;
54 u32 device_ctrl;
55
56 writel(PPC4XX_BYTE_ORDER, dev->ce_base + CRYPTO4XX_BYTE_ORDER_CFG);
57 /* setup pe dma, include reset sg, pdr and pe, then release reset */
58 pe_dma_cfg.w = 0;
59 pe_dma_cfg.bf.bo_sgpd_en = 1;
60 pe_dma_cfg.bf.bo_data_en = 0;
61 pe_dma_cfg.bf.bo_sa_en = 1;
62 pe_dma_cfg.bf.bo_pd_en = 1;
63 pe_dma_cfg.bf.dynamic_sa_en = 1;
64 pe_dma_cfg.bf.reset_sg = 1;
65 pe_dma_cfg.bf.reset_pdr = 1;
66 pe_dma_cfg.bf.reset_pe = 1;
67 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
68 /* un reset pe,sg and pdr */
69 pe_dma_cfg.bf.pe_mode = 0;
70 pe_dma_cfg.bf.reset_sg = 0;
71 pe_dma_cfg.bf.reset_pdr = 0;
72 pe_dma_cfg.bf.reset_pe = 0;
73 pe_dma_cfg.bf.bo_td_en = 0;
74 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
75 writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_PDR_BASE);
76 writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_RDR_BASE);
77 writel(PPC4XX_PRNG_CTRL_AUTO_EN, dev->ce_base + CRYPTO4XX_PRNG_CTRL);
78 get_random_bytes(&rand_num, sizeof(rand_num));
79 writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_L);
80 get_random_bytes(&rand_num, sizeof(rand_num));
81 writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_H);
82 ring_size.w = 0;
83 ring_size.bf.ring_offset = PPC4XX_PD_SIZE;
84 ring_size.bf.ring_size = PPC4XX_NUM_PD;
85 writel(ring_size.w, dev->ce_base + CRYPTO4XX_RING_SIZE);
86 ring_ctrl.w = 0;
87 writel(ring_ctrl.w, dev->ce_base + CRYPTO4XX_RING_CTRL);
88 device_ctrl = readl(dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
89 device_ctrl |= PPC4XX_DC_3DES_EN;
90 writel(device_ctrl, dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
91 writel(dev->gdr_pa, dev->ce_base + CRYPTO4XX_GATH_RING_BASE);
92 writel(dev->sdr_pa, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE);
93 part_ring_size.w = 0;
94 part_ring_size.bf.sdr_size = PPC4XX_SDR_SIZE;
95 part_ring_size.bf.gdr_size = PPC4XX_GDR_SIZE;
96 writel(part_ring_size.w, dev->ce_base + CRYPTO4XX_PART_RING_SIZE);
97 writel(PPC4XX_SD_BUFFER_SIZE, dev->ce_base + CRYPTO4XX_PART_RING_CFG);
98 io_threshold.w = 0;
99 io_threshold.bf.output_threshold = PPC4XX_OUTPUT_THRESHOLD;
100 io_threshold.bf.input_threshold = PPC4XX_INPUT_THRESHOLD;
101 writel(io_threshold.w, dev->ce_base + CRYPTO4XX_IO_THRESHOLD);
102 writel(0, dev->ce_base + CRYPTO4XX_PDR_BASE_UADDR);
103 writel(0, dev->ce_base + CRYPTO4XX_RDR_BASE_UADDR);
104 writel(0, dev->ce_base + CRYPTO4XX_PKT_SRC_UADDR);
105 writel(0, dev->ce_base + CRYPTO4XX_PKT_DEST_UADDR);
106 writel(0, dev->ce_base + CRYPTO4XX_SA_UADDR);
107 writel(0, dev->ce_base + CRYPTO4XX_GATH_RING_BASE_UADDR);
108 writel(0, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE_UADDR);
109 /* un reset pe,sg and pdr */
110 pe_dma_cfg.bf.pe_mode = 1;
111 pe_dma_cfg.bf.reset_sg = 0;
112 pe_dma_cfg.bf.reset_pdr = 0;
113 pe_dma_cfg.bf.reset_pe = 0;
114 pe_dma_cfg.bf.bo_td_en = 0;
115 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
116 /*clear all pending interrupt*/
117 writel(PPC4XX_INTERRUPT_CLR, dev->ce_base + CRYPTO4XX_INT_CLR);
118 writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
119 writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
120 writel(PPC4XX_INT_CFG, dev->ce_base + CRYPTO4XX_INT_CFG);
121 writel(PPC4XX_PD_DONE_INT, dev->ce_base + CRYPTO4XX_INT_EN);
122}
123
124int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size)
125{
126 ctx->sa_in = dma_alloc_coherent(ctx->dev->core_dev->device, size * 4,
127 &ctx->sa_in_dma_addr, GFP_ATOMIC);
128 if (ctx->sa_in == NULL)
129 return -ENOMEM;
130
131 ctx->sa_out = dma_alloc_coherent(ctx->dev->core_dev->device, size * 4,
132 &ctx->sa_out_dma_addr, GFP_ATOMIC);
133 if (ctx->sa_out == NULL) {
134 dma_free_coherent(ctx->dev->core_dev->device,
135 ctx->sa_len * 4,
136 ctx->sa_in, ctx->sa_in_dma_addr);
137 return -ENOMEM;
138 }
139
140 memset(ctx->sa_in, 0, size * 4);
141 memset(ctx->sa_out, 0, size * 4);
142 ctx->sa_len = size;
143
144 return 0;
145}
146
147void crypto4xx_free_sa(struct crypto4xx_ctx *ctx)
148{
149 if (ctx->sa_in != NULL)
150 dma_free_coherent(ctx->dev->core_dev->device, ctx->sa_len * 4,
151 ctx->sa_in, ctx->sa_in_dma_addr);
152 if (ctx->sa_out != NULL)
153 dma_free_coherent(ctx->dev->core_dev->device, ctx->sa_len * 4,
154 ctx->sa_out, ctx->sa_out_dma_addr);
155
156 ctx->sa_in_dma_addr = 0;
157 ctx->sa_out_dma_addr = 0;
158 ctx->sa_len = 0;
159}
160
161u32 crypto4xx_alloc_state_record(struct crypto4xx_ctx *ctx)
162{
163 ctx->state_record = dma_alloc_coherent(ctx->dev->core_dev->device,
164 sizeof(struct sa_state_record),
165 &ctx->state_record_dma_addr, GFP_ATOMIC);
166 if (!ctx->state_record_dma_addr)
167 return -ENOMEM;
168 memset(ctx->state_record, 0, sizeof(struct sa_state_record));
169
170 return 0;
171}
172
173void crypto4xx_free_state_record(struct crypto4xx_ctx *ctx)
174{
175 if (ctx->state_record != NULL)
176 dma_free_coherent(ctx->dev->core_dev->device,
177 sizeof(struct sa_state_record),
178 ctx->state_record,
179 ctx->state_record_dma_addr);
180 ctx->state_record_dma_addr = 0;
181}
182
183/**
184 * alloc memory for the gather ring
185 * no need to alloc buf for the ring
186 * gdr_tail, gdr_head and gdr_count are initialized by this function
187 */
188static u32 crypto4xx_build_pdr(struct crypto4xx_device *dev)
189{
190 int i;
191 struct pd_uinfo *pd_uinfo;
192 dev->pdr = dma_alloc_coherent(dev->core_dev->device,
193 sizeof(struct ce_pd) * PPC4XX_NUM_PD,
194 &dev->pdr_pa, GFP_ATOMIC);
195 if (!dev->pdr)
196 return -ENOMEM;
197
198 dev->pdr_uinfo = kzalloc(sizeof(struct pd_uinfo) * PPC4XX_NUM_PD,
199 GFP_KERNEL);
200 if (!dev->pdr_uinfo) {
201 dma_free_coherent(dev->core_dev->device,
202 sizeof(struct ce_pd) * PPC4XX_NUM_PD,
203 dev->pdr,
204 dev->pdr_pa);
205 return -ENOMEM;
206 }
207 memset(dev->pdr, 0, sizeof(struct ce_pd) * PPC4XX_NUM_PD);
208 dev->shadow_sa_pool = dma_alloc_coherent(dev->core_dev->device,
209 256 * PPC4XX_NUM_PD,
210 &dev->shadow_sa_pool_pa,
211 GFP_ATOMIC);
212 if (!dev->shadow_sa_pool)
213 return -ENOMEM;
214
215 dev->shadow_sr_pool = dma_alloc_coherent(dev->core_dev->device,
216 sizeof(struct sa_state_record) * PPC4XX_NUM_PD,
217 &dev->shadow_sr_pool_pa, GFP_ATOMIC);
218 if (!dev->shadow_sr_pool)
219 return -ENOMEM;
220 for (i = 0; i < PPC4XX_NUM_PD; i++) {
221 pd_uinfo = (struct pd_uinfo *) (dev->pdr_uinfo +
222 sizeof(struct pd_uinfo) * i);
223
224 /* alloc 256 bytes which is enough for any kind of dynamic sa */
225 pd_uinfo->sa_va = dev->shadow_sa_pool + 256 * i;
226 pd_uinfo->sa_pa = dev->shadow_sa_pool_pa + 256 * i;
227
228 /* alloc state record */
229 pd_uinfo->sr_va = dev->shadow_sr_pool +
230 sizeof(struct sa_state_record) * i;
231 pd_uinfo->sr_pa = dev->shadow_sr_pool_pa +
232 sizeof(struct sa_state_record) * i;
233 }
234
235 return 0;
236}
237
238static void crypto4xx_destroy_pdr(struct crypto4xx_device *dev)
239{
240 if (dev->pdr != NULL)
241 dma_free_coherent(dev->core_dev->device,
242 sizeof(struct ce_pd) * PPC4XX_NUM_PD,
243 dev->pdr, dev->pdr_pa);
244 if (dev->shadow_sa_pool)
245 dma_free_coherent(dev->core_dev->device, 256 * PPC4XX_NUM_PD,
246 dev->shadow_sa_pool, dev->shadow_sa_pool_pa);
247 if (dev->shadow_sr_pool)
248 dma_free_coherent(dev->core_dev->device,
249 sizeof(struct sa_state_record) * PPC4XX_NUM_PD,
250 dev->shadow_sr_pool, dev->shadow_sr_pool_pa);
251
252 kfree(dev->pdr_uinfo);
253}
254
255static u32 crypto4xx_get_pd_from_pdr_nolock(struct crypto4xx_device *dev)
256{
257 u32 retval;
258 u32 tmp;
259
260 retval = dev->pdr_head;
261 tmp = (dev->pdr_head + 1) % PPC4XX_NUM_PD;
262
263 if (tmp == dev->pdr_tail)
264 return ERING_WAS_FULL;
265
266 dev->pdr_head = tmp;
267
268 return retval;
269}
270
271static u32 crypto4xx_put_pd_to_pdr(struct crypto4xx_device *dev, u32 idx)
272{
273 struct pd_uinfo *pd_uinfo;
274 unsigned long flags;
275
276 pd_uinfo = (struct pd_uinfo *)(dev->pdr_uinfo +
277 sizeof(struct pd_uinfo) * idx);
278 spin_lock_irqsave(&dev->core_dev->lock, flags);
279 if (dev->pdr_tail != PPC4XX_LAST_PD)
280 dev->pdr_tail++;
281 else
282 dev->pdr_tail = 0;
283 pd_uinfo->state = PD_ENTRY_FREE;
284 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
285
286 return 0;
287}
288
289static struct ce_pd *crypto4xx_get_pdp(struct crypto4xx_device *dev,
290 dma_addr_t *pd_dma, u32 idx)
291{
292 *pd_dma = dev->pdr_pa + sizeof(struct ce_pd) * idx;
293
294 return dev->pdr + sizeof(struct ce_pd) * idx;
295}
296
297/**
298 * alloc memory for the gather ring
299 * no need to alloc buf for the ring
300 * gdr_tail, gdr_head and gdr_count are initialized by this function
301 */
302static u32 crypto4xx_build_gdr(struct crypto4xx_device *dev)
303{
304 dev->gdr = dma_alloc_coherent(dev->core_dev->device,
305 sizeof(struct ce_gd) * PPC4XX_NUM_GD,
306 &dev->gdr_pa, GFP_ATOMIC);
307 if (!dev->gdr)
308 return -ENOMEM;
309
310 memset(dev->gdr, 0, sizeof(struct ce_gd) * PPC4XX_NUM_GD);
311
312 return 0;
313}
314
315static inline void crypto4xx_destroy_gdr(struct crypto4xx_device *dev)
316{
317 dma_free_coherent(dev->core_dev->device,
318 sizeof(struct ce_gd) * PPC4XX_NUM_GD,
319 dev->gdr, dev->gdr_pa);
320}
321
322/*
323 * when this function is called.
324 * preemption or interrupt must be disabled
325 */
326u32 crypto4xx_get_n_gd(struct crypto4xx_device *dev, int n)
327{
328 u32 retval;
329 u32 tmp;
330 if (n >= PPC4XX_NUM_GD)
331 return ERING_WAS_FULL;
332
333 retval = dev->gdr_head;
334 tmp = (dev->gdr_head + n) % PPC4XX_NUM_GD;
335 if (dev->gdr_head > dev->gdr_tail) {
336 if (tmp < dev->gdr_head && tmp >= dev->gdr_tail)
337 return ERING_WAS_FULL;
338 } else if (dev->gdr_head < dev->gdr_tail) {
339 if (tmp < dev->gdr_head || tmp >= dev->gdr_tail)
340 return ERING_WAS_FULL;
341 }
342 dev->gdr_head = tmp;
343
344 return retval;
345}
346
347static u32 crypto4xx_put_gd_to_gdr(struct crypto4xx_device *dev)
348{
349 unsigned long flags;
350
351 spin_lock_irqsave(&dev->core_dev->lock, flags);
352 if (dev->gdr_tail == dev->gdr_head) {
353 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
354 return 0;
355 }
356
357 if (dev->gdr_tail != PPC4XX_LAST_GD)
358 dev->gdr_tail++;
359 else
360 dev->gdr_tail = 0;
361
362 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
363
364 return 0;
365}
366
367static inline struct ce_gd *crypto4xx_get_gdp(struct crypto4xx_device *dev,
368 dma_addr_t *gd_dma, u32 idx)
369{
370 *gd_dma = dev->gdr_pa + sizeof(struct ce_gd) * idx;
371
372 return (struct ce_gd *) (dev->gdr + sizeof(struct ce_gd) * idx);
373}
374
375/**
376 * alloc memory for the scatter ring
377 * need to alloc buf for the ring
378 * sdr_tail, sdr_head and sdr_count are initialized by this function
379 */
380static u32 crypto4xx_build_sdr(struct crypto4xx_device *dev)
381{
382 int i;
383 struct ce_sd *sd_array;
384
385 /* alloc memory for scatter descriptor ring */
386 dev->sdr = dma_alloc_coherent(dev->core_dev->device,
387 sizeof(struct ce_sd) * PPC4XX_NUM_SD,
388 &dev->sdr_pa, GFP_ATOMIC);
389 if (!dev->sdr)
390 return -ENOMEM;
391
392 dev->scatter_buffer_size = PPC4XX_SD_BUFFER_SIZE;
393 dev->scatter_buffer_va =
394 dma_alloc_coherent(dev->core_dev->device,
395 dev->scatter_buffer_size * PPC4XX_NUM_SD,
396 &dev->scatter_buffer_pa, GFP_ATOMIC);
397 if (!dev->scatter_buffer_va) {
398 dma_free_coherent(dev->core_dev->device,
399 sizeof(struct ce_sd) * PPC4XX_NUM_SD,
400 dev->sdr, dev->sdr_pa);
401 return -ENOMEM;
402 }
403
404 sd_array = dev->sdr;
405
406 for (i = 0; i < PPC4XX_NUM_SD; i++) {
407 sd_array[i].ptr = dev->scatter_buffer_pa +
408 dev->scatter_buffer_size * i;
409 }
410
411 return 0;
412}
413
414static void crypto4xx_destroy_sdr(struct crypto4xx_device *dev)
415{
416 if (dev->sdr != NULL)
417 dma_free_coherent(dev->core_dev->device,
418 sizeof(struct ce_sd) * PPC4XX_NUM_SD,
419 dev->sdr, dev->sdr_pa);
420
421 if (dev->scatter_buffer_va != NULL)
422 dma_free_coherent(dev->core_dev->device,
423 dev->scatter_buffer_size * PPC4XX_NUM_SD,
424 dev->scatter_buffer_va,
425 dev->scatter_buffer_pa);
426}
427
428/*
429 * when this function is called.
430 * preemption or interrupt must be disabled
431 */
432static u32 crypto4xx_get_n_sd(struct crypto4xx_device *dev, int n)
433{
434 u32 retval;
435 u32 tmp;
436
437 if (n >= PPC4XX_NUM_SD)
438 return ERING_WAS_FULL;
439
440 retval = dev->sdr_head;
441 tmp = (dev->sdr_head + n) % PPC4XX_NUM_SD;
442 if (dev->sdr_head > dev->gdr_tail) {
443 if (tmp < dev->sdr_head && tmp >= dev->sdr_tail)
444 return ERING_WAS_FULL;
445 } else if (dev->sdr_head < dev->sdr_tail) {
446 if (tmp < dev->sdr_head || tmp >= dev->sdr_tail)
447 return ERING_WAS_FULL;
448 } /* the head = tail, or empty case is already take cared */
449 dev->sdr_head = tmp;
450
451 return retval;
452}
453
454static u32 crypto4xx_put_sd_to_sdr(struct crypto4xx_device *dev)
455{
456 unsigned long flags;
457
458 spin_lock_irqsave(&dev->core_dev->lock, flags);
459 if (dev->sdr_tail == dev->sdr_head) {
460 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
461 return 0;
462 }
463 if (dev->sdr_tail != PPC4XX_LAST_SD)
464 dev->sdr_tail++;
465 else
466 dev->sdr_tail = 0;
467 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
468
469 return 0;
470}
471
472static inline struct ce_sd *crypto4xx_get_sdp(struct crypto4xx_device *dev,
473 dma_addr_t *sd_dma, u32 idx)
474{
475 *sd_dma = dev->sdr_pa + sizeof(struct ce_sd) * idx;
476
477 return (struct ce_sd *)(dev->sdr + sizeof(struct ce_sd) * idx);
478}
479
480static u32 crypto4xx_fill_one_page(struct crypto4xx_device *dev,
481 dma_addr_t *addr, u32 *length,
482 u32 *idx, u32 *offset, u32 *nbytes)
483{
484 u32 len;
485
486 if (*length > dev->scatter_buffer_size) {
487 memcpy(phys_to_virt(*addr),
488 dev->scatter_buffer_va +
489 *idx * dev->scatter_buffer_size + *offset,
490 dev->scatter_buffer_size);
491 *offset = 0;
492 *length -= dev->scatter_buffer_size;
493 *nbytes -= dev->scatter_buffer_size;
494 if (*idx == PPC4XX_LAST_SD)
495 *idx = 0;
496 else
497 (*idx)++;
498 *addr = *addr + dev->scatter_buffer_size;
499 return 1;
500 } else if (*length < dev->scatter_buffer_size) {
501 memcpy(phys_to_virt(*addr),
502 dev->scatter_buffer_va +
503 *idx * dev->scatter_buffer_size + *offset, *length);
504 if ((*offset + *length) == dev->scatter_buffer_size) {
505 if (*idx == PPC4XX_LAST_SD)
506 *idx = 0;
507 else
508 (*idx)++;
509 *nbytes -= *length;
510 *offset = 0;
511 } else {
512 *nbytes -= *length;
513 *offset += *length;
514 }
515
516 return 0;
517 } else {
518 len = (*nbytes <= dev->scatter_buffer_size) ?
519 (*nbytes) : dev->scatter_buffer_size;
520 memcpy(phys_to_virt(*addr),
521 dev->scatter_buffer_va +
522 *idx * dev->scatter_buffer_size + *offset,
523 len);
524 *offset = 0;
525 *nbytes -= len;
526
527 if (*idx == PPC4XX_LAST_SD)
528 *idx = 0;
529 else
530 (*idx)++;
531
532 return 0;
533 }
534}
535
536static void crypto4xx_copy_pkt_to_dst(struct crypto4xx_device *dev,
537 struct ce_pd *pd,
538 struct pd_uinfo *pd_uinfo,
539 u32 nbytes,
540 struct scatterlist *dst)
541{
542 dma_addr_t addr;
543 u32 this_sd;
544 u32 offset;
545 u32 len;
546 u32 i;
547 u32 sg_len;
548 struct scatterlist *sg;
549
550 this_sd = pd_uinfo->first_sd;
551 offset = 0;
552 i = 0;
553
554 while (nbytes) {
555 sg = &dst[i];
556 sg_len = sg->length;
557 addr = dma_map_page(dev->core_dev->device, sg_page(sg),
558 sg->offset, sg->length, DMA_TO_DEVICE);
559
560 if (offset == 0) {
561 len = (nbytes <= sg->length) ? nbytes : sg->length;
562 while (crypto4xx_fill_one_page(dev, &addr, &len,
563 &this_sd, &offset, &nbytes))
564 ;
565 if (!nbytes)
566 return;
567 i++;
568 } else {
569 len = (nbytes <= (dev->scatter_buffer_size - offset)) ?
570 nbytes : (dev->scatter_buffer_size - offset);
571 len = (sg->length < len) ? sg->length : len;
572 while (crypto4xx_fill_one_page(dev, &addr, &len,
573 &this_sd, &offset, &nbytes))
574 ;
575 if (!nbytes)
576 return;
577 sg_len -= len;
578 if (sg_len) {
579 addr += len;
580 while (crypto4xx_fill_one_page(dev, &addr,
581 &sg_len, &this_sd, &offset, &nbytes))
582 ;
583 }
584 i++;
585 }
586 }
587}
588
589static u32 crypto4xx_copy_digest_to_dst(struct pd_uinfo *pd_uinfo,
590 struct crypto4xx_ctx *ctx)
591{
592 struct dynamic_sa_ctl *sa = (struct dynamic_sa_ctl *) ctx->sa_in;
593 struct sa_state_record *state_record =
594 (struct sa_state_record *) pd_uinfo->sr_va;
595
596 if (sa->sa_command_0.bf.hash_alg == SA_HASH_ALG_SHA1) {
597 memcpy((void *) pd_uinfo->dest_va, state_record->save_digest,
598 SA_HASH_ALG_SHA1_DIGEST_SIZE);
599 }
600
601 return 0;
602}
603
604static void crypto4xx_ret_sg_desc(struct crypto4xx_device *dev,
605 struct pd_uinfo *pd_uinfo)
606{
607 int i;
608 if (pd_uinfo->num_gd) {
609 for (i = 0; i < pd_uinfo->num_gd; i++)
610 crypto4xx_put_gd_to_gdr(dev);
611 pd_uinfo->first_gd = 0xffffffff;
612 pd_uinfo->num_gd = 0;
613 }
614 if (pd_uinfo->num_sd) {
615 for (i = 0; i < pd_uinfo->num_sd; i++)
616 crypto4xx_put_sd_to_sdr(dev);
617
618 pd_uinfo->first_sd = 0xffffffff;
619 pd_uinfo->num_sd = 0;
620 }
621}
622
623static u32 crypto4xx_ablkcipher_done(struct crypto4xx_device *dev,
624 struct pd_uinfo *pd_uinfo,
625 struct ce_pd *pd)
626{
627 struct crypto4xx_ctx *ctx;
628 struct ablkcipher_request *ablk_req;
629 struct scatterlist *dst;
630 dma_addr_t addr;
631
632 ablk_req = ablkcipher_request_cast(pd_uinfo->async_req);
633 ctx = crypto_tfm_ctx(ablk_req->base.tfm);
634
635 if (pd_uinfo->using_sd) {
636 crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo, ablk_req->nbytes,
637 ablk_req->dst);
638 } else {
639 dst = pd_uinfo->dest_va;
640 addr = dma_map_page(dev->core_dev->device, sg_page(dst),
641 dst->offset, dst->length, DMA_FROM_DEVICE);
642 }
643 crypto4xx_ret_sg_desc(dev, pd_uinfo);
644 if (ablk_req->base.complete != NULL)
645 ablk_req->base.complete(&ablk_req->base, 0);
646
647 return 0;
648}
649
650static u32 crypto4xx_ahash_done(struct crypto4xx_device *dev,
651 struct pd_uinfo *pd_uinfo)
652{
653 struct crypto4xx_ctx *ctx;
654 struct ahash_request *ahash_req;
655
656 ahash_req = ahash_request_cast(pd_uinfo->async_req);
657 ctx = crypto_tfm_ctx(ahash_req->base.tfm);
658
659 crypto4xx_copy_digest_to_dst(pd_uinfo,
660 crypto_tfm_ctx(ahash_req->base.tfm));
661 crypto4xx_ret_sg_desc(dev, pd_uinfo);
662 /* call user provided callback function x */
663 if (ahash_req->base.complete != NULL)
664 ahash_req->base.complete(&ahash_req->base, 0);
665
666 return 0;
667}
668
669static u32 crypto4xx_pd_done(struct crypto4xx_device *dev, u32 idx)
670{
671 struct ce_pd *pd;
672 struct pd_uinfo *pd_uinfo;
673
674 pd = dev->pdr + sizeof(struct ce_pd)*idx;
675 pd_uinfo = dev->pdr_uinfo + sizeof(struct pd_uinfo)*idx;
676 if (crypto_tfm_alg_type(pd_uinfo->async_req->tfm) ==
677 CRYPTO_ALG_TYPE_ABLKCIPHER)
678 return crypto4xx_ablkcipher_done(dev, pd_uinfo, pd);
679 else
680 return crypto4xx_ahash_done(dev, pd_uinfo);
681}
682
683/**
684 * Note: Only use this function to copy items that is word aligned.
685 */
686void crypto4xx_memcpy_le(unsigned int *dst,
687 const unsigned char *buf,
688 int len)
689{
690 u8 *tmp;
691 for (; len >= 4; buf += 4, len -= 4)
692 *dst++ = cpu_to_le32(*(unsigned int *) buf);
693
694 tmp = (u8 *)dst;
695 switch (len) {
696 case 3:
697 *tmp++ = 0;
698 *tmp++ = *(buf+2);
699 *tmp++ = *(buf+1);
700 *tmp++ = *buf;
701 break;
702 case 2:
703 *tmp++ = 0;
704 *tmp++ = 0;
705 *tmp++ = *(buf+1);
706 *tmp++ = *buf;
707 break;
708 case 1:
709 *tmp++ = 0;
710 *tmp++ = 0;
711 *tmp++ = 0;
712 *tmp++ = *buf;
713 break;
714 default:
715 break;
716 }
717}
718
719static void crypto4xx_stop_all(struct crypto4xx_core_device *core_dev)
720{
721 crypto4xx_destroy_pdr(core_dev->dev);
722 crypto4xx_destroy_gdr(core_dev->dev);
723 crypto4xx_destroy_sdr(core_dev->dev);
724 dev_set_drvdata(core_dev->device, NULL);
725 iounmap(core_dev->dev->ce_base);
726 kfree(core_dev->dev);
727 kfree(core_dev);
728}
729
730void crypto4xx_return_pd(struct crypto4xx_device *dev,
731 u32 pd_entry, struct ce_pd *pd,
732 struct pd_uinfo *pd_uinfo)
733{
734 /* irq should be already disabled */
735 dev->pdr_head = pd_entry;
736 pd->pd_ctl.w = 0;
737 pd->pd_ctl_len.w = 0;
738 pd_uinfo->state = PD_ENTRY_FREE;
739}
740
741/*
742 * derive number of elements in scatterlist
743 * Shamlessly copy from talitos.c
744 */
745static int get_sg_count(struct scatterlist *sg_list, int nbytes)
746{
747 struct scatterlist *sg = sg_list;
748 int sg_nents = 0;
749
750 while (nbytes) {
751 sg_nents++;
752 if (sg->length > nbytes)
753 break;
754 nbytes -= sg->length;
755 sg = sg_next(sg);
756 }
757
758 return sg_nents;
759}
760
761static u32 get_next_gd(u32 current)
762{
763 if (current != PPC4XX_LAST_GD)
764 return current + 1;
765 else
766 return 0;
767}
768
769static u32 get_next_sd(u32 current)
770{
771 if (current != PPC4XX_LAST_SD)
772 return current + 1;
773 else
774 return 0;
775}
776
777u32 crypto4xx_build_pd(struct crypto_async_request *req,
778 struct crypto4xx_ctx *ctx,
779 struct scatterlist *src,
780 struct scatterlist *dst,
781 unsigned int datalen,
782 void *iv, u32 iv_len)
783{
784 struct crypto4xx_device *dev = ctx->dev;
785 dma_addr_t addr, pd_dma, sd_dma, gd_dma;
786 struct dynamic_sa_ctl *sa;
787 struct scatterlist *sg;
788 struct ce_gd *gd;
789 struct ce_pd *pd;
790 u32 num_gd, num_sd;
791 u32 fst_gd = 0xffffffff;
792 u32 fst_sd = 0xffffffff;
793 u32 pd_entry;
794 unsigned long flags;
795 struct pd_uinfo *pd_uinfo = NULL;
796 unsigned int nbytes = datalen, idx;
797 unsigned int ivlen = 0;
798 u32 gd_idx = 0;
799
800 /* figure how many gd is needed */
801 num_gd = get_sg_count(src, datalen);
802 if (num_gd == 1)
803 num_gd = 0;
804
805 /* figure how many sd is needed */
806 if (sg_is_last(dst) || ctx->is_hash) {
807 num_sd = 0;
808 } else {
809 if (datalen > PPC4XX_SD_BUFFER_SIZE) {
810 num_sd = datalen / PPC4XX_SD_BUFFER_SIZE;
811 if (datalen % PPC4XX_SD_BUFFER_SIZE)
812 num_sd++;
813 } else {
814 num_sd = 1;
815 }
816 }
817
818 /*
819 * The follow section of code needs to be protected
820 * The gather ring and scatter ring needs to be consecutive
821 * In case of run out of any kind of descriptor, the descriptor
822 * already got must be return the original place.
823 */
824 spin_lock_irqsave(&dev->core_dev->lock, flags);
825 if (num_gd) {
826 fst_gd = crypto4xx_get_n_gd(dev, num_gd);
827 if (fst_gd == ERING_WAS_FULL) {
828 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
829 return -EAGAIN;
830 }
831 }
832 if (num_sd) {
833 fst_sd = crypto4xx_get_n_sd(dev, num_sd);
834 if (fst_sd == ERING_WAS_FULL) {
835 if (num_gd)
836 dev->gdr_head = fst_gd;
837 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
838 return -EAGAIN;
839 }
840 }
841 pd_entry = crypto4xx_get_pd_from_pdr_nolock(dev);
842 if (pd_entry == ERING_WAS_FULL) {
843 if (num_gd)
844 dev->gdr_head = fst_gd;
845 if (num_sd)
846 dev->sdr_head = fst_sd;
847 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
848 return -EAGAIN;
849 }
850 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
851
852 pd_uinfo = (struct pd_uinfo *)(dev->pdr_uinfo +
853 sizeof(struct pd_uinfo) * pd_entry);
854 pd = crypto4xx_get_pdp(dev, &pd_dma, pd_entry);
855 pd_uinfo->async_req = req;
856 pd_uinfo->num_gd = num_gd;
857 pd_uinfo->num_sd = num_sd;
858
859 if (iv_len || ctx->is_hash) {
860 ivlen = iv_len;
861 pd->sa = pd_uinfo->sa_pa;
862 sa = (struct dynamic_sa_ctl *) pd_uinfo->sa_va;
863 if (ctx->direction == DIR_INBOUND)
864 memcpy(sa, ctx->sa_in, ctx->sa_len * 4);
865 else
866 memcpy(sa, ctx->sa_out, ctx->sa_len * 4);
867
868 memcpy((void *) sa + ctx->offset_to_sr_ptr,
869 &pd_uinfo->sr_pa, 4);
870
871 if (iv_len)
872 crypto4xx_memcpy_le(pd_uinfo->sr_va, iv, iv_len);
873 } else {
874 if (ctx->direction == DIR_INBOUND) {
875 pd->sa = ctx->sa_in_dma_addr;
876 sa = (struct dynamic_sa_ctl *) ctx->sa_in;
877 } else {
878 pd->sa = ctx->sa_out_dma_addr;
879 sa = (struct dynamic_sa_ctl *) ctx->sa_out;
880 }
881 }
882 pd->sa_len = ctx->sa_len;
883 if (num_gd) {
884 /* get first gd we are going to use */
885 gd_idx = fst_gd;
886 pd_uinfo->first_gd = fst_gd;
887 pd_uinfo->num_gd = num_gd;
888 gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
889 pd->src = gd_dma;
890 /* enable gather */
891 sa->sa_command_0.bf.gather = 1;
892 idx = 0;
893 src = &src[0];
894 /* walk the sg, and setup gather array */
895 while (nbytes) {
896 sg = &src[idx];
897 addr = dma_map_page(dev->core_dev->device, sg_page(sg),
898 sg->offset, sg->length, DMA_TO_DEVICE);
899 gd->ptr = addr;
900 gd->ctl_len.len = sg->length;
901 gd->ctl_len.done = 0;
902 gd->ctl_len.ready = 1;
903 if (sg->length >= nbytes)
904 break;
905 nbytes -= sg->length;
906 gd_idx = get_next_gd(gd_idx);
907 gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
908 idx++;
909 }
910 } else {
911 pd->src = (u32)dma_map_page(dev->core_dev->device, sg_page(src),
912 src->offset, src->length, DMA_TO_DEVICE);
913 /*
914 * Disable gather in sa command
915 */
916 sa->sa_command_0.bf.gather = 0;
917 /*
918 * Indicate gather array is not used
919 */
920 pd_uinfo->first_gd = 0xffffffff;
921 pd_uinfo->num_gd = 0;
922 }
923 if (ctx->is_hash || sg_is_last(dst)) {
924 /*
925 * we know application give us dst a whole piece of memory
926 * no need to use scatter ring.
927 * In case of is_hash, the icv is always at end of src data.
928 */
929 pd_uinfo->using_sd = 0;
930 pd_uinfo->first_sd = 0xffffffff;
931 pd_uinfo->num_sd = 0;
932 pd_uinfo->dest_va = dst;
933 sa->sa_command_0.bf.scatter = 0;
934 if (ctx->is_hash)
935 pd->dest = virt_to_phys((void *)dst);
936 else
937 pd->dest = (u32)dma_map_page(dev->core_dev->device,
938 sg_page(dst), dst->offset,
939 dst->length, DMA_TO_DEVICE);
940 } else {
941 struct ce_sd *sd = NULL;
942 u32 sd_idx = fst_sd;
943 nbytes = datalen;
944 sa->sa_command_0.bf.scatter = 1;
945 pd_uinfo->using_sd = 1;
946 pd_uinfo->dest_va = dst;
947 pd_uinfo->first_sd = fst_sd;
948 pd_uinfo->num_sd = num_sd;
949 sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
950 pd->dest = sd_dma;
951 /* setup scatter descriptor */
952 sd->ctl.done = 0;
953 sd->ctl.rdy = 1;
954 /* sd->ptr should be setup by sd_init routine*/
955 idx = 0;
956 if (nbytes >= PPC4XX_SD_BUFFER_SIZE)
957 nbytes -= PPC4XX_SD_BUFFER_SIZE;
958 else
959 nbytes = 0;
960 while (nbytes) {
961 sd_idx = get_next_sd(sd_idx);
962 sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
963 /* setup scatter descriptor */
964 sd->ctl.done = 0;
965 sd->ctl.rdy = 1;
966 if (nbytes >= PPC4XX_SD_BUFFER_SIZE)
967 nbytes -= PPC4XX_SD_BUFFER_SIZE;
968 else
969 /*
970 * SD entry can hold PPC4XX_SD_BUFFER_SIZE,
971 * which is more than nbytes, so done.
972 */
973 nbytes = 0;
974 }
975 }
976
977 sa->sa_command_1.bf.hash_crypto_offset = 0;
978 pd->pd_ctl.w = ctx->pd_ctl;
979 pd->pd_ctl_len.w = 0x00400000 | (ctx->bypass << 24) | datalen;
980 pd_uinfo->state = PD_ENTRY_INUSE;
981 wmb();
982 /* write any value to push engine to read a pd */
983 writel(1, dev->ce_base + CRYPTO4XX_INT_DESCR_RD);
984 return -EINPROGRESS;
985}
986
987/**
988 * Algorithm Registration Functions
989 */
990static int crypto4xx_alg_init(struct crypto_tfm *tfm)
991{
992 struct crypto_alg *alg = tfm->__crt_alg;
993 struct crypto4xx_alg *amcc_alg = crypto_alg_to_crypto4xx_alg(alg);
994 struct crypto4xx_ctx *ctx = crypto_tfm_ctx(tfm);
995
996 ctx->dev = amcc_alg->dev;
997 ctx->sa_in = NULL;
998 ctx->sa_out = NULL;
999 ctx->sa_in_dma_addr = 0;
1000 ctx->sa_out_dma_addr = 0;
1001 ctx->sa_len = 0;
1002
1003 switch (alg->cra_flags & CRYPTO_ALG_TYPE_MASK) {
1004 default:
1005 tfm->crt_ablkcipher.reqsize = sizeof(struct crypto4xx_ctx);
1006 break;
1007 case CRYPTO_ALG_TYPE_AHASH:
1008 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1009 sizeof(struct crypto4xx_ctx));
1010 break;
1011 }
1012
1013 return 0;
1014}
1015
1016static void crypto4xx_alg_exit(struct crypto_tfm *tfm)
1017{
1018 struct crypto4xx_ctx *ctx = crypto_tfm_ctx(tfm);
1019
1020 crypto4xx_free_sa(ctx);
1021 crypto4xx_free_state_record(ctx);
1022}
1023
1024int crypto4xx_register_alg(struct crypto4xx_device *sec_dev,
1025 struct crypto4xx_alg_common *crypto_alg,
1026 int array_size)
1027{
1028 struct crypto4xx_alg *alg;
1029 int i;
1030 int rc = 0;
1031
1032 for (i = 0; i < array_size; i++) {
1033 alg = kzalloc(sizeof(struct crypto4xx_alg), GFP_KERNEL);
1034 if (!alg)
1035 return -ENOMEM;
1036
1037 alg->alg = crypto_alg[i];
1038 alg->dev = sec_dev;
1039
1040 switch (alg->alg.type) {
1041 case CRYPTO_ALG_TYPE_AHASH:
1042 rc = crypto_register_ahash(&alg->alg.u.hash);
1043 break;
1044
1045 default:
1046 rc = crypto_register_alg(&alg->alg.u.cipher);
1047 break;
1048 }
1049
1050 if (rc) {
1051 list_del(&alg->entry);
1052 kfree(alg);
1053 } else {
1054 list_add_tail(&alg->entry, &sec_dev->alg_list);
1055 }
1056 }
1057
1058 return 0;
1059}
1060
1061static void crypto4xx_unregister_alg(struct crypto4xx_device *sec_dev)
1062{
1063 struct crypto4xx_alg *alg, *tmp;
1064
1065 list_for_each_entry_safe(alg, tmp, &sec_dev->alg_list, entry) {
1066 list_del(&alg->entry);
1067 switch (alg->alg.type) {
1068 case CRYPTO_ALG_TYPE_AHASH:
1069 crypto_unregister_ahash(&alg->alg.u.hash);
1070 break;
1071
1072 default:
1073 crypto_unregister_alg(&alg->alg.u.cipher);
1074 }
1075 kfree(alg);
1076 }
1077}
1078
1079static void crypto4xx_bh_tasklet_cb(unsigned long data)
1080{
1081 struct device *dev = (struct device *)data;
1082 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1083 struct pd_uinfo *pd_uinfo;
1084 struct ce_pd *pd;
1085 u32 tail;
1086
1087 while (core_dev->dev->pdr_head != core_dev->dev->pdr_tail) {
1088 tail = core_dev->dev->pdr_tail;
1089 pd_uinfo = core_dev->dev->pdr_uinfo +
1090 sizeof(struct pd_uinfo)*tail;
1091 pd = core_dev->dev->pdr + sizeof(struct ce_pd) * tail;
1092 if ((pd_uinfo->state == PD_ENTRY_INUSE) &&
1093 pd->pd_ctl.bf.pe_done &&
1094 !pd->pd_ctl.bf.host_ready) {
1095 pd->pd_ctl.bf.pe_done = 0;
1096 crypto4xx_pd_done(core_dev->dev, tail);
1097 crypto4xx_put_pd_to_pdr(core_dev->dev, tail);
1098 pd_uinfo->state = PD_ENTRY_FREE;
1099 } else {
1100 /* if tail not done, break */
1101 break;
1102 }
1103 }
1104}
1105
1106/**
1107 * Top Half of isr.
1108 */
1109static irqreturn_t crypto4xx_ce_interrupt_handler(int irq, void *data)
1110{
1111 struct device *dev = (struct device *)data;
1112 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1113
1114 if (core_dev->dev->ce_base == 0)
1115 return 0;
1116
1117 writel(PPC4XX_INTERRUPT_CLR,
1118 core_dev->dev->ce_base + CRYPTO4XX_INT_CLR);
1119 tasklet_schedule(&core_dev->tasklet);
1120
1121 return IRQ_HANDLED;
1122}
1123
1124/**
1125 * Supported Crypto Algorithms
1126 */
1127struct crypto4xx_alg_common crypto4xx_alg[] = {
1128 /* Crypto AES modes */
1129 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .u.cipher = {
1130 .cra_name = "cbc(aes)",
1131 .cra_driver_name = "cbc-aes-ppc4xx",
1132 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1133 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1134 .cra_blocksize = AES_BLOCK_SIZE,
1135 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1136 .cra_type = &crypto_ablkcipher_type,
1137 .cra_init = crypto4xx_alg_init,
1138 .cra_exit = crypto4xx_alg_exit,
1139 .cra_module = THIS_MODULE,
1140 .cra_u = {
1141 .ablkcipher = {
1142 .min_keysize = AES_MIN_KEY_SIZE,
1143 .max_keysize = AES_MAX_KEY_SIZE,
1144 .ivsize = AES_IV_SIZE,
1145 .setkey = crypto4xx_setkey_aes_cbc,
1146 .encrypt = crypto4xx_encrypt,
1147 .decrypt = crypto4xx_decrypt,
1148 }
1149 }
1150 }},
1151};
1152
1153/**
1154 * Module Initialization Routine
1155 */
1156static int __init crypto4xx_probe(struct platform_device *ofdev)
1157{
1158 int rc;
1159 struct resource res;
1160 struct device *dev = &ofdev->dev;
1161 struct crypto4xx_core_device *core_dev;
1162
1163 rc = of_address_to_resource(ofdev->dev.of_node, 0, &res);
1164 if (rc)
1165 return -ENODEV;
1166
1167 if (of_find_compatible_node(NULL, NULL, "amcc,ppc460ex-crypto")) {
1168 mtdcri(SDR0, PPC460EX_SDR0_SRST,
1169 mfdcri(SDR0, PPC460EX_SDR0_SRST) | PPC460EX_CE_RESET);
1170 mtdcri(SDR0, PPC460EX_SDR0_SRST,
1171 mfdcri(SDR0, PPC460EX_SDR0_SRST) & ~PPC460EX_CE_RESET);
1172 } else if (of_find_compatible_node(NULL, NULL,
1173 "amcc,ppc405ex-crypto")) {
1174 mtdcri(SDR0, PPC405EX_SDR0_SRST,
1175 mfdcri(SDR0, PPC405EX_SDR0_SRST) | PPC405EX_CE_RESET);
1176 mtdcri(SDR0, PPC405EX_SDR0_SRST,
1177 mfdcri(SDR0, PPC405EX_SDR0_SRST) & ~PPC405EX_CE_RESET);
1178 } else if (of_find_compatible_node(NULL, NULL,
1179 "amcc,ppc460sx-crypto")) {
1180 mtdcri(SDR0, PPC460SX_SDR0_SRST,
1181 mfdcri(SDR0, PPC460SX_SDR0_SRST) | PPC460SX_CE_RESET);
1182 mtdcri(SDR0, PPC460SX_SDR0_SRST,
1183 mfdcri(SDR0, PPC460SX_SDR0_SRST) & ~PPC460SX_CE_RESET);
1184 } else {
1185 printk(KERN_ERR "Crypto Function Not supported!\n");
1186 return -EINVAL;
1187 }
1188
1189 core_dev = kzalloc(sizeof(struct crypto4xx_core_device), GFP_KERNEL);
1190 if (!core_dev)
1191 return -ENOMEM;
1192
1193 dev_set_drvdata(dev, core_dev);
1194 core_dev->ofdev = ofdev;
1195 core_dev->dev = kzalloc(sizeof(struct crypto4xx_device), GFP_KERNEL);
1196 if (!core_dev->dev)
1197 goto err_alloc_dev;
1198
1199 core_dev->dev->core_dev = core_dev;
1200 core_dev->device = dev;
1201 spin_lock_init(&core_dev->lock);
1202 INIT_LIST_HEAD(&core_dev->dev->alg_list);
1203 rc = crypto4xx_build_pdr(core_dev->dev);
1204 if (rc)
1205 goto err_build_pdr;
1206
1207 rc = crypto4xx_build_gdr(core_dev->dev);
1208 if (rc)
1209 goto err_build_gdr;
1210
1211 rc = crypto4xx_build_sdr(core_dev->dev);
1212 if (rc)
1213 goto err_build_sdr;
1214
1215 /* Init tasklet for bottom half processing */
1216 tasklet_init(&core_dev->tasklet, crypto4xx_bh_tasklet_cb,
1217 (unsigned long) dev);
1218
1219 /* Register for Crypto isr, Crypto Engine IRQ */
1220 core_dev->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1221 rc = request_irq(core_dev->irq, crypto4xx_ce_interrupt_handler, 0,
1222 core_dev->dev->name, dev);
1223 if (rc)
1224 goto err_request_irq;
1225
1226 core_dev->dev->ce_base = of_iomap(ofdev->dev.of_node, 0);
1227 if (!core_dev->dev->ce_base) {
1228 dev_err(dev, "failed to of_iomap\n");
1229 goto err_iomap;
1230 }
1231
1232 /* need to setup pdr, rdr, gdr and sdr before this */
1233 crypto4xx_hw_init(core_dev->dev);
1234
1235 /* Register security algorithms with Linux CryptoAPI */
1236 rc = crypto4xx_register_alg(core_dev->dev, crypto4xx_alg,
1237 ARRAY_SIZE(crypto4xx_alg));
1238 if (rc)
1239 goto err_start_dev;
1240
1241 return 0;
1242
1243err_start_dev:
1244 iounmap(core_dev->dev->ce_base);
1245err_iomap:
1246 free_irq(core_dev->irq, dev);
1247 irq_dispose_mapping(core_dev->irq);
1248 tasklet_kill(&core_dev->tasklet);
1249err_request_irq:
1250 crypto4xx_destroy_sdr(core_dev->dev);
1251err_build_sdr:
1252 crypto4xx_destroy_gdr(core_dev->dev);
1253err_build_gdr:
1254 crypto4xx_destroy_pdr(core_dev->dev);
1255err_build_pdr:
1256 kfree(core_dev->dev);
1257err_alloc_dev:
1258 kfree(core_dev);
1259
1260 return rc;
1261}
1262
1263static int __exit crypto4xx_remove(struct platform_device *ofdev)
1264{
1265 struct device *dev = &ofdev->dev;
1266 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1267
1268 free_irq(core_dev->irq, dev);
1269 irq_dispose_mapping(core_dev->irq);
1270
1271 tasklet_kill(&core_dev->tasklet);
1272 /* Un-register with Linux CryptoAPI */
1273 crypto4xx_unregister_alg(core_dev->dev);
1274 /* Free all allocated memory */
1275 crypto4xx_stop_all(core_dev);
1276
1277 return 0;
1278}
1279
1280static const struct of_device_id crypto4xx_match[] = {
1281 { .compatible = "amcc,ppc4xx-crypto",},
1282 { },
1283};
1284
1285static struct platform_driver crypto4xx_driver = {
1286 .driver = {
1287 .name = "crypto4xx",
1288 .owner = THIS_MODULE,
1289 .of_match_table = crypto4xx_match,
1290 },
1291 .probe = crypto4xx_probe,
1292 .remove = crypto4xx_remove,
1293};
1294
1295static int __init crypto4xx_init(void)
1296{
1297 return platform_driver_register(&crypto4xx_driver);
1298}
1299
1300static void __exit crypto4xx_exit(void)
1301{
1302 platform_driver_unregister(&crypto4xx_driver);
1303}
1304
1305module_init(crypto4xx_init);
1306module_exit(crypto4xx_exit);
1307
1308MODULE_LICENSE("GPL");
1309MODULE_AUTHOR("James Hsiao <jhsiao@amcc.com>");
1310MODULE_DESCRIPTION("Driver for AMCC PPC4xx crypto accelerator");
1311