Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH Timer Support - TMU
4 *
5 * Copyright (C) 2009 Magnus Damm
6 */
7
8#include <linux/clk.h>
9#include <linux/clockchips.h>
10#include <linux/clocksource.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/ioport.h>
17#include <linux/irq.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/pm_domain.h>
22#include <linux/pm_runtime.h>
23#include <linux/sh_timer.h>
24#include <linux/slab.h>
25#include <linux/spinlock.h>
26
27#ifdef CONFIG_SUPERH
28#include <asm/platform_early.h>
29#endif
30
31enum sh_tmu_model {
32 SH_TMU,
33 SH_TMU_SH3,
34};
35
36struct sh_tmu_device;
37
38struct sh_tmu_channel {
39 struct sh_tmu_device *tmu;
40 unsigned int index;
41
42 void __iomem *base;
43 int irq;
44
45 unsigned long periodic;
46 struct clock_event_device ced;
47 struct clocksource cs;
48 bool cs_enabled;
49 unsigned int enable_count;
50};
51
52struct sh_tmu_device {
53 struct platform_device *pdev;
54
55 void __iomem *mapbase;
56 struct clk *clk;
57 unsigned long rate;
58
59 enum sh_tmu_model model;
60
61 raw_spinlock_t lock; /* Protect the shared start/stop register */
62
63 struct sh_tmu_channel *channels;
64 unsigned int num_channels;
65
66 bool has_clockevent;
67 bool has_clocksource;
68};
69
70#define TSTR -1 /* shared register */
71#define TCOR 0 /* channel register */
72#define TCNT 1 /* channel register */
73#define TCR 2 /* channel register */
74
75#define TCR_UNF (1 << 8)
76#define TCR_UNIE (1 << 5)
77#define TCR_TPSC_CLK4 (0 << 0)
78#define TCR_TPSC_CLK16 (1 << 0)
79#define TCR_TPSC_CLK64 (2 << 0)
80#define TCR_TPSC_CLK256 (3 << 0)
81#define TCR_TPSC_CLK1024 (4 << 0)
82#define TCR_TPSC_MASK (7 << 0)
83
84static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
85{
86 unsigned long offs;
87
88 if (reg_nr == TSTR) {
89 switch (ch->tmu->model) {
90 case SH_TMU_SH3:
91 return ioread8(ch->tmu->mapbase + 2);
92 case SH_TMU:
93 return ioread8(ch->tmu->mapbase + 4);
94 }
95 }
96
97 offs = reg_nr << 2;
98
99 if (reg_nr == TCR)
100 return ioread16(ch->base + offs);
101 else
102 return ioread32(ch->base + offs);
103}
104
105static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
106 unsigned long value)
107{
108 unsigned long offs;
109
110 if (reg_nr == TSTR) {
111 switch (ch->tmu->model) {
112 case SH_TMU_SH3:
113 return iowrite8(value, ch->tmu->mapbase + 2);
114 case SH_TMU:
115 return iowrite8(value, ch->tmu->mapbase + 4);
116 }
117 }
118
119 offs = reg_nr << 2;
120
121 if (reg_nr == TCR)
122 iowrite16(value, ch->base + offs);
123 else
124 iowrite32(value, ch->base + offs);
125}
126
127static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
128{
129 unsigned long flags, value;
130
131 /* start stop register shared by multiple timer channels */
132 raw_spin_lock_irqsave(&ch->tmu->lock, flags);
133 value = sh_tmu_read(ch, TSTR);
134
135 if (start)
136 value |= 1 << ch->index;
137 else
138 value &= ~(1 << ch->index);
139
140 sh_tmu_write(ch, TSTR, value);
141 raw_spin_unlock_irqrestore(&ch->tmu->lock, flags);
142}
143
144static int __sh_tmu_enable(struct sh_tmu_channel *ch)
145{
146 int ret;
147
148 /* enable clock */
149 ret = clk_enable(ch->tmu->clk);
150 if (ret) {
151 dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
152 ch->index);
153 return ret;
154 }
155
156 /* make sure channel is disabled */
157 sh_tmu_start_stop_ch(ch, 0);
158
159 /* maximum timeout */
160 sh_tmu_write(ch, TCOR, 0xffffffff);
161 sh_tmu_write(ch, TCNT, 0xffffffff);
162
163 /* configure channel to parent clock / 4, irq off */
164 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
165
166 /* enable channel */
167 sh_tmu_start_stop_ch(ch, 1);
168
169 return 0;
170}
171
172static int sh_tmu_enable(struct sh_tmu_channel *ch)
173{
174 if (ch->enable_count++ > 0)
175 return 0;
176
177 pm_runtime_get_sync(&ch->tmu->pdev->dev);
178 dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
179
180 return __sh_tmu_enable(ch);
181}
182
183static void __sh_tmu_disable(struct sh_tmu_channel *ch)
184{
185 /* disable channel */
186 sh_tmu_start_stop_ch(ch, 0);
187
188 /* disable interrupts in TMU block */
189 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
190
191 /* stop clock */
192 clk_disable(ch->tmu->clk);
193}
194
195static void sh_tmu_disable(struct sh_tmu_channel *ch)
196{
197 if (WARN_ON(ch->enable_count == 0))
198 return;
199
200 if (--ch->enable_count > 0)
201 return;
202
203 __sh_tmu_disable(ch);
204
205 dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
206 pm_runtime_put(&ch->tmu->pdev->dev);
207}
208
209static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
210 int periodic)
211{
212 /* stop timer */
213 sh_tmu_start_stop_ch(ch, 0);
214
215 /* acknowledge interrupt */
216 sh_tmu_read(ch, TCR);
217
218 /* enable interrupt */
219 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
220
221 /* reload delta value in case of periodic timer */
222 if (periodic)
223 sh_tmu_write(ch, TCOR, delta);
224 else
225 sh_tmu_write(ch, TCOR, 0xffffffff);
226
227 sh_tmu_write(ch, TCNT, delta);
228
229 /* start timer */
230 sh_tmu_start_stop_ch(ch, 1);
231}
232
233static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
234{
235 struct sh_tmu_channel *ch = dev_id;
236
237 /* disable or acknowledge interrupt */
238 if (clockevent_state_oneshot(&ch->ced))
239 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
240 else
241 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
242
243 /* notify clockevent layer */
244 ch->ced.event_handler(&ch->ced);
245 return IRQ_HANDLED;
246}
247
248static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
249{
250 return container_of(cs, struct sh_tmu_channel, cs);
251}
252
253static u64 sh_tmu_clocksource_read(struct clocksource *cs)
254{
255 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
256
257 return sh_tmu_read(ch, TCNT) ^ 0xffffffff;
258}
259
260static int sh_tmu_clocksource_enable(struct clocksource *cs)
261{
262 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
263 int ret;
264
265 if (WARN_ON(ch->cs_enabled))
266 return 0;
267
268 ret = sh_tmu_enable(ch);
269 if (!ret)
270 ch->cs_enabled = true;
271
272 return ret;
273}
274
275static void sh_tmu_clocksource_disable(struct clocksource *cs)
276{
277 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
278
279 if (WARN_ON(!ch->cs_enabled))
280 return;
281
282 sh_tmu_disable(ch);
283 ch->cs_enabled = false;
284}
285
286static void sh_tmu_clocksource_suspend(struct clocksource *cs)
287{
288 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
289
290 if (!ch->cs_enabled)
291 return;
292
293 if (--ch->enable_count == 0) {
294 __sh_tmu_disable(ch);
295 dev_pm_genpd_suspend(&ch->tmu->pdev->dev);
296 }
297}
298
299static void sh_tmu_clocksource_resume(struct clocksource *cs)
300{
301 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
302
303 if (!ch->cs_enabled)
304 return;
305
306 if (ch->enable_count++ == 0) {
307 dev_pm_genpd_resume(&ch->tmu->pdev->dev);
308 __sh_tmu_enable(ch);
309 }
310}
311
312static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
313 const char *name)
314{
315 struct clocksource *cs = &ch->cs;
316
317 cs->name = name;
318 cs->rating = 200;
319 cs->read = sh_tmu_clocksource_read;
320 cs->enable = sh_tmu_clocksource_enable;
321 cs->disable = sh_tmu_clocksource_disable;
322 cs->suspend = sh_tmu_clocksource_suspend;
323 cs->resume = sh_tmu_clocksource_resume;
324 cs->mask = CLOCKSOURCE_MASK(32);
325 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
326
327 dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
328 ch->index);
329
330 clocksource_register_hz(cs, ch->tmu->rate);
331 return 0;
332}
333
334static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
335{
336 return container_of(ced, struct sh_tmu_channel, ced);
337}
338
339static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)
340{
341 sh_tmu_enable(ch);
342
343 if (periodic) {
344 ch->periodic = (ch->tmu->rate + HZ/2) / HZ;
345 sh_tmu_set_next(ch, ch->periodic, 1);
346 }
347}
348
349static int sh_tmu_clock_event_shutdown(struct clock_event_device *ced)
350{
351 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
352
353 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
354 sh_tmu_disable(ch);
355 return 0;
356}
357
358static int sh_tmu_clock_event_set_state(struct clock_event_device *ced,
359 int periodic)
360{
361 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
362
363 /* deal with old setting first */
364 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
365 sh_tmu_disable(ch);
366
367 dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n",
368 ch->index, periodic ? "periodic" : "oneshot");
369 sh_tmu_clock_event_start(ch, periodic);
370 return 0;
371}
372
373static int sh_tmu_clock_event_set_oneshot(struct clock_event_device *ced)
374{
375 return sh_tmu_clock_event_set_state(ced, 0);
376}
377
378static int sh_tmu_clock_event_set_periodic(struct clock_event_device *ced)
379{
380 return sh_tmu_clock_event_set_state(ced, 1);
381}
382
383static int sh_tmu_clock_event_next(unsigned long delta,
384 struct clock_event_device *ced)
385{
386 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
387
388 BUG_ON(!clockevent_state_oneshot(ced));
389
390 /* program new delta value */
391 sh_tmu_set_next(ch, delta, 0);
392 return 0;
393}
394
395static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
396{
397 dev_pm_genpd_suspend(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
398}
399
400static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
401{
402 dev_pm_genpd_resume(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
403}
404
405static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
406 const char *name)
407{
408 struct clock_event_device *ced = &ch->ced;
409 int ret;
410
411 ced->name = name;
412 ced->features = CLOCK_EVT_FEAT_PERIODIC;
413 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
414 ced->rating = 200;
415 ced->cpumask = cpu_possible_mask;
416 ced->set_next_event = sh_tmu_clock_event_next;
417 ced->set_state_shutdown = sh_tmu_clock_event_shutdown;
418 ced->set_state_periodic = sh_tmu_clock_event_set_periodic;
419 ced->set_state_oneshot = sh_tmu_clock_event_set_oneshot;
420 ced->suspend = sh_tmu_clock_event_suspend;
421 ced->resume = sh_tmu_clock_event_resume;
422
423 dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",
424 ch->index);
425
426 clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff);
427
428 ret = request_irq(ch->irq, sh_tmu_interrupt,
429 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
430 dev_name(&ch->tmu->pdev->dev), ch);
431 if (ret) {
432 dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",
433 ch->index, ch->irq);
434 return;
435 }
436}
437
438static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
439 bool clockevent, bool clocksource)
440{
441 if (clockevent) {
442 ch->tmu->has_clockevent = true;
443 sh_tmu_register_clockevent(ch, name);
444 } else if (clocksource) {
445 ch->tmu->has_clocksource = true;
446 sh_tmu_register_clocksource(ch, name);
447 }
448
449 return 0;
450}
451
452static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
453 bool clockevent, bool clocksource,
454 struct sh_tmu_device *tmu)
455{
456 /* Skip unused channels. */
457 if (!clockevent && !clocksource)
458 return 0;
459
460 ch->tmu = tmu;
461 ch->index = index;
462
463 if (tmu->model == SH_TMU_SH3)
464 ch->base = tmu->mapbase + 4 + ch->index * 12;
465 else
466 ch->base = tmu->mapbase + 8 + ch->index * 12;
467
468 ch->irq = platform_get_irq(tmu->pdev, index);
469 if (ch->irq < 0)
470 return ch->irq;
471
472 ch->cs_enabled = false;
473 ch->enable_count = 0;
474
475 return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
476 clockevent, clocksource);
477}
478
479static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
480{
481 struct resource *res;
482
483 res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
484 if (!res) {
485 dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
486 return -ENXIO;
487 }
488
489 tmu->mapbase = ioremap(res->start, resource_size(res));
490 if (tmu->mapbase == NULL)
491 return -ENXIO;
492
493 return 0;
494}
495
496static int sh_tmu_parse_dt(struct sh_tmu_device *tmu)
497{
498 struct device_node *np = tmu->pdev->dev.of_node;
499
500 tmu->model = SH_TMU;
501 tmu->num_channels = 3;
502
503 of_property_read_u32(np, "#renesas,channels", &tmu->num_channels);
504
505 if (tmu->num_channels != 2 && tmu->num_channels != 3) {
506 dev_err(&tmu->pdev->dev, "invalid number of channels %u\n",
507 tmu->num_channels);
508 return -EINVAL;
509 }
510
511 return 0;
512}
513
514static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
515{
516 unsigned int i;
517 int ret;
518
519 tmu->pdev = pdev;
520
521 raw_spin_lock_init(&tmu->lock);
522
523 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
524 ret = sh_tmu_parse_dt(tmu);
525 if (ret < 0)
526 return ret;
527 } else if (pdev->dev.platform_data) {
528 const struct platform_device_id *id = pdev->id_entry;
529 struct sh_timer_config *cfg = pdev->dev.platform_data;
530
531 tmu->model = id->driver_data;
532 tmu->num_channels = hweight8(cfg->channels_mask);
533 } else {
534 dev_err(&tmu->pdev->dev, "missing platform data\n");
535 return -ENXIO;
536 }
537
538 /* Get hold of clock. */
539 tmu->clk = clk_get(&tmu->pdev->dev, "fck");
540 if (IS_ERR(tmu->clk)) {
541 dev_err(&tmu->pdev->dev, "cannot get clock\n");
542 return PTR_ERR(tmu->clk);
543 }
544
545 ret = clk_prepare(tmu->clk);
546 if (ret < 0)
547 goto err_clk_put;
548
549 /* Determine clock rate. */
550 ret = clk_enable(tmu->clk);
551 if (ret < 0)
552 goto err_clk_unprepare;
553
554 tmu->rate = clk_get_rate(tmu->clk) / 4;
555 clk_disable(tmu->clk);
556
557 /* Map the memory resource. */
558 ret = sh_tmu_map_memory(tmu);
559 if (ret < 0) {
560 dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
561 goto err_clk_unprepare;
562 }
563
564 /* Allocate and setup the channels. */
565 tmu->channels = kcalloc(tmu->num_channels, sizeof(*tmu->channels),
566 GFP_KERNEL);
567 if (tmu->channels == NULL) {
568 ret = -ENOMEM;
569 goto err_unmap;
570 }
571
572 /*
573 * Use the first channel as a clock event device and the second channel
574 * as a clock source.
575 */
576 for (i = 0; i < tmu->num_channels; ++i) {
577 ret = sh_tmu_channel_setup(&tmu->channels[i], i,
578 i == 0, i == 1, tmu);
579 if (ret < 0)
580 goto err_unmap;
581 }
582
583 platform_set_drvdata(pdev, tmu);
584
585 return 0;
586
587err_unmap:
588 kfree(tmu->channels);
589 iounmap(tmu->mapbase);
590err_clk_unprepare:
591 clk_unprepare(tmu->clk);
592err_clk_put:
593 clk_put(tmu->clk);
594 return ret;
595}
596
597static int sh_tmu_probe(struct platform_device *pdev)
598{
599 struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
600 int ret;
601
602 if (!is_sh_early_platform_device(pdev)) {
603 pm_runtime_set_active(&pdev->dev);
604 pm_runtime_enable(&pdev->dev);
605 }
606
607 if (tmu) {
608 dev_info(&pdev->dev, "kept as earlytimer\n");
609 goto out;
610 }
611
612 tmu = kzalloc(sizeof(*tmu), GFP_KERNEL);
613 if (tmu == NULL)
614 return -ENOMEM;
615
616 ret = sh_tmu_setup(tmu, pdev);
617 if (ret) {
618 kfree(tmu);
619 pm_runtime_idle(&pdev->dev);
620 return ret;
621 }
622
623 if (is_sh_early_platform_device(pdev))
624 return 0;
625
626 out:
627 if (tmu->has_clockevent || tmu->has_clocksource)
628 pm_runtime_irq_safe(&pdev->dev);
629 else
630 pm_runtime_idle(&pdev->dev);
631
632 return 0;
633}
634
635static const struct platform_device_id sh_tmu_id_table[] = {
636 { "sh-tmu", SH_TMU },
637 { "sh-tmu-sh3", SH_TMU_SH3 },
638 { }
639};
640MODULE_DEVICE_TABLE(platform, sh_tmu_id_table);
641
642static const struct of_device_id sh_tmu_of_table[] __maybe_unused = {
643 { .compatible = "renesas,tmu" },
644 { }
645};
646MODULE_DEVICE_TABLE(of, sh_tmu_of_table);
647
648static struct platform_driver sh_tmu_device_driver = {
649 .probe = sh_tmu_probe,
650 .driver = {
651 .name = "sh_tmu",
652 .of_match_table = of_match_ptr(sh_tmu_of_table),
653 .suppress_bind_attrs = true,
654 },
655 .id_table = sh_tmu_id_table,
656};
657
658static int __init sh_tmu_init(void)
659{
660 return platform_driver_register(&sh_tmu_device_driver);
661}
662
663static void __exit sh_tmu_exit(void)
664{
665 platform_driver_unregister(&sh_tmu_device_driver);
666}
667
668#ifdef CONFIG_SUPERH
669sh_early_platform_init("earlytimer", &sh_tmu_device_driver);
670#endif
671
672subsys_initcall(sh_tmu_init);
673module_exit(sh_tmu_exit);
674
675MODULE_AUTHOR("Magnus Damm");
676MODULE_DESCRIPTION("SuperH TMU Timer Driver");
1/*
2 * SuperH Timer Support - TMU
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/clk.h>
28#include <linux/irq.h>
29#include <linux/err.h>
30#include <linux/clocksource.h>
31#include <linux/clockchips.h>
32#include <linux/sh_timer.h>
33#include <linux/slab.h>
34
35struct sh_tmu_priv {
36 void __iomem *mapbase;
37 struct clk *clk;
38 struct irqaction irqaction;
39 struct platform_device *pdev;
40 unsigned long rate;
41 unsigned long periodic;
42 struct clock_event_device ced;
43 struct clocksource cs;
44};
45
46static DEFINE_SPINLOCK(sh_tmu_lock);
47
48#define TSTR -1 /* shared register */
49#define TCOR 0 /* channel register */
50#define TCNT 1 /* channel register */
51#define TCR 2 /* channel register */
52
53static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
54{
55 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
56 void __iomem *base = p->mapbase;
57 unsigned long offs;
58
59 if (reg_nr == TSTR)
60 return ioread8(base - cfg->channel_offset);
61
62 offs = reg_nr << 2;
63
64 if (reg_nr == TCR)
65 return ioread16(base + offs);
66 else
67 return ioread32(base + offs);
68}
69
70static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
71 unsigned long value)
72{
73 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
74 void __iomem *base = p->mapbase;
75 unsigned long offs;
76
77 if (reg_nr == TSTR) {
78 iowrite8(value, base - cfg->channel_offset);
79 return;
80 }
81
82 offs = reg_nr << 2;
83
84 if (reg_nr == TCR)
85 iowrite16(value, base + offs);
86 else
87 iowrite32(value, base + offs);
88}
89
90static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
91{
92 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
93 unsigned long flags, value;
94
95 /* start stop register shared by multiple timer channels */
96 spin_lock_irqsave(&sh_tmu_lock, flags);
97 value = sh_tmu_read(p, TSTR);
98
99 if (start)
100 value |= 1 << cfg->timer_bit;
101 else
102 value &= ~(1 << cfg->timer_bit);
103
104 sh_tmu_write(p, TSTR, value);
105 spin_unlock_irqrestore(&sh_tmu_lock, flags);
106}
107
108static int sh_tmu_enable(struct sh_tmu_priv *p)
109{
110 int ret;
111
112 /* enable clock */
113 ret = clk_enable(p->clk);
114 if (ret) {
115 dev_err(&p->pdev->dev, "cannot enable clock\n");
116 return ret;
117 }
118
119 /* make sure channel is disabled */
120 sh_tmu_start_stop_ch(p, 0);
121
122 /* maximum timeout */
123 sh_tmu_write(p, TCOR, 0xffffffff);
124 sh_tmu_write(p, TCNT, 0xffffffff);
125
126 /* configure channel to parent clock / 4, irq off */
127 p->rate = clk_get_rate(p->clk) / 4;
128 sh_tmu_write(p, TCR, 0x0000);
129
130 /* enable channel */
131 sh_tmu_start_stop_ch(p, 1);
132
133 return 0;
134}
135
136static void sh_tmu_disable(struct sh_tmu_priv *p)
137{
138 /* disable channel */
139 sh_tmu_start_stop_ch(p, 0);
140
141 /* disable interrupts in TMU block */
142 sh_tmu_write(p, TCR, 0x0000);
143
144 /* stop clock */
145 clk_disable(p->clk);
146}
147
148static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
149 int periodic)
150{
151 /* stop timer */
152 sh_tmu_start_stop_ch(p, 0);
153
154 /* acknowledge interrupt */
155 sh_tmu_read(p, TCR);
156
157 /* enable interrupt */
158 sh_tmu_write(p, TCR, 0x0020);
159
160 /* reload delta value in case of periodic timer */
161 if (periodic)
162 sh_tmu_write(p, TCOR, delta);
163 else
164 sh_tmu_write(p, TCOR, 0xffffffff);
165
166 sh_tmu_write(p, TCNT, delta);
167
168 /* start timer */
169 sh_tmu_start_stop_ch(p, 1);
170}
171
172static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
173{
174 struct sh_tmu_priv *p = dev_id;
175
176 /* disable or acknowledge interrupt */
177 if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
178 sh_tmu_write(p, TCR, 0x0000);
179 else
180 sh_tmu_write(p, TCR, 0x0020);
181
182 /* notify clockevent layer */
183 p->ced.event_handler(&p->ced);
184 return IRQ_HANDLED;
185}
186
187static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs)
188{
189 return container_of(cs, struct sh_tmu_priv, cs);
190}
191
192static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
193{
194 struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
195
196 return sh_tmu_read(p, TCNT) ^ 0xffffffff;
197}
198
199static int sh_tmu_clocksource_enable(struct clocksource *cs)
200{
201 struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
202 int ret;
203
204 ret = sh_tmu_enable(p);
205 if (!ret)
206 __clocksource_updatefreq_hz(cs, p->rate);
207 return ret;
208}
209
210static void sh_tmu_clocksource_disable(struct clocksource *cs)
211{
212 sh_tmu_disable(cs_to_sh_tmu(cs));
213}
214
215static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
216 char *name, unsigned long rating)
217{
218 struct clocksource *cs = &p->cs;
219
220 cs->name = name;
221 cs->rating = rating;
222 cs->read = sh_tmu_clocksource_read;
223 cs->enable = sh_tmu_clocksource_enable;
224 cs->disable = sh_tmu_clocksource_disable;
225 cs->mask = CLOCKSOURCE_MASK(32);
226 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
227
228 dev_info(&p->pdev->dev, "used as clock source\n");
229
230 /* Register with dummy 1 Hz value, gets updated in ->enable() */
231 clocksource_register_hz(cs, 1);
232 return 0;
233}
234
235static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced)
236{
237 return container_of(ced, struct sh_tmu_priv, ced);
238}
239
240static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
241{
242 struct clock_event_device *ced = &p->ced;
243
244 sh_tmu_enable(p);
245
246 /* TODO: calculate good shift from rate and counter bit width */
247
248 ced->shift = 32;
249 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
250 ced->max_delta_ns = clockevent_delta2ns(0xffffffff, ced);
251 ced->min_delta_ns = 5000;
252
253 if (periodic) {
254 p->periodic = (p->rate + HZ/2) / HZ;
255 sh_tmu_set_next(p, p->periodic, 1);
256 }
257}
258
259static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
260 struct clock_event_device *ced)
261{
262 struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
263 int disabled = 0;
264
265 /* deal with old setting first */
266 switch (ced->mode) {
267 case CLOCK_EVT_MODE_PERIODIC:
268 case CLOCK_EVT_MODE_ONESHOT:
269 sh_tmu_disable(p);
270 disabled = 1;
271 break;
272 default:
273 break;
274 }
275
276 switch (mode) {
277 case CLOCK_EVT_MODE_PERIODIC:
278 dev_info(&p->pdev->dev, "used for periodic clock events\n");
279 sh_tmu_clock_event_start(p, 1);
280 break;
281 case CLOCK_EVT_MODE_ONESHOT:
282 dev_info(&p->pdev->dev, "used for oneshot clock events\n");
283 sh_tmu_clock_event_start(p, 0);
284 break;
285 case CLOCK_EVT_MODE_UNUSED:
286 if (!disabled)
287 sh_tmu_disable(p);
288 break;
289 case CLOCK_EVT_MODE_SHUTDOWN:
290 default:
291 break;
292 }
293}
294
295static int sh_tmu_clock_event_next(unsigned long delta,
296 struct clock_event_device *ced)
297{
298 struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
299
300 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
301
302 /* program new delta value */
303 sh_tmu_set_next(p, delta, 0);
304 return 0;
305}
306
307static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
308 char *name, unsigned long rating)
309{
310 struct clock_event_device *ced = &p->ced;
311 int ret;
312
313 memset(ced, 0, sizeof(*ced));
314
315 ced->name = name;
316 ced->features = CLOCK_EVT_FEAT_PERIODIC;
317 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
318 ced->rating = rating;
319 ced->cpumask = cpumask_of(0);
320 ced->set_next_event = sh_tmu_clock_event_next;
321 ced->set_mode = sh_tmu_clock_event_mode;
322
323 dev_info(&p->pdev->dev, "used for clock events\n");
324 clockevents_register_device(ced);
325
326 ret = setup_irq(p->irqaction.irq, &p->irqaction);
327 if (ret) {
328 dev_err(&p->pdev->dev, "failed to request irq %d\n",
329 p->irqaction.irq);
330 return;
331 }
332}
333
334static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
335 unsigned long clockevent_rating,
336 unsigned long clocksource_rating)
337{
338 if (clockevent_rating)
339 sh_tmu_register_clockevent(p, name, clockevent_rating);
340 else if (clocksource_rating)
341 sh_tmu_register_clocksource(p, name, clocksource_rating);
342
343 return 0;
344}
345
346static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
347{
348 struct sh_timer_config *cfg = pdev->dev.platform_data;
349 struct resource *res;
350 int irq, ret;
351 ret = -ENXIO;
352
353 memset(p, 0, sizeof(*p));
354 p->pdev = pdev;
355
356 if (!cfg) {
357 dev_err(&p->pdev->dev, "missing platform data\n");
358 goto err0;
359 }
360
361 platform_set_drvdata(pdev, p);
362
363 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
364 if (!res) {
365 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
366 goto err0;
367 }
368
369 irq = platform_get_irq(p->pdev, 0);
370 if (irq < 0) {
371 dev_err(&p->pdev->dev, "failed to get irq\n");
372 goto err0;
373 }
374
375 /* map memory, let mapbase point to our channel */
376 p->mapbase = ioremap_nocache(res->start, resource_size(res));
377 if (p->mapbase == NULL) {
378 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
379 goto err0;
380 }
381
382 /* setup data for setup_irq() (too early for request_irq()) */
383 p->irqaction.name = dev_name(&p->pdev->dev);
384 p->irqaction.handler = sh_tmu_interrupt;
385 p->irqaction.dev_id = p;
386 p->irqaction.irq = irq;
387 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
388 IRQF_IRQPOLL | IRQF_NOBALANCING;
389
390 /* get hold of clock */
391 p->clk = clk_get(&p->pdev->dev, "tmu_fck");
392 if (IS_ERR(p->clk)) {
393 dev_err(&p->pdev->dev, "cannot get clock\n");
394 ret = PTR_ERR(p->clk);
395 goto err1;
396 }
397
398 return sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
399 cfg->clockevent_rating,
400 cfg->clocksource_rating);
401 err1:
402 iounmap(p->mapbase);
403 err0:
404 return ret;
405}
406
407static int __devinit sh_tmu_probe(struct platform_device *pdev)
408{
409 struct sh_tmu_priv *p = platform_get_drvdata(pdev);
410 int ret;
411
412 if (p) {
413 dev_info(&pdev->dev, "kept as earlytimer\n");
414 return 0;
415 }
416
417 p = kmalloc(sizeof(*p), GFP_KERNEL);
418 if (p == NULL) {
419 dev_err(&pdev->dev, "failed to allocate driver data\n");
420 return -ENOMEM;
421 }
422
423 ret = sh_tmu_setup(p, pdev);
424 if (ret) {
425 kfree(p);
426 platform_set_drvdata(pdev, NULL);
427 }
428 return ret;
429}
430
431static int __devexit sh_tmu_remove(struct platform_device *pdev)
432{
433 return -EBUSY; /* cannot unregister clockevent and clocksource */
434}
435
436static struct platform_driver sh_tmu_device_driver = {
437 .probe = sh_tmu_probe,
438 .remove = __devexit_p(sh_tmu_remove),
439 .driver = {
440 .name = "sh_tmu",
441 }
442};
443
444static int __init sh_tmu_init(void)
445{
446 return platform_driver_register(&sh_tmu_device_driver);
447}
448
449static void __exit sh_tmu_exit(void)
450{
451 platform_driver_unregister(&sh_tmu_device_driver);
452}
453
454early_platform_init("earlytimer", &sh_tmu_device_driver);
455module_init(sh_tmu_init);
456module_exit(sh_tmu_exit);
457
458MODULE_AUTHOR("Magnus Damm");
459MODULE_DESCRIPTION("SuperH TMU Timer Driver");
460MODULE_LICENSE("GPL v2");