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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
4 *
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Copyright (C) 2012 Texas Instruments, Inc.
7 * Paul Walmsley
8 *
9 * XXX handle crossbar/shared link difference for L3?
10 * XXX these should be marked initdata for multi-OMAP kernels
11 */
12
13#include <linux/platform_data/i2c-omap.h>
14#include <linux/platform_data/hsmmc-omap.h>
15
16#include "omap_hwmod.h"
17#include "l3_2xxx.h"
18
19#include "soc.h"
20#include "omap_hwmod_common_data.h"
21#include "prm-regbits-24xx.h"
22#include "cm-regbits-24xx.h"
23#include "i2c.h"
24#include "wd_timer.h"
25
26/*
27 * OMAP2430 hardware module integration data
28 *
29 * All of the data in this section should be autogeneratable from the
30 * TI hardware database or other technical documentation. Data that
31 * is driver-specific or driver-kernel integration-specific belongs
32 * elsewhere.
33 */
34
35/*
36 * IP blocks
37 */
38
39/* IVA2 (IVA2) */
40static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
41 { .name = "logic", .rst_shift = 0 },
42 { .name = "mmu", .rst_shift = 1 },
43};
44
45static struct omap_hwmod omap2430_iva_hwmod = {
46 .name = "iva",
47 .class = &iva_hwmod_class,
48 .clkdm_name = "dsp_clkdm",
49 .rst_lines = omap2430_iva_resets,
50 .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets),
51 .main_clk = "dsp_fck",
52};
53
54/* I2C common */
55static struct omap_hwmod_class_sysconfig i2c_sysc = {
56 .rev_offs = 0x00,
57 .sysc_offs = 0x20,
58 .syss_offs = 0x10,
59 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
60 SYSS_HAS_RESET_STATUS),
61 .sysc_fields = &omap_hwmod_sysc_type1,
62};
63
64static struct omap_hwmod_class i2c_class = {
65 .name = "i2c",
66 .sysc = &i2c_sysc,
67 .reset = &omap_i2c_reset,
68};
69
70/* I2C1 */
71static struct omap_hwmod omap2430_i2c1_hwmod = {
72 .name = "i2c1",
73 .flags = HWMOD_16BIT_REG,
74 .main_clk = "i2chs1_fck",
75 .prcm = {
76 .omap2 = {
77 /*
78 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
79 * I2CHS IP's do not follow the usual pattern.
80 * prcm_reg_id alone cannot be used to program
81 * the iclk and fclk. Needs to be handled using
82 * additional flags when clk handling is moved
83 * to hwmod framework.
84 */
85 .module_offs = CORE_MOD,
86 .idlest_reg_id = 1,
87 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
88 },
89 },
90 .class = &i2c_class,
91};
92
93/* I2C2 */
94static struct omap_hwmod omap2430_i2c2_hwmod = {
95 .name = "i2c2",
96 .flags = HWMOD_16BIT_REG,
97 .main_clk = "i2chs2_fck",
98 .prcm = {
99 .omap2 = {
100 .module_offs = CORE_MOD,
101 .idlest_reg_id = 1,
102 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
103 },
104 },
105 .class = &i2c_class,
106};
107
108/* gpio5 */
109static struct omap_hwmod omap2430_gpio5_hwmod = {
110 .name = "gpio5",
111 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
112 .main_clk = "gpio5_fck",
113 .prcm = {
114 .omap2 = {
115 .module_offs = CORE_MOD,
116 .idlest_reg_id = 2,
117 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
118 },
119 },
120 .class = &omap2xxx_gpio_hwmod_class,
121};
122
123/* mailbox */
124static struct omap_hwmod omap2430_mailbox_hwmod = {
125 .name = "mailbox",
126 .class = &omap2xxx_mailbox_hwmod_class,
127 .main_clk = "mailboxes_ick",
128 .prcm = {
129 .omap2 = {
130 .module_offs = CORE_MOD,
131 .idlest_reg_id = 1,
132 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
133 },
134 },
135};
136
137/* mcspi3 */
138static struct omap_hwmod omap2430_mcspi3_hwmod = {
139 .name = "mcspi3",
140 .main_clk = "mcspi3_fck",
141 .prcm = {
142 .omap2 = {
143 .module_offs = CORE_MOD,
144 .idlest_reg_id = 2,
145 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
146 },
147 },
148 .class = &omap2xxx_mcspi_class,
149};
150
151/* usbhsotg */
152static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
153 .rev_offs = 0x0400,
154 .sysc_offs = 0x0404,
155 .syss_offs = 0x0408,
156 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
157 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
158 SYSC_HAS_AUTOIDLE),
159 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
160 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
161 .sysc_fields = &omap_hwmod_sysc_type1,
162};
163
164static struct omap_hwmod_class usbotg_class = {
165 .name = "usbotg",
166 .sysc = &omap2430_usbhsotg_sysc,
167};
168
169/* usb_otg_hs */
170static struct omap_hwmod omap2430_usbhsotg_hwmod = {
171 .name = "usb_otg_hs",
172 .main_clk = "usbhs_ick",
173 .prcm = {
174 .omap2 = {
175 .module_offs = CORE_MOD,
176 .idlest_reg_id = 1,
177 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
178 },
179 },
180 .class = &usbotg_class,
181 /*
182 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
183 * broken when autoidle is enabled
184 * workaround is to disable the autoidle bit at module level.
185 */
186 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
187 | HWMOD_SWSUP_MSTANDBY,
188};
189
190/*
191 * 'mcbsp' class
192 * multi channel buffered serial port controller
193 */
194
195static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
196 .rev_offs = 0x007C,
197 .sysc_offs = 0x008C,
198 .sysc_flags = (SYSC_HAS_SOFTRESET),
199 .sysc_fields = &omap_hwmod_sysc_type1,
200};
201
202static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
203 .name = "mcbsp",
204 .sysc = &omap2430_mcbsp_sysc,
205};
206
207static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
208 { .role = "pad_fck", .clk = "mcbsp_clks" },
209 { .role = "prcm_fck", .clk = "func_96m_ck" },
210};
211
212/* mcbsp1 */
213static struct omap_hwmod omap2430_mcbsp1_hwmod = {
214 .name = "mcbsp1",
215 .class = &omap2430_mcbsp_hwmod_class,
216 .main_clk = "mcbsp1_fck",
217 .prcm = {
218 .omap2 = {
219 .module_offs = CORE_MOD,
220 .idlest_reg_id = 1,
221 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
222 },
223 },
224 .opt_clks = mcbsp_opt_clks,
225 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
226};
227
228/* mcbsp2 */
229static struct omap_hwmod omap2430_mcbsp2_hwmod = {
230 .name = "mcbsp2",
231 .class = &omap2430_mcbsp_hwmod_class,
232 .main_clk = "mcbsp2_fck",
233 .prcm = {
234 .omap2 = {
235 .module_offs = CORE_MOD,
236 .idlest_reg_id = 1,
237 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
238 },
239 },
240 .opt_clks = mcbsp_opt_clks,
241 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
242};
243
244/* mcbsp3 */
245static struct omap_hwmod omap2430_mcbsp3_hwmod = {
246 .name = "mcbsp3",
247 .class = &omap2430_mcbsp_hwmod_class,
248 .main_clk = "mcbsp3_fck",
249 .prcm = {
250 .omap2 = {
251 .module_offs = CORE_MOD,
252 .idlest_reg_id = 2,
253 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
254 },
255 },
256 .opt_clks = mcbsp_opt_clks,
257 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
258};
259
260/* mcbsp4 */
261static struct omap_hwmod omap2430_mcbsp4_hwmod = {
262 .name = "mcbsp4",
263 .class = &omap2430_mcbsp_hwmod_class,
264 .main_clk = "mcbsp4_fck",
265 .prcm = {
266 .omap2 = {
267 .module_offs = CORE_MOD,
268 .idlest_reg_id = 2,
269 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
270 },
271 },
272 .opt_clks = mcbsp_opt_clks,
273 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
274};
275
276/* mcbsp5 */
277static struct omap_hwmod omap2430_mcbsp5_hwmod = {
278 .name = "mcbsp5",
279 .class = &omap2430_mcbsp_hwmod_class,
280 .main_clk = "mcbsp5_fck",
281 .prcm = {
282 .omap2 = {
283 .module_offs = CORE_MOD,
284 .idlest_reg_id = 2,
285 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
286 },
287 },
288 .opt_clks = mcbsp_opt_clks,
289 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
290};
291
292/* MMC/SD/SDIO common */
293static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
294 .rev_offs = 0x1fc,
295 .sysc_offs = 0x10,
296 .syss_offs = 0x14,
297 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
298 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
299 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
300 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
301 .sysc_fields = &omap_hwmod_sysc_type1,
302};
303
304static struct omap_hwmod_class omap2430_mmc_class = {
305 .name = "mmc",
306 .sysc = &omap2430_mmc_sysc,
307};
308
309/* MMC/SD/SDIO1 */
310static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
311 { .role = "dbck", .clk = "mmchsdb1_fck" },
312};
313
314static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
315 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
316};
317
318static struct omap_hwmod omap2430_mmc1_hwmod = {
319 .name = "mmc1",
320 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
321 .opt_clks = omap2430_mmc1_opt_clks,
322 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
323 .main_clk = "mmchs1_fck",
324 .prcm = {
325 .omap2 = {
326 .module_offs = CORE_MOD,
327 .idlest_reg_id = 2,
328 .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
329 },
330 },
331 .dev_attr = &mmc1_dev_attr,
332 .class = &omap2430_mmc_class,
333};
334
335/* MMC/SD/SDIO2 */
336static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
337 { .role = "dbck", .clk = "mmchsdb2_fck" },
338};
339
340static struct omap_hwmod omap2430_mmc2_hwmod = {
341 .name = "mmc2",
342 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
343 .opt_clks = omap2430_mmc2_opt_clks,
344 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
345 .main_clk = "mmchs2_fck",
346 .prcm = {
347 .omap2 = {
348 .module_offs = CORE_MOD,
349 .idlest_reg_id = 2,
350 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
351 },
352 },
353 .class = &omap2430_mmc_class,
354};
355
356/* HDQ1W/1-wire */
357static struct omap_hwmod omap2430_hdq1w_hwmod = {
358 .name = "hdq1w",
359 .main_clk = "hdq_fck",
360 .prcm = {
361 .omap2 = {
362 .module_offs = CORE_MOD,
363 .idlest_reg_id = 1,
364 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
365 },
366 },
367 .class = &omap2_hdq1w_class,
368};
369
370/*
371 * interfaces
372 */
373
374/* L3 -> L4_CORE interface */
375/* l3_core -> usbhsotg interface */
376static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
377 .master = &omap2430_usbhsotg_hwmod,
378 .slave = &omap2xxx_l3_main_hwmod,
379 .clk = "core_l3_ck",
380 .user = OCP_USER_MPU,
381};
382
383/* L4 CORE -> I2C1 interface */
384static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
385 .master = &omap2xxx_l4_core_hwmod,
386 .slave = &omap2430_i2c1_hwmod,
387 .clk = "i2c1_ick",
388 .user = OCP_USER_MPU | OCP_USER_SDMA,
389};
390
391/* L4 CORE -> I2C2 interface */
392static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
393 .master = &omap2xxx_l4_core_hwmod,
394 .slave = &omap2430_i2c2_hwmod,
395 .clk = "i2c2_ick",
396 .user = OCP_USER_MPU | OCP_USER_SDMA,
397};
398
399/* l4_core ->usbhsotg interface */
400static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
401 .master = &omap2xxx_l4_core_hwmod,
402 .slave = &omap2430_usbhsotg_hwmod,
403 .clk = "usb_l4_ick",
404 .user = OCP_USER_MPU,
405};
406
407/* L4 CORE -> MMC1 interface */
408static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
409 .master = &omap2xxx_l4_core_hwmod,
410 .slave = &omap2430_mmc1_hwmod,
411 .clk = "mmchs1_ick",
412 .user = OCP_USER_MPU | OCP_USER_SDMA,
413};
414
415/* L4 CORE -> MMC2 interface */
416static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
417 .master = &omap2xxx_l4_core_hwmod,
418 .slave = &omap2430_mmc2_hwmod,
419 .clk = "mmchs2_ick",
420 .user = OCP_USER_MPU | OCP_USER_SDMA,
421};
422
423/* l4 core -> mcspi3 interface */
424static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
425 .master = &omap2xxx_l4_core_hwmod,
426 .slave = &omap2430_mcspi3_hwmod,
427 .clk = "mcspi3_ick",
428 .user = OCP_USER_MPU | OCP_USER_SDMA,
429};
430
431/* IVA2 <- L3 interface */
432static struct omap_hwmod_ocp_if omap2430_l3__iva = {
433 .master = &omap2xxx_l3_main_hwmod,
434 .slave = &omap2430_iva_hwmod,
435 .clk = "core_l3_ck",
436 .user = OCP_USER_MPU | OCP_USER_SDMA,
437};
438
439/* l4_wkup -> wd_timer2 */
440static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
441 .master = &omap2xxx_l4_wkup_hwmod,
442 .slave = &omap2xxx_wd_timer2_hwmod,
443 .clk = "mpu_wdt_ick",
444 .user = OCP_USER_MPU | OCP_USER_SDMA,
445};
446
447/* l4_wkup -> gpio1 */
448static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
449 .master = &omap2xxx_l4_wkup_hwmod,
450 .slave = &omap2xxx_gpio1_hwmod,
451 .clk = "gpios_ick",
452 .user = OCP_USER_MPU | OCP_USER_SDMA,
453};
454
455/* l4_wkup -> gpio2 */
456static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
457 .master = &omap2xxx_l4_wkup_hwmod,
458 .slave = &omap2xxx_gpio2_hwmod,
459 .clk = "gpios_ick",
460 .user = OCP_USER_MPU | OCP_USER_SDMA,
461};
462
463/* l4_wkup -> gpio3 */
464static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
465 .master = &omap2xxx_l4_wkup_hwmod,
466 .slave = &omap2xxx_gpio3_hwmod,
467 .clk = "gpios_ick",
468 .user = OCP_USER_MPU | OCP_USER_SDMA,
469};
470
471/* l4_wkup -> gpio4 */
472static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
473 .master = &omap2xxx_l4_wkup_hwmod,
474 .slave = &omap2xxx_gpio4_hwmod,
475 .clk = "gpios_ick",
476 .user = OCP_USER_MPU | OCP_USER_SDMA,
477};
478
479/* l4_core -> gpio5 */
480static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
481 .master = &omap2xxx_l4_core_hwmod,
482 .slave = &omap2430_gpio5_hwmod,
483 .clk = "gpio5_ick",
484 .user = OCP_USER_MPU | OCP_USER_SDMA,
485};
486
487/* l4_core -> mailbox */
488static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
489 .master = &omap2xxx_l4_core_hwmod,
490 .slave = &omap2430_mailbox_hwmod,
491 .user = OCP_USER_MPU | OCP_USER_SDMA,
492};
493
494/* l4_core -> mcbsp1 */
495static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
496 .master = &omap2xxx_l4_core_hwmod,
497 .slave = &omap2430_mcbsp1_hwmod,
498 .clk = "mcbsp1_ick",
499 .user = OCP_USER_MPU | OCP_USER_SDMA,
500};
501
502/* l4_core -> mcbsp2 */
503static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
504 .master = &omap2xxx_l4_core_hwmod,
505 .slave = &omap2430_mcbsp2_hwmod,
506 .clk = "mcbsp2_ick",
507 .user = OCP_USER_MPU | OCP_USER_SDMA,
508};
509
510/* l4_core -> mcbsp3 */
511static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
512 .master = &omap2xxx_l4_core_hwmod,
513 .slave = &omap2430_mcbsp3_hwmod,
514 .clk = "mcbsp3_ick",
515 .user = OCP_USER_MPU | OCP_USER_SDMA,
516};
517
518/* l4_core -> mcbsp4 */
519static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
520 .master = &omap2xxx_l4_core_hwmod,
521 .slave = &omap2430_mcbsp4_hwmod,
522 .clk = "mcbsp4_ick",
523 .user = OCP_USER_MPU | OCP_USER_SDMA,
524};
525
526/* l4_core -> mcbsp5 */
527static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
528 .master = &omap2xxx_l4_core_hwmod,
529 .slave = &omap2430_mcbsp5_hwmod,
530 .clk = "mcbsp5_ick",
531 .user = OCP_USER_MPU | OCP_USER_SDMA,
532};
533
534/* l4_core -> hdq1w */
535static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
536 .master = &omap2xxx_l4_core_hwmod,
537 .slave = &omap2430_hdq1w_hwmod,
538 .clk = "hdq_ick",
539 .user = OCP_USER_MPU | OCP_USER_SDMA,
540 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
541};
542
543static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
544 .master = &omap2xxx_l3_main_hwmod,
545 .slave = &omap2xxx_gpmc_hwmod,
546 .clk = "core_l3_ck",
547 .user = OCP_USER_MPU | OCP_USER_SDMA,
548};
549
550static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
551 &omap2xxx_l3_main__l4_core,
552 &omap2xxx_mpu__l3_main,
553 &omap2xxx_dss__l3,
554 &omap2430_usbhsotg__l3,
555 &omap2430_l4_core__i2c1,
556 &omap2430_l4_core__i2c2,
557 &omap2xxx_l4_core__l4_wkup,
558 &omap2_l4_core__uart1,
559 &omap2_l4_core__uart2,
560 &omap2_l4_core__uart3,
561 &omap2430_l4_core__usbhsotg,
562 &omap2430_l4_core__mmc1,
563 &omap2430_l4_core__mmc2,
564 &omap2xxx_l4_core__mcspi1,
565 &omap2xxx_l4_core__mcspi2,
566 &omap2430_l4_core__mcspi3,
567 &omap2430_l3__iva,
568 &omap2xxx_l4_core__timer3,
569 &omap2xxx_l4_core__timer4,
570 &omap2xxx_l4_core__timer5,
571 &omap2xxx_l4_core__timer6,
572 &omap2xxx_l4_core__timer7,
573 &omap2xxx_l4_core__timer8,
574 &omap2xxx_l4_core__timer9,
575 &omap2xxx_l4_core__timer10,
576 &omap2xxx_l4_core__timer11,
577 &omap2xxx_l4_core__timer12,
578 &omap2430_l4_wkup__wd_timer2,
579 &omap2xxx_l4_core__dss,
580 &omap2xxx_l4_core__dss_dispc,
581 &omap2xxx_l4_core__dss_rfbi,
582 &omap2xxx_l4_core__dss_venc,
583 &omap2430_l4_wkup__gpio1,
584 &omap2430_l4_wkup__gpio2,
585 &omap2430_l4_wkup__gpio3,
586 &omap2430_l4_wkup__gpio4,
587 &omap2430_l4_core__gpio5,
588 &omap2430_l4_core__mailbox,
589 &omap2430_l4_core__mcbsp1,
590 &omap2430_l4_core__mcbsp2,
591 &omap2430_l4_core__mcbsp3,
592 &omap2430_l4_core__mcbsp4,
593 &omap2430_l4_core__mcbsp5,
594 &omap2430_l4_core__hdq1w,
595 &omap2xxx_l4_core__rng,
596 &omap2xxx_l4_core__sham,
597 &omap2xxx_l4_core__aes,
598 &omap2430_l3__gpmc,
599 NULL,
600};
601
602int __init omap2430_hwmod_init(void)
603{
604 omap_hwmod_init();
605 return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
606}
1/*
2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * XXX handle crossbar/shared link difference for L3?
12 * XXX these should be marked initdata for multi-OMAP kernels
13 */
14#include <plat/omap_hwmod.h>
15#include <mach/irqs.h>
16#include <plat/cpu.h>
17#include <plat/dma.h>
18#include <plat/serial.h>
19#include <plat/i2c.h>
20#include <plat/gpio.h>
21#include <plat/mcbsp.h>
22#include <plat/mcspi.h>
23#include <plat/dmtimer.h>
24#include <plat/mmc.h>
25#include <plat/l3_2xxx.h>
26
27#include "omap_hwmod_common_data.h"
28
29#include "prm-regbits-24xx.h"
30#include "cm-regbits-24xx.h"
31#include "wd_timer.h"
32
33/*
34 * OMAP2430 hardware module integration data
35 *
36 * ALl of the data in this section should be autogeneratable from the
37 * TI hardware database or other technical documentation. Data that
38 * is driver-specific or driver-kernel integration-specific belongs
39 * elsewhere.
40 */
41
42static struct omap_hwmod omap2430_mpu_hwmod;
43static struct omap_hwmod omap2430_iva_hwmod;
44static struct omap_hwmod omap2430_l3_main_hwmod;
45static struct omap_hwmod omap2430_l4_core_hwmod;
46static struct omap_hwmod omap2430_dss_core_hwmod;
47static struct omap_hwmod omap2430_dss_dispc_hwmod;
48static struct omap_hwmod omap2430_dss_rfbi_hwmod;
49static struct omap_hwmod omap2430_dss_venc_hwmod;
50static struct omap_hwmod omap2430_wd_timer2_hwmod;
51static struct omap_hwmod omap2430_gpio1_hwmod;
52static struct omap_hwmod omap2430_gpio2_hwmod;
53static struct omap_hwmod omap2430_gpio3_hwmod;
54static struct omap_hwmod omap2430_gpio4_hwmod;
55static struct omap_hwmod omap2430_gpio5_hwmod;
56static struct omap_hwmod omap2430_dma_system_hwmod;
57static struct omap_hwmod omap2430_mcbsp1_hwmod;
58static struct omap_hwmod omap2430_mcbsp2_hwmod;
59static struct omap_hwmod omap2430_mcbsp3_hwmod;
60static struct omap_hwmod omap2430_mcbsp4_hwmod;
61static struct omap_hwmod omap2430_mcbsp5_hwmod;
62static struct omap_hwmod omap2430_mcspi1_hwmod;
63static struct omap_hwmod omap2430_mcspi2_hwmod;
64static struct omap_hwmod omap2430_mcspi3_hwmod;
65static struct omap_hwmod omap2430_mmc1_hwmod;
66static struct omap_hwmod omap2430_mmc2_hwmod;
67
68/* L3 -> L4_CORE interface */
69static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
70 .master = &omap2430_l3_main_hwmod,
71 .slave = &omap2430_l4_core_hwmod,
72 .user = OCP_USER_MPU | OCP_USER_SDMA,
73};
74
75/* MPU -> L3 interface */
76static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
77 .master = &omap2430_mpu_hwmod,
78 .slave = &omap2430_l3_main_hwmod,
79 .user = OCP_USER_MPU,
80};
81
82/* Slave interfaces on the L3 interconnect */
83static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
84 &omap2430_mpu__l3_main,
85};
86
87/* DSS -> l3 */
88static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
89 .master = &omap2430_dss_core_hwmod,
90 .slave = &omap2430_l3_main_hwmod,
91 .fw = {
92 .omap2 = {
93 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
94 .flags = OMAP_FIREWALL_L3,
95 }
96 },
97 .user = OCP_USER_MPU | OCP_USER_SDMA,
98};
99
100/* Master interfaces on the L3 interconnect */
101static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
102 &omap2430_l3_main__l4_core,
103};
104
105/* L3 */
106static struct omap_hwmod omap2430_l3_main_hwmod = {
107 .name = "l3_main",
108 .class = &l3_hwmod_class,
109 .masters = omap2430_l3_main_masters,
110 .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters),
111 .slaves = omap2430_l3_main_slaves,
112 .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves),
113 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
114 .flags = HWMOD_NO_IDLEST,
115};
116
117static struct omap_hwmod omap2430_l4_wkup_hwmod;
118static struct omap_hwmod omap2430_uart1_hwmod;
119static struct omap_hwmod omap2430_uart2_hwmod;
120static struct omap_hwmod omap2430_uart3_hwmod;
121static struct omap_hwmod omap2430_i2c1_hwmod;
122static struct omap_hwmod omap2430_i2c2_hwmod;
123
124static struct omap_hwmod omap2430_usbhsotg_hwmod;
125
126/* l3_core -> usbhsotg interface */
127static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
128 .master = &omap2430_usbhsotg_hwmod,
129 .slave = &omap2430_l3_main_hwmod,
130 .clk = "core_l3_ck",
131 .user = OCP_USER_MPU,
132};
133
134/* L4 CORE -> I2C1 interface */
135static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
136 .master = &omap2430_l4_core_hwmod,
137 .slave = &omap2430_i2c1_hwmod,
138 .clk = "i2c1_ick",
139 .addr = omap2_i2c1_addr_space,
140 .user = OCP_USER_MPU | OCP_USER_SDMA,
141};
142
143/* L4 CORE -> I2C2 interface */
144static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
145 .master = &omap2430_l4_core_hwmod,
146 .slave = &omap2430_i2c2_hwmod,
147 .clk = "i2c2_ick",
148 .addr = omap2_i2c2_addr_space,
149 .user = OCP_USER_MPU | OCP_USER_SDMA,
150};
151
152/* L4_CORE -> L4_WKUP interface */
153static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
154 .master = &omap2430_l4_core_hwmod,
155 .slave = &omap2430_l4_wkup_hwmod,
156 .user = OCP_USER_MPU | OCP_USER_SDMA,
157};
158
159/* L4 CORE -> UART1 interface */
160static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
161 .master = &omap2430_l4_core_hwmod,
162 .slave = &omap2430_uart1_hwmod,
163 .clk = "uart1_ick",
164 .addr = omap2xxx_uart1_addr_space,
165 .user = OCP_USER_MPU | OCP_USER_SDMA,
166};
167
168/* L4 CORE -> UART2 interface */
169static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
170 .master = &omap2430_l4_core_hwmod,
171 .slave = &omap2430_uart2_hwmod,
172 .clk = "uart2_ick",
173 .addr = omap2xxx_uart2_addr_space,
174 .user = OCP_USER_MPU | OCP_USER_SDMA,
175};
176
177/* L4 PER -> UART3 interface */
178static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
179 .master = &omap2430_l4_core_hwmod,
180 .slave = &omap2430_uart3_hwmod,
181 .clk = "uart3_ick",
182 .addr = omap2xxx_uart3_addr_space,
183 .user = OCP_USER_MPU | OCP_USER_SDMA,
184};
185
186/*
187* usbhsotg interface data
188*/
189static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
190 {
191 .pa_start = OMAP243X_HS_BASE,
192 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
193 .flags = ADDR_TYPE_RT
194 },
195 { }
196};
197
198/* l4_core ->usbhsotg interface */
199static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
200 .master = &omap2430_l4_core_hwmod,
201 .slave = &omap2430_usbhsotg_hwmod,
202 .clk = "usb_l4_ick",
203 .addr = omap2430_usbhsotg_addrs,
204 .user = OCP_USER_MPU,
205};
206
207static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
208 &omap2430_usbhsotg__l3,
209};
210
211static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
212 &omap2430_l4_core__usbhsotg,
213};
214
215/* L4 CORE -> MMC1 interface */
216static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
217 .master = &omap2430_l4_core_hwmod,
218 .slave = &omap2430_mmc1_hwmod,
219 .clk = "mmchs1_ick",
220 .addr = omap2430_mmc1_addr_space,
221 .user = OCP_USER_MPU | OCP_USER_SDMA,
222};
223
224/* L4 CORE -> MMC2 interface */
225static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
226 .master = &omap2430_l4_core_hwmod,
227 .slave = &omap2430_mmc2_hwmod,
228 .clk = "mmchs2_ick",
229 .addr = omap2430_mmc2_addr_space,
230 .user = OCP_USER_MPU | OCP_USER_SDMA,
231};
232
233/* Slave interfaces on the L4_CORE interconnect */
234static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
235 &omap2430_l3_main__l4_core,
236};
237
238/* Master interfaces on the L4_CORE interconnect */
239static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
240 &omap2430_l4_core__l4_wkup,
241 &omap2430_l4_core__mmc1,
242 &omap2430_l4_core__mmc2,
243};
244
245/* L4 CORE */
246static struct omap_hwmod omap2430_l4_core_hwmod = {
247 .name = "l4_core",
248 .class = &l4_hwmod_class,
249 .masters = omap2430_l4_core_masters,
250 .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters),
251 .slaves = omap2430_l4_core_slaves,
252 .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves),
253 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
254 .flags = HWMOD_NO_IDLEST,
255};
256
257/* Slave interfaces on the L4_WKUP interconnect */
258static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
259 &omap2430_l4_core__l4_wkup,
260 &omap2_l4_core__uart1,
261 &omap2_l4_core__uart2,
262 &omap2_l4_core__uart3,
263};
264
265/* Master interfaces on the L4_WKUP interconnect */
266static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
267};
268
269/* l4 core -> mcspi1 interface */
270static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
271 .master = &omap2430_l4_core_hwmod,
272 .slave = &omap2430_mcspi1_hwmod,
273 .clk = "mcspi1_ick",
274 .addr = omap2_mcspi1_addr_space,
275 .user = OCP_USER_MPU | OCP_USER_SDMA,
276};
277
278/* l4 core -> mcspi2 interface */
279static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
280 .master = &omap2430_l4_core_hwmod,
281 .slave = &omap2430_mcspi2_hwmod,
282 .clk = "mcspi2_ick",
283 .addr = omap2_mcspi2_addr_space,
284 .user = OCP_USER_MPU | OCP_USER_SDMA,
285};
286
287/* l4 core -> mcspi3 interface */
288static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
289 .master = &omap2430_l4_core_hwmod,
290 .slave = &omap2430_mcspi3_hwmod,
291 .clk = "mcspi3_ick",
292 .addr = omap2430_mcspi3_addr_space,
293 .user = OCP_USER_MPU | OCP_USER_SDMA,
294};
295
296/* L4 WKUP */
297static struct omap_hwmod omap2430_l4_wkup_hwmod = {
298 .name = "l4_wkup",
299 .class = &l4_hwmod_class,
300 .masters = omap2430_l4_wkup_masters,
301 .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters),
302 .slaves = omap2430_l4_wkup_slaves,
303 .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves),
304 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
305 .flags = HWMOD_NO_IDLEST,
306};
307
308/* Master interfaces on the MPU device */
309static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
310 &omap2430_mpu__l3_main,
311};
312
313/* MPU */
314static struct omap_hwmod omap2430_mpu_hwmod = {
315 .name = "mpu",
316 .class = &mpu_hwmod_class,
317 .main_clk = "mpu_ck",
318 .masters = omap2430_mpu_masters,
319 .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters),
320 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
321};
322
323/*
324 * IVA2_1 interface data
325 */
326
327/* IVA2 <- L3 interface */
328static struct omap_hwmod_ocp_if omap2430_l3__iva = {
329 .master = &omap2430_l3_main_hwmod,
330 .slave = &omap2430_iva_hwmod,
331 .clk = "dsp_fck",
332 .user = OCP_USER_MPU | OCP_USER_SDMA,
333};
334
335static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
336 &omap2430_l3__iva,
337};
338
339/*
340 * IVA2 (IVA2)
341 */
342
343static struct omap_hwmod omap2430_iva_hwmod = {
344 .name = "iva",
345 .class = &iva_hwmod_class,
346 .masters = omap2430_iva_masters,
347 .masters_cnt = ARRAY_SIZE(omap2430_iva_masters),
348 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
349};
350
351/* timer1 */
352static struct omap_hwmod omap2430_timer1_hwmod;
353
354static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
355 {
356 .pa_start = 0x49018000,
357 .pa_end = 0x49018000 + SZ_1K - 1,
358 .flags = ADDR_TYPE_RT
359 },
360 { }
361};
362
363/* l4_wkup -> timer1 */
364static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
365 .master = &omap2430_l4_wkup_hwmod,
366 .slave = &omap2430_timer1_hwmod,
367 .clk = "gpt1_ick",
368 .addr = omap2430_timer1_addrs,
369 .user = OCP_USER_MPU | OCP_USER_SDMA,
370};
371
372/* timer1 slave port */
373static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
374 &omap2430_l4_wkup__timer1,
375};
376
377/* timer1 hwmod */
378static struct omap_hwmod omap2430_timer1_hwmod = {
379 .name = "timer1",
380 .mpu_irqs = omap2_timer1_mpu_irqs,
381 .main_clk = "gpt1_fck",
382 .prcm = {
383 .omap2 = {
384 .prcm_reg_id = 1,
385 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
386 .module_offs = WKUP_MOD,
387 .idlest_reg_id = 1,
388 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
389 },
390 },
391 .slaves = omap2430_timer1_slaves,
392 .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
393 .class = &omap2xxx_timer_hwmod_class,
394 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
395};
396
397/* timer2 */
398static struct omap_hwmod omap2430_timer2_hwmod;
399
400/* l4_core -> timer2 */
401static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
402 .master = &omap2430_l4_core_hwmod,
403 .slave = &omap2430_timer2_hwmod,
404 .clk = "gpt2_ick",
405 .addr = omap2xxx_timer2_addrs,
406 .user = OCP_USER_MPU | OCP_USER_SDMA,
407};
408
409/* timer2 slave port */
410static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
411 &omap2430_l4_core__timer2,
412};
413
414/* timer2 hwmod */
415static struct omap_hwmod omap2430_timer2_hwmod = {
416 .name = "timer2",
417 .mpu_irqs = omap2_timer2_mpu_irqs,
418 .main_clk = "gpt2_fck",
419 .prcm = {
420 .omap2 = {
421 .prcm_reg_id = 1,
422 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
423 .module_offs = CORE_MOD,
424 .idlest_reg_id = 1,
425 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
426 },
427 },
428 .slaves = omap2430_timer2_slaves,
429 .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
430 .class = &omap2xxx_timer_hwmod_class,
431 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
432};
433
434/* timer3 */
435static struct omap_hwmod omap2430_timer3_hwmod;
436
437/* l4_core -> timer3 */
438static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
439 .master = &omap2430_l4_core_hwmod,
440 .slave = &omap2430_timer3_hwmod,
441 .clk = "gpt3_ick",
442 .addr = omap2xxx_timer3_addrs,
443 .user = OCP_USER_MPU | OCP_USER_SDMA,
444};
445
446/* timer3 slave port */
447static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
448 &omap2430_l4_core__timer3,
449};
450
451/* timer3 hwmod */
452static struct omap_hwmod omap2430_timer3_hwmod = {
453 .name = "timer3",
454 .mpu_irqs = omap2_timer3_mpu_irqs,
455 .main_clk = "gpt3_fck",
456 .prcm = {
457 .omap2 = {
458 .prcm_reg_id = 1,
459 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
460 .module_offs = CORE_MOD,
461 .idlest_reg_id = 1,
462 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
463 },
464 },
465 .slaves = omap2430_timer3_slaves,
466 .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
467 .class = &omap2xxx_timer_hwmod_class,
468 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
469};
470
471/* timer4 */
472static struct omap_hwmod omap2430_timer4_hwmod;
473
474/* l4_core -> timer4 */
475static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
476 .master = &omap2430_l4_core_hwmod,
477 .slave = &omap2430_timer4_hwmod,
478 .clk = "gpt4_ick",
479 .addr = omap2xxx_timer4_addrs,
480 .user = OCP_USER_MPU | OCP_USER_SDMA,
481};
482
483/* timer4 slave port */
484static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
485 &omap2430_l4_core__timer4,
486};
487
488/* timer4 hwmod */
489static struct omap_hwmod omap2430_timer4_hwmod = {
490 .name = "timer4",
491 .mpu_irqs = omap2_timer4_mpu_irqs,
492 .main_clk = "gpt4_fck",
493 .prcm = {
494 .omap2 = {
495 .prcm_reg_id = 1,
496 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
497 .module_offs = CORE_MOD,
498 .idlest_reg_id = 1,
499 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
500 },
501 },
502 .slaves = omap2430_timer4_slaves,
503 .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
504 .class = &omap2xxx_timer_hwmod_class,
505 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
506};
507
508/* timer5 */
509static struct omap_hwmod omap2430_timer5_hwmod;
510
511/* l4_core -> timer5 */
512static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
513 .master = &omap2430_l4_core_hwmod,
514 .slave = &omap2430_timer5_hwmod,
515 .clk = "gpt5_ick",
516 .addr = omap2xxx_timer5_addrs,
517 .user = OCP_USER_MPU | OCP_USER_SDMA,
518};
519
520/* timer5 slave port */
521static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
522 &omap2430_l4_core__timer5,
523};
524
525/* timer5 hwmod */
526static struct omap_hwmod omap2430_timer5_hwmod = {
527 .name = "timer5",
528 .mpu_irqs = omap2_timer5_mpu_irqs,
529 .main_clk = "gpt5_fck",
530 .prcm = {
531 .omap2 = {
532 .prcm_reg_id = 1,
533 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
534 .module_offs = CORE_MOD,
535 .idlest_reg_id = 1,
536 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
537 },
538 },
539 .slaves = omap2430_timer5_slaves,
540 .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
541 .class = &omap2xxx_timer_hwmod_class,
542 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
543};
544
545/* timer6 */
546static struct omap_hwmod omap2430_timer6_hwmod;
547
548/* l4_core -> timer6 */
549static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
550 .master = &omap2430_l4_core_hwmod,
551 .slave = &omap2430_timer6_hwmod,
552 .clk = "gpt6_ick",
553 .addr = omap2xxx_timer6_addrs,
554 .user = OCP_USER_MPU | OCP_USER_SDMA,
555};
556
557/* timer6 slave port */
558static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
559 &omap2430_l4_core__timer6,
560};
561
562/* timer6 hwmod */
563static struct omap_hwmod omap2430_timer6_hwmod = {
564 .name = "timer6",
565 .mpu_irqs = omap2_timer6_mpu_irqs,
566 .main_clk = "gpt6_fck",
567 .prcm = {
568 .omap2 = {
569 .prcm_reg_id = 1,
570 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
571 .module_offs = CORE_MOD,
572 .idlest_reg_id = 1,
573 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
574 },
575 },
576 .slaves = omap2430_timer6_slaves,
577 .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
578 .class = &omap2xxx_timer_hwmod_class,
579 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
580};
581
582/* timer7 */
583static struct omap_hwmod omap2430_timer7_hwmod;
584
585/* l4_core -> timer7 */
586static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
587 .master = &omap2430_l4_core_hwmod,
588 .slave = &omap2430_timer7_hwmod,
589 .clk = "gpt7_ick",
590 .addr = omap2xxx_timer7_addrs,
591 .user = OCP_USER_MPU | OCP_USER_SDMA,
592};
593
594/* timer7 slave port */
595static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
596 &omap2430_l4_core__timer7,
597};
598
599/* timer7 hwmod */
600static struct omap_hwmod omap2430_timer7_hwmod = {
601 .name = "timer7",
602 .mpu_irqs = omap2_timer7_mpu_irqs,
603 .main_clk = "gpt7_fck",
604 .prcm = {
605 .omap2 = {
606 .prcm_reg_id = 1,
607 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
608 .module_offs = CORE_MOD,
609 .idlest_reg_id = 1,
610 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
611 },
612 },
613 .slaves = omap2430_timer7_slaves,
614 .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
615 .class = &omap2xxx_timer_hwmod_class,
616 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
617};
618
619/* timer8 */
620static struct omap_hwmod omap2430_timer8_hwmod;
621
622/* l4_core -> timer8 */
623static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
624 .master = &omap2430_l4_core_hwmod,
625 .slave = &omap2430_timer8_hwmod,
626 .clk = "gpt8_ick",
627 .addr = omap2xxx_timer8_addrs,
628 .user = OCP_USER_MPU | OCP_USER_SDMA,
629};
630
631/* timer8 slave port */
632static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
633 &omap2430_l4_core__timer8,
634};
635
636/* timer8 hwmod */
637static struct omap_hwmod omap2430_timer8_hwmod = {
638 .name = "timer8",
639 .mpu_irqs = omap2_timer8_mpu_irqs,
640 .main_clk = "gpt8_fck",
641 .prcm = {
642 .omap2 = {
643 .prcm_reg_id = 1,
644 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
645 .module_offs = CORE_MOD,
646 .idlest_reg_id = 1,
647 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
648 },
649 },
650 .slaves = omap2430_timer8_slaves,
651 .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
652 .class = &omap2xxx_timer_hwmod_class,
653 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
654};
655
656/* timer9 */
657static struct omap_hwmod omap2430_timer9_hwmod;
658
659/* l4_core -> timer9 */
660static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
661 .master = &omap2430_l4_core_hwmod,
662 .slave = &omap2430_timer9_hwmod,
663 .clk = "gpt9_ick",
664 .addr = omap2xxx_timer9_addrs,
665 .user = OCP_USER_MPU | OCP_USER_SDMA,
666};
667
668/* timer9 slave port */
669static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
670 &omap2430_l4_core__timer9,
671};
672
673/* timer9 hwmod */
674static struct omap_hwmod omap2430_timer9_hwmod = {
675 .name = "timer9",
676 .mpu_irqs = omap2_timer9_mpu_irqs,
677 .main_clk = "gpt9_fck",
678 .prcm = {
679 .omap2 = {
680 .prcm_reg_id = 1,
681 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
682 .module_offs = CORE_MOD,
683 .idlest_reg_id = 1,
684 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
685 },
686 },
687 .slaves = omap2430_timer9_slaves,
688 .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
689 .class = &omap2xxx_timer_hwmod_class,
690 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
691};
692
693/* timer10 */
694static struct omap_hwmod omap2430_timer10_hwmod;
695
696/* l4_core -> timer10 */
697static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
698 .master = &omap2430_l4_core_hwmod,
699 .slave = &omap2430_timer10_hwmod,
700 .clk = "gpt10_ick",
701 .addr = omap2_timer10_addrs,
702 .user = OCP_USER_MPU | OCP_USER_SDMA,
703};
704
705/* timer10 slave port */
706static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
707 &omap2430_l4_core__timer10,
708};
709
710/* timer10 hwmod */
711static struct omap_hwmod omap2430_timer10_hwmod = {
712 .name = "timer10",
713 .mpu_irqs = omap2_timer10_mpu_irqs,
714 .main_clk = "gpt10_fck",
715 .prcm = {
716 .omap2 = {
717 .prcm_reg_id = 1,
718 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
719 .module_offs = CORE_MOD,
720 .idlest_reg_id = 1,
721 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
722 },
723 },
724 .slaves = omap2430_timer10_slaves,
725 .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
726 .class = &omap2xxx_timer_hwmod_class,
727 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
728};
729
730/* timer11 */
731static struct omap_hwmod omap2430_timer11_hwmod;
732
733/* l4_core -> timer11 */
734static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
735 .master = &omap2430_l4_core_hwmod,
736 .slave = &omap2430_timer11_hwmod,
737 .clk = "gpt11_ick",
738 .addr = omap2_timer11_addrs,
739 .user = OCP_USER_MPU | OCP_USER_SDMA,
740};
741
742/* timer11 slave port */
743static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
744 &omap2430_l4_core__timer11,
745};
746
747/* timer11 hwmod */
748static struct omap_hwmod omap2430_timer11_hwmod = {
749 .name = "timer11",
750 .mpu_irqs = omap2_timer11_mpu_irqs,
751 .main_clk = "gpt11_fck",
752 .prcm = {
753 .omap2 = {
754 .prcm_reg_id = 1,
755 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
756 .module_offs = CORE_MOD,
757 .idlest_reg_id = 1,
758 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
759 },
760 },
761 .slaves = omap2430_timer11_slaves,
762 .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
763 .class = &omap2xxx_timer_hwmod_class,
764 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
765};
766
767/* timer12 */
768static struct omap_hwmod omap2430_timer12_hwmod;
769
770/* l4_core -> timer12 */
771static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
772 .master = &omap2430_l4_core_hwmod,
773 .slave = &omap2430_timer12_hwmod,
774 .clk = "gpt12_ick",
775 .addr = omap2xxx_timer12_addrs,
776 .user = OCP_USER_MPU | OCP_USER_SDMA,
777};
778
779/* timer12 slave port */
780static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
781 &omap2430_l4_core__timer12,
782};
783
784/* timer12 hwmod */
785static struct omap_hwmod omap2430_timer12_hwmod = {
786 .name = "timer12",
787 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
788 .main_clk = "gpt12_fck",
789 .prcm = {
790 .omap2 = {
791 .prcm_reg_id = 1,
792 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
793 .module_offs = CORE_MOD,
794 .idlest_reg_id = 1,
795 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
796 },
797 },
798 .slaves = omap2430_timer12_slaves,
799 .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
800 .class = &omap2xxx_timer_hwmod_class,
801 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
802};
803
804/* l4_wkup -> wd_timer2 */
805static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
806 {
807 .pa_start = 0x49016000,
808 .pa_end = 0x4901607f,
809 .flags = ADDR_TYPE_RT
810 },
811 { }
812};
813
814static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
815 .master = &omap2430_l4_wkup_hwmod,
816 .slave = &omap2430_wd_timer2_hwmod,
817 .clk = "mpu_wdt_ick",
818 .addr = omap2430_wd_timer2_addrs,
819 .user = OCP_USER_MPU | OCP_USER_SDMA,
820};
821
822/* wd_timer2 */
823static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
824 &omap2430_l4_wkup__wd_timer2,
825};
826
827static struct omap_hwmod omap2430_wd_timer2_hwmod = {
828 .name = "wd_timer2",
829 .class = &omap2xxx_wd_timer_hwmod_class,
830 .main_clk = "mpu_wdt_fck",
831 .prcm = {
832 .omap2 = {
833 .prcm_reg_id = 1,
834 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
835 .module_offs = WKUP_MOD,
836 .idlest_reg_id = 1,
837 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
838 },
839 },
840 .slaves = omap2430_wd_timer2_slaves,
841 .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves),
842 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
843};
844
845/* UART1 */
846
847static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
848 &omap2_l4_core__uart1,
849};
850
851static struct omap_hwmod omap2430_uart1_hwmod = {
852 .name = "uart1",
853 .mpu_irqs = omap2_uart1_mpu_irqs,
854 .sdma_reqs = omap2_uart1_sdma_reqs,
855 .main_clk = "uart1_fck",
856 .prcm = {
857 .omap2 = {
858 .module_offs = CORE_MOD,
859 .prcm_reg_id = 1,
860 .module_bit = OMAP24XX_EN_UART1_SHIFT,
861 .idlest_reg_id = 1,
862 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
863 },
864 },
865 .slaves = omap2430_uart1_slaves,
866 .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
867 .class = &omap2_uart_class,
868 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
869};
870
871/* UART2 */
872
873static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
874 &omap2_l4_core__uart2,
875};
876
877static struct omap_hwmod omap2430_uart2_hwmod = {
878 .name = "uart2",
879 .mpu_irqs = omap2_uart2_mpu_irqs,
880 .sdma_reqs = omap2_uart2_sdma_reqs,
881 .main_clk = "uart2_fck",
882 .prcm = {
883 .omap2 = {
884 .module_offs = CORE_MOD,
885 .prcm_reg_id = 1,
886 .module_bit = OMAP24XX_EN_UART2_SHIFT,
887 .idlest_reg_id = 1,
888 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
889 },
890 },
891 .slaves = omap2430_uart2_slaves,
892 .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
893 .class = &omap2_uart_class,
894 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
895};
896
897/* UART3 */
898
899static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
900 &omap2_l4_core__uart3,
901};
902
903static struct omap_hwmod omap2430_uart3_hwmod = {
904 .name = "uart3",
905 .mpu_irqs = omap2_uart3_mpu_irqs,
906 .sdma_reqs = omap2_uart3_sdma_reqs,
907 .main_clk = "uart3_fck",
908 .prcm = {
909 .omap2 = {
910 .module_offs = CORE_MOD,
911 .prcm_reg_id = 2,
912 .module_bit = OMAP24XX_EN_UART3_SHIFT,
913 .idlest_reg_id = 2,
914 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
915 },
916 },
917 .slaves = omap2430_uart3_slaves,
918 .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
919 .class = &omap2_uart_class,
920 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
921};
922
923/* dss */
924/* dss master ports */
925static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
926 &omap2430_dss__l3,
927};
928
929/* l4_core -> dss */
930static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
931 .master = &omap2430_l4_core_hwmod,
932 .slave = &omap2430_dss_core_hwmod,
933 .clk = "dss_ick",
934 .addr = omap2_dss_addrs,
935 .user = OCP_USER_MPU | OCP_USER_SDMA,
936};
937
938/* dss slave ports */
939static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
940 &omap2430_l4_core__dss,
941};
942
943static struct omap_hwmod_opt_clk dss_opt_clks[] = {
944 { .role = "tv_clk", .clk = "dss_54m_fck" },
945 { .role = "sys_clk", .clk = "dss2_fck" },
946};
947
948static struct omap_hwmod omap2430_dss_core_hwmod = {
949 .name = "dss_core",
950 .class = &omap2_dss_hwmod_class,
951 .main_clk = "dss1_fck", /* instead of dss_fck */
952 .sdma_reqs = omap2xxx_dss_sdma_chs,
953 .prcm = {
954 .omap2 = {
955 .prcm_reg_id = 1,
956 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
957 .module_offs = CORE_MOD,
958 .idlest_reg_id = 1,
959 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
960 },
961 },
962 .opt_clks = dss_opt_clks,
963 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
964 .slaves = omap2430_dss_slaves,
965 .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves),
966 .masters = omap2430_dss_masters,
967 .masters_cnt = ARRAY_SIZE(omap2430_dss_masters),
968 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
969 .flags = HWMOD_NO_IDLEST,
970};
971
972/* l4_core -> dss_dispc */
973static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
974 .master = &omap2430_l4_core_hwmod,
975 .slave = &omap2430_dss_dispc_hwmod,
976 .clk = "dss_ick",
977 .addr = omap2_dss_dispc_addrs,
978 .user = OCP_USER_MPU | OCP_USER_SDMA,
979};
980
981/* dss_dispc slave ports */
982static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
983 &omap2430_l4_core__dss_dispc,
984};
985
986static struct omap_hwmod omap2430_dss_dispc_hwmod = {
987 .name = "dss_dispc",
988 .class = &omap2_dispc_hwmod_class,
989 .mpu_irqs = omap2_dispc_irqs,
990 .main_clk = "dss1_fck",
991 .prcm = {
992 .omap2 = {
993 .prcm_reg_id = 1,
994 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
995 .module_offs = CORE_MOD,
996 .idlest_reg_id = 1,
997 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
998 },
999 },
1000 .slaves = omap2430_dss_dispc_slaves,
1001 .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves),
1002 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1003 .flags = HWMOD_NO_IDLEST,
1004};
1005
1006/* l4_core -> dss_rfbi */
1007static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
1008 .master = &omap2430_l4_core_hwmod,
1009 .slave = &omap2430_dss_rfbi_hwmod,
1010 .clk = "dss_ick",
1011 .addr = omap2_dss_rfbi_addrs,
1012 .user = OCP_USER_MPU | OCP_USER_SDMA,
1013};
1014
1015/* dss_rfbi slave ports */
1016static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1017 &omap2430_l4_core__dss_rfbi,
1018};
1019
1020static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1021 .name = "dss_rfbi",
1022 .class = &omap2_rfbi_hwmod_class,
1023 .main_clk = "dss1_fck",
1024 .prcm = {
1025 .omap2 = {
1026 .prcm_reg_id = 1,
1027 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1028 .module_offs = CORE_MOD,
1029 },
1030 },
1031 .slaves = omap2430_dss_rfbi_slaves,
1032 .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1033 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1034 .flags = HWMOD_NO_IDLEST,
1035};
1036
1037/* l4_core -> dss_venc */
1038static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1039 .master = &omap2430_l4_core_hwmod,
1040 .slave = &omap2430_dss_venc_hwmod,
1041 .clk = "dss_54m_fck",
1042 .addr = omap2_dss_venc_addrs,
1043 .flags = OCPIF_SWSUP_IDLE,
1044 .user = OCP_USER_MPU | OCP_USER_SDMA,
1045};
1046
1047/* dss_venc slave ports */
1048static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1049 &omap2430_l4_core__dss_venc,
1050};
1051
1052static struct omap_hwmod omap2430_dss_venc_hwmod = {
1053 .name = "dss_venc",
1054 .class = &omap2_venc_hwmod_class,
1055 .main_clk = "dss1_fck",
1056 .prcm = {
1057 .omap2 = {
1058 .prcm_reg_id = 1,
1059 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1060 .module_offs = CORE_MOD,
1061 },
1062 },
1063 .slaves = omap2430_dss_venc_slaves,
1064 .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves),
1065 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1066 .flags = HWMOD_NO_IDLEST,
1067};
1068
1069/* I2C common */
1070static struct omap_hwmod_class_sysconfig i2c_sysc = {
1071 .rev_offs = 0x00,
1072 .sysc_offs = 0x20,
1073 .syss_offs = 0x10,
1074 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1075 SYSS_HAS_RESET_STATUS),
1076 .sysc_fields = &omap_hwmod_sysc_type1,
1077};
1078
1079static struct omap_hwmod_class i2c_class = {
1080 .name = "i2c",
1081 .sysc = &i2c_sysc,
1082 .rev = OMAP_I2C_IP_VERSION_1,
1083 .reset = &omap_i2c_reset,
1084};
1085
1086static struct omap_i2c_dev_attr i2c_dev_attr = {
1087 .fifo_depth = 8, /* bytes */
1088 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1089 OMAP_I2C_FLAG_BUS_SHIFT_2 |
1090 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1091};
1092
1093/* I2C1 */
1094
1095static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
1096 &omap2430_l4_core__i2c1,
1097};
1098
1099static struct omap_hwmod omap2430_i2c1_hwmod = {
1100 .name = "i2c1",
1101 .flags = HWMOD_16BIT_REG,
1102 .mpu_irqs = omap2_i2c1_mpu_irqs,
1103 .sdma_reqs = omap2_i2c1_sdma_reqs,
1104 .main_clk = "i2chs1_fck",
1105 .prcm = {
1106 .omap2 = {
1107 /*
1108 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
1109 * I2CHS IP's do not follow the usual pattern.
1110 * prcm_reg_id alone cannot be used to program
1111 * the iclk and fclk. Needs to be handled using
1112 * additional flags when clk handling is moved
1113 * to hwmod framework.
1114 */
1115 .module_offs = CORE_MOD,
1116 .prcm_reg_id = 1,
1117 .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
1118 .idlest_reg_id = 1,
1119 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
1120 },
1121 },
1122 .slaves = omap2430_i2c1_slaves,
1123 .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves),
1124 .class = &i2c_class,
1125 .dev_attr = &i2c_dev_attr,
1126 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1127};
1128
1129/* I2C2 */
1130
1131static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
1132 &omap2430_l4_core__i2c2,
1133};
1134
1135static struct omap_hwmod omap2430_i2c2_hwmod = {
1136 .name = "i2c2",
1137 .flags = HWMOD_16BIT_REG,
1138 .mpu_irqs = omap2_i2c2_mpu_irqs,
1139 .sdma_reqs = omap2_i2c2_sdma_reqs,
1140 .main_clk = "i2chs2_fck",
1141 .prcm = {
1142 .omap2 = {
1143 .module_offs = CORE_MOD,
1144 .prcm_reg_id = 1,
1145 .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
1146 .idlest_reg_id = 1,
1147 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
1148 },
1149 },
1150 .slaves = omap2430_i2c2_slaves,
1151 .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves),
1152 .class = &i2c_class,
1153 .dev_attr = &i2c_dev_attr,
1154 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1155};
1156
1157/* l4_wkup -> gpio1 */
1158static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
1159 {
1160 .pa_start = 0x4900C000,
1161 .pa_end = 0x4900C1ff,
1162 .flags = ADDR_TYPE_RT
1163 },
1164 { }
1165};
1166
1167static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
1168 .master = &omap2430_l4_wkup_hwmod,
1169 .slave = &omap2430_gpio1_hwmod,
1170 .clk = "gpios_ick",
1171 .addr = omap2430_gpio1_addr_space,
1172 .user = OCP_USER_MPU | OCP_USER_SDMA,
1173};
1174
1175/* l4_wkup -> gpio2 */
1176static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
1177 {
1178 .pa_start = 0x4900E000,
1179 .pa_end = 0x4900E1ff,
1180 .flags = ADDR_TYPE_RT
1181 },
1182 { }
1183};
1184
1185static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
1186 .master = &omap2430_l4_wkup_hwmod,
1187 .slave = &omap2430_gpio2_hwmod,
1188 .clk = "gpios_ick",
1189 .addr = omap2430_gpio2_addr_space,
1190 .user = OCP_USER_MPU | OCP_USER_SDMA,
1191};
1192
1193/* l4_wkup -> gpio3 */
1194static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
1195 {
1196 .pa_start = 0x49010000,
1197 .pa_end = 0x490101ff,
1198 .flags = ADDR_TYPE_RT
1199 },
1200 { }
1201};
1202
1203static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
1204 .master = &omap2430_l4_wkup_hwmod,
1205 .slave = &omap2430_gpio3_hwmod,
1206 .clk = "gpios_ick",
1207 .addr = omap2430_gpio3_addr_space,
1208 .user = OCP_USER_MPU | OCP_USER_SDMA,
1209};
1210
1211/* l4_wkup -> gpio4 */
1212static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
1213 {
1214 .pa_start = 0x49012000,
1215 .pa_end = 0x490121ff,
1216 .flags = ADDR_TYPE_RT
1217 },
1218 { }
1219};
1220
1221static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
1222 .master = &omap2430_l4_wkup_hwmod,
1223 .slave = &omap2430_gpio4_hwmod,
1224 .clk = "gpios_ick",
1225 .addr = omap2430_gpio4_addr_space,
1226 .user = OCP_USER_MPU | OCP_USER_SDMA,
1227};
1228
1229/* l4_core -> gpio5 */
1230static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
1231 {
1232 .pa_start = 0x480B6000,
1233 .pa_end = 0x480B61ff,
1234 .flags = ADDR_TYPE_RT
1235 },
1236 { }
1237};
1238
1239static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
1240 .master = &omap2430_l4_core_hwmod,
1241 .slave = &omap2430_gpio5_hwmod,
1242 .clk = "gpio5_ick",
1243 .addr = omap2430_gpio5_addr_space,
1244 .user = OCP_USER_MPU | OCP_USER_SDMA,
1245};
1246
1247/* gpio dev_attr */
1248static struct omap_gpio_dev_attr gpio_dev_attr = {
1249 .bank_width = 32,
1250 .dbck_flag = false,
1251};
1252
1253/* gpio1 */
1254static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1255 &omap2430_l4_wkup__gpio1,
1256};
1257
1258static struct omap_hwmod omap2430_gpio1_hwmod = {
1259 .name = "gpio1",
1260 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1261 .mpu_irqs = omap2_gpio1_irqs,
1262 .main_clk = "gpios_fck",
1263 .prcm = {
1264 .omap2 = {
1265 .prcm_reg_id = 1,
1266 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1267 .module_offs = WKUP_MOD,
1268 .idlest_reg_id = 1,
1269 .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
1270 },
1271 },
1272 .slaves = omap2430_gpio1_slaves,
1273 .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
1274 .class = &omap2xxx_gpio_hwmod_class,
1275 .dev_attr = &gpio_dev_attr,
1276 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1277};
1278
1279/* gpio2 */
1280static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1281 &omap2430_l4_wkup__gpio2,
1282};
1283
1284static struct omap_hwmod omap2430_gpio2_hwmod = {
1285 .name = "gpio2",
1286 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1287 .mpu_irqs = omap2_gpio2_irqs,
1288 .main_clk = "gpios_fck",
1289 .prcm = {
1290 .omap2 = {
1291 .prcm_reg_id = 1,
1292 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1293 .module_offs = WKUP_MOD,
1294 .idlest_reg_id = 1,
1295 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1296 },
1297 },
1298 .slaves = omap2430_gpio2_slaves,
1299 .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
1300 .class = &omap2xxx_gpio_hwmod_class,
1301 .dev_attr = &gpio_dev_attr,
1302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1303};
1304
1305/* gpio3 */
1306static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1307 &omap2430_l4_wkup__gpio3,
1308};
1309
1310static struct omap_hwmod omap2430_gpio3_hwmod = {
1311 .name = "gpio3",
1312 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1313 .mpu_irqs = omap2_gpio3_irqs,
1314 .main_clk = "gpios_fck",
1315 .prcm = {
1316 .omap2 = {
1317 .prcm_reg_id = 1,
1318 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1319 .module_offs = WKUP_MOD,
1320 .idlest_reg_id = 1,
1321 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1322 },
1323 },
1324 .slaves = omap2430_gpio3_slaves,
1325 .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
1326 .class = &omap2xxx_gpio_hwmod_class,
1327 .dev_attr = &gpio_dev_attr,
1328 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1329};
1330
1331/* gpio4 */
1332static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1333 &omap2430_l4_wkup__gpio4,
1334};
1335
1336static struct omap_hwmod omap2430_gpio4_hwmod = {
1337 .name = "gpio4",
1338 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1339 .mpu_irqs = omap2_gpio4_irqs,
1340 .main_clk = "gpios_fck",
1341 .prcm = {
1342 .omap2 = {
1343 .prcm_reg_id = 1,
1344 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1345 .module_offs = WKUP_MOD,
1346 .idlest_reg_id = 1,
1347 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1348 },
1349 },
1350 .slaves = omap2430_gpio4_slaves,
1351 .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
1352 .class = &omap2xxx_gpio_hwmod_class,
1353 .dev_attr = &gpio_dev_attr,
1354 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1355};
1356
1357/* gpio5 */
1358static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
1359 { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
1360 { .irq = -1 }
1361};
1362
1363static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
1364 &omap2430_l4_core__gpio5,
1365};
1366
1367static struct omap_hwmod omap2430_gpio5_hwmod = {
1368 .name = "gpio5",
1369 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1370 .mpu_irqs = omap243x_gpio5_irqs,
1371 .main_clk = "gpio5_fck",
1372 .prcm = {
1373 .omap2 = {
1374 .prcm_reg_id = 2,
1375 .module_bit = OMAP2430_EN_GPIO5_SHIFT,
1376 .module_offs = CORE_MOD,
1377 .idlest_reg_id = 2,
1378 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
1379 },
1380 },
1381 .slaves = omap2430_gpio5_slaves,
1382 .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
1383 .class = &omap2xxx_gpio_hwmod_class,
1384 .dev_attr = &gpio_dev_attr,
1385 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1386};
1387
1388/* dma attributes */
1389static struct omap_dma_dev_attr dma_dev_attr = {
1390 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1391 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1392 .lch_count = 32,
1393};
1394
1395/* dma_system -> L3 */
1396static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
1397 .master = &omap2430_dma_system_hwmod,
1398 .slave = &omap2430_l3_main_hwmod,
1399 .clk = "core_l3_ck",
1400 .user = OCP_USER_MPU | OCP_USER_SDMA,
1401};
1402
1403/* dma_system master ports */
1404static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
1405 &omap2430_dma_system__l3,
1406};
1407
1408/* l4_core -> dma_system */
1409static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
1410 .master = &omap2430_l4_core_hwmod,
1411 .slave = &omap2430_dma_system_hwmod,
1412 .clk = "sdma_ick",
1413 .addr = omap2_dma_system_addrs,
1414 .user = OCP_USER_MPU | OCP_USER_SDMA,
1415};
1416
1417/* dma_system slave ports */
1418static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1419 &omap2430_l4_core__dma_system,
1420};
1421
1422static struct omap_hwmod omap2430_dma_system_hwmod = {
1423 .name = "dma",
1424 .class = &omap2xxx_dma_hwmod_class,
1425 .mpu_irqs = omap2_dma_system_irqs,
1426 .main_clk = "core_l3_ck",
1427 .slaves = omap2430_dma_system_slaves,
1428 .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
1429 .masters = omap2430_dma_system_masters,
1430 .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters),
1431 .dev_attr = &dma_dev_attr,
1432 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1433 .flags = HWMOD_NO_IDLEST,
1434};
1435
1436/* mailbox */
1437static struct omap_hwmod omap2430_mailbox_hwmod;
1438static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
1439 { .irq = 26 },
1440 { .irq = -1 }
1441};
1442
1443/* l4_core -> mailbox */
1444static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
1445 .master = &omap2430_l4_core_hwmod,
1446 .slave = &omap2430_mailbox_hwmod,
1447 .addr = omap2_mailbox_addrs,
1448 .user = OCP_USER_MPU | OCP_USER_SDMA,
1449};
1450
1451/* mailbox slave ports */
1452static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
1453 &omap2430_l4_core__mailbox,
1454};
1455
1456static struct omap_hwmod omap2430_mailbox_hwmod = {
1457 .name = "mailbox",
1458 .class = &omap2xxx_mailbox_hwmod_class,
1459 .mpu_irqs = omap2430_mailbox_irqs,
1460 .main_clk = "mailboxes_ick",
1461 .prcm = {
1462 .omap2 = {
1463 .prcm_reg_id = 1,
1464 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1465 .module_offs = CORE_MOD,
1466 .idlest_reg_id = 1,
1467 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1468 },
1469 },
1470 .slaves = omap2430_mailbox_slaves,
1471 .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves),
1472 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1473};
1474
1475/* mcspi1 */
1476static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
1477 &omap2430_l4_core__mcspi1,
1478};
1479
1480static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1481 .num_chipselect = 4,
1482};
1483
1484static struct omap_hwmod omap2430_mcspi1_hwmod = {
1485 .name = "mcspi1_hwmod",
1486 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1487 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1488 .main_clk = "mcspi1_fck",
1489 .prcm = {
1490 .omap2 = {
1491 .module_offs = CORE_MOD,
1492 .prcm_reg_id = 1,
1493 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1494 .idlest_reg_id = 1,
1495 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1496 },
1497 },
1498 .slaves = omap2430_mcspi1_slaves,
1499 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
1500 .class = &omap2xxx_mcspi_class,
1501 .dev_attr = &omap_mcspi1_dev_attr,
1502 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1503};
1504
1505/* mcspi2 */
1506static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
1507 &omap2430_l4_core__mcspi2,
1508};
1509
1510static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1511 .num_chipselect = 2,
1512};
1513
1514static struct omap_hwmod omap2430_mcspi2_hwmod = {
1515 .name = "mcspi2_hwmod",
1516 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1517 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1518 .main_clk = "mcspi2_fck",
1519 .prcm = {
1520 .omap2 = {
1521 .module_offs = CORE_MOD,
1522 .prcm_reg_id = 1,
1523 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1524 .idlest_reg_id = 1,
1525 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1526 },
1527 },
1528 .slaves = omap2430_mcspi2_slaves,
1529 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
1530 .class = &omap2xxx_mcspi_class,
1531 .dev_attr = &omap_mcspi2_dev_attr,
1532 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1533};
1534
1535/* mcspi3 */
1536static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
1537 { .irq = 91 },
1538 { .irq = -1 }
1539};
1540
1541static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
1542 { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
1543 { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
1544 { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
1545 { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
1546 { .dma_req = -1 }
1547};
1548
1549static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
1550 &omap2430_l4_core__mcspi3,
1551};
1552
1553static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1554 .num_chipselect = 2,
1555};
1556
1557static struct omap_hwmod omap2430_mcspi3_hwmod = {
1558 .name = "mcspi3_hwmod",
1559 .mpu_irqs = omap2430_mcspi3_mpu_irqs,
1560 .sdma_reqs = omap2430_mcspi3_sdma_reqs,
1561 .main_clk = "mcspi3_fck",
1562 .prcm = {
1563 .omap2 = {
1564 .module_offs = CORE_MOD,
1565 .prcm_reg_id = 2,
1566 .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
1567 .idlest_reg_id = 2,
1568 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
1569 },
1570 },
1571 .slaves = omap2430_mcspi3_slaves,
1572 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
1573 .class = &omap2xxx_mcspi_class,
1574 .dev_attr = &omap_mcspi3_dev_attr,
1575 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1576};
1577
1578/*
1579 * usbhsotg
1580 */
1581static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
1582 .rev_offs = 0x0400,
1583 .sysc_offs = 0x0404,
1584 .syss_offs = 0x0408,
1585 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1586 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1587 SYSC_HAS_AUTOIDLE),
1588 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1589 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1590 .sysc_fields = &omap_hwmod_sysc_type1,
1591};
1592
1593static struct omap_hwmod_class usbotg_class = {
1594 .name = "usbotg",
1595 .sysc = &omap2430_usbhsotg_sysc,
1596};
1597
1598/* usb_otg_hs */
1599static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
1600
1601 { .name = "mc", .irq = 92 },
1602 { .name = "dma", .irq = 93 },
1603 { .irq = -1 }
1604};
1605
1606static struct omap_hwmod omap2430_usbhsotg_hwmod = {
1607 .name = "usb_otg_hs",
1608 .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
1609 .main_clk = "usbhs_ick",
1610 .prcm = {
1611 .omap2 = {
1612 .prcm_reg_id = 1,
1613 .module_bit = OMAP2430_EN_USBHS_MASK,
1614 .module_offs = CORE_MOD,
1615 .idlest_reg_id = 1,
1616 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
1617 },
1618 },
1619 .masters = omap2430_usbhsotg_masters,
1620 .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters),
1621 .slaves = omap2430_usbhsotg_slaves,
1622 .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves),
1623 .class = &usbotg_class,
1624 /*
1625 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1626 * broken when autoidle is enabled
1627 * workaround is to disable the autoidle bit at module level.
1628 */
1629 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1630 | HWMOD_SWSUP_MSTANDBY,
1631 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1632};
1633
1634/*
1635 * 'mcbsp' class
1636 * multi channel buffered serial port controller
1637 */
1638
1639static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
1640 .rev_offs = 0x007C,
1641 .sysc_offs = 0x008C,
1642 .sysc_flags = (SYSC_HAS_SOFTRESET),
1643 .sysc_fields = &omap_hwmod_sysc_type1,
1644};
1645
1646static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
1647 .name = "mcbsp",
1648 .sysc = &omap2430_mcbsp_sysc,
1649 .rev = MCBSP_CONFIG_TYPE2,
1650};
1651
1652/* mcbsp1 */
1653static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
1654 { .name = "tx", .irq = 59 },
1655 { .name = "rx", .irq = 60 },
1656 { .name = "ovr", .irq = 61 },
1657 { .name = "common", .irq = 64 },
1658 { .irq = -1 }
1659};
1660
1661/* l4_core -> mcbsp1 */
1662static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
1663 .master = &omap2430_l4_core_hwmod,
1664 .slave = &omap2430_mcbsp1_hwmod,
1665 .clk = "mcbsp1_ick",
1666 .addr = omap2_mcbsp1_addrs,
1667 .user = OCP_USER_MPU | OCP_USER_SDMA,
1668};
1669
1670/* mcbsp1 slave ports */
1671static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
1672 &omap2430_l4_core__mcbsp1,
1673};
1674
1675static struct omap_hwmod omap2430_mcbsp1_hwmod = {
1676 .name = "mcbsp1",
1677 .class = &omap2430_mcbsp_hwmod_class,
1678 .mpu_irqs = omap2430_mcbsp1_irqs,
1679 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1680 .main_clk = "mcbsp1_fck",
1681 .prcm = {
1682 .omap2 = {
1683 .prcm_reg_id = 1,
1684 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1685 .module_offs = CORE_MOD,
1686 .idlest_reg_id = 1,
1687 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1688 },
1689 },
1690 .slaves = omap2430_mcbsp1_slaves,
1691 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves),
1692 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1693};
1694
1695/* mcbsp2 */
1696static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
1697 { .name = "tx", .irq = 62 },
1698 { .name = "rx", .irq = 63 },
1699 { .name = "common", .irq = 16 },
1700 { .irq = -1 }
1701};
1702
1703/* l4_core -> mcbsp2 */
1704static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
1705 .master = &omap2430_l4_core_hwmod,
1706 .slave = &omap2430_mcbsp2_hwmod,
1707 .clk = "mcbsp2_ick",
1708 .addr = omap2xxx_mcbsp2_addrs,
1709 .user = OCP_USER_MPU | OCP_USER_SDMA,
1710};
1711
1712/* mcbsp2 slave ports */
1713static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
1714 &omap2430_l4_core__mcbsp2,
1715};
1716
1717static struct omap_hwmod omap2430_mcbsp2_hwmod = {
1718 .name = "mcbsp2",
1719 .class = &omap2430_mcbsp_hwmod_class,
1720 .mpu_irqs = omap2430_mcbsp2_irqs,
1721 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1722 .main_clk = "mcbsp2_fck",
1723 .prcm = {
1724 .omap2 = {
1725 .prcm_reg_id = 1,
1726 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1727 .module_offs = CORE_MOD,
1728 .idlest_reg_id = 1,
1729 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1730 },
1731 },
1732 .slaves = omap2430_mcbsp2_slaves,
1733 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves),
1734 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1735};
1736
1737/* mcbsp3 */
1738static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
1739 { .name = "tx", .irq = 89 },
1740 { .name = "rx", .irq = 90 },
1741 { .name = "common", .irq = 17 },
1742 { .irq = -1 }
1743};
1744
1745static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
1746 {
1747 .name = "mpu",
1748 .pa_start = 0x4808C000,
1749 .pa_end = 0x4808C0ff,
1750 .flags = ADDR_TYPE_RT
1751 },
1752 { }
1753};
1754
1755/* l4_core -> mcbsp3 */
1756static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
1757 .master = &omap2430_l4_core_hwmod,
1758 .slave = &omap2430_mcbsp3_hwmod,
1759 .clk = "mcbsp3_ick",
1760 .addr = omap2430_mcbsp3_addrs,
1761 .user = OCP_USER_MPU | OCP_USER_SDMA,
1762};
1763
1764/* mcbsp3 slave ports */
1765static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
1766 &omap2430_l4_core__mcbsp3,
1767};
1768
1769static struct omap_hwmod omap2430_mcbsp3_hwmod = {
1770 .name = "mcbsp3",
1771 .class = &omap2430_mcbsp_hwmod_class,
1772 .mpu_irqs = omap2430_mcbsp3_irqs,
1773 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1774 .main_clk = "mcbsp3_fck",
1775 .prcm = {
1776 .omap2 = {
1777 .prcm_reg_id = 1,
1778 .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
1779 .module_offs = CORE_MOD,
1780 .idlest_reg_id = 2,
1781 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
1782 },
1783 },
1784 .slaves = omap2430_mcbsp3_slaves,
1785 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves),
1786 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1787};
1788
1789/* mcbsp4 */
1790static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
1791 { .name = "tx", .irq = 54 },
1792 { .name = "rx", .irq = 55 },
1793 { .name = "common", .irq = 18 },
1794 { .irq = -1 }
1795};
1796
1797static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
1798 { .name = "rx", .dma_req = 20 },
1799 { .name = "tx", .dma_req = 19 },
1800 { .dma_req = -1 }
1801};
1802
1803static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
1804 {
1805 .name = "mpu",
1806 .pa_start = 0x4808E000,
1807 .pa_end = 0x4808E0ff,
1808 .flags = ADDR_TYPE_RT
1809 },
1810 { }
1811};
1812
1813/* l4_core -> mcbsp4 */
1814static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
1815 .master = &omap2430_l4_core_hwmod,
1816 .slave = &omap2430_mcbsp4_hwmod,
1817 .clk = "mcbsp4_ick",
1818 .addr = omap2430_mcbsp4_addrs,
1819 .user = OCP_USER_MPU | OCP_USER_SDMA,
1820};
1821
1822/* mcbsp4 slave ports */
1823static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
1824 &omap2430_l4_core__mcbsp4,
1825};
1826
1827static struct omap_hwmod omap2430_mcbsp4_hwmod = {
1828 .name = "mcbsp4",
1829 .class = &omap2430_mcbsp_hwmod_class,
1830 .mpu_irqs = omap2430_mcbsp4_irqs,
1831 .sdma_reqs = omap2430_mcbsp4_sdma_chs,
1832 .main_clk = "mcbsp4_fck",
1833 .prcm = {
1834 .omap2 = {
1835 .prcm_reg_id = 1,
1836 .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
1837 .module_offs = CORE_MOD,
1838 .idlest_reg_id = 2,
1839 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
1840 },
1841 },
1842 .slaves = omap2430_mcbsp4_slaves,
1843 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves),
1844 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1845};
1846
1847/* mcbsp5 */
1848static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
1849 { .name = "tx", .irq = 81 },
1850 { .name = "rx", .irq = 82 },
1851 { .name = "common", .irq = 19 },
1852 { .irq = -1 }
1853};
1854
1855static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
1856 { .name = "rx", .dma_req = 22 },
1857 { .name = "tx", .dma_req = 21 },
1858 { .dma_req = -1 }
1859};
1860
1861static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
1862 {
1863 .name = "mpu",
1864 .pa_start = 0x48096000,
1865 .pa_end = 0x480960ff,
1866 .flags = ADDR_TYPE_RT
1867 },
1868 { }
1869};
1870
1871/* l4_core -> mcbsp5 */
1872static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
1873 .master = &omap2430_l4_core_hwmod,
1874 .slave = &omap2430_mcbsp5_hwmod,
1875 .clk = "mcbsp5_ick",
1876 .addr = omap2430_mcbsp5_addrs,
1877 .user = OCP_USER_MPU | OCP_USER_SDMA,
1878};
1879
1880/* mcbsp5 slave ports */
1881static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
1882 &omap2430_l4_core__mcbsp5,
1883};
1884
1885static struct omap_hwmod omap2430_mcbsp5_hwmod = {
1886 .name = "mcbsp5",
1887 .class = &omap2430_mcbsp_hwmod_class,
1888 .mpu_irqs = omap2430_mcbsp5_irqs,
1889 .sdma_reqs = omap2430_mcbsp5_sdma_chs,
1890 .main_clk = "mcbsp5_fck",
1891 .prcm = {
1892 .omap2 = {
1893 .prcm_reg_id = 1,
1894 .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
1895 .module_offs = CORE_MOD,
1896 .idlest_reg_id = 2,
1897 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
1898 },
1899 },
1900 .slaves = omap2430_mcbsp5_slaves,
1901 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves),
1902 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1903};
1904
1905/* MMC/SD/SDIO common */
1906
1907static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
1908 .rev_offs = 0x1fc,
1909 .sysc_offs = 0x10,
1910 .syss_offs = 0x14,
1911 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1912 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1913 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1914 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1915 .sysc_fields = &omap_hwmod_sysc_type1,
1916};
1917
1918static struct omap_hwmod_class omap2430_mmc_class = {
1919 .name = "mmc",
1920 .sysc = &omap2430_mmc_sysc,
1921};
1922
1923/* MMC/SD/SDIO1 */
1924
1925static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
1926 { .irq = 83 },
1927 { .irq = -1 }
1928};
1929
1930static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
1931 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
1932 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
1933 { .dma_req = -1 }
1934};
1935
1936static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
1937 { .role = "dbck", .clk = "mmchsdb1_fck" },
1938};
1939
1940static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
1941 &omap2430_l4_core__mmc1,
1942};
1943
1944static struct omap_mmc_dev_attr mmc1_dev_attr = {
1945 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1946};
1947
1948static struct omap_hwmod omap2430_mmc1_hwmod = {
1949 .name = "mmc1",
1950 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1951 .mpu_irqs = omap2430_mmc1_mpu_irqs,
1952 .sdma_reqs = omap2430_mmc1_sdma_reqs,
1953 .opt_clks = omap2430_mmc1_opt_clks,
1954 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
1955 .main_clk = "mmchs1_fck",
1956 .prcm = {
1957 .omap2 = {
1958 .module_offs = CORE_MOD,
1959 .prcm_reg_id = 2,
1960 .module_bit = OMAP2430_EN_MMCHS1_SHIFT,
1961 .idlest_reg_id = 2,
1962 .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
1963 },
1964 },
1965 .dev_attr = &mmc1_dev_attr,
1966 .slaves = omap2430_mmc1_slaves,
1967 .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves),
1968 .class = &omap2430_mmc_class,
1969 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1970};
1971
1972/* MMC/SD/SDIO2 */
1973
1974static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
1975 { .irq = 86 },
1976 { .irq = -1 }
1977};
1978
1979static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
1980 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
1981 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
1982 { .dma_req = -1 }
1983};
1984
1985static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
1986 { .role = "dbck", .clk = "mmchsdb2_fck" },
1987};
1988
1989static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
1990 &omap2430_l4_core__mmc2,
1991};
1992
1993static struct omap_hwmod omap2430_mmc2_hwmod = {
1994 .name = "mmc2",
1995 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1996 .mpu_irqs = omap2430_mmc2_mpu_irqs,
1997 .sdma_reqs = omap2430_mmc2_sdma_reqs,
1998 .opt_clks = omap2430_mmc2_opt_clks,
1999 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
2000 .main_clk = "mmchs2_fck",
2001 .prcm = {
2002 .omap2 = {
2003 .module_offs = CORE_MOD,
2004 .prcm_reg_id = 2,
2005 .module_bit = OMAP2430_EN_MMCHS2_SHIFT,
2006 .idlest_reg_id = 2,
2007 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
2008 },
2009 },
2010 .slaves = omap2430_mmc2_slaves,
2011 .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves),
2012 .class = &omap2430_mmc_class,
2013 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2014};
2015
2016static __initdata struct omap_hwmod *omap2430_hwmods[] = {
2017 &omap2430_l3_main_hwmod,
2018 &omap2430_l4_core_hwmod,
2019 &omap2430_l4_wkup_hwmod,
2020 &omap2430_mpu_hwmod,
2021 &omap2430_iva_hwmod,
2022
2023 &omap2430_timer1_hwmod,
2024 &omap2430_timer2_hwmod,
2025 &omap2430_timer3_hwmod,
2026 &omap2430_timer4_hwmod,
2027 &omap2430_timer5_hwmod,
2028 &omap2430_timer6_hwmod,
2029 &omap2430_timer7_hwmod,
2030 &omap2430_timer8_hwmod,
2031 &omap2430_timer9_hwmod,
2032 &omap2430_timer10_hwmod,
2033 &omap2430_timer11_hwmod,
2034 &omap2430_timer12_hwmod,
2035
2036 &omap2430_wd_timer2_hwmod,
2037 &omap2430_uart1_hwmod,
2038 &omap2430_uart2_hwmod,
2039 &omap2430_uart3_hwmod,
2040 /* dss class */
2041 &omap2430_dss_core_hwmod,
2042 &omap2430_dss_dispc_hwmod,
2043 &omap2430_dss_rfbi_hwmod,
2044 &omap2430_dss_venc_hwmod,
2045 /* i2c class */
2046 &omap2430_i2c1_hwmod,
2047 &omap2430_i2c2_hwmod,
2048 &omap2430_mmc1_hwmod,
2049 &omap2430_mmc2_hwmod,
2050
2051 /* gpio class */
2052 &omap2430_gpio1_hwmod,
2053 &omap2430_gpio2_hwmod,
2054 &omap2430_gpio3_hwmod,
2055 &omap2430_gpio4_hwmod,
2056 &omap2430_gpio5_hwmod,
2057
2058 /* dma_system class*/
2059 &omap2430_dma_system_hwmod,
2060
2061 /* mcbsp class */
2062 &omap2430_mcbsp1_hwmod,
2063 &omap2430_mcbsp2_hwmod,
2064 &omap2430_mcbsp3_hwmod,
2065 &omap2430_mcbsp4_hwmod,
2066 &omap2430_mcbsp5_hwmod,
2067
2068 /* mailbox class */
2069 &omap2430_mailbox_hwmod,
2070
2071 /* mcspi class */
2072 &omap2430_mcspi1_hwmod,
2073 &omap2430_mcspi2_hwmod,
2074 &omap2430_mcspi3_hwmod,
2075
2076 /* usbotg class*/
2077 &omap2430_usbhsotg_hwmod,
2078
2079 NULL,
2080};
2081
2082int __init omap2430_hwmod_init(void)
2083{
2084 return omap_hwmod_register(omap2430_hwmods);
2085}