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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2009-2014 Realtek Corporation.*/
3
4#ifndef __RTL92E_REG_H__
5#define __RTL92E_REG_H__
6
7#define TXPKT_BUF_SELECT 0x69
8#define RXPKT_BUF_SELECT 0xA5
9#define DISABLE_TRXPKT_BUF_ACCESS 0x0
10
11#define REG_SYS_ISO_CTRL 0x0000
12#define REG_SYS_FUNC_EN 0x0002
13#define REG_APS_FSMCO 0x0004
14#define REG_SYS_CLKR 0x0008
15#define REG_9346CR 0x000A
16#define REG_EE_VPD 0x000C
17#define REG_SYS_SWR_CTRL1 0x0010
18#define REG_SPS0_CTRL 0x0011
19#define REG_SYS_SWR_CTRL2 0x0014
20#define REG_SYS_SWR_CTRL3 0x0018
21#define REG_RSV_CTRL 0x001C
22#define REG_RF_CTRL 0x001F
23#define REG_LPLDO_CTRL 0x0023
24#define REG_AFE_CTRL1 0x0024
25#define REG_AFE_XTAL_CTRL 0x0024
26#define REG_AFE_CTRL2 0x0028
27#define REG_MAC_PHY_CTRL 0x002c
28#define REG_AFE_CTRL3 0x002c
29#define REG_EFUSE_CTRL 0x0030
30#define REG_EFUSE_TEST 0x0034
31#define REG_PWR_DATA 0x0038
32#define REG_CAL_TIMER 0x003C
33#define REG_ACLK_MON 0x003E
34#define REG_GPIO_MUXCFG 0x0040
35#define REG_GPIO_IO_SEL 0x0042
36#define REG_MAC_PINMUX_CFG 0x0043
37#define REG_GPIO_PIN_CTRL 0x0044
38#define REG_GPIO_INTM 0x0048
39#define REG_LEDCFG0 0x004C
40#define REG_LEDCFG1 0x004D
41#define REG_LEDCFG2 0x004E
42#define REG_LEDCFG3 0x004F
43#define REG_FSIMR 0x0050
44#define REG_FSISR 0x0054
45#define REG_HSIMR 0x0058
46#define REG_HSISR 0x005c
47#define REG_SDIO_CTRL 0x0070
48#define REG_OPT_CTRL 0x0074
49#define REG_GPIO_OUTPUT 0x006c
50#define REG_AFE_CTRL4 0x0078
51#define REG_MCUFWDL 0x0080
52
53#define REG_HIMR 0x00B0
54#define REG_HISR 0x00B4
55#define REG_HIMRE 0x00B8
56#define REG_HISRE 0x00BC
57
58#define REG_PMC_DBG_CTRL2 0x00CC
59#define REG_EFUSE_ACCESS 0x00CF
60#define REG_HPON_FSM 0x00EC
61#define REG_SYS_CFG1 0x00F0
62#define REG_MAC_PHY_CTRL_NORMAL 0x00F8
63#define REG_SYS_CFG2 0x00FC
64
65#define REG_CR 0x0100
66#define REG_PBP 0x0104
67#define REG_PKT_BUFF_ACCESS_CTRL 0x0106
68#define REG_TRXDMA_CTRL 0x010C
69#define REG_TRXFF_BNDY 0x0114
70#define REG_TRXFF_STATUS 0x0118
71#define REG_RXFF_PTR 0x011C
72
73#define REG_CPWM 0x012F
74#define REG_FWIMR 0x0130
75#define REG_FWISR 0x0134
76#define REG_PKTBUF_DBG_CTRL 0x0140
77#define REG_RXPKTBUF_CTRL 0x0142
78#define REG_PKTBUF_DBG_DATA_L 0x0144
79#define REG_PKTBUF_DBG_DATA_H 0x0148
80
81#define REG_TC0_CTRL 0x0150
82#define REG_TC1_CTRL 0x0154
83#define REG_TC2_CTRL 0x0158
84#define REG_TC3_CTRL 0x015C
85#define REG_TC4_CTRL 0x0160
86#define REG_TCUNIT_BASE 0x0164
87#define REG_RSVD3 0x0168
88#define REG_C2HEVT_MSG_NORMAL 0x01A0
89#define REG_C2HEVT_CLEAR 0x01AF
90#define REG_MCUTST_1 0x01c0
91#define REG_MCUTST_WOWLAN 0x01C7
92#define REG_FMETHR 0x01C8
93#define REG_HMETFR 0x01CC
94#define REG_HMEBOX_0 0x01D0
95#define REG_HMEBOX_1 0x01D4
96#define REG_HMEBOX_2 0x01D8
97#define REG_HMEBOX_3 0x01DC
98
99#define REG_LLT_INIT 0x01E0
100
101#define REG_HMEBOX_EXT_0 0x01F0
102#define REG_HMEBOX_EXT_1 0x01F4
103#define REG_HMEBOX_EXT_2 0x01F8
104#define REG_HMEBOX_EXT_3 0x01FC
105
106/*-----------------------------------------------------
107 *
108 * 0x0200h ~ 0x027Fh TXDMA Configuration
109 *
110 *-----------------------------------------------------
111 */
112#define REG_RQPN 0x0200
113#define REG_FIFOPAGE 0x0204
114#define REG_DWBCN0_CTRL 0x0208
115#define REG_TXDMA_OFFSET_CHK 0x020C
116#define REG_TXDMA_STATUS 0x0210
117#define REG_RQPN_NPQ 0x0214
118#define REG_AUTO_LLT 0x0224
119#define REG_DWBCN1_CTRL 0x0228
120
121/*-----------------------------------------------------
122 *
123 * 0x0280h ~ 0x02FFh RXDMA Configuration
124 *
125 *-----------------------------------------------------
126 */
127#define REG_RXDMA_AGG_PG_TH 0x0280
128#define REG_FW_UPD_RDPTR 0x0284
129#define REG_RXDMA_CONTROL 0x0286
130#define REG_RXPKT_NUM 0x0287
131#define REG_RXDMA_STATUS 0x0288
132#define REG_RXDMA_PRO 0x0290
133#define REG_EARLY_MODE_CONTROL 0x02BC
134#define REG_RSVD5 0x02F0
135#define REG_RSVD6 0x02F4
136
137/*-----------------------------------------------------
138 *
139 * 0x0300h ~ 0x03FFh PCIe
140 *
141 *-----------------------------------------------------
142 */
143#define REG_PCIE_CTRL_REG 0x0300
144#define REG_INT_MIG 0x0304
145#define REG_BCNQ_DESA 0x0308
146#define REG_MGQ_DESA 0x0310
147#define REG_VOQ_DESA 0x0318
148#define REG_VIQ_DESA 0x0320
149#define REG_BEQ_DESA 0x0328
150#define REG_BKQ_DESA 0x0330
151#define REG_RX_DESA 0x0338
152#define REG_HQ0_DESA 0x0340
153#define REG_HQ1_DESA 0x0348
154#define REG_HQ2_DESA 0x0350
155#define REG_HQ3_DESA 0x0358
156#define REG_HQ4_DESA 0x0360
157#define REG_HQ5_DESA 0x0368
158#define REG_HQ6_DESA 0x0370
159#define REG_HQ7_DESA 0x0378
160#define REG_MGQ_TXBD_NUM 0x0380
161#define REG_RX_RXBD_NUM 0x0382
162#define REG_VOQ_TXBD_NUM 0x0384
163#define REG_VIQ_TXBD_NUM 0x0386
164#define REG_BEQ_TXBD_NUM 0x0388
165#define REG_BKQ_TXBD_NUM 0x038A
166#define REG_HI0Q_TXBD_NUM 0x038C
167#define REG_HI1Q_TXBD_NUM 0x038E
168#define REG_HI2Q_TXBD_NUM 0x0390
169#define REG_HI3Q_TXBD_NUM 0x0392
170#define REG_HI4Q_TXBD_NUM 0x0394
171#define REG_HI5Q_TXBD_NUM 0x0396
172#define REG_HI6Q_TXBD_NUM 0x0398
173#define REG_HI7Q_TXBD_NUM 0x039A
174#define REG_TSFTIMER_HCI 0x039C
175/*Read Write Point*/
176#define REG_VOQ_TXBD_IDX 0x03A0
177#define REG_VIQ_TXBD_IDX 0x03A4
178#define REG_BEQ_TXBD_IDX 0x03A8
179#define REG_BKQ_TXBD_IDX 0x03AC
180#define REG_MGQ_TXBD_IDX 0x03B0
181#define REG_RXQ_TXBD_IDX 0x03B4
182
183#define REG_HI0Q_TXBD_IDX 0x03B8
184#define REG_HI1Q_TXBD_IDX 0x03BC
185#define REG_HI2Q_TXBD_IDX 0x03C0
186#define REG_HI3Q_TXBD_IDX 0x03C4
187
188#define REG_HI4Q_TXBD_IDX 0x03C8
189#define REG_HI5Q_TXBD_IDX 0x03CC
190#define REG_HI6Q_TXBD_IDX 0x03D0
191#define REG_HI7Q_TXBD_IDX 0x03D4
192#define REG_PCIE_HCPWM 0x03D8
193#define REG_PCIE_CTRL2 0x03DB
194#define REG_PCIE_HRPWM 0x03DC
195#define REG_H2C_MSG_DRV2FW_INFO 0x03E0
196#define REG_PCIE_C2H_MSG_REQUEST 0x03E4
197#define REG_BACKDOOR_DBI_WDATA 0x03E8
198#define REG_BACKDOOR_DBI_RDATA 0x03EC
199#define REG_BACKDOOR_DBI_DATA 0x03F0
200#define REG_MDIO 0x03F4
201#define REG_MDIO_DATA 0x03F8
202
203#define REG_HDAQ_DESA_NODEF 0x0000
204#define REG_CMDQ_DESA_NODEF 0x0000
205/* spec version 11
206 *-----------------------------------------------------
207 *
208 * 0x0400h ~ 0x047Fh Protocol Configuration
209 *
210 *-----------------------------------------------------
211 */
212#define REG_VOQ_INFORMATION 0x0400
213#define REG_VIQ_INFORMATION 0x0404
214#define REG_BEQ_INFORMATION 0x0408
215#define REG_BKQ_INFORMATION 0x040C
216#define REG_MGQ_INFORMATION 0x0410
217#define REG_HGQ_INFORMATION 0x0414
218#define REG_BCNQ_INFORMATION 0x0418
219#define REG_TXPKT_EMPTY 0x041A
220
221#define REG_FWHW_TXQ_CTRL 0x0420
222#define REG_HWSEQ_CTRL 0x0423
223#define REG_BCNQ_BDNY 0x0424
224#define REG_MGQ_BDNY 0x0425
225#define REG_LIFECTRL_CTRL 0x0426
226#define REG_MULTI_BCNQ_OFFSET 0x0427
227#define REG_SPEC_SIFS 0x0428
228#define REG_RETRY_LIMIT 0x042A
229#define REG_TXBF_CTRL 0x042C
230#define REG_DARFRC 0x0430
231#define REG_RARFRC 0x0438
232#define REG_RRSR 0x0440
233#define REG_ARFR0 0x0444
234#define REG_ARFR1 0x044C
235#define REG_AMPDU_MAX_TIME 0x0456
236#define REG_BCNQ1_BDNY 0x0457
237#define REG_AGGLEN_LMT 0x0458
238#define REG_AMPDU_MIN_SPACE 0x045C
239#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
240#define REG_NDPA_OPT_CTRL 0x045F
241#define REG_FAST_EDCA_CTRL 0x0460
242#define REG_RD_RESP_PKT_TH 0x0463
243#define REG_POWER_STAGE1 0x04B4
244#define REG_POWER_STAGE2 0x04B8
245#define REG_AMPDU_BURST_MODE 0x04BC
246#define REG_PKT_VO_VI_LIFE_TIME 0x04C0
247#define REG_PKT_BE_BK_LIFE_TIME 0x04C2
248#define REG_STBC_SETTING 0x04C4
249#define REG_PROT_MODE_CTRL 0x04C8
250#define REG_MAX_AGGR_NUM 0x04CA
251#define REG_RTS_MAX_AGGR_NUM 0x04CB
252#define REG_BAR_MODE_CTRL 0x04CC
253#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
254#define REG_MACID_PKT_DROP0 0x04D0
255
256/*-----------------------------------------------------
257 *
258 * 0x0500h ~ 0x05FFh EDCA Configuration
259 *
260 *-----------------------------------------------------
261 */
262#define REG_EDCA_VO_PARAM 0x0500
263#define REG_EDCA_VI_PARAM 0x0504
264#define REG_EDCA_BE_PARAM 0x0508
265#define REG_EDCA_BK_PARAM 0x050C
266#define REG_BCNTCFG 0x0510
267#define REG_PIFS 0x0512
268#define REG_RDG_PIFS 0x0513
269#define REG_SIFS_CTX 0x0514
270#define REG_SIFS_TRX 0x0516
271#define REG_AGGR_BREAK_TIME 0x051A
272#define REG_SLOT 0x051B
273#define REG_TX_PTCL_CTRL 0x0520
274#define REG_TXPAUSE 0x0522
275#define REG_DIS_TXREQ_CLR 0x0523
276#define REG_RD_CTRL 0x0524
277
278#define REG_TBTT_PROHIBIT 0x0540
279#define REG_RD_NAV_NXT 0x0544
280#define REG_NAV_PROT_LEN 0x0546
281#define REG_BCN_CTRL 0x0550
282#define REG_BCN_CTRL_1 0x0551
283#define REG_MBID_NUM 0x0552
284#define REG_DUAL_TSF_RST 0x0553
285#define REG_BCN_INTERVAL 0x0554
286#define REG_DRVERLYINT 0x0558
287#define REG_BCNDMATIM 0x0559
288#define REG_ATIMWND 0x055A
289#define REG_BCN_MAX_ERR 0x055D
290#define REG_RXTSF_OFFSET_CCK 0x055E
291#define REG_RXTSF_OFFSET_OFDM 0x055F
292#define REG_TSFTR 0x0560
293#define REG_CTWND 0x0572
294#define REG_PSTIMER 0x0580
295#define REG_TIMER0 0x0584
296#define REG_TIMER1 0x0588
297#define REG_BCN_PREDL_ITV 0x058F
298#define REG_ACMHWCTRL 0x05C0
299
300/*-----------------------------------------------------
301 *
302 * 0x0600h ~ 0x07FFh WMAC Configuration
303 *
304 *-----------------------------------------------------
305 */
306#define REG_MAC_CR 0x0600
307#define REG_BWOPMODE 0x0603
308#define REG_TCR 0x0604
309#define REG_RCR 0x0608
310#define REG_RX_PKT_LIMIT 0x060C
311#define REG_RX_DLK_TIME 0x060D
312#define REG_RX_DRVINFO_SZ 0x060F
313
314#define REG_MACID 0x0610
315#define REG_BSSID 0x0618
316#define REG_MAR 0x0620
317#define REG_MBIDCAMCFG 0x0628
318
319#define REG_USTIME_EDCA 0x0638
320#define REG_MAC_SPEC_SIFS 0x063A
321#define REG_RESP_SIFS_CCK 0x063C
322#define REG_RESP_SIFS_OFDM 0x063E
323#define REG_ACKTO 0x0640
324#define REG_CTS2TO 0x0641
325#define REG_EIFS 0x0642
326
327#define REG_NAV_UPPER 0x0652
328
329/* Security*/
330#define REG_CAMCMD 0x0670
331#define REG_CAMWRITE 0x0674
332#define REG_CAMREAD 0x0678
333#define REG_CAMDBG 0x067C
334#define REG_SECCFG 0x0680
335
336/* Power*/
337#define REG_WOW_CTRL 0x0690
338#define REG_PS_RX_INFO 0x0692
339#define REG_UAPSD_TID 0x0693
340#define REG_WKFMCAM_NUM 0x0698
341#define REG_WKFMCAM_RWD 0x069C
342#define REG_RXFLTMAP0 0x06A0
343#define REG_RXFLTMAP1 0x06A2
344#define REG_RXFLTMAP2 0x06A4
345#define REG_BCN_PSR_RPT 0x06A8
346#define REG_BT_COEX_TABLE 0x06C0
347#define REG_BFMER0_INFO 0x06E4
348#define REG_BFMER1_INFO 0x06EC
349#define REG_CSI_RPT_PARAM_BW20 0x06F4
350#define REG_CSI_RPT_PARAM_BW40 0x06F8
351#define REG_CSI_RPT_PARAM_BW80 0x06FC
352/* Hardware Port 2*/
353#define REG_MACID1 0x0700
354#define REG_BSSID1 0x0708
355#define REG_BFMEE_SEL 0x0714
356#define REG_SND_PTCL_CTRL 0x0718
357
358#define CR9346 REG_9346CR
359#define MSR (REG_CR + 2)
360#define ISR REG_HISR
361#define TSFR REG_TSFTR
362
363#define MACIDR0 REG_MACID
364#define MACIDR4 (REG_MACID + 4)
365
366#define PBP REG_PBP
367
368#define IDR0 MACIDR0
369#define IDR4 MACIDR4
370
371#define UNUSED_REGISTER 0x1BF
372#define DCAM UNUSED_REGISTER
373#define PSR UNUSED_REGISTER
374#define BBADDR UNUSED_REGISTER
375#define PHYDATAR UNUSED_REGISTER
376
377#define INVALID_BBRF_VALUE 0x12345678
378
379#define MAX_MSS_DENSITY_2T 0x13
380#define MAX_MSS_DENSITY_1T 0x0A
381
382#define CMDEEPROM_EN BIT(5)
383#define CMDEEPROM_SEL BIT(4)
384#define CMD9346CR_9356SEL BIT(4)
385#define AUTOLOAD_EEPROM (CMDEEPROM_EN | CMDEEPROM_SEL)
386#define AUTOLOAD_EFUSE CMDEEPROM_EN
387
388#define GPIOSEL_GPIO 0
389#define GPIOSEL_ENBT BIT(5)
390
391#define GPIO_IN REG_GPIO_PIN_CTRL
392#define GPIO_OUT (REG_GPIO_PIN_CTRL + 1)
393#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL + 2)
394#define GPIO_MOD (REG_GPIO_PIN_CTRL + 3)
395
396#define MSR_NOLINK 0x00
397#define MSR_ADHOC 0x01
398#define MSR_INFRA 0x02
399#define MSR_AP 0x03
400
401#define RRSR_RSC_OFFSET 21
402#define RRSR_SHORT_OFFSET 23
403#define RRSR_RSC_BW_40M 0x600000
404#define RRSR_RSC_UPSUBCHNL 0x400000
405#define RRSR_RSC_LOWSUBCHNL 0x200000
406#define RRSR_SHORT 0x800000
407#define RRSR_1M BIT(0)
408#define RRSR_2M BIT(1)
409#define RRSR_5_5M BIT(2)
410#define RRSR_11M BIT(3)
411#define RRSR_6M BIT(4)
412#define RRSR_9M BIT(5)
413#define RRSR_12M BIT(6)
414#define RRSR_18M BIT(7)
415#define RRSR_24M BIT(8)
416#define RRSR_36M BIT(9)
417#define RRSR_48M BIT(10)
418#define RRSR_54M BIT(11)
419#define RRSR_MCS0 BIT(12)
420#define RRSR_MCS1 BIT(13)
421#define RRSR_MCS2 BIT(14)
422#define RRSR_MCS3 BIT(15)
423#define RRSR_MCS4 BIT(16)
424#define RRSR_MCS5 BIT(17)
425#define RRSR_MCS6 BIT(18)
426#define RRSR_MCS7 BIT(19)
427#define BRSR_ACKSHORTPMB BIT(23)
428
429#define RATR_1M 0x00000001
430#define RATR_2M 0x00000002
431#define RATR_55M 0x00000004
432#define RATR_11M 0x00000008
433#define RATR_6M 0x00000010
434#define RATR_9M 0x00000020
435#define RATR_12M 0x00000040
436#define RATR_18M 0x00000080
437#define RATR_24M 0x00000100
438#define RATR_36M 0x00000200
439#define RATR_48M 0x00000400
440#define RATR_54M 0x00000800
441#define RATR_MCS0 0x00001000
442#define RATR_MCS1 0x00002000
443#define RATR_MCS2 0x00004000
444#define RATR_MCS3 0x00008000
445#define RATR_MCS4 0x00010000
446#define RATR_MCS5 0x00020000
447#define RATR_MCS6 0x00040000
448#define RATR_MCS7 0x00080000
449#define RATR_MCS8 0x00100000
450#define RATR_MCS9 0x00200000
451#define RATR_MCS10 0x00400000
452#define RATR_MCS11 0x00800000
453#define RATR_MCS12 0x01000000
454#define RATR_MCS13 0x02000000
455#define RATR_MCS14 0x04000000
456#define RATR_MCS15 0x08000000
457
458#define RATE_1M BIT(0)
459#define RATE_2M BIT(1)
460#define RATE_5_5M BIT(2)
461#define RATE_11M BIT(3)
462#define RATE_6M BIT(4)
463#define RATE_9M BIT(5)
464#define RATE_12M BIT(6)
465#define RATE_18M BIT(7)
466#define RATE_24M BIT(8)
467#define RATE_36M BIT(9)
468#define RATE_48M BIT(10)
469#define RATE_54M BIT(11)
470#define RATE_MCS0 BIT(12)
471#define RATE_MCS1 BIT(13)
472#define RATE_MCS2 BIT(14)
473#define RATE_MCS3 BIT(15)
474#define RATE_MCS4 BIT(16)
475#define RATE_MCS5 BIT(17)
476#define RATE_MCS6 BIT(18)
477#define RATE_MCS7 BIT(19)
478#define RATE_MCS8 BIT(20)
479#define RATE_MCS9 BIT(21)
480#define RATE_MCS10 BIT(22)
481#define RATE_MCS11 BIT(23)
482#define RATE_MCS12 BIT(24)
483#define RATE_MCS13 BIT(25)
484#define RATE_MCS14 BIT(26)
485#define RATE_MCS15 BIT(27)
486
487#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
488#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\
489 RATR_24M | RATR_36M | RATR_48M | RATR_54M)
490#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\
491 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\
492 RATR_MCS6 | RATR_MCS7)
493#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\
494 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 |\
495 RATR_MCS14 | RATR_MCS15)
496
497#define BW_OPMODE_20MHZ BIT(2)
498#define BW_OPMODE_5G BIT(1)
499#define CAM_VALID BIT(15)
500#define CAM_NOTVALID 0x0000
501#define CAM_USEDK BIT(5)
502
503#define CAM_NONE 0x0
504#define CAM_WEP40 0x01
505#define CAM_TKIP 0x02
506#define CAM_AES 0x04
507#define CAM_WEP104 0x05
508
509#define TOTAL_CAM_ENTRY 32
510#define HALF_CAM_ENTRY 16
511
512#define CAM_WRITE BIT(16)
513#define CAM_READ 0x00000000
514#define CAM_POLLINIG BIT(31)
515
516#define SCR_USEDK 0x01
517#define SCR_TXSEC_ENABLE 0x02
518#define SCR_RXSEC_ENABLE 0x04
519
520/*********************************************
521* 8192EE IMR/ISR bits
522**********************************************/
523#define IMR_DISABLED 0x0
524/* IMR DW0(0x0060-0063) Bit 0-31 */
525#define IMR_TIMER2 BIT(31)
526#define IMR_TIMER1 BIT(30)
527#define IMR_PSTIMEOUT BIT(29)
528#define IMR_GTINT4 BIT(28)
529#define IMR_GTINT3 BIT(27)
530#define IMR_TBDER BIT(26)
531#define IMR_TBDOK BIT(25)
532#define IMR_TSF_BIT32_TOGGLE BIT(24)
533#define IMR_BCNDMAINT0 BIT(20)
534#define IMR_BCNDOK0 BIT(16)
535#define IMR_BCNDMAINT_E BIT(14)
536#define IMR_ATIMEND BIT(12)
537#define IMR_HISR1_IND_INT BIT(11)
538#define IMR_C2HCMD BIT(10)
539#define IMR_CPWM2 BIT(9)
540#define IMR_CPWM BIT(8)
541#define IMR_HIGHDOK BIT(7)
542#define IMR_MGNTDOK BIT(6)
543#define IMR_BKDOK BIT(5)
544#define IMR_BEDOK BIT(4)
545#define IMR_VIDOK BIT(3)
546#define IMR_VODOK BIT(2)
547#define IMR_RDU BIT(1)
548#define IMR_ROK BIT(0)
549
550/* IMR DW1(0x00B4-00B7) Bit 0-31 */
551#define IMR_MCUERR BIT(28)
552#define IMR_BCNDMAINT7 BIT(27)
553#define IMR_BCNDMAINT6 BIT(26)
554#define IMR_BCNDMAINT5 BIT(25)
555#define IMR_BCNDMAINT4 BIT(24)
556#define IMR_BCNDMAINT3 BIT(23)
557#define IMR_BCNDMAINT2 BIT(22)
558#define IMR_BCNDMAINT1 BIT(21)
559#define IMR_BCNDOK7 BIT(20)
560#define IMR_BCNDOK6 BIT(19)
561#define IMR_BCNDOK5 BIT(18)
562#define IMR_BCNDOK4 BIT(17)
563#define IMR_BCNDOK3 BIT(16)
564#define IMR_BCNDOK2 BIT(15)
565#define IMR_BCNDOK1 BIT(14)
566#define IMR_ATIMEND_E BIT(13)
567#define IMR_TXERR BIT(11)
568#define IMR_RXERR BIT(10)
569#define IMR_TXFOVW BIT(9)
570#define IMR_RXFOVW BIT(8)
571
572#define HWSET_MAX_SIZE 512
573#define EFUSE_MAX_SECTION 64
574#define EFUSE_REAL_CONTENT_LEN 256
575#define EFUSE_OOB_PROTECT_BYTES 18
576
577#define EEPROM_DEFAULT_TSSI 0x0
578#define EEPROM_DEFAULT_TXPOWERDIFF 0x0
579#define EEPROM_DEFAULT_CRYSTALCAP 0x5
580#define EEPROM_DEFAULT_BOARDTYPE 0x02
581#define EEPROM_DEFAULT_TXPOWER 0x1010
582#define EEPROM_DEFAULT_HT2T_TXPWR 0x10
583
584#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
585#define EEPROM_DEFAULT_THERMALMETER 0x1A
586#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0
587#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5
588#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22
589#define EEPROM_DEFAULT_HT40_2SDIFF 0x0
590#define EEPROM_DEFAULT_HT20_DIFF 2
591#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
592#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0
593#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0
594
595#define RF_OPTION1 0x79
596#define RF_OPTION2 0x7A
597#define RF_OPTION3 0x7B
598#define RF_OPTION4 0x7C
599
600#define EEPROM_DEFAULT_PID 0x1234
601#define EEPROM_DEFAULT_VID 0x5678
602#define EEPROM_DEFAULT_CUSTOMERID 0xAB
603#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD
604#define EEPROM_DEFAULT_VERSION 0
605
606#define EEPROM_CHANNEL_PLAN_FCC 0x0
607#define EEPROM_CHANNEL_PLAN_IC 0x1
608#define EEPROM_CHANNEL_PLAN_ETSI 0x2
609#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
610#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
611#define EEPROM_CHANNEL_PLAN_MKK 0x5
612#define EEPROM_CHANNEL_PLAN_MKK1 0x6
613#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
614#define EEPROM_CHANNEL_PLAN_TELEC 0x8
615#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
616#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
617#define EEPROM_CHANNEL_PLAN_NCC 0xB
618#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
619
620#define EEPROM_CID_DEFAULT 0x0
621#define EEPROM_CID_TOSHIBA 0x4
622#define EEPROM_CID_CCX 0x10
623#define EEPROM_CID_QMI 0x0D
624#define EEPROM_CID_WHQL 0xFE
625
626#define RTL8192E_EEPROM_ID 0x8129
627
628#define EEPROM_HPON 0x02
629#define EEPROM_CLK 0x06
630#define EEPROM_TESTR 0x08
631
632#define EEPROM_TXPOWERCCK 0x10
633#define EEPROM_TXPOWERHT40_1S 0x16
634#define EEPROM_TXPOWERHT20DIFF 0x1B
635#define EEPROM_TXPOWER_OFDMDIFF 0x1B
636
637#define EEPROM_TX_PWR_INX 0x10
638
639#define EEPROM_CHANNELPLAN 0xB8
640#define EEPROM_XTAL_92E 0xB9
641#define EEPROM_THERMAL_METER_92E 0xBA
642#define EEPROM_IQK_LCK_92E 0xBB
643
644#define EEPROM_RF_BOARD_OPTION_92E 0xC1
645#define EEPROM_RF_FEATURE_OPTION_92E 0xC2
646#define EEPROM_RF_BT_SETTING_92E 0xC3
647#define EEPROM_VERSION 0xC4
648#define EEPROM_CUSTOMER_ID 0xC5
649#define EEPROM_RF_ANTENNA_OPT_92E 0xC9
650
651#define EEPROM_MAC_ADDR 0xD0
652#define EEPROM_VID 0xD6
653#define EEPROM_DID 0xD8
654#define EEPROM_SVID 0xDA
655#define EEPROM_SMID 0xDC
656
657#define STOPBECON BIT(6)
658#define STOPHIGHT BIT(5)
659#define STOPMGT BIT(4)
660#define STOPVO BIT(3)
661#define STOPVI BIT(2)
662#define STOPBE BIT(1)
663#define STOPBK BIT(0)
664
665#define RCR_APPFCS BIT(31)
666#define RCR_APP_MIC BIT(30)
667#define RCR_APP_ICV BIT(29)
668#define RCR_APP_PHYST_RXFF BIT(28)
669#define RCR_APP_BA_SSN BIT(27)
670#define RCR_ENMBID BIT(24)
671#define RCR_LSIGEN BIT(23)
672#define RCR_MFBEN BIT(22)
673#define RCR_HTC_LOC_CTRL BIT(14)
674#define RCR_AMF BIT(13)
675#define RCR_ACF BIT(12)
676#define RCR_ADF BIT(11)
677#define RCR_AICV BIT(9)
678#define RCR_ACRC32 BIT(8)
679#define RCR_CBSSID_BCN BIT(7)
680#define RCR_CBSSID_DATA BIT(6)
681#define RCR_CBSSID RCR_CBSSID_DATA
682#define RCR_APWRMGT BIT(5)
683#define RCR_ADD3 BIT(4)
684#define RCR_AB BIT(3)
685#define RCR_AM BIT(2)
686#define RCR_APM BIT(1)
687#define RCR_AAP BIT(0)
688#define RCR_MXDMA_OFFSET 8
689#define RCR_FIFO_OFFSET 13
690
691#define RSV_CTRL 0x001C
692#define RD_CTRL 0x0524
693
694#define REG_USB_INFO 0xFE17
695#define REG_USB_SPECIAL_OPTION 0xFE55
696#define REG_USB_DMA_AGG_TO 0xFE5B
697#define REG_USB_AGG_TO 0xFE5C
698#define REG_USB_AGG_TH 0xFE5D
699
700#define REG_USB_VID 0xFE60
701#define REG_USB_PID 0xFE62
702#define REG_USB_OPTIONAL 0xFE64
703#define REG_USB_CHIRP_K 0xFE65
704#define REG_USB_PHY 0xFE66
705#define REG_USB_MAC_ADDR 0xFE70
706#define REG_USB_HRPWM 0xFE58
707#define REG_USB_HCPWM 0xFE57
708
709#define SW18_FPWM BIT(3)
710
711#define ISO_MD2PP BIT(0)
712#define ISO_UA2USB BIT(1)
713#define ISO_UD2CORE BIT(2)
714#define ISO_PA2PCIE BIT(3)
715#define ISO_PD2CORE BIT(4)
716#define ISO_IP2MAC BIT(5)
717#define ISO_DIOP BIT(6)
718#define ISO_DIOE BIT(7)
719#define ISO_EB2CORE BIT(8)
720#define ISO_DIOR BIT(9)
721
722#define PWC_EV25V BIT(14)
723#define PWC_EV12V BIT(15)
724
725#define FEN_BBRSTB BIT(0)
726#define FEN_BB_GLB_RSTN BIT(1)
727#define FEN_USBA BIT(2)
728#define FEN_UPLL BIT(3)
729#define FEN_USBD BIT(4)
730#define FEN_DIO_PCIE BIT(5)
731#define FEN_PCIEA BIT(6)
732#define FEN_PPLL BIT(7)
733#define FEN_PCIED BIT(8)
734#define FEN_DIOE BIT(9)
735#define FEN_CPUEN BIT(10)
736#define FEN_DCORE BIT(11)
737#define FEN_ELDR BIT(12)
738#define FEN_DIO_RF BIT(13)
739#define FEN_HWPDN BIT(14)
740#define FEN_MREGEN BIT(15)
741
742#define PFM_LDALL BIT(0)
743#define PFM_ALDN BIT(1)
744#define PFM_LDKP BIT(2)
745#define PFM_WOWL BIT(3)
746#define ENPDN BIT(4)
747#define PDN_PL BIT(5)
748#define APFM_ONMAC BIT(8)
749#define APFM_OFF BIT(9)
750#define APFM_RSM BIT(10)
751#define AFSM_HSUS BIT(11)
752#define AFSM_PCIE BIT(12)
753#define APDM_MAC BIT(13)
754#define APDM_HOST BIT(14)
755#define APDM_HPDN BIT(15)
756#define RDY_MACON BIT(16)
757#define SUS_HOST BIT(17)
758#define ROP_ALD BIT(20)
759#define ROP_PWR BIT(21)
760#define ROP_SPS BIT(22)
761#define SOP_MRST BIT(25)
762#define SOP_FUSE BIT(26)
763#define SOP_ABG BIT(27)
764#define SOP_AMB BIT(28)
765#define SOP_RCK BIT(29)
766#define SOP_A8M BIT(30)
767#define XOP_BTCK BIT(31)
768
769#define ANAD16V_EN BIT(0)
770#define ANA8M BIT(1)
771#define MACSLP BIT(4)
772#define LOADER_CLK_EN BIT(5)
773#define _80M_SSC_DIS BIT(7)
774#define _80M_SSC_EN_HO BIT(8)
775#define PHY_SSC_RSTB BIT(9)
776#define SEC_CLK_EN BIT(10)
777#define MAC_CLK_EN BIT(11)
778#define SYS_CLK_EN BIT(12)
779#define RING_CLK_EN BIT(13)
780
781#define BOOT_FROM_EEPROM BIT(4)
782#define EEPROM_EN BIT(5)
783
784#define AFE_BGEN BIT(0)
785#define AFE_MBEN BIT(1)
786#define MAC_ID_EN BIT(7)
787
788#define WLOCK_ALL BIT(0)
789#define WLOCK_00 BIT(1)
790#define WLOCK_04 BIT(2)
791#define WLOCK_08 BIT(3)
792#define WLOCK_40 BIT(4)
793#define R_DIS_PRST_0 BIT(5)
794#define R_DIS_PRST_1 BIT(6)
795#define LOCK_ALL_EN BIT(7)
796
797#define RF_EN BIT(0)
798#define RF_RSTB BIT(1)
799#define RF_SDMRSTB BIT(2)
800
801#define LDA15_EN BIT(0)
802#define LDA15_STBY BIT(1)
803#define LDA15_OBUF BIT(2)
804#define LDA15_REG_VOS BIT(3)
805#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
806
807#define LDV12_EN BIT(0)
808#define LDV12_SDBY BIT(1)
809#define LPLDO_HSM BIT(2)
810#define LPLDO_LSM_DIS BIT(3)
811#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
812
813#define XTAL_EN BIT(0)
814#define XTAL_BSEL BIT(1)
815#define _XTAL_BOSC(x) (((x) & 0x3) << 2)
816#define _XTAL_CADJ(x) (((x) & 0xF) << 4)
817#define XTAL_GATE_USB BIT(8)
818#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)
819#define XTAL_GATE_AFE BIT(11)
820#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)
821#define XTAL_RF_GATE BIT(14)
822#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)
823#define XTAL_GATE_DIG BIT(17)
824#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)
825#define XTAL_BT_GATE BIT(20)
826#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
827#define _XTAL_GPIO(x) (((x) & 0x7) << 23)
828
829#define CKDLY_AFE BIT(26)
830#define CKDLY_USB BIT(27)
831#define CKDLY_DIG BIT(28)
832#define CKDLY_BT BIT(29)
833
834#define APLL_EN BIT(0)
835#define APLL_320_EN BIT(1)
836#define APLL_FREF_SEL BIT(2)
837#define APLL_EDGE_SEL BIT(3)
838#define APLL_WDOGB BIT(4)
839#define APLL_LPFEN BIT(5)
840
841#define APLL_REF_CLK_13MHZ 0x1
842#define APLL_REF_CLK_19_2MHZ 0x2
843#define APLL_REF_CLK_20MHZ 0x3
844#define APLL_REF_CLK_25MHZ 0x4
845#define APLL_REF_CLK_26MHZ 0x5
846#define APLL_REF_CLK_38_4MHZ 0x6
847#define APLL_REF_CLK_40MHZ 0x7
848
849#define APLL_320EN BIT(14)
850#define APLL_80EN BIT(15)
851#define APLL_1MEN BIT(24)
852
853#define ALD_EN BIT(18)
854#define EF_PD BIT(19)
855#define EF_FLAG BIT(31)
856
857#define EF_TRPT BIT(7)
858#define LDOE25_EN BIT(31)
859
860#define RSM_EN BIT(0)
861#define TIMER_EN BIT(4)
862
863#define TRSW0EN BIT(2)
864#define TRSW1EN BIT(3)
865#define EROM_EN BIT(4)
866#define ENBT BIT(5)
867#define ENUART BIT(8)
868#define UART_910 BIT(9)
869#define ENPMAC BIT(10)
870#define SIC_SWRST BIT(11)
871#define ENSIC BIT(12)
872#define SIC_23 BIT(13)
873#define ENHDP BIT(14)
874#define SIC_LBK BIT(15)
875
876#define LED0PL BIT(4)
877#define LED1PL BIT(12)
878#define LED0DIS BIT(7)
879
880#define MCUFWDL_EN BIT(0)
881#define MCUFWDL_RDY BIT(1)
882#define FWDL_CHKSUM_RPT BIT(2)
883#define MACINI_RDY BIT(3)
884#define BBINI_RDY BIT(4)
885#define RFINI_RDY BIT(5)
886#define WINTINI_RDY BIT(6)
887#define CPRST BIT(23)
888
889#define XCLK_VLD BIT(0)
890#define ACLK_VLD BIT(1)
891#define UCLK_VLD BIT(2)
892#define PCLK_VLD BIT(3)
893#define PCIRSTB BIT(4)
894#define V15_VLD BIT(5)
895#define TRP_B15V_EN BIT(7)
896#define SIC_IDLE BIT(8)
897#define BD_MAC2 BIT(9)
898#define BD_MAC1 BIT(10)
899#define IC_MACPHY_MODE BIT(11)
900#define VENDOR_ID BIT(19)
901#define PAD_HWPD_IDN BIT(22)
902#define TRP_VAUX_EN BIT(23)
903#define TRP_BT_EN BIT(24)
904#define BD_PKG_SEL BIT(25)
905#define BD_HCI_SEL BIT(26)
906#define TYPE_ID BIT(27)
907
908#define CHIP_VER_RTL_MASK 0xF000
909#define CHIP_VER_RTL_SHIFT 12
910
911#define REG_LBMODE (REG_CR + 3)
912
913#define HCI_TXDMA_EN BIT(0)
914#define HCI_RXDMA_EN BIT(1)
915#define TXDMA_EN BIT(2)
916#define RXDMA_EN BIT(3)
917#define PROTOCOL_EN BIT(4)
918#define SCHEDULE_EN BIT(5)
919#define MACTXEN BIT(6)
920#define MACRXEN BIT(7)
921#define ENSWBCN BIT(8)
922#define ENSEC BIT(9)
923
924#define _NETTYPE(x) (((x) & 0x3) << 16)
925#define MASK_NETTYPE 0x30000
926#define NT_NO_LINK 0x0
927#define NT_LINK_AD_HOC 0x1
928#define NT_LINK_AP 0x2
929#define NT_AS_AP 0x3
930
931#define _LBMODE(x) (((x) & 0xF) << 24)
932#define MASK_LBMODE 0xF000000
933#define LOOPBACK_NORMAL 0x0
934#define LOOPBACK_IMMEDIATELY 0xB
935#define LOOPBACK_MAC_DELAY 0x3
936#define LOOPBACK_PHY 0x1
937#define LOOPBACK_DMA 0x7
938
939#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
940#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
941#define _PSRX_MASK 0xF
942#define _PSTX_MASK 0xF0
943#define _PSRX(x) (x)
944#define _PSTX(x) ((x) << 4)
945
946#define PBP_64 0x0
947#define PBP_128 0x1
948#define PBP_256 0x2
949#define PBP_512 0x3
950#define PBP_1024 0x4
951
952#define RXDMA_ARBBW_EN BIT(0)
953#define RXSHFT_EN BIT(1)
954#define RXDMA_AGG_EN BIT(2)
955#define QS_VO_QUEUE BIT(8)
956#define QS_VI_QUEUE BIT(9)
957#define QS_BE_QUEUE BIT(10)
958#define QS_BK_QUEUE BIT(11)
959#define QS_MANAGER_QUEUE BIT(12)
960#define QS_HIGH_QUEUE BIT(13)
961
962#define HQSEL_VOQ BIT(0)
963#define HQSEL_VIQ BIT(1)
964#define HQSEL_BEQ BIT(2)
965#define HQSEL_BKQ BIT(3)
966#define HQSEL_MGTQ BIT(4)
967#define HQSEL_HIQ BIT(5)
968
969#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
970#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
971#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
972#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8)
973#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6)
974#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4)
975
976#define QUEUE_LOW 1
977#define QUEUE_NORMAL 2
978#define QUEUE_HIGH 3
979
980#define _LLT_NO_ACTIVE 0x0
981#define _LLT_WRITE_ACCESS 0x1
982#define _LLT_READ_ACCESS 0x2
983
984#define _LLT_INIT_DATA(x) ((x) & 0xFF)
985#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
986#define _LLT_OP(x) (((x) & 0x3) << 30)
987#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
988
989#define BB_WRITE_READ_MASK (BIT(31) | BIT(30))
990#define BB_WRITE_EN BIT(30)
991#define BB_READ_EN BIT(31)
992
993#define _HPQ(x) ((x) & 0xFF)
994#define _LPQ(x) (((x) & 0xFF) << 8)
995#define _PUBQ(x) (((x) & 0xFF) << 16)
996#define _NPQ(x) ((x) & 0xFF)
997
998#define HPQ_PUBLIC_DIS BIT(24)
999#define LPQ_PUBLIC_DIS BIT(25)
1000#define LD_RQPN BIT(31)
1001
1002#define BCN_VALID BIT(16)
1003#define BCN_HEAD(x) (((x) & 0xFF) << 8)
1004#define BCN_HEAD_MASK 0xFF00
1005
1006#define BLK_DESC_NUM_SHIFT 4
1007#define BLK_DESC_NUM_MASK 0xF
1008
1009#define DROP_DATA_EN BIT(9)
1010
1011#define EN_AMPDU_RTY_NEW BIT(7)
1012
1013#define _INIRTSMCS_SEL(x) ((x) & 0x3F)
1014
1015#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
1016#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
1017
1018#define RATE_REG_BITMAP_ALL 0xFFFFF
1019
1020#define _RRSC_BITMAP(x) ((x) & 0xFFFFF)
1021
1022#define _RRSR_RSC(x) (((x) & 0x3) << 21)
1023#define RRSR_RSC_RESERVED 0x0
1024#define RRSR_RSC_UPPER_SUBCHANNEL 0x1
1025#define RRSR_RSC_LOWER_SUBCHANNEL 0x2
1026#define RRSR_RSC_DUPLICATE_MODE 0x3
1027
1028#define USE_SHORT_G1 BIT(20)
1029
1030#define _AGGLMT_MCS0(x) ((x) & 0xF)
1031#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)
1032#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)
1033#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)
1034#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)
1035#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)
1036#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)
1037#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)
1038
1039#define RETRY_LIMIT_SHORT_SHIFT 8
1040#define RETRY_LIMIT_LONG_SHIFT 0
1041
1042#define _DARF_RC1(x) ((x) & 0x1F)
1043#define _DARF_RC2(x) (((x) & 0x1F) << 8)
1044#define _DARF_RC3(x) (((x) & 0x1F) << 16)
1045#define _DARF_RC4(x) (((x) & 0x1F) << 24)
1046#define _DARF_RC5(x) ((x) & 0x1F)
1047#define _DARF_RC6(x) (((x) & 0x1F) << 8)
1048#define _DARF_RC7(x) (((x) & 0x1F) << 16)
1049#define _DARF_RC8(x) (((x) & 0x1F) << 24)
1050
1051#define _RARF_RC1(x) ((x) & 0x1F)
1052#define _RARF_RC2(x) (((x) & 0x1F) << 8)
1053#define _RARF_RC3(x) (((x) & 0x1F) << 16)
1054#define _RARF_RC4(x) (((x) & 0x1F) << 24)
1055#define _RARF_RC5(x) ((x) & 0x1F)
1056#define _RARF_RC6(x) (((x) & 0x1F) << 8)
1057#define _RARF_RC7(x) (((x) & 0x1F) << 16)
1058#define _RARF_RC8(x) (((x) & 0x1F) << 24)
1059
1060#define AC_PARAM_TXOP_LIMIT_OFFSET 16
1061#define AC_PARAM_ECW_MAX_OFFSET 12
1062#define AC_PARAM_ECW_MIN_OFFSET 8
1063#define AC_PARAM_AIFS_OFFSET 0
1064
1065#define _AIFS(x) (x)
1066#define _ECW_MAX_MIN(x) ((x) << 8)
1067#define _TXOP_LIMIT(x) ((x) << 16)
1068
1069#define _BCNIFS(x) ((x) & 0xFF)
1070#define _BCNECW(x) ((((x) & 0xF)) << 8)
1071
1072#define _LRL(x) ((x) & 0x3F)
1073#define _SRL(x) (((x) & 0x3F) << 8)
1074
1075#define _SIFS_CCK_CTX(x) ((x) & 0xFF)
1076#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8)
1077
1078#define _SIFS_OFDM_CTX(x) ((x) & 0xFF)
1079#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8)
1080
1081#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)
1082
1083#define DIS_EDCA_CNT_DWN BIT(11)
1084
1085#define EN_MBSSID BIT(1)
1086#define EN_TXBCN_RPT BIT(2)
1087#define EN_BCN_FUNCTION BIT(3)
1088
1089#define TSFTR_RST BIT(0)
1090#define TSFTR1_RST BIT(1)
1091
1092#define STOP_BCNQ BIT(6)
1093
1094#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
1095#define DIS_TSF_UDT0_TEST_CHIP BIT(5)
1096
1097#define ACMHW_HWEN BIT(0)
1098#define ACMHW_BEQEN BIT(1)
1099#define ACMHW_VIQEN BIT(2)
1100#define ACMHW_VOQEN BIT(3)
1101#define ACMHW_BEQSTATUS BIT(4)
1102#define ACMHW_VIQSTATUS BIT(5)
1103#define ACMHW_VOQSTATUS BIT(6)
1104
1105#define APSDOFF BIT(6)
1106#define APSDOFF_STATUS BIT(7)
1107
1108#define BW_20MHZ BIT(2)
1109
1110#define RATE_BITMAP_ALL 0xFFFFF
1111
1112#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
1113
1114#define TSFRST BIT(0)
1115#define DIS_GCLK BIT(1)
1116#define PAD_SEL BIT(2)
1117#define PWR_ST BIT(6)
1118#define PWRBIT_OW_EN BIT(7)
1119#define ACRC BIT(8)
1120#define CFENDFORM BIT(9)
1121#define ICV BIT(10)
1122
1123#define AAP BIT(0)
1124#define APM BIT(1)
1125#define AM BIT(2)
1126#define AB BIT(3)
1127#define ADD3 BIT(4)
1128#define APWRMGT BIT(5)
1129#define CBSSID BIT(6)
1130#define CBSSID_DATA BIT(6)
1131#define CBSSID_BCN BIT(7)
1132#define ACRC32 BIT(8)
1133#define AICV BIT(9)
1134#define ADF BIT(11)
1135#define ACF BIT(12)
1136#define AMF BIT(13)
1137#define HTC_LOC_CTRL BIT(14)
1138#define UC_DATA_EN BIT(16)
1139#define BM_DATA_EN BIT(17)
1140#define MFBEN BIT(22)
1141#define LSIGEN BIT(23)
1142#define ENMBID BIT(24)
1143#define APP_BASSN BIT(27)
1144#define APP_PHYSTS BIT(28)
1145#define APP_ICV BIT(29)
1146#define APP_MIC BIT(30)
1147#define APP_FCS BIT(31)
1148
1149#define _MIN_SPACE(x) ((x) & 0x7)
1150#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)
1151
1152#define RXERR_TYPE_OFDM_PPDU 0
1153#define RXERR_TYPE_OFDM_FALSE_ALARM 1
1154#define RXERR_TYPE_OFDM_MPDU_OK 2
1155#define RXERR_TYPE_OFDM_MPDU_FAIL 3
1156#define RXERR_TYPE_CCK_PPDU 4
1157#define RXERR_TYPE_CCK_FALSE_ALARM 5
1158#define RXERR_TYPE_CCK_MPDU_OK 6
1159#define RXERR_TYPE_CCK_MPDU_FAIL 7
1160#define RXERR_TYPE_HT_PPDU 8
1161#define RXERR_TYPE_HT_FALSE_ALARM 9
1162#define RXERR_TYPE_HT_MPDU_TOTAL 10
1163#define RXERR_TYPE_HT_MPDU_OK 11
1164#define RXERR_TYPE_HT_MPDU_FAIL 12
1165#define RXERR_TYPE_RX_FULL_DROP 15
1166
1167#define RXERR_COUNTER_MASK 0xFFFFF
1168#define RXERR_RPT_RST BIT(27)
1169#define _RXERR_RPT_SEL(type) ((type) << 28)
1170
1171#define SCR_TXUSEDK BIT(0)
1172#define SCR_RXUSEDK BIT(1)
1173#define SCR_TXENCENABLE BIT(2)
1174#define SCR_RXDECENABLE BIT(3)
1175#define SCR_SKBYA2 BIT(4)
1176#define SCR_NOSKMC BIT(5)
1177#define SCR_TXBCUSEDK BIT(6)
1178#define SCR_RXBCUSEDK BIT(7)
1179
1180#define USB_IS_HIGH_SPEED 0
1181#define USB_IS_FULL_SPEED 1
1182#define USB_SPEED_MASK BIT(5)
1183
1184#define USB_NORMAL_SIE_EP_MASK 0xF
1185#define USB_NORMAL_SIE_EP_SHIFT 4
1186
1187#define USB_TEST_EP_MASK 0x30
1188#define USB_TEST_EP_SHIFT 4
1189
1190#define USB_AGG_EN BIT(3)
1191
1192#define MAC_ADDR_LEN 6
1193#define LAST_ENTRY_OF_TX_PKT_BUFFER 175
1194
1195#define POLLING_LLT_THRESHOLD 20
1196#define POLLING_READY_TIMEOUT_COUNT 3000
1197
1198#define MAX_MSS_DENSITY_2T 0x13
1199#define MAX_MSS_DENSITY_1T 0x0A
1200
1201#define EPROM_CMD_OPERATING_MODE_MASK ((1 << 7) | (1 << 6))
1202#define EPROM_CMD_CONFIG 0x3
1203#define EPROM_CMD_LOAD 1
1204
1205#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE
1206
1207#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
1208
1209#define RPMAC_RESET 0x100
1210#define RPMAC_TXSTART 0x104
1211#define RPMAC_TXLEGACYSIG 0x108
1212#define RPMAC_TXHTSIG1 0x10c
1213#define RPMAC_TXHTSIG2 0x110
1214#define RPMAC_PHYDEBUG 0x114
1215#define RPMAC_TXPACKETNUM 0x118
1216#define RPMAC_TXIDLE 0x11c
1217#define RPMAC_TXMACHEADER0 0x120
1218#define RPMAC_TXMACHEADER1 0x124
1219#define RPMAC_TXMACHEADER2 0x128
1220#define RPMAC_TXMACHEADER3 0x12c
1221#define RPMAC_TXMACHEADER4 0x130
1222#define RPMAC_TXMACHEADER5 0x134
1223#define RPMAC_TXDADATYPE 0x138
1224#define RPMAC_TXRANDOMSEED 0x13c
1225#define RPMAC_CCKPLCPPREAMBLE 0x140
1226#define RPMAC_CCKPLCPHEADER 0x144
1227#define RPMAC_CCKCRC16 0x148
1228#define RPMAC_OFDMRXCRC32OK 0x170
1229#define RPMAC_OFDMRXCRC32ER 0x174
1230#define RPMAC_OFDMRXPARITYER 0x178
1231#define RPMAC_OFDMRXCRC8ER 0x17c
1232#define RPMAC_CCKCRXRC16ER 0x180
1233#define RPMAC_CCKCRXRC32ER 0x184
1234#define RPMAC_CCKCRXRC32OK 0x188
1235#define RPMAC_TXSTATUS 0x18c
1236
1237#define RFPGA0_RFMOD 0x800
1238
1239#define RFPGA0_TXINFO 0x804
1240#define RFPGA0_PSDFUNCTION 0x808
1241
1242#define RFPGA0_TXGAINSTAGE 0x80c
1243
1244#define RFPGA0_RFTIMING1 0x810
1245#define RFPGA0_RFTIMING2 0x814
1246
1247#define RFPGA0_XA_HSSIPARAMETER1 0x820
1248#define RFPGA0_XA_HSSIPARAMETER2 0x824
1249#define RFPGA0_XB_HSSIPARAMETER1 0x828
1250#define RFPGA0_XB_HSSIPARAMETER2 0x82c
1251
1252#define RFPGA0_XA_LSSIPARAMETER 0x840
1253#define RFPGA0_XB_LSSIPARAMETER 0x844
1254
1255#define RFPGA0_RFWAKEUPPARAMETER 0x850
1256#define RFPGA0_RFSLEEPUPPARAMETER 0x854
1257
1258#define RFPGA0_XAB_SWITCHCONTROL 0x858
1259#define RFPGA0_XCD_SWITCHCONTROL 0x85c
1260
1261#define RFPGA0_XA_RFINTERFACEOE 0x860
1262#define RFPGA0_XB_RFINTERFACEOE 0x864
1263
1264#define RFPGA0_XAB_RFINTERFACESW 0x870
1265#define RFPGA0_XCD_RFINTERFACESW 0x874
1266
1267#define RFPGA0_XAB_RFPARAMETER 0x878
1268#define RFPGA0_XCD_RFPARAMETER 0x87c
1269
1270#define RFPGA0_ANALOGPARAMETER1 0x880
1271#define RFPGA0_ANALOGPARAMETER2 0x884
1272#define RFPGA0_ANALOGPARAMETER3 0x888
1273#define RFPGA0_ANALOGPARAMETER4 0x88c
1274
1275#define RFPGA0_XA_LSSIREADBACK 0x8a0
1276#define RFPGA0_XB_LSSIREADBACK 0x8a4
1277#define RFPGA0_XC_LSSIREADBACK 0x8a8
1278#define RFPGA0_XD_LSSIREADBACK 0x8ac
1279
1280#define RFPGA0_PSDREPORT 0x8b4
1281#define TRANSCEIVEA_HSPI_READBACK 0x8b8
1282#define TRANSCEIVEB_HSPI_READBACK 0x8bc
1283#define REG_SC_CNT 0x8c4
1284#define RFPGA0_XAB_RFINTERFACERB 0x8e0
1285#define RFPGA0_XCD_RFINTERFACERB 0x8e4
1286
1287#define RFPGA1_RFMOD 0x900
1288
1289#define RFPGA1_TXBLOCK 0x904
1290#define RFPGA1_DEBUGSELECT 0x908
1291#define RFPGA1_TXINFO 0x90c
1292
1293#define RCCK0_SYSTEM 0xa00
1294
1295#define RCCK0_AFESETTING 0xa04
1296#define RCCK0_CCA 0xa08
1297
1298#define RCCK0_RXAGC1 0xa0c
1299#define RCCK0_RXAGC2 0xa10
1300
1301#define RCCK0_RXHP 0xa14
1302
1303#define RCCK0_DSPPARAMETER1 0xa18
1304#define RCCK0_DSPPARAMETER2 0xa1c
1305
1306#define RCCK0_TXFILTER1 0xa20
1307#define RCCK0_TXFILTER2 0xa24
1308#define RCCK0_DEBUGPORT 0xa28
1309#define RCCK0_FALSEALARMREPORT 0xa2c
1310#define RCCK0_TRSSIREPORT 0xa50
1311#define RCCK0_RXREPORT 0xa54
1312#define RCCK0_FACOUNTERLOWER 0xa5c
1313#define RCCK0_FACOUNTERUPPER 0xa58
1314#define RCCK0_CCA_CNT 0xa60
1315
1316/* PageB(0xB00) */
1317#define RPDP_ANTA 0xb00
1318#define RPDP_ANTA_4 0xb04
1319#define RPDP_ANTA_8 0xb08
1320#define RPDP_ANTA_C 0xb0c
1321#define RPDP_ANTA_10 0xb10
1322#define RPDP_ANTA_14 0xb14
1323#define RPDP_ANTA_18 0xb18
1324#define RPDP_ANTA_1C 0xb1c
1325#define RPDP_ANTA_20 0xb20
1326#define RPDP_ANTA_24 0xb24
1327
1328#define RCONFIG_PMPD_ANTA 0xb28
1329#define RCONFIG_RAM64x16 0xb2c
1330
1331#define RBNDA 0xb30
1332#define RHSSIPAR 0xb34
1333
1334#define RCONFIG_ANTA 0xb68
1335#define RCONFIG_ANTB 0xb6c
1336
1337#define RPDP_ANTB 0xb70
1338#define RPDP_ANTB_4 0xb74
1339#define RPDP_ANTB_8 0xb78
1340#define RPDP_ANTB_C 0xb7c
1341#define RPDP_ANTB_10 0xb80
1342#define RPDP_ANTB_14 0xb84
1343#define RPDP_ANTB_18 0xb88
1344#define RPDP_ANTB_1C 0xb8c
1345#define RPDP_ANTB_20 0xb90
1346#define RPDP_ANTB_24 0xb94
1347
1348#define RCONFIG_PMPD_ANTB 0xb98
1349
1350#define RBNDB 0xba0
1351
1352#define RAPK 0xbd8
1353#define RPM_RX0_ANTA 0xbdc
1354#define RPM_RX1_ANTA 0xbe0
1355#define RPM_RX2_ANTA 0xbe4
1356#define RPM_RX3_ANTA 0xbe8
1357#define RPM_RX0_ANTB 0xbec
1358#define RPM_RX1_ANTB 0xbf0
1359#define RPM_RX2_ANTB 0xbf4
1360#define RPM_RX3_ANTB 0xbf8
1361
1362/*Page C*/
1363#define ROFDM0_LSTF 0xc00
1364
1365#define ROFDM0_TRXPATHENABLE 0xc04
1366#define ROFDM0_TRMUXPAR 0xc08
1367#define ROFDM0_TRSWISOLATION 0xc0c
1368
1369#define ROFDM0_XARXAFE 0xc10
1370#define ROFDM0_XARXIQIMBALANCE 0xc14
1371#define ROFDM0_XBRXAFE 0xc18
1372#define ROFDM0_XBRXIQIMBALANCE 0xc1c
1373#define ROFDM0_XCRXAFE 0xc20
1374#define ROFDM0_XCRXIQIMBANLANCE 0xc24
1375#define ROFDM0_XDRXAFE 0xc28
1376#define ROFDM0_XDRXIQIMBALANCE 0xc2c
1377
1378#define ROFDM0_RXDETECTOR1 0xc30
1379#define ROFDM0_RXDETECTOR2 0xc34
1380#define ROFDM0_RXDETECTOR3 0xc38
1381#define ROFDM0_RXDETECTOR4 0xc3c
1382
1383#define ROFDM0_RXDSP 0xc40
1384#define ROFDM0_CFOANDDAGC 0xc44
1385#define ROFDM0_CCADROPTHRESHOLD 0xc48
1386#define ROFDM0_ECCATHRESHOLD 0xc4c
1387
1388#define ROFDM0_XAAGCCORE1 0xc50
1389#define ROFDM0_XAAGCCORE2 0xc54
1390#define ROFDM0_XBAGCCORE1 0xc58
1391#define ROFDM0_XBAGCCORE2 0xc5c
1392#define ROFDM0_XCAGCCORE1 0xc60
1393#define ROFDM0_XCAGCCORE2 0xc64
1394#define ROFDM0_XDAGCCORE1 0xc68
1395#define ROFDM0_XDAGCCORE2 0xc6c
1396
1397#define ROFDM0_AGCPARAMETER1 0xc70
1398#define ROFDM0_AGCPARAMETER2 0xc74
1399#define ROFDM0_AGCRSSITABLE 0xc78
1400#define ROFDM0_HTSTFAGC 0xc7c
1401
1402#define ROFDM0_XATXIQIMBALANCE 0xc80
1403#define ROFDM0_XATXAFE 0xc84
1404#define ROFDM0_XBTXIQIMBALANCE 0xc88
1405#define ROFDM0_XBTXAFE 0xc8c
1406#define ROFDM0_XCTXIQIMBALANCE 0xc90
1407#define ROFDM0_XCTXAFE 0xc94
1408#define ROFDM0_XDTXIQIMBALANCE 0xc98
1409#define ROFDM0_XDTXAFE 0xc9c
1410
1411#define ROFDM0_RXIQEXTANTA 0xca0
1412#define ROFDM0_TXCOEFF1 0xca4
1413#define ROFDM0_TXCOEFF2 0xca8
1414#define ROFDM0_TXCOEFF3 0xcac
1415#define ROFDM0_TXCOEFF4 0xcb0
1416#define ROFDM0_TXCOEFF5 0xcb4
1417#define ROFDM0_TXCOEFF6 0xcb8
1418
1419#define ROFDM0_RXHPPARAMETER 0xce0
1420#define ROFDM0_TXPSEUDONOISEWGT 0xce4
1421#define ROFDM0_FRAMESYNC 0xcf0
1422#define ROFDM0_DFSREPORT 0xcf4
1423
1424#define ROFDM1_LSTF 0xd00
1425#define ROFDM1_TRXPATHENABLE 0xd04
1426
1427#define ROFDM1_CF0 0xd08
1428#define ROFDM1_CSI1 0xd10
1429#define ROFDM1_SBD 0xd14
1430#define ROFDM1_CSI2 0xd18
1431#define ROFDM1_CFOTRACKING 0xd2c
1432#define ROFDM1_TRXMESAURE1 0xd34
1433#define ROFDM1_INTFDET 0xd3c
1434#define ROFDM1_PSEUDONOISESTATEAB 0xd50
1435#define ROFDM1_PSEUDONOISESTATECD 0xd54
1436#define ROFDM1_RXPSEUDONOISEWGT 0xd58
1437
1438#define ROFDM_PHYCOUNTER1 0xda0
1439#define ROFDM_PHYCOUNTER2 0xda4
1440#define ROFDM_PHYCOUNTER3 0xda8
1441
1442#define ROFDM_SHORTCFOAB 0xdac
1443#define ROFDM_SHORTCFOCD 0xdb0
1444#define ROFDM_LONGCFOAB 0xdb4
1445#define ROFDM_LONGCFOCD 0xdb8
1446#define ROFDM_TAILCF0AB 0xdbc
1447#define ROFDM_TAILCF0CD 0xdc0
1448#define ROFDM_PWMEASURE1 0xdc4
1449#define ROFDM_PWMEASURE2 0xdc8
1450#define ROFDM_BWREPORT 0xdcc
1451#define ROFDM_AGCREPORT 0xdd0
1452#define ROFDM_RXSNR 0xdd4
1453#define ROFDM_RXEVMCSI 0xdd8
1454#define ROFDM_SIGREPORT 0xddc
1455
1456#define RTXAGC_A_RATE18_06 0xe00
1457#define RTXAGC_A_RATE54_24 0xe04
1458#define RTXAGC_A_CCK1_MCS32 0xe08
1459#define RTXAGC_A_MCS03_MCS00 0xe10
1460#define RTXAGC_A_MCS07_MCS04 0xe14
1461#define RTXAGC_A_MCS11_MCS08 0xe18
1462#define RTXAGC_A_MCS15_MCS12 0xe1c
1463
1464#define RTXAGC_B_RATE18_06 0x830
1465#define RTXAGC_B_RATE54_24 0x834
1466#define RTXAGC_B_CCK1_55_MCS32 0x838
1467#define RTXAGC_B_MCS03_MCS00 0x83c
1468#define RTXAGC_B_MCS07_MCS04 0x848
1469#define RTXAGC_B_MCS11_MCS08 0x84c
1470#define RTXAGC_B_MCS15_MCS12 0x868
1471#define RTXAGC_B_CCK11_A_CCK2_11 0x86c
1472
1473#define RFPGA0_IQK 0xe28
1474#define RTX_IQK_TONE_A 0xe30
1475#define RRX_IQK_TONE_A 0xe34
1476#define RTX_IQK_PI_A 0xe38
1477#define RRX_IQK_PI_A 0xe3c
1478
1479#define RTX_IQK 0xe40
1480#define RRX_IQK 0xe44
1481#define RIQK_AGC_PTS 0xe48
1482#define RIQK_AGC_RSP 0xe4c
1483#define RTX_IQK_TONE_B 0xe50
1484#define RRX_IQK_TONE_B 0xe54
1485#define RTX_IQK_PI_B 0xe58
1486#define RRX_IQK_PI_B 0xe5c
1487#define RIQK_AGC_CONT 0xe60
1488
1489#define RBLUE_TOOTH 0xe6c
1490#define RRX_WAIT_CCA 0xe70
1491#define RTX_CCK_RFON 0xe74
1492#define RTX_CCK_BBON 0xe78
1493#define RTX_OFDM_RFON 0xe7c
1494#define RTX_OFDM_BBON 0xe80
1495#define RTX_TO_RX 0xe84
1496#define RTX_TO_TX 0xe88
1497#define RRX_CCK 0xe8c
1498
1499#define RTX_POWER_BEFORE_IQK_A 0xe94
1500#define RTX_POWER_AFTER_IQK_A 0xe9c
1501
1502#define RRX_POWER_BEFORE_IQK_A 0xea0
1503#define RRX_POWER_BEFORE_IQK_A_2 0xea4
1504#define RRX_POWER_AFTER_IQK_A 0xea8
1505#define RRX_POWER_AFTER_IQK_A_2 0xeac
1506
1507#define RTX_POWER_BEFORE_IQK_B 0xeb4
1508#define RTX_POWER_AFTER_IQK_B 0xebc
1509
1510#define RRX_POWER_BEFORE_IQK_B 0xec0
1511#define RRX_POWER_BEFORE_IQK_B_2 0xec4
1512#define RRX_POWER_AFTER_IQK_B 0xec8
1513#define RRX_POWER_AFTER_IQK_B_2 0xecc
1514
1515#define RRX_OFDM 0xed0
1516#define RRX_WAIT_RIFS 0xed4
1517#define RRX_TO_RX 0xed8
1518#define RSTANDBY 0xedc
1519#define RSLEEP 0xee0
1520#define RPMPD_ANAEN 0xeec
1521
1522#define RZEBRA1_HSSIENABLE 0x0
1523#define RZEBRA1_TRXENABLE1 0x1
1524#define RZEBRA1_TRXENABLE2 0x2
1525#define RZEBRA1_AGC 0x4
1526#define RZEBRA1_CHARGEPUMP 0x5
1527#define RZEBRA1_CHANNEL 0x7
1528
1529#define RZEBRA1_TXGAIN 0x8
1530#define RZEBRA1_TXLPF 0x9
1531#define RZEBRA1_RXLPF 0xb
1532#define RZEBRA1_RXHPFCORNER 0xc
1533
1534#define RGLOBALCTRL 0
1535#define RRTL8256_TXLPF 19
1536#define RRTL8256_RXLPF 11
1537#define RRTL8258_TXLPF 0x11
1538#define RRTL8258_RXLPF 0x13
1539#define RRTL8258_RSSILPF 0xa
1540
1541#define RF_AC 0x00
1542
1543#define RF_IQADJ_G1 0x01
1544#define RF_IQADJ_G2 0x02
1545#define RF_POW_TRSW 0x05
1546
1547#define RF_GAIN_RX 0x06
1548#define RF_GAIN_TX 0x07
1549
1550#define RF_TXM_IDAC 0x08
1551#define RF_BS_IQGEN 0x0F
1552
1553#define RF_MODE1 0x10
1554#define RF_MODE2 0x11
1555
1556#define RF_RX_AGC_HP 0x12
1557#define RF_TX_AGC 0x13
1558#define RF_BIAS 0x14
1559#define RF_IPA 0x15
1560#define RF_POW_ABILITY 0x17
1561#define RF_MODE_AG 0x18
1562#define RRFCHANNEL 0x18
1563#define RF_CHNLBW 0x18
1564#define RF_TOP 0x19
1565
1566#define RF_RX_G1 0x1A
1567#define RF_RX_G2 0x1B
1568
1569#define RF_RX_BB2 0x1C
1570#define RF_RX_BB1 0x1D
1571
1572#define RF_RCK1 0x1E
1573#define RF_RCK2 0x1F
1574
1575#define RF_TX_G1 0x20
1576#define RF_TX_G2 0x21
1577#define RF_TX_G3 0x22
1578
1579#define RF_TX_BB1 0x23
1580#define RF_T_METER 0x42
1581
1582#define RF_SYN_G1 0x25
1583#define RF_SYN_G2 0x26
1584#define RF_SYN_G3 0x27
1585#define RF_SYN_G4 0x28
1586#define RF_SYN_G5 0x29
1587#define RF_SYN_G6 0x2A
1588#define RF_SYN_G7 0x2B
1589#define RF_SYN_G8 0x2C
1590
1591#define RF_RCK_OS 0x30
1592#define RF_TXPA_G1 0x31
1593#define RF_TXPA_G2 0x32
1594#define RF_TXPA_G3 0x33
1595
1596#define RF_TX_BIAS_A 0x35
1597#define RF_TX_BIAS_D 0x36
1598#define RF_LOBF_9 0x38
1599#define RF_RXRF_A3 0x3C
1600#define RF_TRSW 0x3F
1601
1602#define RF_TXRF_A2 0x41
1603#define RF_TXPA_G4 0x46
1604#define RF_TXPA_A4 0x4B
1605
1606#define RF_WE_LUT 0xEF
1607
1608#define BBBRESETB 0x100
1609#define BGLOBALRESETB 0x200
1610#define BOFDMTXSTART 0x4
1611#define BCCKTXSTART 0x8
1612#define BCRC32DEBUG 0x100
1613#define BPMACLOOPBACK 0x10
1614#define BTXLSIG 0xffffff
1615#define BOFDMTXRATE 0xf
1616#define BOFDMTXRESERVED 0x10
1617#define BOFDMTXLENGTH 0x1ffe0
1618#define BOFDMTXPARITY 0x20000
1619#define BTXHTSIG1 0xffffff
1620#define BTXHTMCSRATE 0x7f
1621#define BTXHTBW 0x80
1622#define BTXHTLENGTH 0xffff00
1623#define BTXHTSIG2 0xffffff
1624#define BTXHTSMOOTHING 0x1
1625#define BTXHTSOUNDING 0x2
1626#define BTXHTRESERVED 0x4
1627#define BTXHTAGGREATION 0x8
1628#define BTXHTSTBC 0x30
1629#define BTXHTADVANCECODING 0x40
1630#define BTXHTSHORTGI 0x80
1631#define BTXHTNUMBERHT_LTF 0x300
1632#define BTXHTCRC8 0x3fc00
1633#define BCOUNTERRESET 0x10000
1634#define BNUMOFOFDMTX 0xffff
1635#define BNUMOFCCKTX 0xffff0000
1636#define BTXIDLEINTERVAL 0xffff
1637#define BOFDMSERVICE 0xffff0000
1638#define BTXMACHEADER 0xffffffff
1639#define BTXDATAINIT 0xff
1640#define BTXHTMODE 0x100
1641#define BTXDATATYPE 0x30000
1642#define BTXRANDOMSEED 0xffffffff
1643#define BCCKTXPREAMBLE 0x1
1644#define BCCKTXSFD 0xffff0000
1645#define BCCKTXSIG 0xff
1646#define BCCKTXSERVICE 0xff00
1647#define BCCKLENGTHEXT 0x8000
1648#define BCCKTXLENGHT 0xffff0000
1649#define BCCKTXCRC16 0xffff
1650#define BCCKTXSTATUS 0x1
1651#define BOFDMTXSTATUS 0x2
1652#define IS_BB_REG_OFFSET_92S(_offset) \
1653 ((_offset >= 0x800) && (_offset <= 0xfff))
1654
1655#define BRFMOD 0x1
1656#define BJAPANMODE 0x2
1657#define BCCKTXSC 0x30
1658#define BCCKEN 0x1000000
1659#define BOFDMEN 0x2000000
1660
1661#define BOFDMRXADCPHASE 0x10000
1662#define BOFDMTXDACPHASE 0x40000
1663#define BXATXAGC 0x3f
1664
1665#define BXBTXAGC 0xf00
1666#define BXCTXAGC 0xf000
1667#define BXDTXAGC 0xf0000
1668
1669#define BPASTART 0xf0000000
1670#define BTRSTART 0x00f00000
1671#define BRFSTART 0x0000f000
1672#define BBBSTART 0x000000f0
1673#define BBBCCKSTART 0x0000000f
1674#define BPAEND 0xf
1675#define BTREND 0x0f000000
1676#define BRFEND 0x000f0000
1677#define BCCAMASK 0x000000f0
1678#define BR2RCCAMASK 0x00000f00
1679#define BHSSI_R2TDELAY 0xf8000000
1680#define BHSSI_T2RDELAY 0xf80000
1681#define BCONTXHSSI 0x400
1682#define BIGFROMCCK 0x200
1683#define BAGCADDRESS 0x3f
1684#define BRXHPTX 0x7000
1685#define BRXHP2RX 0x38000
1686#define BRXHPCCKINI 0xc0000
1687#define BAGCTXCODE 0xc00000
1688#define BAGCRXCODE 0x300000
1689
1690#define B3WIREDATALENGTH 0x800
1691#define B3WIREADDREAALENGTH 0x400
1692
1693#define B3WIRERFPOWERDOWN 0x1
1694#define B5GPAPEPOLARITY 0x40000000
1695#define B2GPAPEPOLARITY 0x80000000
1696#define BRFSW_TXDEFAULTANT 0x3
1697#define BRFSW_TXOPTIONANT 0x30
1698#define BRFSW_RXDEFAULTANT 0x300
1699#define BRFSW_RXOPTIONANT 0x3000
1700#define BRFSI_3WIREDATA 0x1
1701#define BRFSI_3WIRECLOCK 0x2
1702#define BRFSI_3WIRELOAD 0x4
1703#define BRFSI_3WIRERW 0x8
1704#define BRFSI_3WIRE 0xf
1705
1706#define BRFSI_RFENV 0x10
1707
1708#define BRFSI_TRSW 0x20
1709#define BRFSI_TRSWB 0x40
1710#define BRFSI_ANTSW 0x100
1711#define BRFSI_ANTSWB 0x200
1712#define BRFSI_PAPE 0x400
1713#define BRFSI_PAPE5G 0x800
1714#define BBANDSELECT 0x1
1715#define BHTSIG2_GI 0x80
1716#define BHTSIG2_SMOOTHING 0x01
1717#define BHTSIG2_SOUNDING 0x02
1718#define BHTSIG2_AGGREATON 0x08
1719#define BHTSIG2_STBC 0x30
1720#define BHTSIG2_ADVCODING 0x40
1721#define BHTSIG2_NUMOFHTLTF 0x300
1722#define BHTSIG2_CRC8 0x3fc
1723#define BHTSIG1_MCS 0x7f
1724#define BHTSIG1_BANDWIDTH 0x80
1725#define BHTSIG1_HTLENGTH 0xffff
1726#define BLSIG_RATE 0xf
1727#define BLSIG_RESERVED 0x10
1728#define BLSIG_LENGTH 0x1fffe
1729#define BLSIG_PARITY 0x20
1730#define BCCKRXPHASE 0x4
1731
1732#define BLSSIREADADDRESS 0x7f800000
1733#define BLSSIREADEDGE 0x80000000
1734
1735#define BLSSIREADBACKDATA 0xfffff
1736
1737#define BLSSIREADOKFLAG 0x1000
1738#define BCCKSAMPLERATE 0x8
1739#define BREGULATOR0STANDBY 0x1
1740#define BREGULATORPLLSTANDBY 0x2
1741#define BREGULATOR1STANDBY 0x4
1742#define BPLLPOWERUP 0x8
1743#define BDPLLPOWERUP 0x10
1744#define BDA10POWERUP 0x20
1745#define BAD7POWERUP 0x200
1746#define BDA6POWERUP 0x2000
1747#define BXTALPOWERUP 0x4000
1748#define B40MDCLKPOWERUP 0x8000
1749#define BDA6DEBUGMODE 0x20000
1750#define BDA6SWING 0x380000
1751
1752#define BADCLKPHASE 0x4000000
1753#define B80MCLKDELAY 0x18000000
1754#define BAFEWATCHDOGENABLE 0x20000000
1755
1756#define BXTALCAP01 0xc0000000
1757#define BXTALCAP23 0x3
1758#define BXTALCAP92X 0x0f000000
1759#define BXTALCAP 0x0f000000
1760
1761#define BINTDIFCLKENABLE 0x400
1762#define BEXTSIGCLKENABLE 0x800
1763#define BBANDGAP_MBIAS_POWERUP 0x10000
1764#define BAD11SH_GAIN 0xc0000
1765#define BAD11NPUT_RANGE 0x700000
1766#define BAD110P_CURRENT 0x3800000
1767#define BLPATH_LOOPBACK 0x4000000
1768#define BQPATH_LOOPBACK 0x8000000
1769#define BAFE_LOOPBACK 0x10000000
1770#define BDA10_SWING 0x7e0
1771#define BDA10_REVERSE 0x800
1772#define BDA_CLK_SOURCE 0x1000
1773#define BDA7INPUT_RANGE 0x6000
1774#define BDA7_GAIN 0x38000
1775#define BDA7OUTPUT_CM_MODE 0x40000
1776#define BDA7INPUT_CM_MODE 0x380000
1777#define BDA7CURRENT 0xc00000
1778#define BREGULATOR_ADJUST 0x7000000
1779#define BAD11POWERUP_ATTX 0x1
1780#define BDA10PS_ATTX 0x10
1781#define BAD11POWERUP_ATRX 0x100
1782#define BDA10PS_ATRX 0x1000
1783#define BCCKRX_AGC_FORMAT 0x200
1784#define BPSDFFT_SAMPLE_POINT 0xc000
1785#define BPSD_AVERAGE_NUM 0x3000
1786#define BIQPATH_CONTROL 0xc00
1787#define BPSD_FREQ 0x3ff
1788#define BPSD_ANTENNA_PATH 0x30
1789#define BPSD_IQ_SWITCH 0x40
1790#define BPSD_RX_TRIGGER 0x400000
1791#define BPSD_TX_TRIGGER 0x80000000
1792#define BPSD_SINE_TONE_SCALE 0x7f000000
1793#define BPSD_REPORT 0xffff
1794
1795#define BOFDM_TXSC 0x30000000
1796#define BCCK_TXON 0x1
1797#define BOFDM_TXON 0x2
1798#define BDEBUG_PAGE 0xfff
1799#define BDEBUG_ITEM 0xff
1800#define BANTL 0x10
1801#define BANT_NONHT 0x100
1802#define BANT_HT1 0x1000
1803#define BANT_HT2 0x10000
1804#define BANT_HT1S1 0x100000
1805#define BANT_NONHTS1 0x1000000
1806
1807#define BCCK_BBMODE 0x3
1808#define BCCK_TXPOWERSAVING 0x80
1809#define BCCK_RXPOWERSAVING 0x40
1810
1811#define BCCK_SIDEBAND 0x10
1812
1813#define BCCK_SCRAMBLE 0x8
1814#define BCCK_ANTDIVERSITY 0x8000
1815#define BCCK_CARRIER_RECOVERY 0x4000
1816#define BCCK_TXRATE 0x3000
1817#define BCCK_DCCANCEL 0x0800
1818#define BCCK_ISICANCEL 0x0400
1819#define BCCK_MATCH_FILTER 0x0200
1820#define BCCK_EQUALIZER 0x0100
1821#define BCCK_PREAMBLE_DETECT 0x800000
1822#define BCCK_FAST_FALSECCA 0x400000
1823#define BCCK_CH_ESTSTART 0x300000
1824#define BCCK_CCA_COUNT 0x080000
1825#define BCCK_CS_LIM 0x070000
1826#define BCCK_BIST_MODE 0x80000000
1827#define BCCK_CCAMASK 0x40000000
1828#define BCCK_TX_DAC_PHASE 0x4
1829#define BCCK_RX_ADC_PHASE 0x20000000
1830#define BCCKR_CP_MODE 0x0100
1831#define BCCK_TXDC_OFFSET 0xf0
1832#define BCCK_RXDC_OFFSET 0xf
1833#define BCCK_CCA_MODE 0xc000
1834#define BCCK_FALSECS_LIM 0x3f00
1835#define BCCK_CS_RATIO 0xc00000
1836#define BCCK_CORGBIT_SEL 0x300000
1837#define BCCK_PD_LIM 0x0f0000
1838#define BCCK_NEWCCA 0x80000000
1839#define BCCK_RXHP_OF_IG 0x8000
1840#define BCCK_RXIG 0x7f00
1841#define BCCK_LNA_POLARITY 0x800000
1842#define BCCK_RX1ST_BAIN 0x7f0000
1843#define BCCK_RF_EXTEND 0x20000000
1844#define BCCK_RXAGC_SATLEVEL 0x1f000000
1845#define BCCK_RXAGC_SATCOUNT 0xe0
1846#define BCCKRXRFSETTLE 0x1f
1847#define BCCK_FIXED_RXAGC 0x8000
1848#define BCCK_ANTENNA_POLARITY 0x2000
1849#define BCCK_TXFILTER_TYPE 0x0c00
1850#define BCCK_RXAGC_REPORTTYPE 0x0300
1851#define BCCK_RXDAGC_EN 0x80000000
1852#define BCCK_RXDAGC_PERIOD 0x20000000
1853#define BCCK_RXDAGC_SATLEVEL 0x1f000000
1854#define BCCK_TIMING_RECOVERY 0x800000
1855#define BCCK_TXC0 0x3f0000
1856#define BCCK_TXC1 0x3f000000
1857#define BCCK_TXC2 0x3f
1858#define BCCK_TXC3 0x3f00
1859#define BCCK_TXC4 0x3f0000
1860#define BCCK_TXC5 0x3f000000
1861#define BCCK_TXC6 0x3f
1862#define BCCK_TXC7 0x3f00
1863#define BCCK_DEBUGPORT 0xff0000
1864#define BCCK_DAC_DEBUG 0x0f000000
1865#define BCCK_FALSEALARM_ENABLE 0x8000
1866#define BCCK_FALSEALARM_READ 0x4000
1867#define BCCK_TRSSI 0x7f
1868#define BCCK_RXAGC_REPORT 0xfe
1869#define BCCK_RXREPORT_ANTSEL 0x80000000
1870#define BCCK_RXREPORT_MFOFF 0x40000000
1871#define BCCK_RXREPORT_SQLOSS 0x20000000
1872#define BCCK_RXREPORT_PKTLOSS 0x10000000
1873#define BCCK_RXREPORT_LOCKEDBIT 0x08000000
1874#define BCCK_RXREPORT_RATEERROR 0x04000000
1875#define BCCK_RXREPORT_RXRATE 0x03000000
1876#define BCCK_RXFA_COUNTER_LOWER 0xff
1877#define BCCK_RXFA_COUNTER_UPPER 0xff000000
1878#define BCCK_RXHPAGC_START 0xe000
1879#define BCCK_RXHPAGC_FINAL 0x1c00
1880#define BCCK_RXFALSEALARM_ENABLE 0x8000
1881#define BCCK_FACOUNTER_FREEZE 0x4000
1882#define BCCK_TXPATH_SEL 0x10000000
1883#define BCCK_DEFAULT_RXPATH 0xc000000
1884#define BCCK_OPTION_RXPATH 0x3000000
1885
1886#define BNUM_OFSTF 0x3
1887#define BSHIFT_L 0xc0
1888#define BGI_TH 0xc
1889#define BRXPATH_A 0x1
1890#define BRXPATH_B 0x2
1891#define BRXPATH_C 0x4
1892#define BRXPATH_D 0x8
1893#define BTXPATH_A 0x1
1894#define BTXPATH_B 0x2
1895#define BTXPATH_C 0x4
1896#define BTXPATH_D 0x8
1897#define BTRSSI_FREQ 0x200
1898#define BADC_BACKOFF 0x3000
1899#define BDFIR_BACKOFF 0xc000
1900#define BTRSSI_LATCH_PHASE 0x10000
1901#define BRX_LDC_OFFSET 0xff
1902#define BRX_QDC_OFFSET 0xff00
1903#define BRX_DFIR_MODE 0x1800000
1904#define BRX_DCNF_TYPE 0xe000000
1905#define BRXIQIMB_A 0x3ff
1906#define BRXIQIMB_B 0xfc00
1907#define BRXIQIMB_C 0x3f0000
1908#define BRXIQIMB_D 0xffc00000
1909#define BDC_DC_NOTCH 0x60000
1910#define BRXNB_NOTCH 0x1f000000
1911#define BPD_TH 0xf
1912#define BPD_TH_OPT2 0xc000
1913#define BPWED_TH 0x700
1914#define BIFMF_WIN_L 0x800
1915#define BPD_OPTION 0x1000
1916#define BMF_WIN_L 0xe000
1917#define BBW_SEARCH_L 0x30000
1918#define BWIN_ENH_L 0xc0000
1919#define BBW_TH 0x700000
1920#define BED_TH2 0x3800000
1921#define BBW_OPTION 0x4000000
1922#define BRADIO_TH 0x18000000
1923#define BWINDOW_L 0xe0000000
1924#define BSBD_OPTION 0x1
1925#define BFRAME_TH 0x1c
1926#define BFS_OPTION 0x60
1927#define BDC_SLOPE_CHECK 0x80
1928#define BFGUARD_COUNTER_DC_L 0xe00
1929#define BFRAME_WEIGHT_SHORT 0x7000
1930#define BSUB_TUNE 0xe00000
1931#define BFRAME_DC_LENGTH 0xe000000
1932#define BSBD_START_OFFSET 0x30000000
1933#define BFRAME_TH_2 0x7
1934#define BFRAME_GI2_TH 0x38
1935#define BGI2_SYNC_EN 0x40
1936#define BSARCH_SHORT_EARLY 0x300
1937#define BSARCH_SHORT_LATE 0xc00
1938#define BSARCH_GI2_LATE 0x70000
1939#define BCFOANTSUM 0x1
1940#define BCFOACC 0x2
1941#define BCFOSTARTOFFSET 0xc
1942#define BCFOLOOPBACK 0x70
1943#define BCFOSUMWEIGHT 0x80
1944#define BDAGCENABLE 0x10000
1945#define BTXIQIMB_A 0x3ff
1946#define BTXIQIMB_b 0xfc00
1947#define BTXIQIMB_C 0x3f0000
1948#define BTXIQIMB_D 0xffc00000
1949#define BTXIDCOFFSET 0xff
1950#define BTXIQDCOFFSET 0xff00
1951#define BTXDFIRMODE 0x10000
1952#define BTXPESUDO_NOISEON 0x4000000
1953#define BTXPESUDO_NOISE_A 0xff
1954#define BTXPESUDO_NOISE_B 0xff00
1955#define BTXPESUDO_NOISE_C 0xff0000
1956#define BTXPESUDO_NOISE_D 0xff000000
1957#define BCCA_DROPOPTION 0x20000
1958#define BCCA_DROPTHRES 0xfff00000
1959#define BEDCCA_H 0xf
1960#define BEDCCA_L 0xf0
1961#define BLAMBDA_ED 0x300
1962#define BRX_INITIALGAIN 0x7f
1963#define BRX_ANTDIV_EN 0x80
1964#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00
1965#define BRX_HIGHPOWER_FLOW 0x8000
1966#define BRX_AGC_FREEZE_THRES 0xc0000
1967#define BRX_FREEZESTEP_AGC1 0x300000
1968#define BRX_FREEZESTEP_AGC2 0xc00000
1969#define BRX_FREEZESTEP_AGC3 0x3000000
1970#define BRX_FREEZESTEP_AGC0 0xc000000
1971#define BRXRSSI_CMP_EN 0x10000000
1972#define BRXQUICK_AGCEN 0x20000000
1973#define BRXAGC_FREEZE_THRES_MODE 0x40000000
1974#define BRX_OVERFLOW_CHECKTYPE 0x80000000
1975#define BRX_AGCSHIFT 0x7f
1976#define BTRSW_TRI_ONLY 0x80
1977#define BPOWER_THRES 0x300
1978#define BRXAGC_EN 0x1
1979#define BRXAGC_TOGETHER_EN 0x2
1980#define BRXAGC_MIN 0x4
1981#define BRXHP_INI 0x7
1982#define BRXHP_TRLNA 0x70
1983#define BRXHP_RSSI 0x700
1984#define BRXHP_BBP1 0x7000
1985#define BRXHP_BBP2 0x70000
1986#define BRXHP_BBP3 0x700000
1987#define BRSSI_H 0x7f0000
1988#define BRSSI_GEN 0x7f000000
1989#define BRXSETTLE_TRSW 0x7
1990#define BRXSETTLE_LNA 0x38
1991#define BRXSETTLE_RSSI 0x1c0
1992#define BRXSETTLE_BBP 0xe00
1993#define BRXSETTLE_RXHP 0x7000
1994#define BRXSETTLE_ANTSW_RSSI 0x38000
1995#define BRXSETTLE_ANTSW 0xc0000
1996#define BRXPROCESS_TIME_DAGC 0x300000
1997#define BRXSETTLE_HSSI 0x400000
1998#define BRXPROCESS_TIME_BBPPW 0x800000
1999#define BRXANTENNA_POWER_SHIFT 0x3000000
2000#define BRSSI_TABLE_SELECT 0xc000000
2001#define BRXHP_FINAL 0x7000000
2002#define BRXHPSETTLE_BBP 0x7
2003#define BRXHTSETTLE_HSSI 0x8
2004#define BRXHTSETTLE_RXHP 0x70
2005#define BRXHTSETTLE_BBPPW 0x80
2006#define BRXHTSETTLE_IDLE 0x300
2007#define BRXHTSETTLE_RESERVED 0x1c00
2008#define BRXHT_RXHP_EN 0x8000
2009#define BRXAGC_FREEZE_THRES 0x30000
2010#define BRXAGC_TOGETHEREN 0x40000
2011#define BRXHTAGC_MIN 0x80000
2012#define BRXHTAGC_EN 0x100000
2013#define BRXHTDAGC_EN 0x200000
2014#define BRXHT_RXHP_BBP 0x1c00000
2015#define BRXHT_RXHP_FINAL 0xe0000000
2016#define BRXPW_RADIO_TH 0x3
2017#define BRXPW_RADIO_EN 0x4
2018#define BRXMF_HOLD 0x3800
2019#define BRXPD_DELAY_TH1 0x38
2020#define BRXPD_DELAY_TH2 0x1c0
2021#define BRXPD_DC_COUNT_MAX 0x600
2022#define BRXPD_DELAY_TH 0x8000
2023#define BRXPROCESS_DELAY 0xf0000
2024#define BRXSEARCHRANGE_GI2_EARLY 0x700000
2025#define BRXFRAME_FUARD_COUNTER_L 0x3800000
2026#define BRXSGI_GUARD_L 0xc000000
2027#define BRXSGI_SEARCH_L 0x30000000
2028#define BRXSGI_TH 0xc0000000
2029#define BDFSCNT0 0xff
2030#define BDFSCNT1 0xff00
2031#define BDFSFLAG 0xf0000
2032#define BMF_WEIGHT_SUM 0x300000
2033#define BMINIDX_TH 0x7f000000
2034#define BDAFORMAT 0x40000
2035#define BTXCH_EMU_ENABLE 0x01000000
2036#define BTRSW_ISOLATION_A 0x7f
2037#define BTRSW_ISOLATION_B 0x7f00
2038#define BTRSW_ISOLATION_C 0x7f0000
2039#define BTRSW_ISOLATION_D 0x7f000000
2040#define BEXT_LNA_GAIN 0x7c00
2041
2042#define BSTBC_EN 0x4
2043#define BANTENNA_MAPPING 0x10
2044#define BNSS 0x20
2045#define BCFO_ANTSUM_ID 0x200
2046#define BPHY_COUNTER_RESET 0x8000000
2047#define BCFO_REPORT_GET 0x4000000
2048#define BOFDM_CONTINUE_TX 0x10000000
2049#define BOFDM_SINGLE_CARRIER 0x20000000
2050#define BOFDM_SINGLE_TONE 0x40000000
2051#define BHT_DETECT 0x100
2052#define BCFOEN 0x10000
2053#define BCFOVALUE 0xfff00000
2054#define BSIGTONE_RE 0x3f
2055#define BSIGTONE_IM 0x7f00
2056#define BCOUNTER_CCA 0xffff
2057#define BCOUNTER_PARITYFAIL 0xffff0000
2058#define BCOUNTER_RATEILLEGAL 0xffff
2059#define BCOUNTER_CRC8FAIL 0xffff0000
2060#define BCOUNTER_MCSNOSUPPORT 0xffff
2061#define BCOUNTER_FASTSYNC 0xffff
2062#define BSHORTCFO 0xfff
2063#define BSHORTCFOT_LENGTH 12
2064#define BSHORTCFOF_LENGTH 11
2065#define BLONGCFO 0x7ff
2066#define BLONGCFOT_LENGTH 11
2067#define BLONGCFOF_LENGTH 11
2068#define BTAILCFO 0x1fff
2069#define BTAILCFOT_LENGTH 13
2070#define BTAILCFOF_LENGTH 12
2071#define BNOISE_EN_PWDB 0xffff
2072#define BCC_POWER_DB 0xffff0000
2073#define BMOISE_PWDB 0xffff
2074#define BPOWERMEAST_LENGTH 10
2075#define BPOWERMEASF_LENGTH 3
2076#define BRX_HT_BW 0x1
2077#define BRXSC 0x6
2078#define BRX_HT 0x8
2079#define BNB_INTF_DET_ON 0x1
2080#define BINTF_WIN_LEN_CFG 0x30
2081#define BNB_INTF_TH_CFG 0x1c0
2082#define BRFGAIN 0x3f
2083#define BTABLESEL 0x40
2084#define BTRSW 0x80
2085#define BRXSNR_A 0xff
2086#define BRXSNR_B 0xff00
2087#define BRXSNR_C 0xff0000
2088#define BRXSNR_D 0xff000000
2089#define BSNR_EVMT_LENGTH 8
2090#define BSNR_EVMF_LENGTH 1
2091#define BCSI1ST 0xff
2092#define BCSI2ND 0xff00
2093#define BRXEVM1ST 0xff0000
2094#define BRXEVM2ND 0xff000000
2095#define BSIGEVM 0xff
2096#define BPWDB 0xff00
2097#define BSGIEN 0x10000
2098
2099#define BSFACTOR_QMA1 0xf
2100#define BSFACTOR_QMA2 0xf0
2101#define BSFACTOR_QMA3 0xf00
2102#define BSFACTOR_QMA4 0xf000
2103#define BSFACTOR_QMA5 0xf0000
2104#define BSFACTOR_QMA6 0xf0000
2105#define BSFACTOR_QMA7 0xf00000
2106#define BSFACTOR_QMA8 0xf000000
2107#define BSFACTOR_QMA9 0xf0000000
2108#define BCSI_SCHEME 0x100000
2109
2110#define BNOISE_LVL_TOP_SET 0x3
2111#define BCHSMOOTH 0x4
2112#define BCHSMOOTH_CFG1 0x38
2113#define BCHSMOOTH_CFG2 0x1c0
2114#define BCHSMOOTH_CFG3 0xe00
2115#define BCHSMOOTH_CFG4 0x7000
2116#define BMRCMODE 0x800000
2117#define BTHEVMCFG 0x7000000
2118
2119#define BLOOP_FIT_TYPE 0x1
2120#define BUPD_CFO 0x40
2121#define BUPD_CFO_OFFDATA 0x80
2122#define BADV_UPD_CFO 0x100
2123#define BADV_TIME_CTRL 0x800
2124#define BUPD_CLKO 0x1000
2125#define BFC 0x6000
2126#define BTRACKING_MODE 0x8000
2127#define BPHCMP_ENABLE 0x10000
2128#define BUPD_CLKO_LTF 0x20000
2129#define BCOM_CH_CFO 0x40000
2130#define BCSI_ESTI_MODE 0x80000
2131#define BADV_UPD_EQZ 0x100000
2132#define BUCHCFG 0x7000000
2133#define BUPDEQZ 0x8000000
2134
2135#define BRX_PESUDO_NOISE_ON 0x20000000
2136#define BRX_PESUDO_NOISE_A 0xff
2137#define BRX_PESUDO_NOISE_B 0xff00
2138#define BRX_PESUDO_NOISE_C 0xff0000
2139#define BRX_PESUDO_NOISE_D 0xff000000
2140#define BRX_PESUDO_NOISESTATE_A 0xffff
2141#define BRX_PESUDO_NOISESTATE_B 0xffff0000
2142#define BRX_PESUDO_NOISESTATE_C 0xffff
2143#define BRX_PESUDO_NOISESTATE_D 0xffff0000
2144
2145#define BZEBRA1_HSSIENABLE 0x8
2146#define BZEBRA1_TRXCONTROL 0xc00
2147#define BZEBRA1_TRXGAINSETTING 0x07f
2148#define BZEBRA1_RXCOUNTER 0xc00
2149#define BZEBRA1_TXCHANGEPUMP 0x38
2150#define BZEBRA1_RXCHANGEPUMP 0x7
2151#define BZEBRA1_CHANNEL_NUM 0xf80
2152#define BZEBRA1_TXLPFBW 0x400
2153#define BZEBRA1_RXLPFBW 0x600
2154
2155#define BRTL8256REG_MODE_CTRL1 0x100
2156#define BRTL8256REG_MODE_CTRL0 0x40
2157#define BRTL8256REG_TXLPFBW 0x18
2158#define BRTL8256REG_RXLPFBW 0x600
2159
2160#define BRTL8258_TXLPFBW 0xc
2161#define BRTL8258_RXLPFBW 0xc00
2162#define BRTL8258_RSSILPFBW 0xc0
2163
2164#define BBYTE0 0x1
2165#define BBYTE1 0x2
2166#define BBYTE2 0x4
2167#define BBYTE3 0x8
2168#define BWORD0 0x3
2169#define BWORD1 0xc
2170#define BWORD 0xf
2171
2172#define MASKBYTE0 0xff
2173#define MASKBYTE1 0xff00
2174#define MASKBYTE2 0xff0000
2175#define MASKBYTE3 0xff000000
2176#define MASKHWORD 0xffff0000
2177#define MASKLWORD 0x0000ffff
2178#define MASKDWORD 0xffffffff
2179#define MASK12BITS 0xfff
2180#define MASKH4BITS 0xf0000000
2181#define MASKOFDM_D 0xffc00000
2182#define MASKCCK 0x3f3f3f3f
2183
2184#define MASK4BITS 0x0f
2185#define MASK20BITS 0xfffff
2186#define RFREG_OFFSET_MASK 0xfffff
2187
2188#define BENABLE 0x1
2189#define BDISABLE 0x0
2190
2191#define LEFT_ANTENNA 0x0
2192#define RIGHT_ANTENNA 0x1
2193
2194#define TCHECK_TXSTATUS 500
2195#define TUPDATE_RXCOUNTER 100
2196
2197#define REG_UN_used_register 0x01bf
2198
2199/* WOL bit information */
2200#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0)
2201#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1)
2202#define HAL92C_WOL_DISASSOC_EVENT BIT(2)
2203#define HAL92C_WOL_DEAUTH_EVENT BIT(3)
2204#define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4)
2205
2206#define WOL_REASON_PTK_UPDATE BIT(0)
2207#define WOL_REASON_GTK_UPDATE BIT(1)
2208#define WOL_REASON_DISASSOC BIT(2)
2209#define WOL_REASON_DEAUTH BIT(3)
2210#define WOL_REASON_FW_DISCONNECT BIT(4)
2211#endif