1/* SPDX-License-Identifier: GPL-2.0+ */
 2/*
 3 * Copyright 2020 Kévin L'hôpital <kevin.lhopital@bootlin.com>
 4 * Copyright 2020-2022 Bootlin
 5 * Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
 6 */
 7
 8#ifndef _SUN8I_A83T_DPHY_H_
 9#define _SUN8I_A83T_DPHY_H_
10
11#include "sun8i_a83t_mipi_csi2.h"
12
13#define SUN8I_A83T_DPHY_CTRL_REG		0x10
14#define SUN8I_A83T_DPHY_CTRL_INIT_VALUE		0xb8df698e
15#define SUN8I_A83T_DPHY_CTRL_RESET_N		BIT(31)
16#define SUN8I_A83T_DPHY_CTRL_SHUTDOWN_N		BIT(15)
17#define SUN8I_A83T_DPHY_CTRL_DEBUG		BIT(8)
18#define SUN8I_A83T_DPHY_STATUS_REG		0x14
19#define SUN8I_A83T_DPHY_STATUS_CLK_STOP		BIT(10)
20#define SUN8I_A83T_DPHY_STATUS_CLK_ULPS		BIT(9)
21#define SUN8I_A83T_DPHY_STATUS_HSCLK		BIT(8)
22#define SUN8I_A83T_DPHY_STATUS_D3_STOP		BIT(7)
23#define SUN8I_A83T_DPHY_STATUS_D2_STOP		BIT(6)
24#define SUN8I_A83T_DPHY_STATUS_D1_STOP		BIT(5)
25#define SUN8I_A83T_DPHY_STATUS_D0_STOP		BIT(4)
26#define SUN8I_A83T_DPHY_STATUS_D3_ULPS		BIT(3)
27#define SUN8I_A83T_DPHY_STATUS_D2_ULPS		BIT(2)
28#define SUN8I_A83T_DPHY_STATUS_D1_ULPS		BIT(1)
29#define SUN8I_A83T_DPHY_STATUS_D0_ULPS		BIT(0)
30
31#define SUN8I_A83T_DPHY_ANA0_REG		0x30
32#define SUN8I_A83T_DPHY_ANA0_REXT_EN		BIT(31)
33#define SUN8I_A83T_DPHY_ANA0_REXT		BIT(30)
34#define SUN8I_A83T_DPHY_ANA0_RINT(v)		(((v) << 28) & GENMASK(29, 28))
35#define SUN8I_A83T_DPHY_ANA0_SNK(v)		(((v) << 20) & GENMASK(22, 20))
36
37int sun8i_a83t_dphy_register(struct sun8i_a83t_mipi_csi2_device *csi2_dev);
38
39#endif