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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 | /* SPDX-License-Identifier: MIT */ /* * Copyright (C) 2013-2019 NVIDIA Corporation. * Copyright (C) 2015 Rob Clark */ #ifndef DRM_TEGRA_DP_H #define DRM_TEGRA_DP_H 1 #include <linux/types.h> struct drm_display_info; struct drm_display_mode; struct drm_dp_aux; struct drm_dp_link; /** * struct drm_dp_link_caps - DP link capabilities */ struct drm_dp_link_caps { /** * @enhanced_framing: * * enhanced framing capability (mandatory as of DP 1.2) */ bool enhanced_framing; /** * tps3_supported: * * training pattern sequence 3 supported for equalization */ bool tps3_supported; /** * @fast_training: * * AUX CH handshake not required for link training */ bool fast_training; /** * @channel_coding: * * ANSI 8B/10B channel coding capability */ bool channel_coding; /** * @alternate_scrambler_reset: * * eDP alternate scrambler reset capability */ bool alternate_scrambler_reset; }; void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, const struct drm_dp_link_caps *src); /** * struct drm_dp_link_ops - DP link operations */ struct drm_dp_link_ops { /** * @apply_training: */ int (*apply_training)(struct drm_dp_link *link); /** * @configure: */ int (*configure)(struct drm_dp_link *link); }; #define DP_TRAIN_VOLTAGE_SWING_LEVEL(x) ((x) << 0) #define DP_TRAIN_PRE_EMPHASIS_LEVEL(x) ((x) << 3) #define DP_LANE_POST_CURSOR(i, x) (((x) & 0x3) << (((i) & 1) << 2)) /** * struct drm_dp_link_train_set - link training settings * @voltage_swing: per-lane voltage swing * @pre_emphasis: per-lane pre-emphasis * @post_cursor: per-lane post-cursor */ struct drm_dp_link_train_set { unsigned int voltage_swing[4]; unsigned int pre_emphasis[4]; unsigned int post_cursor[4]; }; /** * struct drm_dp_link_train - link training state information * @request: currently requested settings * @adjust: adjustments requested by sink * @pattern: currently requested training pattern * @clock_recovered: flag to track if clock recovery has completed * @channel_equalized: flag to track if channel equalization has completed */ struct drm_dp_link_train { struct drm_dp_link_train_set request; struct drm_dp_link_train_set adjust; unsigned int pattern; bool clock_recovered; bool channel_equalized; }; /** * struct drm_dp_link - DP link capabilities and configuration * @revision: DP specification revision supported on the link * @max_rate: maximum clock rate supported on the link * @max_lanes: maximum number of lanes supported on the link * @caps: capabilities supported on the link (see &drm_dp_link_caps) * @aux_rd_interval: AUX read interval to use for training (in microseconds) * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...) * @rate: currently configured link rate * @lanes: currently configured number of lanes * @rates: additional supported link rates in kHz (eDP 1.4) * @num_rates: number of additional supported link rates (eDP 1.4) */ struct drm_dp_link { unsigned char revision; unsigned int max_rate; unsigned int max_lanes; struct drm_dp_link_caps caps; /** * @cr: clock recovery read interval * @ce: channel equalization read interval */ struct { unsigned int cr; unsigned int ce; } aux_rd_interval; unsigned char edp; unsigned int rate; unsigned int lanes; unsigned long rates[DP_MAX_SUPPORTED_RATES]; unsigned int num_rates; /** * @ops: DP link operations */ const struct drm_dp_link_ops *ops; /** * @aux: DP AUX channel */ struct drm_dp_aux *aux; /** * @train: DP link training state */ struct drm_dp_link_train train; }; int drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate); int drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate); void drm_dp_link_update_rates(struct drm_dp_link *link); int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link); int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link); int drm_dp_link_choose(struct drm_dp_link *link, const struct drm_display_mode *mode, const struct drm_display_info *info); void drm_dp_link_train_init(struct drm_dp_link_train *train); int drm_dp_link_train(struct drm_dp_link *link); #endif |