1/*
 2 * Copyright 2019 Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22#ifndef __IRQSRCS_SDMA3_5_0_H__
23#define __IRQSRCS_SDMA3_5_0_H__
24
25
26#define SDMA3_5_0__SRCID__SDMA_ATOMIC_RTN_DONE				217		// 0xD9 SDMA atomic*_rtn ops complete
27#define SDMA3_5_0__SRCID__SDMA_ATOMIC_TIMEOUT				218		// 0xDA SDMA atomic CMPSWAP loop timeout
28#define SDMA3_5_0__SRCID__SDMA_IB_PREEMPT					219		// 0xDB sdma mid-command buffer preempt interrupt
29#define SDMA3_5_0__SRCID__SDMA_ECC					        220		// 0xDC ECC  Error
30#define SDMA3_5_0__SRCID__SDMA_PAGE_FAULT					221		// 0xDD Page Fault Error from UTCL2 when nack=3
31#define SDMA3_5_0__SRCID__SDMA_PAGE_NULL					222		// 0xDE Page Null from UTCL2 when nack=2
32#define SDMA3_5_0__SRCID__SDMA_XNACK					    223		// 0xDF Page retry  timeout after UTCL2 return nack=1
33#define SDMA3_5_0__SRCID__SDMA_TRAP					        224		// 0xE0 Trap
34#define SDMA3_5_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT		225		// 0xE1 0xDAGPF (Sem incomplete timeout)
35#define SDMA3_5_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT		226		// 0xE2 Semaphore wait fail timeout
36#define SDMA3_5_0__SRCID__SDMA_SRAM_ECC					    228		// 0xE4 SRAM ECC Error
37#define SDMA3_5_0__SRCID__SDMA_PREEMPT					    240		// 0xF0 SDMA New Run List
38#define SDMA3_5_0__SRCID__SDMA_VM_HOLE					    242		// 0xF2 MC or SEM address in VM hole
39#define SDMA3_5_0__SRCID__SDMA_CTXEMPTY					    243		// 0xF3 Context Empty
40#define SDMA3_5_0__SRCID__SDMA_DOORBELL_INVALID				244		// 0xF4 Doorbell BE invalid
41#define SDMA3_5_0__SRCID__SDMA_FROZEN					    245		// 0xF5 SDMA Frozen
42#define SDMA3_5_0__SRCID__SDMA_POLL_TIMEOUT					246		// 0xF6 SRBM read poll timeout
43#define SDMA3_5_0__SRCID__SDMA_SRBMWRITE					247		// 0xF7 SRBM write Protection
44
45#endif // __IRQSRCS_SDMA3_5_0_H__