1/*
  2 * Copyright 2012-15 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef __DC_OPTC_DCN20_H__
 27#define __DC_OPTC_DCN20_H__
 28
 29#include "../dcn10/dcn10_optc.h"
 30
 31#define TG_COMMON_REG_LIST_DCN2_0(inst) \
 32	TG_COMMON_REG_LIST_DCN(inst),\
 33	SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
 34	SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
 35	SRI(OTG_GSL_WINDOW_X, OTG, inst),\
 36	SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
 37	SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
 38	SRI(OTG_DSC_START_POSITION, OTG, inst),\
 39	SRI(OTG_CRC_CNTL2, OTG, inst),\
 40	SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
 41	SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
 42	SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
 43	SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
 44	SR(DWB_SOURCE_SELECT),\
 45	SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \
 46	SRI(OTG_DRR_CONTROL, OTG, inst)
 47
 48#define TG_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
 49	TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
 50	SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
 51	SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
 52	SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
 53	SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
 54	SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\
 55	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
 56	SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
 57	SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
 58	SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
 59	SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
 60	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
 61	SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
 62	SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
 63	SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
 64	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
 65	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
 66	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
 67	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\
 68	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
 69	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
 70	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
 71	SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
 72	SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
 73	SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
 74	SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
 75	SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
 76	SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
 77	SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
 78	SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
 79	SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh), \
 80	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
 81
 82void dcn20_timing_generator_init(struct optc *optc);
 83
 84void optc2_get_last_used_drr_vtotal(struct timing_generator *optc,
 85		uint32_t *refresh_rate);
 86
 87bool optc2_enable_crtc(struct timing_generator *optc);
 88
 89void optc2_set_gsl(struct timing_generator *optc,
 90		const struct gsl_params *params);
 91
 92void optc2_set_gsl_source_select(struct timing_generator *optc,
 93		int group_idx,
 94		uint32_t gsl_ready_signal);
 95
 96void optc2_set_dsc_config(struct timing_generator *optc,
 97					enum optc_dsc_mode dsc_mode,
 98					uint32_t dsc_bytes_per_pixel,
 99					uint32_t dsc_slice_width);
100
101void optc2_get_dsc_status(struct timing_generator *optc,
102					uint32_t *dsc_mode);
103
104void optc2_set_odm_bypass(struct timing_generator *optc,
105		const struct dc_crtc_timing *dc_crtc_timing);
106
107void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
108		struct dc_crtc_timing *timing);
109
110void optc2_get_optc_source(struct timing_generator *optc,
111		uint32_t *num_of_src_opp,
112		uint32_t *src_opp_id_0,
113		uint32_t *src_opp_id_1);
114
115void optc2_triplebuffer_lock(struct timing_generator *optc);
116void optc2_triplebuffer_unlock(struct timing_generator *optc);
117void optc2_lock_doublebuffer_disable(struct timing_generator *optc);
118void optc2_lock_doublebuffer_enable(struct timing_generator *optc);
119void optc2_setup_manual_trigger(struct timing_generator *optc);
120void optc2_program_manual_trigger(struct timing_generator *optc);
121bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
122bool optc2_configure_crc(struct timing_generator *optc,
123			  const struct crc_params *params);
124#endif /* __DC_OPTC_DCN20_H__ */