1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/bitops.h>
   7#include <linux/debugfs.h>
   8#include <linux/delay.h>
   9#include <linux/device.h>
  10#include <linux/gpio/consumer.h>
  11#include <linux/init.h>
  12#include <linux/kernel.h>
  13#include <linux/module.h>
  14#include <linux/of_gpio.h>
  15#include <linux/of_platform.h>
  16#include <linux/platform_device.h>
  17#include <linux/pm_runtime.h>
  18#include <linux/printk.h>
  19#include <linux/regmap.h>
  20#include <linux/regulator/consumer.h>
  21#include <linux/slab.h>
  22#include <linux/soundwire/sdw.h>
  23#include <linux/soundwire/sdw_registers.h>
  24#include <linux/soundwire/sdw_type.h>
  25#include <sound/pcm.h>
  26#include <sound/pcm_params.h>
  27#include <sound/soc-dapm.h>
  28#include <sound/soc.h>
  29#include <sound/tlv.h>
  30
  31#define WSA883X_BASE                    0x3000
  32#define WSA883X_ANA_BG_TSADC_BASE       (WSA883X_BASE + 0x00000001)
  33#define WSA883X_REF_CTRL                (WSA883X_ANA_BG_TSADC_BASE + 0x0000)
  34#define WSA883X_TEST_CTL_0              (WSA883X_ANA_BG_TSADC_BASE + 0x0001)
  35#define WSA883X_BIAS_0                  (WSA883X_ANA_BG_TSADC_BASE + 0x0002)
  36#define WSA883X_OP_CTL                  (WSA883X_ANA_BG_TSADC_BASE + 0x0003)
  37#define WSA883X_IREF_CTL                (WSA883X_ANA_BG_TSADC_BASE + 0x0004)
  38#define WSA883X_ISENS_CTL               (WSA883X_ANA_BG_TSADC_BASE + 0x0005)
  39#define WSA883X_CLK_CTL                 (WSA883X_ANA_BG_TSADC_BASE + 0x0006)
  40#define WSA883X_TEST_CTL_1              (WSA883X_ANA_BG_TSADC_BASE + 0x0007)
  41#define WSA883X_BIAS_1                  (WSA883X_ANA_BG_TSADC_BASE + 0x0008)
  42#define WSA883X_ADC_CTL                 (WSA883X_ANA_BG_TSADC_BASE + 0x0009)
  43#define WSA883X_DOUT_MSB                (WSA883X_ANA_BG_TSADC_BASE + 0x000A)
  44#define WSA883X_DOUT_LSB                (WSA883X_ANA_BG_TSADC_BASE + 0x000B)
  45#define WSA883X_VBAT_SNS                (WSA883X_ANA_BG_TSADC_BASE + 0x000C)
  46#define WSA883X_ITRIM_CODE              (WSA883X_ANA_BG_TSADC_BASE + 0x000D)
  47
  48#define WSA883X_ANA_IVSENSE_BASE        (WSA883X_BASE + 0x0000000F)
  49#define WSA883X_EN                      (WSA883X_ANA_IVSENSE_BASE + 0x0000)
  50#define WSA883X_OVERRIDE1               (WSA883X_ANA_IVSENSE_BASE + 0x0001)
  51#define WSA883X_OVERRIDE2               (WSA883X_ANA_IVSENSE_BASE + 0x0002)
  52#define WSA883X_VSENSE1                 (WSA883X_ANA_IVSENSE_BASE + 0x0003)
  53#define WSA883X_ISENSE1                 (WSA883X_ANA_IVSENSE_BASE + 0x0004)
  54#define WSA883X_ISENSE2                 (WSA883X_ANA_IVSENSE_BASE + 0x0005)
  55#define WSA883X_ISENSE_CAL              (WSA883X_ANA_IVSENSE_BASE + 0x0006)
  56#define WSA883X_MISC                    (WSA883X_ANA_IVSENSE_BASE + 0x0007)
  57#define WSA883X_ADC_0                   (WSA883X_ANA_IVSENSE_BASE + 0x0008)
  58#define WSA883X_ADC_1                   (WSA883X_ANA_IVSENSE_BASE + 0x0009)
  59#define WSA883X_ADC_2                   (WSA883X_ANA_IVSENSE_BASE + 0x000A)
  60#define WSA883X_ADC_3                   (WSA883X_ANA_IVSENSE_BASE + 0x000B)
  61#define WSA883X_ADC_4                   (WSA883X_ANA_IVSENSE_BASE + 0x000C)
  62#define WSA883X_ADC_5                   (WSA883X_ANA_IVSENSE_BASE + 0x000D)
  63#define WSA883X_ADC_6                   (WSA883X_ANA_IVSENSE_BASE + 0x000E)
  64#define WSA883X_ADC_7                   (WSA883X_ANA_IVSENSE_BASE + 0x000F)
  65#define WSA883X_STATUS                  (WSA883X_ANA_IVSENSE_BASE + 0x0010)
  66
  67#define WSA883X_ANA_SPK_TOP_BASE        (WSA883X_BASE + 0x00000025)
  68#define WSA883X_DAC_CTRL_REG            (WSA883X_ANA_SPK_TOP_BASE + 0x0000)
  69#define WSA883X_DAC_EN_DEBUG_REG        (WSA883X_ANA_SPK_TOP_BASE + 0x0001)
  70#define WSA883X_DAC_OPAMP_BIAS1_REG     (WSA883X_ANA_SPK_TOP_BASE + 0x0002)
  71#define WSA883X_DAC_OPAMP_BIAS2_REG     (WSA883X_ANA_SPK_TOP_BASE + 0x0003)
  72#define WSA883X_DAC_VCM_CTRL_REG        (WSA883X_ANA_SPK_TOP_BASE + 0x0004)
  73#define WSA883X_DAC_VOLTAGE_CTRL_REG    (WSA883X_ANA_SPK_TOP_BASE + 0x0005)
  74#define WSA883X_ATEST1_REG              (WSA883X_ANA_SPK_TOP_BASE + 0x0006)
  75#define WSA883X_ATEST2_REG              (WSA883X_ANA_SPK_TOP_BASE + 0x0007)
  76#define WSA883X_SPKR_TOP_BIAS_REG1      (WSA883X_ANA_SPK_TOP_BASE + 0x0008)
  77#define WSA883X_SPKR_TOP_BIAS_REG2      (WSA883X_ANA_SPK_TOP_BASE + 0x0009)
  78#define WSA883X_SPKR_TOP_BIAS_REG3      (WSA883X_ANA_SPK_TOP_BASE + 0x000A)
  79#define WSA883X_SPKR_TOP_BIAS_REG4      (WSA883X_ANA_SPK_TOP_BASE + 0x000B)
  80#define WSA883X_SPKR_CLIP_DET_REG       (WSA883X_ANA_SPK_TOP_BASE + 0x000C)
  81#define WSA883X_SPKR_DRV_LF_BLK_EN      (WSA883X_ANA_SPK_TOP_BASE + 0x000D)
  82#define WSA883X_SPKR_DRV_LF_EN          (WSA883X_ANA_SPK_TOP_BASE + 0x000E)
  83#define WSA883X_SPKR_DRV_LF_MASK_DCC_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x000F)
  84#define WSA883X_SPKR_DRV_LF_MISC_CTL    (WSA883X_ANA_SPK_TOP_BASE + 0x0010)
  85#define WSA883X_SPKR_DRV_LF_REG_GAIN    (WSA883X_ANA_SPK_TOP_BASE + 0x0011)
  86#define WSA883X_SPKR_DRV_OS_CAL_CTL     (WSA883X_ANA_SPK_TOP_BASE + 0x0012)
  87#define WSA883X_SPKR_DRV_OS_CAL_CTL1     (WSA883X_ANA_SPK_TOP_BASE + 0x0013)
  88#define WSA883X_SPKR_PWM_CLK_CTL        (WSA883X_ANA_SPK_TOP_BASE + 0x0014)
  89#define WSA883X_SPKR_PWM_FREQ_SEL_MASK	BIT(3)
  90#define WSA883X_SPKR_PWM_FREQ_F300KHZ	0
  91#define WSA883X_SPKR_PWM_FREQ_F600KHZ	1
  92#define WSA883X_SPKR_PDRV_HS_CTL        (WSA883X_ANA_SPK_TOP_BASE + 0x0015)
  93#define WSA883X_SPKR_PDRV_LS_CTL        (WSA883X_ANA_SPK_TOP_BASE + 0x0016)
  94#define WSA883X_SPKR_PWRSTG_DBG         (WSA883X_ANA_SPK_TOP_BASE + 0x0017)
  95#define WSA883X_SPKR_OCP_CTL            (WSA883X_ANA_SPK_TOP_BASE + 0x0018)
  96#define WSA883X_SPKR_BBM_CTL            (WSA883X_ANA_SPK_TOP_BASE + 0x0019)
  97#define WSA883X_PA_STATUS0              (WSA883X_ANA_SPK_TOP_BASE + 0x001A)
  98#define WSA883X_PA_STATUS1              (WSA883X_ANA_SPK_TOP_BASE + 0x001B)
  99#define WSA883X_PA_STATUS2              (WSA883X_ANA_SPK_TOP_BASE + 0x001C)
 100
 101#define WSA883X_ANA_BOOST_BASE          (WSA883X_BASE + 0x00000043)
 102#define WSA883X_EN_CTRL                 (WSA883X_ANA_BOOST_BASE + 0x0000)
 103#define WSA883X_CURRENT_LIMIT           (WSA883X_ANA_BOOST_BASE + 0x0001)
 104#define WSA883X_IBIAS1                  (WSA883X_ANA_BOOST_BASE + 0x0002)
 105#define WSA883X_IBIAS2                  (WSA883X_ANA_BOOST_BASE + 0x0003)
 106#define WSA883X_IBIAS3                  (WSA883X_ANA_BOOST_BASE + 0x0004)
 107#define WSA883X_LDO_PROG                (WSA883X_ANA_BOOST_BASE + 0x0005)
 108#define WSA883X_STABILITY_CTRL1         (WSA883X_ANA_BOOST_BASE + 0x0006)
 109#define WSA883X_STABILITY_CTRL2         (WSA883X_ANA_BOOST_BASE + 0x0007)
 110#define WSA883X_PWRSTAGE_CTRL1          (WSA883X_ANA_BOOST_BASE + 0x0008)
 111#define WSA883X_PWRSTAGE_CTRL2          (WSA883X_ANA_BOOST_BASE + 0x0009)
 112#define WSA883X_BYPASS_1                (WSA883X_ANA_BOOST_BASE + 0x000A)
 113#define WSA883X_BYPASS_2                (WSA883X_ANA_BOOST_BASE + 0x000B)
 114#define WSA883X_ZX_CTRL_1               (WSA883X_ANA_BOOST_BASE + 0x000C)
 115#define WSA883X_ZX_CTRL_2               (WSA883X_ANA_BOOST_BASE + 0x000D)
 116#define WSA883X_MISC1                   (WSA883X_ANA_BOOST_BASE + 0x000E)
 117#define WSA883X_MISC2                   (WSA883X_ANA_BOOST_BASE + 0x000F)
 118#define WSA883X_GMAMP_SUP1              (WSA883X_ANA_BOOST_BASE + 0x0010)
 119#define WSA883X_PWRSTAGE_CTRL3          (WSA883X_ANA_BOOST_BASE + 0x0011)
 120#define WSA883X_PWRSTAGE_CTRL4          (WSA883X_ANA_BOOST_BASE + 0x0012)
 121#define WSA883X_TEST1                   (WSA883X_ANA_BOOST_BASE + 0x0013)
 122#define WSA883X_SPARE1                  (WSA883X_ANA_BOOST_BASE + 0x0014)
 123#define WSA883X_SPARE2                  (WSA883X_ANA_BOOST_BASE + 0x0015)
 124
 125#define WSA883X_ANA_PON_LDOL_BASE       (WSA883X_BASE + 0x00000059)
 126#define WSA883X_PON_CTL_0               (WSA883X_ANA_PON_LDOL_BASE + 0x0000)
 127#define WSA883X_PON_CLT_1               (WSA883X_ANA_PON_LDOL_BASE + 0x0001)
 128#define WSA883X_PON_CTL_2               (WSA883X_ANA_PON_LDOL_BASE + 0x0002)
 129#define WSA883X_PON_CTL_3               (WSA883X_ANA_PON_LDOL_BASE + 0x0003)
 130#define WSA883X_CKWD_CTL_0              (WSA883X_ANA_PON_LDOL_BASE + 0x0004)
 131#define WSA883X_CKWD_CTL_1              (WSA883X_ANA_PON_LDOL_BASE + 0x0005)
 132#define WSA883X_CKWD_CTL_2              (WSA883X_ANA_PON_LDOL_BASE + 0x0006)
 133#define WSA883X_CKSK_CTL_0              (WSA883X_ANA_PON_LDOL_BASE + 0x0007)
 134#define WSA883X_PADSW_CTL_0             (WSA883X_ANA_PON_LDOL_BASE + 0x0008)
 135#define WSA883X_TEST_0                  (WSA883X_ANA_PON_LDOL_BASE + 0x0009)
 136#define WSA883X_TEST_1                  (WSA883X_ANA_PON_LDOL_BASE + 0x000A)
 137#define WSA883X_STATUS_0                (WSA883X_ANA_PON_LDOL_BASE + 0x000B)
 138#define WSA883X_STATUS_1                (WSA883X_ANA_PON_LDOL_BASE + 0x000C)
 139
 140#define WSA883X_DIG_CTRL_BASE           (WSA883X_BASE + 0x00000400)
 141#define WSA883X_CHIP_ID0                (WSA883X_DIG_CTRL_BASE + 0x0001)
 142#define WSA883X_CHIP_ID1                (WSA883X_DIG_CTRL_BASE + 0x0002)
 143#define WSA883X_CHIP_ID2                (WSA883X_DIG_CTRL_BASE + 0x0003)
 144#define WSA883X_CHIP_ID3                (WSA883X_DIG_CTRL_BASE + 0x0004)
 145#define WSA883X_BUS_ID                  (WSA883X_DIG_CTRL_BASE + 0x0005)
 146#define WSA883X_CDC_RST_CTL             (WSA883X_DIG_CTRL_BASE + 0x0006)
 147#define WSA883X_TOP_CLK_CFG             (WSA883X_DIG_CTRL_BASE + 0x0007)
 148#define WSA883X_CDC_PATH_MODE           (WSA883X_DIG_CTRL_BASE + 0x0008)
 149#define WSA883X_RXD_MODE_MASK		BIT(1)
 150#define WSA883X_RXD_MODE_NORMAL		0
 151#define WSA883X_RXD_MODE_HIFI		1
 152#define WSA883X_CDC_CLK_CTL             (WSA883X_DIG_CTRL_BASE + 0x0009)
 153#define WSA883X_SWR_RESET_EN            (WSA883X_DIG_CTRL_BASE + 0x000A)
 154#define WSA883X_RESET_CTL               (WSA883X_DIG_CTRL_BASE + 0x000B)
 155#define WSA883X_PA_FSM_CTL              (WSA883X_DIG_CTRL_BASE + 0x0010)
 156#define WSA883X_GLOBAL_PA_EN_MASK	BIT(0)
 157#define WSA883X_GLOBAL_PA_ENABLE	1
 158#define WSA883X_PA_FSM_TIMER0           (WSA883X_DIG_CTRL_BASE + 0x0011)
 159#define WSA883X_PA_FSM_TIMER1           (WSA883X_DIG_CTRL_BASE + 0x0012)
 160#define WSA883X_PA_FSM_STA              (WSA883X_DIG_CTRL_BASE + 0x0013)
 161#define WSA883X_PA_FSM_ERR_COND         (WSA883X_DIG_CTRL_BASE + 0x0014)
 162#define WSA883X_PA_FSM_MSK              (WSA883X_DIG_CTRL_BASE + 0x0015)
 163#define WSA883X_PA_FSM_BYP              (WSA883X_DIG_CTRL_BASE + 0x0016)
 164#define WSA883X_PA_FSM_DBG              (WSA883X_DIG_CTRL_BASE + 0x0017)
 165#define WSA883X_TADC_VALUE_CTL          (WSA883X_DIG_CTRL_BASE + 0x0020)
 166#define WSA883X_TEMP_DETECT_CTL         (WSA883X_DIG_CTRL_BASE + 0x0021)
 167#define WSA883X_TEMP_MSB                (WSA883X_DIG_CTRL_BASE + 0x0022)
 168#define WSA883X_TEMP_LSB                (WSA883X_DIG_CTRL_BASE + 0x0023)
 169#define WSA883X_TEMP_CONFIG0            (WSA883X_DIG_CTRL_BASE + 0x0024)
 170#define WSA883X_TEMP_CONFIG1            (WSA883X_DIG_CTRL_BASE + 0x0025)
 171#define WSA883X_VBAT_ADC_FLT_CTL        (WSA883X_DIG_CTRL_BASE + 0x0026)
 172#define WSA883X_VBAT_ADC_FLT_EN_MASK	BIT(0)
 173#define WSA883X_VBAT_ADC_COEF_SEL_MASK	GENMASK(3, 1)
 174#define WSA883X_VBAT_ADC_COEF_F_1DIV2	0x0
 175#define WSA883X_VBAT_ADC_COEF_F_1DIV16	0x3
 176#define WSA883X_VBAT_DIN_MSB            (WSA883X_DIG_CTRL_BASE + 0x0027)
 177#define WSA883X_VBAT_DIN_LSB            (WSA883X_DIG_CTRL_BASE + 0x0028)
 178#define WSA883X_VBAT_DOUT               (WSA883X_DIG_CTRL_BASE + 0x0029)
 179#define WSA883X_SDM_PDM9_LSB            (WSA883X_DIG_CTRL_BASE + 0x002A)
 180#define WSA883X_SDM_PDM9_MSB            (WSA883X_DIG_CTRL_BASE + 0x002B)
 181#define WSA883X_CDC_RX_CTL              (WSA883X_DIG_CTRL_BASE + 0x0030)
 182#define WSA883X_CDC_SPK_DSM_A1_0        (WSA883X_DIG_CTRL_BASE + 0x0031)
 183#define WSA883X_CDC_SPK_DSM_A1_1        (WSA883X_DIG_CTRL_BASE + 0x0032)
 184#define WSA883X_CDC_SPK_DSM_A2_0        (WSA883X_DIG_CTRL_BASE + 0x0033)
 185#define WSA883X_CDC_SPK_DSM_A2_1        (WSA883X_DIG_CTRL_BASE + 0x0034)
 186#define WSA883X_CDC_SPK_DSM_A3_0        (WSA883X_DIG_CTRL_BASE + 0x0035)
 187#define WSA883X_CDC_SPK_DSM_A3_1        (WSA883X_DIG_CTRL_BASE + 0x0036)
 188#define WSA883X_CDC_SPK_DSM_A4_0        (WSA883X_DIG_CTRL_BASE + 0x0037)
 189#define WSA883X_CDC_SPK_DSM_A4_1        (WSA883X_DIG_CTRL_BASE + 0x0038)
 190#define WSA883X_CDC_SPK_DSM_A5_0        (WSA883X_DIG_CTRL_BASE + 0x0039)
 191#define WSA883X_CDC_SPK_DSM_A5_1        (WSA883X_DIG_CTRL_BASE + 0x003A)
 192#define WSA883X_CDC_SPK_DSM_A6_0        (WSA883X_DIG_CTRL_BASE + 0x003B)
 193#define WSA883X_CDC_SPK_DSM_A7_0        (WSA883X_DIG_CTRL_BASE + 0x003C)
 194#define WSA883X_CDC_SPK_DSM_C_0         (WSA883X_DIG_CTRL_BASE + 0x003D)
 195#define WSA883X_CDC_SPK_DSM_C_1         (WSA883X_DIG_CTRL_BASE + 0x003E)
 196#define WSA883X_CDC_SPK_DSM_C_2         (WSA883X_DIG_CTRL_BASE + 0x003F)
 197#define WSA883X_CDC_SPK_DSM_C_3         (WSA883X_DIG_CTRL_BASE + 0x0040)
 198#define WSA883X_CDC_SPK_DSM_R1          (WSA883X_DIG_CTRL_BASE + 0x0041)
 199#define WSA883X_CDC_SPK_DSM_R2          (WSA883X_DIG_CTRL_BASE + 0x0042)
 200#define WSA883X_CDC_SPK_DSM_R3          (WSA883X_DIG_CTRL_BASE + 0x0043)
 201#define WSA883X_CDC_SPK_DSM_R4          (WSA883X_DIG_CTRL_BASE + 0x0044)
 202#define WSA883X_CDC_SPK_DSM_R5          (WSA883X_DIG_CTRL_BASE + 0x0045)
 203#define WSA883X_CDC_SPK_DSM_R6          (WSA883X_DIG_CTRL_BASE + 0x0046)
 204#define WSA883X_CDC_SPK_DSM_R7          (WSA883X_DIG_CTRL_BASE + 0x0047)
 205#define WSA883X_CDC_SPK_GAIN_PDM_0      (WSA883X_DIG_CTRL_BASE + 0x0048)
 206#define WSA883X_CDC_SPK_GAIN_PDM_1      (WSA883X_DIG_CTRL_BASE + 0x0049)
 207#define WSA883X_CDC_SPK_GAIN_PDM_2      (WSA883X_DIG_CTRL_BASE + 0x004A)
 208#define WSA883X_PDM_WD_CTL              (WSA883X_DIG_CTRL_BASE + 0x004B)
 209#define WSA883X_PDM_EN_MASK		BIT(0)
 210#define WSA883X_PDM_ENABLE		BIT(0)
 211#define WSA883X_DEM_BYPASS_DATA0        (WSA883X_DIG_CTRL_BASE + 0x004C)
 212#define WSA883X_DEM_BYPASS_DATA1        (WSA883X_DIG_CTRL_BASE + 0x004D)
 213#define WSA883X_DEM_BYPASS_DATA2        (WSA883X_DIG_CTRL_BASE + 0x004E)
 214#define WSA883X_DEM_BYPASS_DATA3        (WSA883X_DIG_CTRL_BASE + 0x004F)
 215#define WSA883X_WAVG_CTL                (WSA883X_DIG_CTRL_BASE + 0x0050)
 216#define WSA883X_WAVG_LRA_PER_0          (WSA883X_DIG_CTRL_BASE + 0x0051)
 217#define WSA883X_WAVG_LRA_PER_1          (WSA883X_DIG_CTRL_BASE + 0x0052)
 218#define WSA883X_WAVG_DELTA_THETA_0      (WSA883X_DIG_CTRL_BASE + 0x0053)
 219#define WSA883X_WAVG_DELTA_THETA_1      (WSA883X_DIG_CTRL_BASE + 0x0054)
 220#define WSA883X_WAVG_DIRECT_AMP_0       (WSA883X_DIG_CTRL_BASE + 0x0055)
 221#define WSA883X_WAVG_DIRECT_AMP_1       (WSA883X_DIG_CTRL_BASE + 0x0056)
 222#define WSA883X_WAVG_PTRN_AMP0_0        (WSA883X_DIG_CTRL_BASE + 0x0057)
 223#define WSA883X_WAVG_PTRN_AMP0_1        (WSA883X_DIG_CTRL_BASE + 0x0058)
 224#define WSA883X_WAVG_PTRN_AMP1_0        (WSA883X_DIG_CTRL_BASE + 0x0059)
 225#define WSA883X_WAVG_PTRN_AMP1_1        (WSA883X_DIG_CTRL_BASE + 0x005A)
 226#define WSA883X_WAVG_PTRN_AMP2_0        (WSA883X_DIG_CTRL_BASE + 0x005B)
 227#define WSA883X_WAVG_PTRN_AMP2_1        (WSA883X_DIG_CTRL_BASE + 0x005C)
 228#define WSA883X_WAVG_PTRN_AMP3_0        (WSA883X_DIG_CTRL_BASE + 0x005D)
 229#define WSA883X_WAVG_PTRN_AMP3_1        (WSA883X_DIG_CTRL_BASE + 0x005E)
 230#define WSA883X_WAVG_PTRN_AMP4_0        (WSA883X_DIG_CTRL_BASE + 0x005F)
 231#define WSA883X_WAVG_PTRN_AMP4_1        (WSA883X_DIG_CTRL_BASE + 0x0060)
 232#define WSA883X_WAVG_PTRN_AMP5_0        (WSA883X_DIG_CTRL_BASE + 0x0061)
 233#define WSA883X_WAVG_PTRN_AMP5_1        (WSA883X_DIG_CTRL_BASE + 0x0062)
 234#define WSA883X_WAVG_PTRN_AMP6_0        (WSA883X_DIG_CTRL_BASE + 0x0063)
 235#define WSA883X_WAVG_PTRN_AMP6_1        (WSA883X_DIG_CTRL_BASE + 0x0064)
 236#define WSA883X_WAVG_PTRN_AMP7_0        (WSA883X_DIG_CTRL_BASE + 0x0065)
 237#define WSA883X_WAVG_PTRN_AMP7_1        (WSA883X_DIG_CTRL_BASE + 0x0066)
 238#define WSA883X_WAVG_PER_0_1            (WSA883X_DIG_CTRL_BASE + 0x0067)
 239#define WSA883X_WAVG_PER_2_3            (WSA883X_DIG_CTRL_BASE + 0x0068)
 240#define WSA883X_WAVG_PER_4_5            (WSA883X_DIG_CTRL_BASE + 0x0069)
 241#define WSA883X_WAVG_PER_6_7            (WSA883X_DIG_CTRL_BASE + 0x006A)
 242#define WSA883X_WAVG_STA                (WSA883X_DIG_CTRL_BASE + 0x006B)
 243#define WSA883X_DRE_CTL_0               (WSA883X_DIG_CTRL_BASE + 0x006C)
 244#define WSA883X_DRE_OFFSET_MASK		GENMASK(2, 0)
 245#define WSA883X_DRE_PROG_DELAY_MASK	GENMASK(7, 4)
 246#define WSA883X_DRE_CTL_1               (WSA883X_DIG_CTRL_BASE + 0x006D)
 247#define WSA883X_DRE_GAIN_EN_MASK	BIT(0)
 248#define WSA883X_DRE_GAIN_FROM_CSR	1
 249#define WSA883X_DRE_IDLE_DET_CTL        (WSA883X_DIG_CTRL_BASE + 0x006E)
 250#define WSA883X_CLSH_CTL_0              (WSA883X_DIG_CTRL_BASE + 0x0070)
 251#define WSA883X_CLSH_CTL_1              (WSA883X_DIG_CTRL_BASE + 0x0071)
 252#define WSA883X_CLSH_V_HD_PA            (WSA883X_DIG_CTRL_BASE + 0x0072)
 253#define WSA883X_CLSH_V_PA_MIN           (WSA883X_DIG_CTRL_BASE + 0x0073)
 254#define WSA883X_CLSH_OVRD_VAL           (WSA883X_DIG_CTRL_BASE + 0x0074)
 255#define WSA883X_CLSH_HARD_MAX           (WSA883X_DIG_CTRL_BASE + 0x0075)
 256#define WSA883X_CLSH_SOFT_MAX           (WSA883X_DIG_CTRL_BASE + 0x0076)
 257#define WSA883X_CLSH_SIG_DP             (WSA883X_DIG_CTRL_BASE + 0x0077)
 258#define WSA883X_TAGC_CTL                (WSA883X_DIG_CTRL_BASE + 0x0078)
 259#define WSA883X_TAGC_TIME               (WSA883X_DIG_CTRL_BASE + 0x0079)
 260#define WSA883X_TAGC_E2E_GAIN           (WSA883X_DIG_CTRL_BASE + 0x007A)
 261#define WSA883X_TAGC_FORCE_VAL          (WSA883X_DIG_CTRL_BASE + 0x007B)
 262#define WSA883X_VAGC_CTL                (WSA883X_DIG_CTRL_BASE + 0x007C)
 263#define WSA883X_VAGC_TIME               (WSA883X_DIG_CTRL_BASE + 0x007D)
 264#define WSA883X_VAGC_ATTN_LVL_1_2       (WSA883X_DIG_CTRL_BASE + 0x007E)
 265#define WSA883X_VAGC_ATTN_LVL_3         (WSA883X_DIG_CTRL_BASE + 0x007F)
 266#define WSA883X_INTR_MODE               (WSA883X_DIG_CTRL_BASE + 0x0080)
 267#define WSA883X_INTR_MASK0              (WSA883X_DIG_CTRL_BASE + 0x0081)
 268#define WSA883X_INTR_MASK1              (WSA883X_DIG_CTRL_BASE + 0x0082)
 269#define WSA883X_INTR_STATUS0            (WSA883X_DIG_CTRL_BASE + 0x0083)
 270#define WSA883X_INTR_STATUS1            (WSA883X_DIG_CTRL_BASE + 0x0084)
 271#define WSA883X_INTR_CLEAR0             (WSA883X_DIG_CTRL_BASE + 0x0085)
 272#define WSA883X_INTR_CLEAR1             (WSA883X_DIG_CTRL_BASE + 0x0086)
 273#define WSA883X_INTR_LEVEL0             (WSA883X_DIG_CTRL_BASE + 0x0087)
 274#define WSA883X_INTR_LEVEL1             (WSA883X_DIG_CTRL_BASE + 0x0088)
 275#define WSA883X_INTR_SET0               (WSA883X_DIG_CTRL_BASE + 0x0089)
 276#define WSA883X_INTR_SET1               (WSA883X_DIG_CTRL_BASE + 0x008A)
 277#define WSA883X_INTR_TEST0              (WSA883X_DIG_CTRL_BASE + 0x008B)
 278#define WSA883X_INTR_TEST1              (WSA883X_DIG_CTRL_BASE + 0x008C)
 279#define WSA883X_OTP_CTRL0               (WSA883X_DIG_CTRL_BASE + 0x0090)
 280#define WSA883X_OTP_CTRL1               (WSA883X_DIG_CTRL_BASE + 0x0091)
 281#define WSA883X_HDRIVE_CTL_GROUP1       (WSA883X_DIG_CTRL_BASE + 0x0092)
 282#define WSA883X_PIN_CTL                 (WSA883X_DIG_CTRL_BASE + 0x0093)
 283#define WSA883X_PIN_CTL_OE              (WSA883X_DIG_CTRL_BASE + 0x0094)
 284#define WSA883X_PIN_WDATA_IOPAD         (WSA883X_DIG_CTRL_BASE + 0x0095)
 285#define WSA883X_PIN_STATUS              (WSA883X_DIG_CTRL_BASE + 0x0096)
 286#define WSA883X_I2C_SLAVE_CTL           (WSA883X_DIG_CTRL_BASE + 0x0097)
 287#define WSA883X_PDM_TEST_MODE           (WSA883X_DIG_CTRL_BASE + 0x00A0)
 288#define WSA883X_ATE_TEST_MODE           (WSA883X_DIG_CTRL_BASE + 0x00A1)
 289#define WSA883X_DIG_DEBUG_MODE          (WSA883X_DIG_CTRL_BASE + 0x00A3)
 290#define WSA883X_DIG_DEBUG_SEL           (WSA883X_DIG_CTRL_BASE + 0x00A4)
 291#define WSA883X_DIG_DEBUG_EN            (WSA883X_DIG_CTRL_BASE + 0x00A5)
 292#define WSA883X_SWR_HM_TEST0            (WSA883X_DIG_CTRL_BASE + 0x00A6)
 293#define WSA883X_SWR_HM_TEST1            (WSA883X_DIG_CTRL_BASE + 0x00A7)
 294#define WSA883X_SWR_PAD_CTL             (WSA883X_DIG_CTRL_BASE + 0x00A8)
 295#define WSA883X_TADC_DETECT_DBG_CTL     (WSA883X_DIG_CTRL_BASE + 0x00A9)
 296#define WSA883X_TADC_DEBUG_MSB          (WSA883X_DIG_CTRL_BASE + 0x00AA)
 297#define WSA883X_TADC_DEBUG_LSB          (WSA883X_DIG_CTRL_BASE + 0x00AB)
 298#define WSA883X_SAMPLE_EDGE_SEL         (WSA883X_DIG_CTRL_BASE + 0x00AC)
 299#define WSA883X_SWR_EDGE_SEL            (WSA883X_DIG_CTRL_BASE + 0x00AD)
 300#define WSA883X_TEST_MODE_CTL           (WSA883X_DIG_CTRL_BASE + 0x00AE)
 301#define WSA883X_IOPAD_CTL               (WSA883X_DIG_CTRL_BASE + 0x00AF)
 302#define WSA883X_ANA_CSR_DBG_ADD         (WSA883X_DIG_CTRL_BASE + 0x00B0)
 303#define WSA883X_ANA_CSR_DBG_CTL         (WSA883X_DIG_CTRL_BASE + 0x00B1)
 304#define WSA883X_SPARE_R                 (WSA883X_DIG_CTRL_BASE + 0x00BC)
 305#define WSA883X_SPARE_0                 (WSA883X_DIG_CTRL_BASE + 0x00BD)
 306#define WSA883X_SPARE_1                 (WSA883X_DIG_CTRL_BASE + 0x00BE)
 307#define WSA883X_SPARE_2                 (WSA883X_DIG_CTRL_BASE + 0x00BF)
 308#define WSA883X_SCODE                   (WSA883X_DIG_CTRL_BASE + 0x00C0)
 309
 310#define WSA883X_DIG_TRIM_BASE           (WSA883X_BASE + 0x00000500)
 311#define WSA883X_OTP_REG_0               (WSA883X_DIG_TRIM_BASE + 0x0080)
 312#define WSA883X_ID_MASK			GENMASK(3, 0)
 313#define WSA883X_OTP_REG_1               (WSA883X_DIG_TRIM_BASE + 0x0081)
 314#define WSA883X_OTP_REG_2               (WSA883X_DIG_TRIM_BASE + 0x0082)
 315#define WSA883X_OTP_REG_3               (WSA883X_DIG_TRIM_BASE + 0x0083)
 316#define WSA883X_OTP_REG_4               (WSA883X_DIG_TRIM_BASE + 0x0084)
 317#define WSA883X_OTP_REG_5               (WSA883X_DIG_TRIM_BASE + 0x0085)
 318#define WSA883X_OTP_REG_6               (WSA883X_DIG_TRIM_BASE + 0x0086)
 319#define WSA883X_OTP_REG_7               (WSA883X_DIG_TRIM_BASE + 0x0087)
 320#define WSA883X_OTP_REG_8               (WSA883X_DIG_TRIM_BASE + 0x0088)
 321#define WSA883X_OTP_REG_9               (WSA883X_DIG_TRIM_BASE + 0x0089)
 322#define WSA883X_OTP_REG_10              (WSA883X_DIG_TRIM_BASE + 0x008A)
 323#define WSA883X_OTP_REG_11              (WSA883X_DIG_TRIM_BASE + 0x008B)
 324#define WSA883X_OTP_REG_12              (WSA883X_DIG_TRIM_BASE + 0x008C)
 325#define WSA883X_OTP_REG_13              (WSA883X_DIG_TRIM_BASE + 0x008D)
 326#define WSA883X_OTP_REG_14              (WSA883X_DIG_TRIM_BASE + 0x008E)
 327#define WSA883X_OTP_REG_15              (WSA883X_DIG_TRIM_BASE + 0x008F)
 328#define WSA883X_OTP_REG_16              (WSA883X_DIG_TRIM_BASE + 0x0090)
 329#define WSA883X_OTP_REG_17              (WSA883X_DIG_TRIM_BASE + 0x0091)
 330#define WSA883X_OTP_REG_18              (WSA883X_DIG_TRIM_BASE + 0x0092)
 331#define WSA883X_OTP_REG_19              (WSA883X_DIG_TRIM_BASE + 0x0093)
 332#define WSA883X_OTP_REG_20              (WSA883X_DIG_TRIM_BASE + 0x0094)
 333#define WSA883X_OTP_REG_21              (WSA883X_DIG_TRIM_BASE + 0x0095)
 334#define WSA883X_OTP_REG_22              (WSA883X_DIG_TRIM_BASE + 0x0096)
 335#define WSA883X_OTP_REG_23              (WSA883X_DIG_TRIM_BASE + 0x0097)
 336#define WSA883X_OTP_REG_24              (WSA883X_DIG_TRIM_BASE + 0x0098)
 337#define WSA883X_OTP_REG_25              (WSA883X_DIG_TRIM_BASE + 0x0099)
 338#define WSA883X_OTP_REG_26              (WSA883X_DIG_TRIM_BASE + 0x009A)
 339#define WSA883X_OTP_REG_27              (WSA883X_DIG_TRIM_BASE + 0x009B)
 340#define WSA883X_OTP_REG_28              (WSA883X_DIG_TRIM_BASE + 0x009C)
 341#define WSA883X_OTP_REG_29              (WSA883X_DIG_TRIM_BASE + 0x009D)
 342#define WSA883X_OTP_REG_30              (WSA883X_DIG_TRIM_BASE + 0x009E)
 343#define WSA883X_OTP_REG_31              (WSA883X_DIG_TRIM_BASE + 0x009F)
 344#define WSA883X_OTP_REG_32              (WSA883X_DIG_TRIM_BASE + 0x00A0)
 345#define WSA883X_OTP_REG_33              (WSA883X_DIG_TRIM_BASE + 0x00A1)
 346#define WSA883X_OTP_REG_34              (WSA883X_DIG_TRIM_BASE + 0x00A2)
 347#define WSA883X_OTP_REG_35              (WSA883X_DIG_TRIM_BASE + 0x00A3)
 348#define WSA883X_OTP_REG_63              (WSA883X_DIG_TRIM_BASE + 0x00BF)
 349
 350#define WSA883X_DIG_EMEM_BASE           (WSA883X_BASE + 0x000005C0)
 351#define WSA883X_EMEM_0                  (WSA883X_DIG_EMEM_BASE + 0x0000)
 352#define WSA883X_EMEM_1                  (WSA883X_DIG_EMEM_BASE + 0x0001)
 353#define WSA883X_EMEM_2                  (WSA883X_DIG_EMEM_BASE + 0x0002)
 354#define WSA883X_EMEM_3                  (WSA883X_DIG_EMEM_BASE + 0x0003)
 355#define WSA883X_EMEM_4                  (WSA883X_DIG_EMEM_BASE + 0x0004)
 356#define WSA883X_EMEM_5                  (WSA883X_DIG_EMEM_BASE + 0x0005)
 357#define WSA883X_EMEM_6                  (WSA883X_DIG_EMEM_BASE + 0x0006)
 358#define WSA883X_EMEM_7                  (WSA883X_DIG_EMEM_BASE + 0x0007)
 359#define WSA883X_EMEM_8                  (WSA883X_DIG_EMEM_BASE + 0x0008)
 360#define WSA883X_EMEM_9                  (WSA883X_DIG_EMEM_BASE + 0x0009)
 361#define WSA883X_EMEM_10                 (WSA883X_DIG_EMEM_BASE + 0x000A)
 362#define WSA883X_EMEM_11                 (WSA883X_DIG_EMEM_BASE + 0x000B)
 363#define WSA883X_EMEM_12                 (WSA883X_DIG_EMEM_BASE + 0x000C)
 364#define WSA883X_EMEM_13                 (WSA883X_DIG_EMEM_BASE + 0x000D)
 365#define WSA883X_EMEM_14                 (WSA883X_DIG_EMEM_BASE + 0x000E)
 366#define WSA883X_EMEM_15                 (WSA883X_DIG_EMEM_BASE + 0x000F)
 367#define WSA883X_EMEM_16                 (WSA883X_DIG_EMEM_BASE + 0x0010)
 368#define WSA883X_EMEM_17                 (WSA883X_DIG_EMEM_BASE + 0x0011)
 369#define WSA883X_EMEM_18                 (WSA883X_DIG_EMEM_BASE + 0x0012)
 370#define WSA883X_EMEM_19                 (WSA883X_DIG_EMEM_BASE + 0x0013)
 371#define WSA883X_EMEM_20                 (WSA883X_DIG_EMEM_BASE + 0x0014)
 372#define WSA883X_EMEM_21                 (WSA883X_DIG_EMEM_BASE + 0x0015)
 373#define WSA883X_EMEM_22                 (WSA883X_DIG_EMEM_BASE + 0x0016)
 374#define WSA883X_EMEM_23                 (WSA883X_DIG_EMEM_BASE + 0x0017)
 375#define WSA883X_EMEM_24                 (WSA883X_DIG_EMEM_BASE + 0x0018)
 376#define WSA883X_EMEM_25                 (WSA883X_DIG_EMEM_BASE + 0x0019)
 377#define WSA883X_EMEM_26                 (WSA883X_DIG_EMEM_BASE + 0x001A)
 378#define WSA883X_EMEM_27                 (WSA883X_DIG_EMEM_BASE + 0x001B)
 379#define WSA883X_EMEM_28                 (WSA883X_DIG_EMEM_BASE + 0x001C)
 380#define WSA883X_EMEM_29                 (WSA883X_DIG_EMEM_BASE + 0x001D)
 381#define WSA883X_EMEM_30                 (WSA883X_DIG_EMEM_BASE + 0x001E)
 382#define WSA883X_EMEM_31                 (WSA883X_DIG_EMEM_BASE + 0x001F)
 383#define WSA883X_EMEM_32                 (WSA883X_DIG_EMEM_BASE + 0x0020)
 384#define WSA883X_EMEM_33                 (WSA883X_DIG_EMEM_BASE + 0x0021)
 385#define WSA883X_EMEM_34                 (WSA883X_DIG_EMEM_BASE + 0x0022)
 386#define WSA883X_EMEM_35                 (WSA883X_DIG_EMEM_BASE + 0x0023)
 387#define WSA883X_EMEM_36                 (WSA883X_DIG_EMEM_BASE + 0x0024)
 388#define WSA883X_EMEM_37                 (WSA883X_DIG_EMEM_BASE + 0x0025)
 389#define WSA883X_EMEM_38                 (WSA883X_DIG_EMEM_BASE + 0x0026)
 390#define WSA883X_EMEM_39                 (WSA883X_DIG_EMEM_BASE + 0x0027)
 391#define WSA883X_EMEM_40                 (WSA883X_DIG_EMEM_BASE + 0x0028)
 392#define WSA883X_EMEM_41                 (WSA883X_DIG_EMEM_BASE + 0x0029)
 393#define WSA883X_EMEM_42                 (WSA883X_DIG_EMEM_BASE + 0x002A)
 394#define WSA883X_EMEM_43                 (WSA883X_DIG_EMEM_BASE + 0x002B)
 395#define WSA883X_EMEM_44                 (WSA883X_DIG_EMEM_BASE + 0x002C)
 396#define WSA883X_EMEM_45                 (WSA883X_DIG_EMEM_BASE + 0x002D)
 397#define WSA883X_EMEM_46                 (WSA883X_DIG_EMEM_BASE + 0x002E)
 398#define WSA883X_EMEM_47                 (WSA883X_DIG_EMEM_BASE + 0x002F)
 399#define WSA883X_EMEM_48                 (WSA883X_DIG_EMEM_BASE + 0x0030)
 400#define WSA883X_EMEM_49                 (WSA883X_DIG_EMEM_BASE + 0x0031)
 401#define WSA883X_EMEM_50                 (WSA883X_DIG_EMEM_BASE + 0x0032)
 402#define WSA883X_EMEM_51                 (WSA883X_DIG_EMEM_BASE + 0x0033)
 403#define WSA883X_EMEM_52                 (WSA883X_DIG_EMEM_BASE + 0x0034)
 404#define WSA883X_EMEM_53                 (WSA883X_DIG_EMEM_BASE + 0x0035)
 405#define WSA883X_EMEM_54                 (WSA883X_DIG_EMEM_BASE + 0x0036)
 406#define WSA883X_EMEM_55                 (WSA883X_DIG_EMEM_BASE + 0x0037)
 407#define WSA883X_EMEM_56                 (WSA883X_DIG_EMEM_BASE + 0x0038)
 408#define WSA883X_EMEM_57                 (WSA883X_DIG_EMEM_BASE + 0x0039)
 409#define WSA883X_EMEM_58                 (WSA883X_DIG_EMEM_BASE + 0x003A)
 410#define WSA883X_EMEM_59                 (WSA883X_DIG_EMEM_BASE + 0x003B)
 411#define WSA883X_EMEM_60                 (WSA883X_DIG_EMEM_BASE + 0x003C)
 412#define WSA883X_EMEM_61                 (WSA883X_DIG_EMEM_BASE + 0x003D)
 413#define WSA883X_EMEM_62                 (WSA883X_DIG_EMEM_BASE + 0x003E)
 414#define WSA883X_EMEM_63                 (WSA883X_DIG_EMEM_BASE + 0x003F)
 415
 416#define WSA883X_NUM_REGISTERS           (WSA883X_EMEM_63 + 1)
 417#define WSA883X_MAX_REGISTER            (WSA883X_NUM_REGISTERS - 1)
 418
 419#define WSA883X_VERSION_1_0 0
 420#define WSA883X_VERSION_1_1 1
 421
 422#define WSA883X_MAX_SWR_PORTS   4
 423#define WSA883X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
 424			SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
 425			SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
 426			SNDRV_PCM_RATE_384000)
 427/* Fractional Rates */
 428#define WSA883X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
 429				SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
 430
 431#define WSA883X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 432		SNDRV_PCM_FMTBIT_S24_LE |\
 433		SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
 434
 435struct wsa883x_priv {
 436	struct regmap *regmap;
 437	struct device *dev;
 438	struct regulator *vdd;
 439	struct sdw_slave *slave;
 440	struct sdw_stream_config sconfig;
 441	struct sdw_stream_runtime *sruntime;
 442	struct sdw_port_config port_config[WSA883X_MAX_SWR_PORTS];
 443	struct gpio_desc *sd_n;
 444	bool port_prepared[WSA883X_MAX_SWR_PORTS];
 445	bool port_enable[WSA883X_MAX_SWR_PORTS];
 446	int version;
 447	int variant;
 448	int active_ports;
 449	int dev_mode;
 450	int comp_offset;
 451};
 452
 453enum {
 454	WSA8830 = 0,
 455	WSA8835,
 456	WSA8832,
 457	WSA8835_V2 = 5,
 458};
 459
 460enum {
 461	COMP_OFFSET0,
 462	COMP_OFFSET1,
 463	COMP_OFFSET2,
 464	COMP_OFFSET3,
 465	COMP_OFFSET4,
 466};
 467
 468enum wsa_port_ids {
 469	WSA883X_PORT_DAC,
 470	WSA883X_PORT_COMP,
 471	WSA883X_PORT_BOOST,
 472	WSA883X_PORT_VISENSE,
 473};
 474
 475static const char * const wsa_dev_mode_text[] = {
 476	"Speaker", "Receiver", "Ultrasound"
 477};
 478
 479enum {
 480	SPEAKER,
 481	RECEIVER,
 482	ULTRASOUND,
 483};
 484
 485static const struct soc_enum wsa_dev_mode_enum =
 486	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_dev_mode_text), wsa_dev_mode_text);
 487
 488/* 4 ports */
 489static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA883X_MAX_SWR_PORTS] = {
 490	{
 491		/* DAC */
 492		.num = 1,
 493		.type = SDW_DPN_SIMPLE,
 494		.min_ch = 1,
 495		.max_ch = 1,
 496		.simple_ch_prep_sm = true,
 497		.read_only_wordlength = true,
 498	}, {
 499		/* COMP */
 500		.num = 2,
 501		.type = SDW_DPN_SIMPLE,
 502		.min_ch = 1,
 503		.max_ch = 1,
 504		.simple_ch_prep_sm = true,
 505		.read_only_wordlength = true,
 506	}, {
 507		/* BOOST */
 508		.num = 3,
 509		.type = SDW_DPN_SIMPLE,
 510		.min_ch = 1,
 511		.max_ch = 1,
 512		.simple_ch_prep_sm = true,
 513		.read_only_wordlength = true,
 514	}, {
 515		/* VISENSE */
 516		.num = 4,
 517		.type = SDW_DPN_SIMPLE,
 518		.min_ch = 1,
 519		.max_ch = 1,
 520		.simple_ch_prep_sm = true,
 521		.read_only_wordlength = true,
 522	}
 523};
 524
 525static struct sdw_port_config wsa883x_pconfig[WSA883X_MAX_SWR_PORTS] = {
 526	{
 527		.num = 1,
 528		.ch_mask = 0x1,
 529	}, {
 530		.num = 2,
 531		.ch_mask = 0xf,
 532	}, {
 533		.num = 3,
 534		.ch_mask = 0x3,
 535	}, {	/* IV feedback */
 536		.num = 4,
 537		.ch_mask = 0x3,
 538	},
 539};
 540
 541static struct reg_default wsa883x_defaults[] = {
 542	{ WSA883X_REF_CTRL, 0xD5 },
 543	{ WSA883X_TEST_CTL_0, 0x06 },
 544	{ WSA883X_BIAS_0, 0xD2 },
 545	{ WSA883X_OP_CTL, 0xE0 },
 546	{ WSA883X_IREF_CTL, 0x57 },
 547	{ WSA883X_ISENS_CTL, 0x47 },
 548	{ WSA883X_CLK_CTL, 0x87 },
 549	{ WSA883X_TEST_CTL_1, 0x00 },
 550	{ WSA883X_BIAS_1, 0x51 },
 551	{ WSA883X_ADC_CTL, 0x01 },
 552	{ WSA883X_DOUT_MSB, 0x00 },
 553	{ WSA883X_DOUT_LSB, 0x00 },
 554	{ WSA883X_VBAT_SNS, 0x40 },
 555	{ WSA883X_ITRIM_CODE, 0x9F },
 556	{ WSA883X_EN, 0x20 },
 557	{ WSA883X_OVERRIDE1, 0x00 },
 558	{ WSA883X_OVERRIDE2, 0x08 },
 559	{ WSA883X_VSENSE1, 0xD3 },
 560	{ WSA883X_ISENSE1, 0xD4 },
 561	{ WSA883X_ISENSE2, 0x20 },
 562	{ WSA883X_ISENSE_CAL, 0x00 },
 563	{ WSA883X_MISC, 0x08 },
 564	{ WSA883X_ADC_0, 0x00 },
 565	{ WSA883X_ADC_1, 0x00 },
 566	{ WSA883X_ADC_2, 0x40 },
 567	{ WSA883X_ADC_3, 0x80 },
 568	{ WSA883X_ADC_4, 0x25 },
 569	{ WSA883X_ADC_5, 0x25 },
 570	{ WSA883X_ADC_6, 0x08 },
 571	{ WSA883X_ADC_7, 0x81 },
 572	{ WSA883X_STATUS, 0x00 },
 573	{ WSA883X_DAC_CTRL_REG, 0x53 },
 574	{ WSA883X_DAC_EN_DEBUG_REG, 0x00 },
 575	{ WSA883X_DAC_OPAMP_BIAS1_REG, 0x48 },
 576	{ WSA883X_DAC_OPAMP_BIAS2_REG, 0x48 },
 577	{ WSA883X_DAC_VCM_CTRL_REG, 0x88 },
 578	{ WSA883X_DAC_VOLTAGE_CTRL_REG, 0xA5 },
 579	{ WSA883X_ATEST1_REG, 0x00 },
 580	{ WSA883X_ATEST2_REG, 0x00 },
 581	{ WSA883X_SPKR_TOP_BIAS_REG1, 0x6A },
 582	{ WSA883X_SPKR_TOP_BIAS_REG2, 0x65 },
 583	{ WSA883X_SPKR_TOP_BIAS_REG3, 0x55 },
 584	{ WSA883X_SPKR_TOP_BIAS_REG4, 0xA9 },
 585	{ WSA883X_SPKR_CLIP_DET_REG, 0x9C },
 586	{ WSA883X_SPKR_DRV_LF_BLK_EN, 0x0F },
 587	{ WSA883X_SPKR_DRV_LF_EN, 0x0A },
 588	{ WSA883X_SPKR_DRV_LF_MASK_DCC_CTL, 0x00 },
 589	{ WSA883X_SPKR_DRV_LF_MISC_CTL, 0x3A },
 590	{ WSA883X_SPKR_DRV_LF_REG_GAIN, 0x00 },
 591	{ WSA883X_SPKR_DRV_OS_CAL_CTL, 0x00 },
 592	{ WSA883X_SPKR_DRV_OS_CAL_CTL1, 0x90 },
 593	{ WSA883X_SPKR_PWM_CLK_CTL, 0x00 },
 594	{ WSA883X_SPKR_PDRV_HS_CTL, 0x52 },
 595	{ WSA883X_SPKR_PDRV_LS_CTL, 0x48 },
 596	{ WSA883X_SPKR_PWRSTG_DBG, 0x08 },
 597	{ WSA883X_SPKR_OCP_CTL, 0xE2 },
 598	{ WSA883X_SPKR_BBM_CTL, 0x92 },
 599	{ WSA883X_PA_STATUS0, 0x00 },
 600	{ WSA883X_PA_STATUS1, 0x00 },
 601	{ WSA883X_PA_STATUS2, 0x80 },
 602	{ WSA883X_EN_CTRL, 0x44 },
 603	{ WSA883X_CURRENT_LIMIT, 0xCC },
 604	{ WSA883X_IBIAS1, 0x00 },
 605	{ WSA883X_IBIAS2, 0x00 },
 606	{ WSA883X_IBIAS3, 0x00 },
 607	{ WSA883X_LDO_PROG, 0x02 },
 608	{ WSA883X_STABILITY_CTRL1, 0x8E },
 609	{ WSA883X_STABILITY_CTRL2, 0x10 },
 610	{ WSA883X_PWRSTAGE_CTRL1, 0x06 },
 611	{ WSA883X_PWRSTAGE_CTRL2, 0x00 },
 612	{ WSA883X_BYPASS_1, 0x19 },
 613	{ WSA883X_BYPASS_2, 0x13 },
 614	{ WSA883X_ZX_CTRL_1, 0xF0 },
 615	{ WSA883X_ZX_CTRL_2, 0x04 },
 616	{ WSA883X_MISC1, 0x06 },
 617	{ WSA883X_MISC2, 0xA0 },
 618	{ WSA883X_GMAMP_SUP1, 0x82 },
 619	{ WSA883X_PWRSTAGE_CTRL3, 0x39 },
 620	{ WSA883X_PWRSTAGE_CTRL4, 0x5F },
 621	{ WSA883X_TEST1, 0x00 },
 622	{ WSA883X_SPARE1, 0x00 },
 623	{ WSA883X_SPARE2, 0x00 },
 624	{ WSA883X_PON_CTL_0, 0x10 },
 625	{ WSA883X_PON_CLT_1, 0xE0 },
 626	{ WSA883X_PON_CTL_2, 0x90 },
 627	{ WSA883X_PON_CTL_3, 0x70 },
 628	{ WSA883X_CKWD_CTL_0, 0x34 },
 629	{ WSA883X_CKWD_CTL_1, 0x0F },
 630	{ WSA883X_CKWD_CTL_2, 0x00 },
 631	{ WSA883X_CKSK_CTL_0, 0x00 },
 632	{ WSA883X_PADSW_CTL_0, 0x00 },
 633	{ WSA883X_TEST_0, 0x00 },
 634	{ WSA883X_TEST_1, 0x00 },
 635	{ WSA883X_STATUS_0, 0x00 },
 636	{ WSA883X_STATUS_1, 0x00 },
 637	{ WSA883X_CHIP_ID0, 0x00 },
 638	{ WSA883X_CHIP_ID1, 0x00 },
 639	{ WSA883X_CHIP_ID2, 0x02 },
 640	{ WSA883X_CHIP_ID3, 0x02 },
 641	{ WSA883X_BUS_ID, 0x00 },
 642	{ WSA883X_CDC_RST_CTL, 0x01 },
 643	{ WSA883X_TOP_CLK_CFG, 0x00 },
 644	{ WSA883X_CDC_PATH_MODE, 0x00 },
 645	{ WSA883X_CDC_CLK_CTL, 0xFF },
 646	{ WSA883X_SWR_RESET_EN, 0x00 },
 647	{ WSA883X_RESET_CTL, 0x00 },
 648	{ WSA883X_PA_FSM_CTL, 0x00 },
 649	{ WSA883X_PA_FSM_TIMER0, 0x80 },
 650	{ WSA883X_PA_FSM_TIMER1, 0x80 },
 651	{ WSA883X_PA_FSM_STA, 0x00 },
 652	{ WSA883X_PA_FSM_ERR_COND, 0x00 },
 653	{ WSA883X_PA_FSM_MSK, 0x00 },
 654	{ WSA883X_PA_FSM_BYP, 0x01 },
 655	{ WSA883X_PA_FSM_DBG, 0x00 },
 656	{ WSA883X_TADC_VALUE_CTL, 0x03 },
 657	{ WSA883X_TEMP_DETECT_CTL, 0x01 },
 658	{ WSA883X_TEMP_MSB, 0x00 },
 659	{ WSA883X_TEMP_LSB, 0x00 },
 660	{ WSA883X_TEMP_CONFIG0, 0x00 },
 661	{ WSA883X_TEMP_CONFIG1, 0x00 },
 662	{ WSA883X_VBAT_ADC_FLT_CTL, 0x00 },
 663	{ WSA883X_VBAT_DIN_MSB, 0x00 },
 664	{ WSA883X_VBAT_DIN_LSB, 0x00 },
 665	{ WSA883X_VBAT_DOUT, 0x00 },
 666	{ WSA883X_SDM_PDM9_LSB, 0x00 },
 667	{ WSA883X_SDM_PDM9_MSB, 0x00 },
 668	{ WSA883X_CDC_RX_CTL, 0xFE },
 669	{ WSA883X_CDC_SPK_DSM_A1_0, 0x00 },
 670	{ WSA883X_CDC_SPK_DSM_A1_1, 0x01 },
 671	{ WSA883X_CDC_SPK_DSM_A2_0, 0x96 },
 672	{ WSA883X_CDC_SPK_DSM_A2_1, 0x09 },
 673	{ WSA883X_CDC_SPK_DSM_A3_0, 0xAB },
 674	{ WSA883X_CDC_SPK_DSM_A3_1, 0x05 },
 675	{ WSA883X_CDC_SPK_DSM_A4_0, 0x1C },
 676	{ WSA883X_CDC_SPK_DSM_A4_1, 0x02 },
 677	{ WSA883X_CDC_SPK_DSM_A5_0, 0x17 },
 678	{ WSA883X_CDC_SPK_DSM_A5_1, 0x02 },
 679	{ WSA883X_CDC_SPK_DSM_A6_0, 0xAA },
 680	{ WSA883X_CDC_SPK_DSM_A7_0, 0xE3 },
 681	{ WSA883X_CDC_SPK_DSM_C_0, 0x69 },
 682	{ WSA883X_CDC_SPK_DSM_C_1, 0x54 },
 683	{ WSA883X_CDC_SPK_DSM_C_2, 0x02 },
 684	{ WSA883X_CDC_SPK_DSM_C_3, 0x15 },
 685	{ WSA883X_CDC_SPK_DSM_R1, 0xA4 },
 686	{ WSA883X_CDC_SPK_DSM_R2, 0xB5 },
 687	{ WSA883X_CDC_SPK_DSM_R3, 0x86 },
 688	{ WSA883X_CDC_SPK_DSM_R4, 0x85 },
 689	{ WSA883X_CDC_SPK_DSM_R5, 0xAA },
 690	{ WSA883X_CDC_SPK_DSM_R6, 0xE2 },
 691	{ WSA883X_CDC_SPK_DSM_R7, 0x62 },
 692	{ WSA883X_CDC_SPK_GAIN_PDM_0, 0x00 },
 693	{ WSA883X_CDC_SPK_GAIN_PDM_1, 0xFC },
 694	{ WSA883X_CDC_SPK_GAIN_PDM_2, 0x05 },
 695	{ WSA883X_PDM_WD_CTL, 0x00 },
 696	{ WSA883X_DEM_BYPASS_DATA0, 0x00 },
 697	{ WSA883X_DEM_BYPASS_DATA1, 0x00 },
 698	{ WSA883X_DEM_BYPASS_DATA2, 0x00 },
 699	{ WSA883X_DEM_BYPASS_DATA3, 0x00 },
 700	{ WSA883X_WAVG_CTL, 0x06 },
 701	{ WSA883X_WAVG_LRA_PER_0, 0xD1 },
 702	{ WSA883X_WAVG_LRA_PER_1, 0x00 },
 703	{ WSA883X_WAVG_DELTA_THETA_0, 0xE6 },
 704	{ WSA883X_WAVG_DELTA_THETA_1, 0x04 },
 705	{ WSA883X_WAVG_DIRECT_AMP_0, 0x50 },
 706	{ WSA883X_WAVG_DIRECT_AMP_1, 0x00 },
 707	{ WSA883X_WAVG_PTRN_AMP0_0, 0x50 },
 708	{ WSA883X_WAVG_PTRN_AMP0_1, 0x00 },
 709	{ WSA883X_WAVG_PTRN_AMP1_0, 0x50 },
 710	{ WSA883X_WAVG_PTRN_AMP1_1, 0x00 },
 711	{ WSA883X_WAVG_PTRN_AMP2_0, 0x50 },
 712	{ WSA883X_WAVG_PTRN_AMP2_1, 0x00 },
 713	{ WSA883X_WAVG_PTRN_AMP3_0, 0x50 },
 714	{ WSA883X_WAVG_PTRN_AMP3_1, 0x00 },
 715	{ WSA883X_WAVG_PTRN_AMP4_0, 0x50 },
 716	{ WSA883X_WAVG_PTRN_AMP4_1, 0x00 },
 717	{ WSA883X_WAVG_PTRN_AMP5_0, 0x50 },
 718	{ WSA883X_WAVG_PTRN_AMP5_1, 0x00 },
 719	{ WSA883X_WAVG_PTRN_AMP6_0, 0x50 },
 720	{ WSA883X_WAVG_PTRN_AMP6_1, 0x00 },
 721	{ WSA883X_WAVG_PTRN_AMP7_0, 0x50 },
 722	{ WSA883X_WAVG_PTRN_AMP7_1, 0x00 },
 723	{ WSA883X_WAVG_PER_0_1, 0x88 },
 724	{ WSA883X_WAVG_PER_2_3, 0x88 },
 725	{ WSA883X_WAVG_PER_4_5, 0x88 },
 726	{ WSA883X_WAVG_PER_6_7, 0x88 },
 727	{ WSA883X_WAVG_STA, 0x00 },
 728	{ WSA883X_DRE_CTL_0, 0x70 },
 729	{ WSA883X_DRE_CTL_1, 0x08 },
 730	{ WSA883X_DRE_IDLE_DET_CTL, 0x1F },
 731	{ WSA883X_CLSH_CTL_0, 0x37 },
 732	{ WSA883X_CLSH_CTL_1, 0x81 },
 733	{ WSA883X_CLSH_V_HD_PA, 0x0F },
 734	{ WSA883X_CLSH_V_PA_MIN, 0x00 },
 735	{ WSA883X_CLSH_OVRD_VAL, 0x00 },
 736	{ WSA883X_CLSH_HARD_MAX, 0xFF },
 737	{ WSA883X_CLSH_SOFT_MAX, 0xF5 },
 738	{ WSA883X_CLSH_SIG_DP, 0x00 },
 739	{ WSA883X_TAGC_CTL, 0x10 },
 740	{ WSA883X_TAGC_TIME, 0x20 },
 741	{ WSA883X_TAGC_E2E_GAIN, 0x02 },
 742	{ WSA883X_TAGC_FORCE_VAL, 0x00 },
 743	{ WSA883X_VAGC_CTL, 0x00 },
 744	{ WSA883X_VAGC_TIME, 0x08 },
 745	{ WSA883X_VAGC_ATTN_LVL_1_2, 0x21 },
 746	{ WSA883X_VAGC_ATTN_LVL_3, 0x03 },
 747	{ WSA883X_INTR_MODE, 0x00 },
 748	{ WSA883X_INTR_MASK0, 0x90 },
 749	{ WSA883X_INTR_MASK1, 0x00 },
 750	{ WSA883X_INTR_STATUS0, 0x00 },
 751	{ WSA883X_INTR_STATUS1, 0x00 },
 752	{ WSA883X_INTR_CLEAR0, 0x00 },
 753	{ WSA883X_INTR_CLEAR1, 0x00 },
 754	{ WSA883X_INTR_LEVEL0, 0x00 },
 755	{ WSA883X_INTR_LEVEL1, 0x00 },
 756	{ WSA883X_INTR_SET0, 0x00 },
 757	{ WSA883X_INTR_SET1, 0x00 },
 758	{ WSA883X_INTR_TEST0, 0x00 },
 759	{ WSA883X_INTR_TEST1, 0x00 },
 760	{ WSA883X_OTP_CTRL0, 0x00 },
 761	{ WSA883X_OTP_CTRL1, 0x00 },
 762	{ WSA883X_HDRIVE_CTL_GROUP1, 0x00 },
 763	{ WSA883X_PIN_CTL, 0x04 },
 764	{ WSA883X_PIN_CTL_OE, 0x00 },
 765	{ WSA883X_PIN_WDATA_IOPAD, 0x00 },
 766	{ WSA883X_PIN_STATUS, 0x00 },
 767	{ WSA883X_I2C_SLAVE_CTL, 0x00 },
 768	{ WSA883X_PDM_TEST_MODE, 0x00 },
 769	{ WSA883X_ATE_TEST_MODE, 0x00 },
 770	{ WSA883X_DIG_DEBUG_MODE, 0x00 },
 771	{ WSA883X_DIG_DEBUG_SEL, 0x00 },
 772	{ WSA883X_DIG_DEBUG_EN, 0x00 },
 773	{ WSA883X_SWR_HM_TEST0, 0x08 },
 774	{ WSA883X_SWR_HM_TEST1, 0x00 },
 775	{ WSA883X_SWR_PAD_CTL, 0x37 },
 776	{ WSA883X_TADC_DETECT_DBG_CTL, 0x00 },
 777	{ WSA883X_TADC_DEBUG_MSB, 0x00 },
 778	{ WSA883X_TADC_DEBUG_LSB, 0x00 },
 779	{ WSA883X_SAMPLE_EDGE_SEL, 0x7F },
 780	{ WSA883X_SWR_EDGE_SEL, 0x00 },
 781	{ WSA883X_TEST_MODE_CTL, 0x04 },
 782	{ WSA883X_IOPAD_CTL, 0x00 },
 783	{ WSA883X_ANA_CSR_DBG_ADD, 0x00 },
 784	{ WSA883X_ANA_CSR_DBG_CTL, 0x12 },
 785	{ WSA883X_SPARE_R, 0x00 },
 786	{ WSA883X_SPARE_0, 0x00 },
 787	{ WSA883X_SPARE_1, 0x00 },
 788	{ WSA883X_SPARE_2, 0x00 },
 789	{ WSA883X_SCODE, 0x00 },
 790	{ WSA883X_OTP_REG_0, 0x05 },
 791	{ WSA883X_OTP_REG_1, 0xFF },
 792	{ WSA883X_OTP_REG_2, 0xC0 },
 793	{ WSA883X_OTP_REG_3, 0xFF },
 794	{ WSA883X_OTP_REG_4, 0xC0 },
 795	{ WSA883X_OTP_REG_5, 0xFF },
 796	{ WSA883X_OTP_REG_6, 0xFF },
 797	{ WSA883X_OTP_REG_7, 0xFF },
 798	{ WSA883X_OTP_REG_8, 0xFF },
 799	{ WSA883X_OTP_REG_9, 0xFF },
 800	{ WSA883X_OTP_REG_10, 0xFF },
 801	{ WSA883X_OTP_REG_11, 0xFF },
 802	{ WSA883X_OTP_REG_12, 0xFF },
 803	{ WSA883X_OTP_REG_13, 0xFF },
 804	{ WSA883X_OTP_REG_14, 0xFF },
 805	{ WSA883X_OTP_REG_15, 0xFF },
 806	{ WSA883X_OTP_REG_16, 0xFF },
 807	{ WSA883X_OTP_REG_17, 0xFF },
 808	{ WSA883X_OTP_REG_18, 0xFF },
 809	{ WSA883X_OTP_REG_19, 0xFF },
 810	{ WSA883X_OTP_REG_20, 0xFF },
 811	{ WSA883X_OTP_REG_21, 0xFF },
 812	{ WSA883X_OTP_REG_22, 0xFF },
 813	{ WSA883X_OTP_REG_23, 0xFF },
 814	{ WSA883X_OTP_REG_24, 0x37 },
 815	{ WSA883X_OTP_REG_25, 0x3F },
 816	{ WSA883X_OTP_REG_26, 0x03 },
 817	{ WSA883X_OTP_REG_27, 0x00 },
 818	{ WSA883X_OTP_REG_28, 0x00 },
 819	{ WSA883X_OTP_REG_29, 0x00 },
 820	{ WSA883X_OTP_REG_30, 0x00 },
 821	{ WSA883X_OTP_REG_31, 0x03 },
 822	{ WSA883X_OTP_REG_32, 0x00 },
 823	{ WSA883X_OTP_REG_33, 0xFF },
 824	{ WSA883X_OTP_REG_34, 0x00 },
 825	{ WSA883X_OTP_REG_35, 0x00 },
 826	{ WSA883X_OTP_REG_63, 0x40 },
 827	{ WSA883X_EMEM_0, 0x00 },
 828	{ WSA883X_EMEM_1, 0x00 },
 829	{ WSA883X_EMEM_2, 0x00 },
 830	{ WSA883X_EMEM_3, 0x00 },
 831	{ WSA883X_EMEM_4, 0x00 },
 832	{ WSA883X_EMEM_5, 0x00 },
 833	{ WSA883X_EMEM_6, 0x00 },
 834	{ WSA883X_EMEM_7, 0x00 },
 835	{ WSA883X_EMEM_8, 0x00 },
 836	{ WSA883X_EMEM_9, 0x00 },
 837	{ WSA883X_EMEM_10, 0x00 },
 838	{ WSA883X_EMEM_11, 0x00 },
 839	{ WSA883X_EMEM_12, 0x00 },
 840	{ WSA883X_EMEM_13, 0x00 },
 841	{ WSA883X_EMEM_14, 0x00 },
 842	{ WSA883X_EMEM_15, 0x00 },
 843	{ WSA883X_EMEM_16, 0x00 },
 844	{ WSA883X_EMEM_17, 0x00 },
 845	{ WSA883X_EMEM_18, 0x00 },
 846	{ WSA883X_EMEM_19, 0x00 },
 847	{ WSA883X_EMEM_20, 0x00 },
 848	{ WSA883X_EMEM_21, 0x00 },
 849	{ WSA883X_EMEM_22, 0x00 },
 850	{ WSA883X_EMEM_23, 0x00 },
 851	{ WSA883X_EMEM_24, 0x00 },
 852	{ WSA883X_EMEM_25, 0x00 },
 853	{ WSA883X_EMEM_26, 0x00 },
 854	{ WSA883X_EMEM_27, 0x00 },
 855	{ WSA883X_EMEM_28, 0x00 },
 856	{ WSA883X_EMEM_29, 0x00 },
 857	{ WSA883X_EMEM_30, 0x00 },
 858	{ WSA883X_EMEM_31, 0x00 },
 859	{ WSA883X_EMEM_32, 0x00 },
 860	{ WSA883X_EMEM_33, 0x00 },
 861	{ WSA883X_EMEM_34, 0x00 },
 862	{ WSA883X_EMEM_35, 0x00 },
 863	{ WSA883X_EMEM_36, 0x00 },
 864	{ WSA883X_EMEM_37, 0x00 },
 865	{ WSA883X_EMEM_38, 0x00 },
 866	{ WSA883X_EMEM_39, 0x00 },
 867	{ WSA883X_EMEM_40, 0x00 },
 868	{ WSA883X_EMEM_41, 0x00 },
 869	{ WSA883X_EMEM_42, 0x00 },
 870	{ WSA883X_EMEM_43, 0x00 },
 871	{ WSA883X_EMEM_44, 0x00 },
 872	{ WSA883X_EMEM_45, 0x00 },
 873	{ WSA883X_EMEM_46, 0x00 },
 874	{ WSA883X_EMEM_47, 0x00 },
 875	{ WSA883X_EMEM_48, 0x00 },
 876	{ WSA883X_EMEM_49, 0x00 },
 877	{ WSA883X_EMEM_50, 0x00 },
 878	{ WSA883X_EMEM_51, 0x00 },
 879	{ WSA883X_EMEM_52, 0x00 },
 880	{ WSA883X_EMEM_53, 0x00 },
 881	{ WSA883X_EMEM_54, 0x00 },
 882	{ WSA883X_EMEM_55, 0x00 },
 883	{ WSA883X_EMEM_56, 0x00 },
 884	{ WSA883X_EMEM_57, 0x00 },
 885	{ WSA883X_EMEM_58, 0x00 },
 886	{ WSA883X_EMEM_59, 0x00 },
 887	{ WSA883X_EMEM_60, 0x00 },
 888	{ WSA883X_EMEM_61, 0x00 },
 889	{ WSA883X_EMEM_62, 0x00 },
 890	{ WSA883X_EMEM_63, 0x00 },
 891};
 892
 893static bool wsa883x_readonly_register(struct device *dev, unsigned int reg)
 894{
 895	switch (reg) {
 896	case WSA883X_DOUT_MSB:
 897	case WSA883X_DOUT_LSB:
 898	case WSA883X_STATUS:
 899	case WSA883X_PA_STATUS0:
 900	case WSA883X_PA_STATUS1:
 901	case WSA883X_PA_STATUS2:
 902	case WSA883X_STATUS_0:
 903	case WSA883X_STATUS_1:
 904	case WSA883X_CHIP_ID0:
 905	case WSA883X_CHIP_ID1:
 906	case WSA883X_CHIP_ID2:
 907	case WSA883X_CHIP_ID3:
 908	case WSA883X_BUS_ID:
 909	case WSA883X_PA_FSM_STA:
 910	case WSA883X_PA_FSM_ERR_COND:
 911	case WSA883X_TEMP_MSB:
 912	case WSA883X_TEMP_LSB:
 913	case WSA883X_VBAT_DIN_MSB:
 914	case WSA883X_VBAT_DIN_LSB:
 915	case WSA883X_VBAT_DOUT:
 916	case WSA883X_SDM_PDM9_LSB:
 917	case WSA883X_SDM_PDM9_MSB:
 918	case WSA883X_WAVG_STA:
 919	case WSA883X_INTR_STATUS0:
 920	case WSA883X_INTR_STATUS1:
 921	case WSA883X_OTP_CTRL1:
 922	case WSA883X_PIN_STATUS:
 923	case WSA883X_ATE_TEST_MODE:
 924	case WSA883X_SWR_HM_TEST1:
 925	case WSA883X_SPARE_R:
 926	case WSA883X_OTP_REG_0:
 927		return true;
 928	}
 929	return false;
 930}
 931
 932static bool wsa883x_writeable_register(struct device *dev, unsigned int reg)
 933{
 934	return !wsa883x_readonly_register(dev, reg);
 935}
 936
 937static bool wsa883x_volatile_register(struct device *dev, unsigned int reg)
 938{
 939	return wsa883x_readonly_register(dev, reg);
 940}
 941
 942static struct regmap_config wsa883x_regmap_config = {
 943	.reg_bits = 32,
 944	.val_bits = 8,
 945	.cache_type = REGCACHE_RBTREE,
 946	.reg_defaults = wsa883x_defaults,
 947	.max_register = WSA883X_MAX_REGISTER,
 948	.num_reg_defaults = ARRAY_SIZE(wsa883x_defaults),
 949	.volatile_reg = wsa883x_volatile_register,
 950	.writeable_reg = wsa883x_writeable_register,
 951	.reg_format_endian = REGMAP_ENDIAN_NATIVE,
 952	.val_format_endian = REGMAP_ENDIAN_NATIVE,
 953	.can_multi_write = true,
 954	.use_single_read = true,
 955};
 956
 957static const struct reg_sequence reg_init[] = {
 958	{WSA883X_PA_FSM_BYP, 0x00},
 959	{WSA883X_ADC_6, 0x02},
 960	{WSA883X_CDC_SPK_DSM_A2_0, 0x0A},
 961	{WSA883X_CDC_SPK_DSM_A2_1, 0x08},
 962	{WSA883X_CDC_SPK_DSM_A3_0, 0xF3},
 963	{WSA883X_CDC_SPK_DSM_A3_1, 0x07},
 964	{WSA883X_CDC_SPK_DSM_A4_0, 0x79},
 965	{WSA883X_CDC_SPK_DSM_A4_1, 0x02},
 966	{WSA883X_CDC_SPK_DSM_A5_0, 0x0B},
 967	{WSA883X_CDC_SPK_DSM_A5_1, 0x02},
 968	{WSA883X_CDC_SPK_DSM_A6_0, 0x8A},
 969	{WSA883X_CDC_SPK_DSM_A7_0, 0x9B},
 970	{WSA883X_CDC_SPK_DSM_C_0, 0x68},
 971	{WSA883X_CDC_SPK_DSM_C_1, 0x54},
 972	{WSA883X_CDC_SPK_DSM_C_2, 0xF2},
 973	{WSA883X_CDC_SPK_DSM_C_3, 0x20},
 974	{WSA883X_CDC_SPK_DSM_R1, 0x83},
 975	{WSA883X_CDC_SPK_DSM_R2, 0x7F},
 976	{WSA883X_CDC_SPK_DSM_R3, 0x9D},
 977	{WSA883X_CDC_SPK_DSM_R4, 0x82},
 978	{WSA883X_CDC_SPK_DSM_R5, 0x8B},
 979	{WSA883X_CDC_SPK_DSM_R6, 0x9B},
 980	{WSA883X_CDC_SPK_DSM_R7, 0x3F},
 981	{WSA883X_VBAT_SNS, 0x20},
 982	{WSA883X_DRE_CTL_0, 0x92},
 983	{WSA883X_DRE_IDLE_DET_CTL, 0x0F},
 984	{WSA883X_CURRENT_LIMIT, 0xC4},
 985	{WSA883X_VAGC_TIME, 0x0F},
 986	{WSA883X_VAGC_ATTN_LVL_1_2, 0x00},
 987	{WSA883X_VAGC_ATTN_LVL_3, 0x01},
 988	{WSA883X_VAGC_CTL, 0x01},
 989	{WSA883X_TAGC_CTL, 0x1A},
 990	{WSA883X_TAGC_TIME, 0x2C},
 991	{WSA883X_TEMP_CONFIG0, 0x02},
 992	{WSA883X_TEMP_CONFIG1, 0x02},
 993	{WSA883X_OTP_REG_1, 0x49},
 994	{WSA883X_OTP_REG_2, 0x80},
 995	{WSA883X_OTP_REG_3, 0xC9},
 996	{WSA883X_OTP_REG_4, 0x40},
 997	{WSA883X_TAGC_CTL, 0x1B},
 998	{WSA883X_ADC_2, 0x00},
 999	{WSA883X_ADC_7, 0x85},
1000	{WSA883X_ADC_7, 0x87},
1001	{WSA883X_CKWD_CTL_0, 0x14},
1002	{WSA883X_CKWD_CTL_1, 0x1B},
1003	{WSA883X_GMAMP_SUP1, 0xE2},
1004};
1005
1006static void wsa883x_init(struct wsa883x_priv *wsa883x)
1007{
1008	struct regmap *regmap = wsa883x->regmap;
1009	int variant, version;
1010
1011	regmap_read(regmap, WSA883X_OTP_REG_0, &variant);
1012	wsa883x->variant = variant & WSA883X_ID_MASK;
1013
1014	regmap_read(regmap, WSA883X_CHIP_ID0, &version);
1015	wsa883x->version = version;
1016
1017	switch (wsa883x->variant) {
1018	case WSA8830:
1019		dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8830\n",
1020			 wsa883x->version);
1021		break;
1022	case WSA8835:
1023		dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8835\n",
1024			 wsa883x->version);
1025		break;
1026	case WSA8832:
1027		dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8832\n",
1028			 wsa883x->version);
1029		break;
1030	case WSA8835_V2:
1031		dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8835_V2\n",
1032			 wsa883x->version);
1033		break;
1034	default:
1035		break;
1036	}
1037
1038	wsa883x->comp_offset = COMP_OFFSET2;
1039
1040	/* Initial settings */
1041	regmap_multi_reg_write(regmap, reg_init, ARRAY_SIZE(reg_init));
1042
1043	if (wsa883x->variant == WSA8830 || wsa883x->variant == WSA8832) {
1044		wsa883x->comp_offset = COMP_OFFSET3;
1045		regmap_update_bits(regmap, WSA883X_DRE_CTL_0,
1046				   WSA883X_DRE_OFFSET_MASK,
1047				   wsa883x->comp_offset);
1048	}
1049}
1050
1051static int wsa883x_update_status(struct sdw_slave *slave,
1052				 enum sdw_slave_status status)
1053{
1054	struct wsa883x_priv *wsa883x = dev_get_drvdata(&slave->dev);
1055
1056	if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0)
1057		wsa883x_init(wsa883x);
1058
1059	return 0;
1060}
1061
1062static int wsa883x_port_prep(struct sdw_slave *slave,
1063			     struct sdw_prepare_ch *prepare_ch,
1064			     enum sdw_port_prep_ops state)
1065{
1066	struct wsa883x_priv *wsa883x = dev_get_drvdata(&slave->dev);
1067
1068	if (state == SDW_OPS_PORT_POST_PREP)
1069		wsa883x->port_prepared[prepare_ch->num - 1] = true;
1070	else
1071		wsa883x->port_prepared[prepare_ch->num - 1] = false;
1072
1073	return 0;
1074}
1075
1076static struct sdw_slave_ops wsa883x_slave_ops = {
1077	.update_status = wsa883x_update_status,
1078	.port_prep = wsa883x_port_prep,
1079};
1080
1081static int wsa_dev_mode_get(struct snd_kcontrol *kcontrol,
1082			    struct snd_ctl_elem_value *ucontrol)
1083{
1084	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1085	struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1086
1087	ucontrol->value.enumerated.item[0] = wsa883x->dev_mode;
1088
1089	return 0;
1090}
1091
1092static int wsa_dev_mode_put(struct snd_kcontrol *kcontrol,
1093			    struct snd_ctl_elem_value *ucontrol)
1094{
1095	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1096	struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1097
1098	if (wsa883x->dev_mode == ucontrol->value.enumerated.item[0])
1099		return 0;
1100
1101	wsa883x->dev_mode = ucontrol->value.enumerated.item[0];
1102
1103	return 1;
1104}
1105
1106static const DECLARE_TLV_DB_SCALE(pa_gain, -300, 150, -300);
 
 
 
 
1107
1108static int wsa883x_get_swr_port(struct snd_kcontrol *kcontrol,
1109				struct snd_ctl_elem_value *ucontrol)
1110{
1111	struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1112	struct wsa883x_priv *data = snd_soc_component_get_drvdata(comp);
1113	struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1114	int portidx = mixer->reg;
1115
1116	ucontrol->value.integer.value[0] = data->port_enable[portidx];
1117
1118	return 0;
1119}
1120
1121static int wsa883x_set_swr_port(struct snd_kcontrol *kcontrol,
1122				struct snd_ctl_elem_value *ucontrol)
1123{
1124	struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1125	struct wsa883x_priv *data = snd_soc_component_get_drvdata(comp);
1126	struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1127	int portidx = mixer->reg;
1128
1129	if (ucontrol->value.integer.value[0]) {
1130		if (data->port_enable[portidx])
1131			return 0;
1132
1133		data->port_enable[portidx] = true;
1134	} else {
1135		if (!data->port_enable[portidx])
1136			return 0;
1137
1138		data->port_enable[portidx] = false;
1139	}
1140
1141	return 1;
1142}
1143
1144static int wsa883x_get_comp_offset(struct snd_kcontrol *kcontrol,
1145				   struct snd_ctl_elem_value *ucontrol)
1146{
1147	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1148	struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1149
1150	ucontrol->value.integer.value[0] = wsa883x->comp_offset;
1151
1152	return 0;
1153}
1154
1155static int wsa883x_set_comp_offset(struct snd_kcontrol *kcontrol,
1156				   struct snd_ctl_elem_value *ucontrol)
1157{
1158	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1159	struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1160
1161	if (wsa883x->comp_offset == ucontrol->value.integer.value[0])
1162		return 0;
1163
1164	wsa883x->comp_offset = ucontrol->value.integer.value[0];
1165
1166	return 1;
1167}
1168
1169static int wsa883x_codec_probe(struct snd_soc_component *comp)
1170{
1171	struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(comp);
1172
1173	snd_soc_component_init_regmap(comp, wsa883x->regmap);
1174
1175	return 0;
1176}
1177
1178static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w,
1179			      struct snd_kcontrol *kcontrol, int event)
1180{
1181	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1182	struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1183
1184	switch (event) {
1185	case SND_SOC_DAPM_POST_PMU:
1186		switch (wsa883x->dev_mode) {
1187		case RECEIVER:
1188			snd_soc_component_write_field(component, WSA883X_CDC_PATH_MODE,
1189						      WSA883X_RXD_MODE_MASK,
1190						      WSA883X_RXD_MODE_HIFI);
1191			snd_soc_component_write_field(component, WSA883X_SPKR_PWM_CLK_CTL,
1192						      WSA883X_SPKR_PWM_FREQ_SEL_MASK,
1193						      WSA883X_SPKR_PWM_FREQ_F600KHZ);
1194			snd_soc_component_write_field(component, WSA883X_DRE_CTL_0,
1195						       WSA883X_DRE_PROG_DELAY_MASK, 0x0);
1196			break;
1197		case SPEAKER:
1198			snd_soc_component_write_field(component, WSA883X_CDC_PATH_MODE,
1199						      WSA883X_RXD_MODE_MASK,
1200						      WSA883X_RXD_MODE_NORMAL);
1201			snd_soc_component_write_field(component, WSA883X_SPKR_PWM_CLK_CTL,
1202						      WSA883X_SPKR_PWM_FREQ_SEL_MASK,
1203						      WSA883X_SPKR_PWM_FREQ_F300KHZ);
1204			snd_soc_component_write_field(component, WSA883X_DRE_CTL_0,
1205						       WSA883X_DRE_PROG_DELAY_MASK, 0x9);
1206			break;
1207		default:
1208			break;
1209		}
1210
1211		snd_soc_component_write_field(component, WSA883X_DRE_CTL_1,
1212					      WSA883X_DRE_GAIN_EN_MASK,
1213					      WSA883X_DRE_GAIN_FROM_CSR);
1214		if (wsa883x->port_enable[WSA883X_PORT_COMP])
1215			snd_soc_component_write_field(component, WSA883X_DRE_CTL_0,
1216						      WSA883X_DRE_OFFSET_MASK,
1217						      wsa883x->comp_offset);
1218		snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
1219					      WSA883X_VBAT_ADC_COEF_SEL_MASK,
1220					      WSA883X_VBAT_ADC_COEF_F_1DIV16);
1221		snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
1222					      WSA883X_VBAT_ADC_FLT_EN_MASK, 0x1);
1223		snd_soc_component_write_field(component, WSA883X_PDM_WD_CTL,
1224					      WSA883X_PDM_EN_MASK,
1225					      WSA883X_PDM_ENABLE);
1226		snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
1227					      WSA883X_GLOBAL_PA_EN_MASK,
1228					      WSA883X_GLOBAL_PA_ENABLE);
1229
1230		break;
1231	case SND_SOC_DAPM_PRE_PMD:
1232		snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
1233					      WSA883X_VBAT_ADC_FLT_EN_MASK, 0x0);
1234		snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
1235					      WSA883X_VBAT_ADC_COEF_SEL_MASK,
1236					      WSA883X_VBAT_ADC_COEF_F_1DIV2);
1237		snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
1238					      WSA883X_GLOBAL_PA_EN_MASK, 0);
1239		snd_soc_component_write_field(component, WSA883X_PDM_WD_CTL,
1240					      WSA883X_PDM_EN_MASK, 0);
1241		break;
1242	}
1243	return 0;
1244}
1245
1246static const struct snd_soc_dapm_widget wsa883x_dapm_widgets[] = {
1247	SND_SOC_DAPM_INPUT("IN"),
1248	SND_SOC_DAPM_SPK("SPKR", wsa883x_spkr_event),
1249};
1250
1251static const struct snd_kcontrol_new wsa883x_snd_controls[] = {
1252	SOC_SINGLE_RANGE_TLV("PA Volume", WSA883X_DRE_CTL_1, 1,
1253			     0x0, 0x1f, 1, pa_gain),
1254	SOC_ENUM_EXT("WSA MODE", wsa_dev_mode_enum,
1255		     wsa_dev_mode_get, wsa_dev_mode_put),
1256	SOC_SINGLE_EXT("COMP Offset", SND_SOC_NOPM, 0, 4, 0,
1257		       wsa883x_get_comp_offset, wsa883x_set_comp_offset),
1258	SOC_SINGLE_EXT("DAC Switch", WSA883X_PORT_DAC, 0, 1, 0,
1259		       wsa883x_get_swr_port, wsa883x_set_swr_port),
1260	SOC_SINGLE_EXT("COMP Switch", WSA883X_PORT_COMP, 0, 1, 0,
1261		       wsa883x_get_swr_port, wsa883x_set_swr_port),
1262	SOC_SINGLE_EXT("BOOST Switch", WSA883X_PORT_BOOST, 0, 1, 0,
1263		       wsa883x_get_swr_port, wsa883x_set_swr_port),
1264	SOC_SINGLE_EXT("VISENSE Switch", WSA883X_PORT_VISENSE, 0, 1, 0,
1265		       wsa883x_get_swr_port, wsa883x_set_swr_port),
1266};
1267
1268static const struct snd_soc_dapm_route wsa883x_audio_map[] = {
1269	{"SPKR", NULL, "IN"},
1270};
1271
1272static const struct snd_soc_component_driver wsa883x_component_drv = {
1273	.name = "WSA883x",
1274	.probe = wsa883x_codec_probe,
1275	.controls = wsa883x_snd_controls,
1276	.num_controls = ARRAY_SIZE(wsa883x_snd_controls),
1277	.dapm_widgets = wsa883x_dapm_widgets,
1278	.num_dapm_widgets = ARRAY_SIZE(wsa883x_dapm_widgets),
1279	.dapm_routes = wsa883x_audio_map,
1280	.num_dapm_routes = ARRAY_SIZE(wsa883x_audio_map),
1281};
1282
1283static int wsa883x_hw_params(struct snd_pcm_substream *substream,
1284			     struct snd_pcm_hw_params *params,
1285			     struct snd_soc_dai *dai)
1286{
1287	struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
1288	int i;
1289
1290	wsa883x->active_ports = 0;
1291	for (i = 0; i < WSA883X_MAX_SWR_PORTS; i++) {
1292		if (!wsa883x->port_enable[i])
1293			continue;
1294
1295		wsa883x->port_config[wsa883x->active_ports] = wsa883x_pconfig[i];
1296		wsa883x->active_ports++;
1297	}
1298
1299	wsa883x->sconfig.frame_rate = params_rate(params);
1300
1301	return sdw_stream_add_slave(wsa883x->slave, &wsa883x->sconfig,
1302				    wsa883x->port_config, wsa883x->active_ports,
1303				    wsa883x->sruntime);
1304}
1305
1306static int wsa883x_hw_free(struct snd_pcm_substream *substream,
1307			   struct snd_soc_dai *dai)
1308{
1309	struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
1310
1311	sdw_stream_remove_slave(wsa883x->slave, wsa883x->sruntime);
1312
1313	return 0;
1314}
1315
1316static int wsa883x_set_sdw_stream(struct snd_soc_dai *dai,
1317				  void *stream, int direction)
1318{
1319	struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
1320
1321	wsa883x->sruntime = stream;
1322
1323	return 0;
1324}
1325
1326static int wsa883x_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1327{
1328	struct snd_soc_component *component = dai->component;
1329
1330	if (mute) {
1331		snd_soc_component_write_field(component, WSA883X_DRE_CTL_1,
1332					      WSA883X_DRE_GAIN_EN_MASK, 0);
1333		snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
1334					      WSA883X_GLOBAL_PA_EN_MASK, 0);
1335
1336	} else {
1337		snd_soc_component_write_field(component, WSA883X_DRE_CTL_1,
1338					      WSA883X_DRE_GAIN_EN_MASK,
1339					      WSA883X_DRE_GAIN_FROM_CSR);
1340		snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
1341					      WSA883X_GLOBAL_PA_EN_MASK, 1);
 
1342
1343	}
1344
1345	return 0;
1346}
1347
1348static const struct snd_soc_dai_ops wsa883x_dai_ops = {
1349	.hw_params = wsa883x_hw_params,
1350	.hw_free = wsa883x_hw_free,
1351	.mute_stream = wsa883x_digital_mute,
1352	.set_stream = wsa883x_set_sdw_stream,
 
1353};
1354
1355static struct snd_soc_dai_driver wsa883x_dais[] = {
1356	{
1357		.name = "SPKR",
1358		.playback = {
1359			.stream_name = "SPKR Playback",
1360			.rates = WSA883X_RATES | WSA883X_FRAC_RATES,
1361			.formats = WSA883X_FORMATS,
1362			.rate_min = 8000,
1363			.rate_max = 352800,
1364			.channels_min = 1,
1365			.channels_max = 1,
1366		},
1367		.ops = &wsa883x_dai_ops,
1368	},
1369};
1370
1371static int wsa883x_probe(struct sdw_slave *pdev,
1372			 const struct sdw_device_id *id)
1373{
1374	struct wsa883x_priv *wsa883x;
1375	struct device *dev = &pdev->dev;
1376	int ret;
1377
1378	wsa883x = devm_kzalloc(&pdev->dev, sizeof(*wsa883x), GFP_KERNEL);
1379	if (!wsa883x)
1380		return -ENOMEM;
1381
1382	wsa883x->vdd = devm_regulator_get(dev, "vdd");
1383	if (IS_ERR(wsa883x->vdd))
1384		return dev_err_probe(dev, PTR_ERR(wsa883x->vdd),
1385				     "No vdd regulator found\n");
1386
1387	ret = regulator_enable(wsa883x->vdd);
1388	if (ret)
1389		return dev_err_probe(dev, ret, "Failed to enable vdd regulator\n");
1390
1391	wsa883x->sd_n = devm_gpiod_get_optional(&pdev->dev, "powerdown",
1392						GPIOD_FLAGS_BIT_NONEXCLUSIVE | GPIOD_OUT_HIGH);
1393	if (IS_ERR(wsa883x->sd_n)) {
1394		ret = dev_err_probe(&pdev->dev, PTR_ERR(wsa883x->sd_n),
1395				    "Shutdown Control GPIO not found\n");
1396		goto err;
1397	}
1398
1399	dev_set_drvdata(&pdev->dev, wsa883x);
1400	wsa883x->slave = pdev;
1401	wsa883x->dev = &pdev->dev;
1402	wsa883x->sconfig.ch_count = 1;
1403	wsa883x->sconfig.bps = 1;
1404	wsa883x->sconfig.direction = SDW_DATA_DIR_RX;
1405	wsa883x->sconfig.type = SDW_STREAM_PDM;
1406
1407	pdev->prop.sink_ports = GENMASK(WSA883X_MAX_SWR_PORTS, 0);
1408	pdev->prop.simple_clk_stop_capable = true;
1409	pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
1410	pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
1411	gpiod_direction_output(wsa883x->sd_n, 0);
1412
1413	wsa883x->regmap = devm_regmap_init_sdw(pdev, &wsa883x_regmap_config);
1414	if (IS_ERR(wsa883x->regmap)) {
1415		gpiod_direction_output(wsa883x->sd_n, 1);
1416		ret = dev_err_probe(&pdev->dev, PTR_ERR(wsa883x->regmap),
1417				    "regmap_init failed\n");
1418		goto err;
1419	}
1420	pm_runtime_set_autosuspend_delay(dev, 3000);
1421	pm_runtime_use_autosuspend(dev);
1422	pm_runtime_mark_last_busy(dev);
1423	pm_runtime_set_active(dev);
1424	pm_runtime_enable(dev);
1425
1426	ret = devm_snd_soc_register_component(&pdev->dev,
1427					      &wsa883x_component_drv,
1428					       wsa883x_dais,
1429					       ARRAY_SIZE(wsa883x_dais));
1430err:
1431	if (ret)
1432		regulator_disable(wsa883x->vdd);
1433
1434	return ret;
1435
1436}
1437
1438static int __maybe_unused wsa883x_runtime_suspend(struct device *dev)
1439{
1440	struct regmap *regmap = dev_get_regmap(dev, NULL);
1441
1442	regcache_cache_only(regmap, true);
1443	regcache_mark_dirty(regmap);
1444
1445	return 0;
1446}
1447
1448static int __maybe_unused wsa883x_runtime_resume(struct device *dev)
1449{
1450	struct regmap *regmap = dev_get_regmap(dev, NULL);
1451
1452	regcache_cache_only(regmap, false);
1453	regcache_sync(regmap);
1454
1455	return 0;
1456}
1457
1458static const struct dev_pm_ops wsa883x_pm_ops = {
1459	SET_RUNTIME_PM_OPS(wsa883x_runtime_suspend, wsa883x_runtime_resume, NULL)
1460};
1461
1462static const struct sdw_device_id wsa883x_swr_id[] = {
1463	SDW_SLAVE_ENTRY(0x0217, 0x0202, 0),
1464	{},
1465};
1466
1467MODULE_DEVICE_TABLE(sdw, wsa883x_swr_id);
1468
1469static struct sdw_driver wsa883x_codec_driver = {
1470	.driver = {
1471		.name = "wsa883x-codec",
1472		.pm = &wsa883x_pm_ops,
1473		.suppress_bind_attrs = true,
1474	},
1475	.probe = wsa883x_probe,
1476	.ops = &wsa883x_slave_ops,
1477	.id_table = wsa883x_swr_id,
1478};
1479
1480module_sdw_driver(wsa883x_codec_driver);
1481
1482MODULE_DESCRIPTION("WSA883x codec driver");
1483MODULE_LICENSE("GPL");