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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/drivers/mmc/host/sdhci_f_sdh30.c
4 *
5 * Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
6 * Vincent Yang <vincent.yang@tw.fujitsu.com>
7 * Copyright (C) 2015 Linaro Ltd Andy Green <andy.green@linaro.org>
8 * Copyright (C) 2019 Socionext Inc.
9 */
10
11#include <linux/acpi.h>
12#include <linux/err.h>
13#include <linux/delay.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/property.h>
17#include <linux/clk.h>
18#include <linux/reset.h>
19
20#include "sdhci-pltfm.h"
21#include "sdhci_f_sdh30.h"
22
23struct f_sdhost_priv {
24 struct clk *clk_iface;
25 struct clk *clk;
26 struct reset_control *rst;
27 u32 vendor_hs200;
28 struct device *dev;
29 bool enable_cmd_dat_delay;
30};
31
32static void sdhci_f_sdh30_soft_voltage_switch(struct sdhci_host *host)
33{
34 struct f_sdhost_priv *priv = sdhci_priv(host);
35 u32 ctrl = 0;
36
37 usleep_range(2500, 3000);
38 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
39 ctrl |= F_SDH30_CRES_O_DN;
40 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
41 ctrl |= F_SDH30_MSEL_O_1_8;
42 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
43
44 ctrl &= ~F_SDH30_CRES_O_DN;
45 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
46 usleep_range(2500, 3000);
47
48 if (priv->vendor_hs200) {
49 dev_info(priv->dev, "%s: setting hs200\n", __func__);
50 ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
51 ctrl |= priv->vendor_hs200;
52 sdhci_writel(host, ctrl, F_SDH30_ESD_CONTROL);
53 }
54
55 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING);
56 ctrl |= F_SDH30_CMD_CHK_DIS;
57 sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING);
58}
59
60static unsigned int sdhci_f_sdh30_get_min_clock(struct sdhci_host *host)
61{
62 return F_SDH30_MIN_CLOCK;
63}
64
65static void sdhci_f_sdh30_reset(struct sdhci_host *host, u8 mask)
66{
67 struct f_sdhost_priv *priv = sdhci_priv(host);
68 u32 ctl;
69
70 if (sdhci_readw(host, SDHCI_CLOCK_CONTROL) == 0)
71 sdhci_writew(host, 0xBC01, SDHCI_CLOCK_CONTROL);
72
73 sdhci_reset(host, mask);
74
75 if (priv->enable_cmd_dat_delay) {
76 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
77 ctl |= F_SDH30_CMD_DAT_DELAY;
78 sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL);
79 }
80
81 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) &&
82 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
83 ctl = sdhci_readl(host, F_SDH30_TEST);
84 ctl |= F_SDH30_FORCE_CARD_INSERT;
85 sdhci_writel(host, ctl, F_SDH30_TEST);
86 }
87}
88
89static const struct sdhci_ops sdhci_f_sdh30_ops = {
90 .voltage_switch = sdhci_f_sdh30_soft_voltage_switch,
91 .get_min_clock = sdhci_f_sdh30_get_min_clock,
92 .reset = sdhci_f_sdh30_reset,
93 .set_clock = sdhci_set_clock,
94 .set_bus_width = sdhci_set_bus_width,
95 .set_uhs_signaling = sdhci_set_uhs_signaling,
96};
97
98static int sdhci_f_sdh30_probe(struct platform_device *pdev)
99{
100 struct sdhci_host *host;
101 struct device *dev = &pdev->dev;
102 int irq, ctrl = 0, ret = 0;
103 struct f_sdhost_priv *priv;
104 u32 reg = 0;
105
106 irq = platform_get_irq(pdev, 0);
107 if (irq < 0)
108 return irq;
109
110 host = sdhci_alloc_host(dev, sizeof(struct f_sdhost_priv));
111 if (IS_ERR(host))
112 return PTR_ERR(host);
113
114 priv = sdhci_priv(host);
115 priv->dev = dev;
116
117 host->quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
118 SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
119 host->quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE |
120 SDHCI_QUIRK2_TUNING_WORK_AROUND;
121
122 priv->enable_cmd_dat_delay = device_property_read_bool(dev,
123 "fujitsu,cmd-dat-delay-select");
124
125 ret = mmc_of_parse(host->mmc);
126 if (ret)
127 goto err;
128
129 platform_set_drvdata(pdev, host);
130
131 host->hw_name = "f_sdh30";
132 host->ops = &sdhci_f_sdh30_ops;
133 host->irq = irq;
134
135 host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
136 if (IS_ERR(host->ioaddr)) {
137 ret = PTR_ERR(host->ioaddr);
138 goto err;
139 }
140
141 if (dev_of_node(dev)) {
142 sdhci_get_of_property(pdev);
143
144 priv->clk_iface = devm_clk_get(&pdev->dev, "iface");
145 if (IS_ERR(priv->clk_iface)) {
146 ret = PTR_ERR(priv->clk_iface);
147 goto err;
148 }
149
150 ret = clk_prepare_enable(priv->clk_iface);
151 if (ret)
152 goto err;
153
154 priv->clk = devm_clk_get(&pdev->dev, "core");
155 if (IS_ERR(priv->clk)) {
156 ret = PTR_ERR(priv->clk);
157 goto err_clk;
158 }
159
160 ret = clk_prepare_enable(priv->clk);
161 if (ret)
162 goto err_clk;
163
164 priv->rst = devm_reset_control_get_optional_shared(dev, NULL);
165 if (IS_ERR(priv->rst)) {
166 ret = PTR_ERR(priv->rst);
167 goto err_rst;
168 }
169
170 ret = reset_control_deassert(priv->rst);
171 if (ret)
172 goto err_rst;
173 }
174
175 /* init vendor specific regs */
176 ctrl = sdhci_readw(host, F_SDH30_AHB_CONFIG);
177 ctrl |= F_SDH30_SIN | F_SDH30_AHB_INCR_16 | F_SDH30_AHB_INCR_8 |
178 F_SDH30_AHB_INCR_4;
179 ctrl &= ~(F_SDH30_AHB_BIGED | F_SDH30_BUSLOCK_EN);
180 sdhci_writew(host, ctrl, F_SDH30_AHB_CONFIG);
181
182 reg = sdhci_readl(host, F_SDH30_ESD_CONTROL);
183 sdhci_writel(host, reg & ~F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
184 msleep(20);
185 sdhci_writel(host, reg | F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
186
187 reg = sdhci_readl(host, SDHCI_CAPABILITIES);
188 if (reg & SDHCI_CAN_DO_8BIT)
189 priv->vendor_hs200 = F_SDH30_EMMC_HS200;
190
191 if (!(reg & SDHCI_TIMEOUT_CLK_MASK))
192 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
193
194 ret = sdhci_add_host(host);
195 if (ret)
196 goto err_add_host;
197
198 return 0;
199
200err_add_host:
201 reset_control_assert(priv->rst);
202err_rst:
203 clk_disable_unprepare(priv->clk);
204err_clk:
205 clk_disable_unprepare(priv->clk_iface);
206err:
207 sdhci_free_host(host);
208 return ret;
209}
210
211static int sdhci_f_sdh30_remove(struct platform_device *pdev)
212{
213 struct sdhci_host *host = platform_get_drvdata(pdev);
214 struct f_sdhost_priv *priv = sdhci_priv(host);
215
216 sdhci_remove_host(host, readl(host->ioaddr + SDHCI_INT_STATUS) ==
217 0xffffffff);
218
219 reset_control_assert(priv->rst);
220 clk_disable_unprepare(priv->clk);
221 clk_disable_unprepare(priv->clk_iface);
222
223 sdhci_free_host(host);
224 platform_set_drvdata(pdev, NULL);
225
226 return 0;
227}
228
229#ifdef CONFIG_OF
230static const struct of_device_id f_sdh30_dt_ids[] = {
231 { .compatible = "fujitsu,mb86s70-sdhci-3.0" },
232 { .compatible = "socionext,f-sdh30-e51-mmc" },
233 { /* sentinel */ }
234};
235MODULE_DEVICE_TABLE(of, f_sdh30_dt_ids);
236#endif
237
238#ifdef CONFIG_ACPI
239static const struct acpi_device_id f_sdh30_acpi_ids[] = {
240 { "SCX0002" },
241 { /* sentinel */ }
242};
243MODULE_DEVICE_TABLE(acpi, f_sdh30_acpi_ids);
244#endif
245
246static struct platform_driver sdhci_f_sdh30_driver = {
247 .driver = {
248 .name = "f_sdh30",
249 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
250 .of_match_table = of_match_ptr(f_sdh30_dt_ids),
251 .acpi_match_table = ACPI_PTR(f_sdh30_acpi_ids),
252 .pm = &sdhci_pltfm_pmops,
253 },
254 .probe = sdhci_f_sdh30_probe,
255 .remove = sdhci_f_sdh30_remove,
256};
257
258module_platform_driver(sdhci_f_sdh30_driver);
259
260MODULE_DESCRIPTION("F_SDH30 SD Card Controller driver");
261MODULE_LICENSE("GPL v2");
262MODULE_AUTHOR("FUJITSU SEMICONDUCTOR LTD., Socionext Inc.");
263MODULE_ALIAS("platform:f_sdh30");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/drivers/mmc/host/sdhci_f_sdh30.c
4 *
5 * Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
6 * Vincent Yang <vincent.yang@tw.fujitsu.com>
7 * Copyright (C) 2015 Linaro Ltd Andy Green <andy.green@linaro.org>
8 * Copyright (C) 2019 Socionext Inc.
9 */
10
11#include <linux/acpi.h>
12#include <linux/err.h>
13#include <linux/delay.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/property.h>
17#include <linux/clk.h>
18#include <linux/reset.h>
19
20#include "sdhci-pltfm.h"
21#include "sdhci_f_sdh30.h"
22
23struct f_sdhost_priv {
24 struct clk *clk_iface;
25 struct clk *clk;
26 struct reset_control *rst;
27 u32 vendor_hs200;
28 struct device *dev;
29 bool enable_cmd_dat_delay;
30};
31
32static void *sdhci_f_sdhost_priv(struct sdhci_host *host)
33{
34 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
35
36 return sdhci_pltfm_priv(pltfm_host);
37}
38
39static void sdhci_f_sdh30_soft_voltage_switch(struct sdhci_host *host)
40{
41 struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
42 u32 ctrl = 0;
43
44 usleep_range(2500, 3000);
45 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
46 ctrl |= F_SDH30_CRES_O_DN;
47 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
48 ctrl |= F_SDH30_MSEL_O_1_8;
49 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
50
51 ctrl &= ~F_SDH30_CRES_O_DN;
52 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
53 usleep_range(2500, 3000);
54
55 if (priv->vendor_hs200) {
56 dev_info(priv->dev, "%s: setting hs200\n", __func__);
57 ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
58 ctrl |= priv->vendor_hs200;
59 sdhci_writel(host, ctrl, F_SDH30_ESD_CONTROL);
60 }
61
62 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING);
63 ctrl |= F_SDH30_CMD_CHK_DIS;
64 sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING);
65}
66
67static unsigned int sdhci_f_sdh30_get_min_clock(struct sdhci_host *host)
68{
69 return F_SDH30_MIN_CLOCK;
70}
71
72static void sdhci_f_sdh30_reset(struct sdhci_host *host, u8 mask)
73{
74 struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
75 u32 ctl;
76
77 if (sdhci_readw(host, SDHCI_CLOCK_CONTROL) == 0)
78 sdhci_writew(host, 0xBC01, SDHCI_CLOCK_CONTROL);
79
80 sdhci_reset(host, mask);
81
82 if (priv->enable_cmd_dat_delay) {
83 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
84 ctl |= F_SDH30_CMD_DAT_DELAY;
85 sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL);
86 }
87
88 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) &&
89 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
90 ctl = sdhci_readl(host, F_SDH30_TEST);
91 ctl |= F_SDH30_FORCE_CARD_INSERT;
92 sdhci_writel(host, ctl, F_SDH30_TEST);
93 }
94}
95
96static const struct sdhci_ops sdhci_f_sdh30_ops = {
97 .voltage_switch = sdhci_f_sdh30_soft_voltage_switch,
98 .get_min_clock = sdhci_f_sdh30_get_min_clock,
99 .reset = sdhci_f_sdh30_reset,
100 .set_clock = sdhci_set_clock,
101 .set_bus_width = sdhci_set_bus_width,
102 .set_uhs_signaling = sdhci_set_uhs_signaling,
103};
104
105static const struct sdhci_pltfm_data sdhci_f_sdh30_pltfm_data = {
106 .ops = &sdhci_f_sdh30_ops,
107 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
108 | SDHCI_QUIRK_INVERTED_WRITE_PROTECT,
109 .quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE
110 | SDHCI_QUIRK2_TUNING_WORK_AROUND,
111};
112
113static int sdhci_f_sdh30_probe(struct platform_device *pdev)
114{
115 struct sdhci_host *host;
116 struct device *dev = &pdev->dev;
117 int ctrl = 0, ret = 0;
118 struct f_sdhost_priv *priv;
119 struct sdhci_pltfm_host *pltfm_host;
120 u32 reg = 0;
121
122 host = sdhci_pltfm_init(pdev, &sdhci_f_sdh30_pltfm_data,
123 sizeof(struct f_sdhost_priv));
124 if (IS_ERR(host))
125 return PTR_ERR(host);
126
127 pltfm_host = sdhci_priv(host);
128 priv = sdhci_pltfm_priv(pltfm_host);
129 priv->dev = dev;
130
131 priv->enable_cmd_dat_delay = device_property_read_bool(dev,
132 "fujitsu,cmd-dat-delay-select");
133
134 ret = mmc_of_parse(host->mmc);
135 if (ret)
136 goto err;
137
138 if (dev_of_node(dev)) {
139 sdhci_get_of_property(pdev);
140
141 priv->clk_iface = devm_clk_get(&pdev->dev, "iface");
142 if (IS_ERR(priv->clk_iface)) {
143 ret = PTR_ERR(priv->clk_iface);
144 goto err;
145 }
146
147 ret = clk_prepare_enable(priv->clk_iface);
148 if (ret)
149 goto err;
150
151 priv->clk = devm_clk_get(&pdev->dev, "core");
152 if (IS_ERR(priv->clk)) {
153 ret = PTR_ERR(priv->clk);
154 goto err_clk;
155 }
156
157 ret = clk_prepare_enable(priv->clk);
158 if (ret)
159 goto err_clk;
160
161 priv->rst = devm_reset_control_get_optional_shared(dev, NULL);
162 if (IS_ERR(priv->rst)) {
163 ret = PTR_ERR(priv->rst);
164 goto err_rst;
165 }
166
167 ret = reset_control_deassert(priv->rst);
168 if (ret)
169 goto err_rst;
170 }
171
172 /* init vendor specific regs */
173 ctrl = sdhci_readw(host, F_SDH30_AHB_CONFIG);
174 ctrl |= F_SDH30_SIN | F_SDH30_AHB_INCR_16 | F_SDH30_AHB_INCR_8 |
175 F_SDH30_AHB_INCR_4;
176 ctrl &= ~(F_SDH30_AHB_BIGED | F_SDH30_BUSLOCK_EN);
177 sdhci_writew(host, ctrl, F_SDH30_AHB_CONFIG);
178
179 reg = sdhci_readl(host, F_SDH30_ESD_CONTROL);
180 sdhci_writel(host, reg & ~F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
181 msleep(20);
182 sdhci_writel(host, reg | F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
183
184 reg = sdhci_readl(host, SDHCI_CAPABILITIES);
185 if (reg & SDHCI_CAN_DO_8BIT)
186 priv->vendor_hs200 = F_SDH30_EMMC_HS200;
187
188 if (!(reg & SDHCI_TIMEOUT_CLK_MASK))
189 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
190
191 ret = sdhci_add_host(host);
192 if (ret)
193 goto err_add_host;
194
195 return 0;
196
197err_add_host:
198 reset_control_assert(priv->rst);
199err_rst:
200 clk_disable_unprepare(priv->clk);
201err_clk:
202 clk_disable_unprepare(priv->clk_iface);
203err:
204 sdhci_pltfm_free(pdev);
205
206 return ret;
207}
208
209static void sdhci_f_sdh30_remove(struct platform_device *pdev)
210{
211 struct sdhci_host *host = platform_get_drvdata(pdev);
212 struct f_sdhost_priv *priv = sdhci_f_sdhost_priv(host);
213 struct clk *clk_iface = priv->clk_iface;
214 struct reset_control *rst = priv->rst;
215 struct clk *clk = priv->clk;
216
217 sdhci_pltfm_remove(pdev);
218
219 reset_control_assert(rst);
220 clk_disable_unprepare(clk);
221 clk_disable_unprepare(clk_iface);
222}
223
224#ifdef CONFIG_OF
225static const struct of_device_id f_sdh30_dt_ids[] = {
226 { .compatible = "fujitsu,mb86s70-sdhci-3.0" },
227 { .compatible = "socionext,f-sdh30-e51-mmc" },
228 { /* sentinel */ }
229};
230MODULE_DEVICE_TABLE(of, f_sdh30_dt_ids);
231#endif
232
233#ifdef CONFIG_ACPI
234static const struct acpi_device_id f_sdh30_acpi_ids[] = {
235 { "SCX0002" },
236 { /* sentinel */ }
237};
238MODULE_DEVICE_TABLE(acpi, f_sdh30_acpi_ids);
239#endif
240
241static struct platform_driver sdhci_f_sdh30_driver = {
242 .driver = {
243 .name = "f_sdh30",
244 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
245 .of_match_table = of_match_ptr(f_sdh30_dt_ids),
246 .acpi_match_table = ACPI_PTR(f_sdh30_acpi_ids),
247 .pm = &sdhci_pltfm_pmops,
248 },
249 .probe = sdhci_f_sdh30_probe,
250 .remove_new = sdhci_f_sdh30_remove,
251};
252
253module_platform_driver(sdhci_f_sdh30_driver);
254
255MODULE_DESCRIPTION("F_SDH30 SD Card Controller driver");
256MODULE_LICENSE("GPL v2");
257MODULE_AUTHOR("FUJITSU SEMICONDUCTOR LTD., Socionext Inc.");
258MODULE_ALIAS("platform:f_sdh30");