Loading...
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/ingenic,jz4780-cgu.h>
3#include <dt-bindings/clock/ingenic,tcu.h>
4#include <dt-bindings/dma/jz4780-dma.h>
5
6/ {
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "ingenic,jz4780";
10
11 cpus {
12 #address-cells = <1>;
13 #size-cells = <0>;
14
15 cpu0: cpu@0 {
16 device_type = "cpu";
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
19
20 clocks = <&cgu JZ4780_CLK_CPU>;
21 clock-names = "cpu";
22 };
23
24 cpu1: cpu@1 {
25 device_type = "cpu";
26 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
27 reg = <1>;
28
29 clocks = <&cgu JZ4780_CLK_CORE1>;
30 clock-names = "cpu";
31 };
32 };
33
34 cpuintc: interrupt-controller {
35 #address-cells = <0>;
36 #interrupt-cells = <1>;
37 interrupt-controller;
38 compatible = "mti,cpu-interrupt-controller";
39 };
40
41 intc: interrupt-controller@10001000 {
42 compatible = "ingenic,jz4780-intc";
43 reg = <0x10001000 0x50>;
44
45 interrupt-controller;
46 #interrupt-cells = <1>;
47
48 interrupt-parent = <&cpuintc>;
49 interrupts = <2>;
50 };
51
52 ext: ext {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 };
56
57 rtc: rtc {
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
61 };
62
63 cgu: jz4780-cgu@10000000 {
64 compatible = "ingenic,jz4780-cgu", "simple-mfd";
65 reg = <0x10000000 0x100>;
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges = <0x0 0x10000000 0x100>;
69
70 #clock-cells = <1>;
71
72 clocks = <&ext>, <&rtc>;
73 clock-names = "ext", "rtc";
74
75 otg_phy: usb-phy@3c {
76 compatible = "ingenic,jz4780-phy";
77 reg = <0x3c 0x10>;
78
79 clocks = <&cgu JZ4780_CLK_OTG1>;
80
81 #phy-cells = <0>;
82
83 status = "disabled";
84 };
85
86 rng: rng@d8 {
87 compatible = "ingenic,jz4780-rng";
88 reg = <0xd8 0x8>;
89
90 status = "disabled";
91 };
92 };
93
94 tcu: timer@10002000 {
95 compatible = "ingenic,jz4780-tcu",
96 "ingenic,jz4770-tcu",
97 "simple-mfd";
98 reg = <0x10002000 0x1000>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges = <0x0 0x10002000 0x1000>;
102
103 #clock-cells = <1>;
104
105 clocks = <&cgu JZ4780_CLK_RTCLK>,
106 <&cgu JZ4780_CLK_EXCLK>,
107 <&cgu JZ4780_CLK_PCLK>;
108 clock-names = "rtc", "ext", "pclk";
109
110 interrupt-controller;
111 #interrupt-cells = <1>;
112
113 interrupt-parent = <&intc>;
114 interrupts = <27 26 25>;
115
116 watchdog: watchdog@0 {
117 compatible = "ingenic,jz4780-watchdog";
118 reg = <0x0 0xc>;
119
120 clocks = <&tcu TCU_CLK_WDT>;
121 clock-names = "wdt";
122 };
123
124 pwm: pwm@40 {
125 compatible = "ingenic,jz4780-pwm", "ingenic,jz4740-pwm";
126 reg = <0x40 0x80>;
127
128 #pwm-cells = <3>;
129
130 clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
131 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
132 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
133 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
134 clock-names = "timer0", "timer1", "timer2", "timer3",
135 "timer4", "timer5", "timer6", "timer7";
136 };
137
138 ost: timer@e0 {
139 compatible = "ingenic,jz4780-ost", "ingenic,jz4770-ost";
140 reg = <0xe0 0x20>;
141
142 clocks = <&tcu TCU_CLK_OST>;
143 clock-names = "ost";
144
145 interrupts = <15>;
146 };
147 };
148
149 rtc_dev: rtc@10003000 {
150 compatible = "ingenic,jz4780-rtc";
151 reg = <0x10003000 0x4c>;
152
153 interrupt-parent = <&intc>;
154 interrupts = <32>;
155
156 clocks = <&cgu JZ4780_CLK_RTCLK>;
157 clock-names = "rtc";
158 };
159
160 pinctrl: pin-controller@10010000 {
161 compatible = "ingenic,jz4780-pinctrl";
162 reg = <0x10010000 0x600>;
163
164 #address-cells = <1>;
165 #size-cells = <0>;
166
167 gpa: gpio@0 {
168 compatible = "ingenic,jz4780-gpio";
169 reg = <0>;
170
171 gpio-controller;
172 gpio-ranges = <&pinctrl 0 0 32>;
173 #gpio-cells = <2>;
174
175 interrupt-controller;
176 #interrupt-cells = <2>;
177
178 interrupt-parent = <&intc>;
179 interrupts = <17>;
180 };
181
182 gpb: gpio@1 {
183 compatible = "ingenic,jz4780-gpio";
184 reg = <1>;
185
186 gpio-controller;
187 gpio-ranges = <&pinctrl 0 32 32>;
188 #gpio-cells = <2>;
189
190 interrupt-controller;
191 #interrupt-cells = <2>;
192
193 interrupt-parent = <&intc>;
194 interrupts = <16>;
195 };
196
197 gpc: gpio@2 {
198 compatible = "ingenic,jz4780-gpio";
199 reg = <2>;
200
201 gpio-controller;
202 gpio-ranges = <&pinctrl 0 64 32>;
203 #gpio-cells = <2>;
204
205 interrupt-controller;
206 #interrupt-cells = <2>;
207
208 interrupt-parent = <&intc>;
209 interrupts = <15>;
210 };
211
212 gpd: gpio@3 {
213 compatible = "ingenic,jz4780-gpio";
214 reg = <3>;
215
216 gpio-controller;
217 gpio-ranges = <&pinctrl 0 96 32>;
218 #gpio-cells = <2>;
219
220 interrupt-controller;
221 #interrupt-cells = <2>;
222
223 interrupt-parent = <&intc>;
224 interrupts = <14>;
225 };
226
227 gpe: gpio@4 {
228 compatible = "ingenic,jz4780-gpio";
229 reg = <4>;
230
231 gpio-controller;
232 gpio-ranges = <&pinctrl 0 128 32>;
233 #gpio-cells = <2>;
234
235 interrupt-controller;
236 #interrupt-cells = <2>;
237
238 interrupt-parent = <&intc>;
239 interrupts = <13>;
240 };
241
242 gpf: gpio@5 {
243 compatible = "ingenic,jz4780-gpio";
244 reg = <5>;
245
246 gpio-controller;
247 gpio-ranges = <&pinctrl 0 160 32>;
248 #gpio-cells = <2>;
249
250 interrupt-controller;
251 #interrupt-cells = <2>;
252
253 interrupt-parent = <&intc>;
254 interrupts = <12>;
255 };
256 };
257
258 spi0: spi@10043000 {
259 compatible = "ingenic,jz4780-spi";
260 reg = <0x10043000 0x1c>;
261 #address-cells = <1>;
262 #size-cells = <0>;
263
264 interrupt-parent = <&intc>;
265 interrupts = <8>;
266
267 clocks = <&cgu JZ4780_CLK_SSI0>;
268 clock-names = "spi";
269
270 dmas = <&dma JZ4780_DMA_SSI0_RX 0xffffffff>,
271 <&dma JZ4780_DMA_SSI0_TX 0xffffffff>;
272 dma-names = "rx", "tx";
273
274 status = "disabled";
275 };
276
277 uart0: serial@10030000 {
278 compatible = "ingenic,jz4780-uart";
279 reg = <0x10030000 0x100>;
280
281 interrupt-parent = <&intc>;
282 interrupts = <51>;
283
284 clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
285 clock-names = "baud", "module";
286
287 status = "disabled";
288 };
289
290 uart1: serial@10031000 {
291 compatible = "ingenic,jz4780-uart";
292 reg = <0x10031000 0x100>;
293
294 interrupt-parent = <&intc>;
295 interrupts = <50>;
296
297 clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
298 clock-names = "baud", "module";
299
300 status = "disabled";
301 };
302
303 uart2: serial@10032000 {
304 compatible = "ingenic,jz4780-uart";
305 reg = <0x10032000 0x100>;
306
307 interrupt-parent = <&intc>;
308 interrupts = <49>;
309
310 clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
311 clock-names = "baud", "module";
312
313 status = "disabled";
314 };
315
316 uart3: serial@10033000 {
317 compatible = "ingenic,jz4780-uart";
318 reg = <0x10033000 0x100>;
319
320 interrupt-parent = <&intc>;
321 interrupts = <48>;
322
323 clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
324 clock-names = "baud", "module";
325
326 status = "disabled";
327 };
328
329 uart4: serial@10034000 {
330 compatible = "ingenic,jz4780-uart";
331 reg = <0x10034000 0x100>;
332
333 interrupt-parent = <&intc>;
334 interrupts = <34>;
335
336 clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
337 clock-names = "baud", "module";
338
339 status = "disabled";
340 };
341
342 spi1: spi@10044000 {
343 compatible = "ingenic,jz4780-spi";
344 reg = <0x10044000 0x1c>;
345 #address-cells = <1>;
346 #size-sells = <0>;
347
348 interrupt-parent = <&intc>;
349 interrupts = <7>;
350
351 clocks = <&cgu JZ4780_CLK_SSI1>;
352 clock-names = "spi";
353
354 dmas = <&dma JZ4780_DMA_SSI1_RX 0xffffffff>,
355 <&dma JZ4780_DMA_SSI1_TX 0xffffffff>;
356 dma-names = "rx", "tx";
357
358 status = "disabled";
359 };
360
361 i2c0: i2c@10050000 {
362 compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
363 #address-cells = <1>;
364 #size-cells = <0>;
365
366 reg = <0x10050000 0x1000>;
367
368 interrupt-parent = <&intc>;
369 interrupts = <60>;
370
371 clocks = <&cgu JZ4780_CLK_SMB0>;
372 clock-frequency = <100000>;
373 pinctrl-names = "default";
374 pinctrl-0 = <&pins_i2c0_data>;
375
376 status = "disabled";
377 };
378
379 i2c1: i2c@10051000 {
380 compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
381 #address-cells = <1>;
382 #size-cells = <0>;
383 reg = <0x10051000 0x1000>;
384
385 interrupt-parent = <&intc>;
386 interrupts = <59>;
387
388 clocks = <&cgu JZ4780_CLK_SMB1>;
389 clock-frequency = <100000>;
390 pinctrl-names = "default";
391 pinctrl-0 = <&pins_i2c1_data>;
392
393 status = "disabled";
394 };
395
396 i2c2: i2c@10052000 {
397 compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
398 #address-cells = <1>;
399 #size-cells = <0>;
400 reg = <0x10052000 0x1000>;
401
402 interrupt-parent = <&intc>;
403 interrupts = <58>;
404
405 clocks = <&cgu JZ4780_CLK_SMB2>;
406 clock-frequency = <100000>;
407 pinctrl-names = "default";
408 pinctrl-0 = <&pins_i2c2_data>;
409
410 status = "disabled";
411 };
412
413 i2c3: i2c@10053000 {
414 compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
415 #address-cells = <1>;
416 #size-cells = <0>;
417 reg = <0x10053000 0x1000>;
418
419 interrupt-parent = <&intc>;
420 interrupts = <57>;
421
422 clocks = <&cgu JZ4780_CLK_SMB3>;
423 clock-frequency = <100000>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&pins_i2c3_data>;
426
427 status = "disabled";
428 };
429
430 i2c4: i2c@10054000 {
431 compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
432 #address-cells = <1>;
433 #size-cells = <0>;
434 reg = <0x10054000 0x1000>;
435
436 interrupt-parent = <&intc>;
437 interrupts = <56>;
438
439 clocks = <&cgu JZ4780_CLK_SMB4>;
440 clock-frequency = <100000>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&pins_i2c4_data>;
443
444 status = "disabled";
445 };
446
447 hdmi: hdmi@10180000 {
448 compatible = "ingenic,jz4780-dw-hdmi";
449 reg = <0x10180000 0x8000>;
450 reg-io-width = <4>;
451
452 clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
453 clock-names = "iahb", "isfr";
454
455 interrupt-parent = <&intc>;
456 interrupts = <3>;
457
458 status = "disabled";
459 };
460
461 lcdc0: lcdc0@13050000 {
462 compatible = "ingenic,jz4780-lcd";
463 reg = <0x13050000 0x1800>;
464
465 clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>;
466 clock-names = "lcd", "lcd_pclk";
467
468 interrupt-parent = <&intc>;
469 interrupts = <31>;
470
471 status = "disabled";
472 };
473
474 lcdc1: lcdc1@130a0000 {
475 compatible = "ingenic,jz4780-lcd";
476 reg = <0x130a0000 0x1800>;
477
478 clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD1PIXCLK>;
479 clock-names = "lcd", "lcd_pclk";
480
481 interrupt-parent = <&intc>;
482 interrupts = <23>;
483
484 status = "disabled";
485 };
486
487 nemc: nemc@13410000 {
488 compatible = "ingenic,jz4780-nemc", "simple-mfd";
489 reg = <0x13410000 0x10000>;
490 #address-cells = <2>;
491 #size-cells = <1>;
492 ranges = <0 0 0x13410000 0x10000>,
493 <1 0 0x1b000000 0x1000000>,
494 <2 0 0x1a000000 0x1000000>,
495 <3 0 0x19000000 0x1000000>,
496 <4 0 0x18000000 0x1000000>,
497 <5 0 0x17000000 0x1000000>,
498 <6 0 0x16000000 0x1000000>;
499
500 clocks = <&cgu JZ4780_CLK_NEMC>;
501
502 status = "disabled";
503
504 efuse: efuse@d0 {
505 reg = <0 0xd0 0x30>;
506 compatible = "ingenic,jz4780-efuse";
507
508 clocks = <&cgu JZ4780_CLK_AHB2>;
509
510 #address-cells = <1>;
511 #size-cells = <1>;
512
513 eth0_addr: eth-mac-addr@22 {
514 reg = <0x22 0x6>;
515 };
516 };
517 };
518
519 dma: dma@13420000 {
520 compatible = "ingenic,jz4780-dma";
521 reg = <0x13420000 0x400>, <0x13421000 0x40>;
522 #dma-cells = <2>;
523
524 interrupt-parent = <&intc>;
525 interrupts = <10>;
526
527 clocks = <&cgu JZ4780_CLK_PDMA>;
528 };
529
530 mmc0: mmc@13450000 {
531 compatible = "ingenic,jz4780-mmc";
532 reg = <0x13450000 0x1000>;
533
534 interrupt-parent = <&intc>;
535 interrupts = <37>;
536
537 clocks = <&cgu JZ4780_CLK_MSC0>;
538 clock-names = "mmc";
539
540 cap-sd-highspeed;
541 cap-mmc-highspeed;
542 cap-sdio-irq;
543 dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>,
544 <&dma JZ4780_DMA_MSC0_TX 0xffffffff>;
545 dma-names = "rx", "tx";
546
547 status = "disabled";
548 };
549
550 mmc1: mmc@13460000 {
551 compatible = "ingenic,jz4780-mmc";
552 reg = <0x13460000 0x1000>;
553
554 interrupt-parent = <&intc>;
555 interrupts = <36>;
556
557 clocks = <&cgu JZ4780_CLK_MSC1>;
558 clock-names = "mmc";
559
560 cap-sd-highspeed;
561 cap-mmc-highspeed;
562 cap-sdio-irq;
563 dmas = <&dma JZ4780_DMA_MSC1_RX 0xffffffff>,
564 <&dma JZ4780_DMA_MSC1_TX 0xffffffff>;
565 dma-names = "rx", "tx";
566
567 status = "disabled";
568 };
569
570 bch: bch@134d0000 {
571 compatible = "ingenic,jz4780-bch";
572 reg = <0x134d0000 0x10000>;
573
574 clocks = <&cgu JZ4780_CLK_BCH>;
575
576 status = "disabled";
577 };
578
579 otg: usb@13500000 {
580 compatible = "ingenic,jz4780-otg";
581 reg = <0x13500000 0x40000>;
582
583 interrupt-parent = <&intc>;
584 interrupts = <21>;
585
586 clocks = <&cgu JZ4780_CLK_UHC>;
587 clock-names = "otg";
588
589 phys = <&otg_phy>;
590 phy-names = "usb2-phy";
591
592 g-rx-fifo-size = <768>;
593 g-np-tx-fifo-size = <256>;
594 g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
595
596 status = "disabled";
597 };
598};
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/ingenic,jz4780-cgu.h>
3#include <dt-bindings/clock/ingenic,tcu.h>
4#include <dt-bindings/dma/jz4780-dma.h>
5
6/ {
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "ingenic,jz4780";
10
11 cpus {
12 #address-cells = <1>;
13 #size-cells = <0>;
14
15 cpu0: cpu@0 {
16 device_type = "cpu";
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
19
20 clocks = <&cgu JZ4780_CLK_CPU>;
21 clock-names = "cpu";
22 };
23
24 cpu1: cpu@1 {
25 device_type = "cpu";
26 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
27 reg = <1>;
28
29 clocks = <&cgu JZ4780_CLK_CORE1>;
30 clock-names = "cpu";
31 };
32 };
33
34 cpuintc: interrupt-controller {
35 #address-cells = <0>;
36 #interrupt-cells = <1>;
37 interrupt-controller;
38 compatible = "mti,cpu-interrupt-controller";
39 };
40
41 intc: interrupt-controller@10001000 {
42 compatible = "ingenic,jz4780-intc";
43 reg = <0x10001000 0x50>;
44
45 interrupt-controller;
46 #interrupt-cells = <1>;
47
48 interrupt-parent = <&cpuintc>;
49 interrupts = <2>;
50 };
51
52 ext: ext {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 };
56
57 rtc: rtc {
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
61 };
62
63 cgu: jz4780-cgu@10000000 {
64 compatible = "ingenic,jz4780-cgu", "simple-mfd";
65 reg = <0x10000000 0x100>;
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges = <0x0 0x10000000 0x100>;
69
70 #clock-cells = <1>;
71
72 clocks = <&ext>, <&rtc>;
73 clock-names = "ext", "rtc";
74
75 otg_phy: usb-phy@3c {
76 compatible = "ingenic,jz4780-phy";
77 reg = <0x3c 0x10>;
78
79 clocks = <&cgu JZ4780_CLK_OTG1>;
80
81 #phy-cells = <0>;
82
83 status = "disabled";
84 };
85
86 rng: rng@d8 {
87 compatible = "ingenic,jz4780-rng";
88 reg = <0xd8 0x8>;
89
90 status = "disabled";
91 };
92 };
93
94 tcu: timer@10002000 {
95 compatible = "ingenic,jz4780-tcu",
96 "ingenic,jz4770-tcu",
97 "simple-mfd";
98 reg = <0x10002000 0x1000>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges = <0x0 0x10002000 0x1000>;
102
103 #clock-cells = <1>;
104
105 clocks = <&cgu JZ4780_CLK_RTCLK>,
106 <&cgu JZ4780_CLK_EXCLK>,
107 <&cgu JZ4780_CLK_PCLK>;
108 clock-names = "rtc", "ext", "pclk";
109
110 interrupt-controller;
111 #interrupt-cells = <1>;
112
113 interrupt-parent = <&intc>;
114 interrupts = <27 26 25>;
115
116 watchdog: watchdog@0 {
117 compatible = "ingenic,jz4780-watchdog";
118 reg = <0x0 0xc>;
119
120 clocks = <&tcu TCU_CLK_WDT>;
121 clock-names = "wdt";
122 };
123
124 pwm: pwm@40 {
125 compatible = "ingenic,jz4780-pwm", "ingenic,jz4740-pwm";
126 reg = <0x40 0x80>;
127
128 #pwm-cells = <3>;
129
130 clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
131 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
132 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
133 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
134 clock-names = "timer0", "timer1", "timer2", "timer3",
135 "timer4", "timer5", "timer6", "timer7";
136 };
137
138 ost: timer@e0 {
139 compatible = "ingenic,jz4780-ost", "ingenic,jz4770-ost";
140 reg = <0xe0 0x20>;
141
142 clocks = <&tcu TCU_CLK_OST>;
143 clock-names = "ost";
144
145 interrupts = <15>;
146 };
147 };
148
149 rtc_dev: rtc@10003000 {
150 compatible = "ingenic,jz4780-rtc";
151 reg = <0x10003000 0x4c>;
152
153 interrupt-parent = <&intc>;
154 interrupts = <32>;
155
156 clocks = <&cgu JZ4780_CLK_RTCLK>;
157 clock-names = "rtc";
158
159 #clock-cells = <0>;
160 };
161
162 pinctrl: pin-controller@10010000 {
163 compatible = "ingenic,jz4780-pinctrl";
164 reg = <0x10010000 0x600>;
165
166 #address-cells = <1>;
167 #size-cells = <0>;
168
169 gpa: gpio@0 {
170 compatible = "ingenic,jz4780-gpio";
171 reg = <0>;
172
173 gpio-controller;
174 gpio-ranges = <&pinctrl 0 0 32>;
175 #gpio-cells = <2>;
176
177 interrupt-controller;
178 #interrupt-cells = <2>;
179
180 interrupt-parent = <&intc>;
181 interrupts = <17>;
182 };
183
184 gpb: gpio@1 {
185 compatible = "ingenic,jz4780-gpio";
186 reg = <1>;
187
188 gpio-controller;
189 gpio-ranges = <&pinctrl 0 32 32>;
190 #gpio-cells = <2>;
191
192 interrupt-controller;
193 #interrupt-cells = <2>;
194
195 interrupt-parent = <&intc>;
196 interrupts = <16>;
197 };
198
199 gpc: gpio@2 {
200 compatible = "ingenic,jz4780-gpio";
201 reg = <2>;
202
203 gpio-controller;
204 gpio-ranges = <&pinctrl 0 64 32>;
205 #gpio-cells = <2>;
206
207 interrupt-controller;
208 #interrupt-cells = <2>;
209
210 interrupt-parent = <&intc>;
211 interrupts = <15>;
212 };
213
214 gpd: gpio@3 {
215 compatible = "ingenic,jz4780-gpio";
216 reg = <3>;
217
218 gpio-controller;
219 gpio-ranges = <&pinctrl 0 96 32>;
220 #gpio-cells = <2>;
221
222 interrupt-controller;
223 #interrupt-cells = <2>;
224
225 interrupt-parent = <&intc>;
226 interrupts = <14>;
227 };
228
229 gpe: gpio@4 {
230 compatible = "ingenic,jz4780-gpio";
231 reg = <4>;
232
233 gpio-controller;
234 gpio-ranges = <&pinctrl 0 128 32>;
235 #gpio-cells = <2>;
236
237 interrupt-controller;
238 #interrupt-cells = <2>;
239
240 interrupt-parent = <&intc>;
241 interrupts = <13>;
242 };
243
244 gpf: gpio@5 {
245 compatible = "ingenic,jz4780-gpio";
246 reg = <5>;
247
248 gpio-controller;
249 gpio-ranges = <&pinctrl 0 160 32>;
250 #gpio-cells = <2>;
251
252 interrupt-controller;
253 #interrupt-cells = <2>;
254
255 interrupt-parent = <&intc>;
256 interrupts = <12>;
257 };
258 };
259
260 spi0: spi@10043000 {
261 compatible = "ingenic,jz4780-spi";
262 reg = <0x10043000 0x1c>;
263 #address-cells = <1>;
264 #size-cells = <0>;
265
266 interrupt-parent = <&intc>;
267 interrupts = <8>;
268
269 clocks = <&cgu JZ4780_CLK_SSI0>;
270 clock-names = "spi";
271
272 dmas = <&dma JZ4780_DMA_SSI0_RX 0xffffffff>,
273 <&dma JZ4780_DMA_SSI0_TX 0xffffffff>;
274 dma-names = "rx", "tx";
275
276 status = "disabled";
277 };
278
279 uart0: serial@10030000 {
280 compatible = "ingenic,jz4780-uart";
281 reg = <0x10030000 0x100>;
282
283 interrupt-parent = <&intc>;
284 interrupts = <51>;
285
286 clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
287 clock-names = "baud", "module";
288
289 status = "disabled";
290 };
291
292 uart1: serial@10031000 {
293 compatible = "ingenic,jz4780-uart";
294 reg = <0x10031000 0x100>;
295
296 interrupt-parent = <&intc>;
297 interrupts = <50>;
298
299 clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
300 clock-names = "baud", "module";
301
302 status = "disabled";
303 };
304
305 uart2: serial@10032000 {
306 compatible = "ingenic,jz4780-uart";
307 reg = <0x10032000 0x100>;
308
309 interrupt-parent = <&intc>;
310 interrupts = <49>;
311
312 clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
313 clock-names = "baud", "module";
314
315 status = "disabled";
316 };
317
318 uart3: serial@10033000 {
319 compatible = "ingenic,jz4780-uart";
320 reg = <0x10033000 0x100>;
321
322 interrupt-parent = <&intc>;
323 interrupts = <48>;
324
325 clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
326 clock-names = "baud", "module";
327
328 status = "disabled";
329 };
330
331 uart4: serial@10034000 {
332 compatible = "ingenic,jz4780-uart";
333 reg = <0x10034000 0x100>;
334
335 interrupt-parent = <&intc>;
336 interrupts = <34>;
337
338 clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
339 clock-names = "baud", "module";
340
341 status = "disabled";
342 };
343
344 spi1: spi@10044000 {
345 compatible = "ingenic,jz4780-spi";
346 reg = <0x10044000 0x1c>;
347 #address-cells = <1>;
348 #size-sells = <0>;
349
350 interrupt-parent = <&intc>;
351 interrupts = <7>;
352
353 clocks = <&cgu JZ4780_CLK_SSI1>;
354 clock-names = "spi";
355
356 dmas = <&dma JZ4780_DMA_SSI1_RX 0xffffffff>,
357 <&dma JZ4780_DMA_SSI1_TX 0xffffffff>;
358 dma-names = "rx", "tx";
359
360 status = "disabled";
361 };
362
363 i2c0: i2c@10050000 {
364 compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
365 #address-cells = <1>;
366 #size-cells = <0>;
367
368 reg = <0x10050000 0x1000>;
369
370 interrupt-parent = <&intc>;
371 interrupts = <60>;
372
373 clocks = <&cgu JZ4780_CLK_SMB0>;
374 clock-frequency = <100000>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&pins_i2c0_data>;
377
378 status = "disabled";
379 };
380
381 i2c1: i2c@10051000 {
382 compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
383 #address-cells = <1>;
384 #size-cells = <0>;
385 reg = <0x10051000 0x1000>;
386
387 interrupt-parent = <&intc>;
388 interrupts = <59>;
389
390 clocks = <&cgu JZ4780_CLK_SMB1>;
391 clock-frequency = <100000>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&pins_i2c1_data>;
394
395 status = "disabled";
396 };
397
398 i2c2: i2c@10052000 {
399 compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
400 #address-cells = <1>;
401 #size-cells = <0>;
402 reg = <0x10052000 0x1000>;
403
404 interrupt-parent = <&intc>;
405 interrupts = <58>;
406
407 clocks = <&cgu JZ4780_CLK_SMB2>;
408 clock-frequency = <100000>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&pins_i2c2_data>;
411
412 status = "disabled";
413 };
414
415 i2c3: i2c@10053000 {
416 compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
417 #address-cells = <1>;
418 #size-cells = <0>;
419 reg = <0x10053000 0x1000>;
420
421 interrupt-parent = <&intc>;
422 interrupts = <57>;
423
424 clocks = <&cgu JZ4780_CLK_SMB3>;
425 clock-frequency = <100000>;
426 pinctrl-names = "default";
427 pinctrl-0 = <&pins_i2c3_data>;
428
429 status = "disabled";
430 };
431
432 i2c4: i2c@10054000 {
433 compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
434 #address-cells = <1>;
435 #size-cells = <0>;
436 reg = <0x10054000 0x1000>;
437
438 interrupt-parent = <&intc>;
439 interrupts = <56>;
440
441 clocks = <&cgu JZ4780_CLK_SMB4>;
442 clock-frequency = <100000>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&pins_i2c4_data>;
445
446 status = "disabled";
447 };
448
449 hdmi: hdmi@10180000 {
450 compatible = "ingenic,jz4780-dw-hdmi";
451 reg = <0x10180000 0x8000>;
452 reg-io-width = <4>;
453
454 clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
455 clock-names = "iahb", "isfr";
456
457 interrupt-parent = <&intc>;
458 interrupts = <3>;
459
460 status = "disabled";
461 };
462
463 lcdc0: lcdc0@13050000 {
464 compatible = "ingenic,jz4780-lcd";
465 reg = <0x13050000 0x1800>;
466
467 clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>;
468 clock-names = "lcd", "lcd_pclk";
469
470 interrupt-parent = <&intc>;
471 interrupts = <31>;
472
473 status = "disabled";
474 };
475
476 lcdc1: lcdc1@130a0000 {
477 compatible = "ingenic,jz4780-lcd";
478 reg = <0x130a0000 0x1800>;
479
480 clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD1PIXCLK>;
481 clock-names = "lcd", "lcd_pclk";
482
483 interrupt-parent = <&intc>;
484 interrupts = <23>;
485
486 status = "disabled";
487 };
488
489 nemc: nemc@13410000 {
490 compatible = "ingenic,jz4780-nemc", "simple-mfd";
491 reg = <0x13410000 0x10000>;
492 #address-cells = <2>;
493 #size-cells = <1>;
494 ranges = <0 0 0x13410000 0x10000>,
495 <1 0 0x1b000000 0x1000000>,
496 <2 0 0x1a000000 0x1000000>,
497 <3 0 0x19000000 0x1000000>,
498 <4 0 0x18000000 0x1000000>,
499 <5 0 0x17000000 0x1000000>,
500 <6 0 0x16000000 0x1000000>;
501
502 clocks = <&cgu JZ4780_CLK_NEMC>;
503
504 status = "disabled";
505
506 efuse: efuse@d0 {
507 reg = <0 0xd0 0x30>;
508 compatible = "ingenic,jz4780-efuse";
509
510 clocks = <&cgu JZ4780_CLK_AHB2>;
511
512 #address-cells = <1>;
513 #size-cells = <1>;
514
515 eth0_addr: eth-mac-addr@22 {
516 reg = <0x22 0x6>;
517 };
518 };
519 };
520
521 dma: dma@13420000 {
522 compatible = "ingenic,jz4780-dma";
523 reg = <0x13420000 0x400>, <0x13421000 0x40>;
524 #dma-cells = <2>;
525
526 interrupt-parent = <&intc>;
527 interrupts = <10>;
528
529 clocks = <&cgu JZ4780_CLK_PDMA>;
530 };
531
532 mmc0: mmc@13450000 {
533 compatible = "ingenic,jz4780-mmc";
534 reg = <0x13450000 0x1000>;
535
536 interrupt-parent = <&intc>;
537 interrupts = <37>;
538
539 clocks = <&cgu JZ4780_CLK_MSC0>;
540 clock-names = "mmc";
541
542 cap-sd-highspeed;
543 cap-mmc-highspeed;
544 cap-sdio-irq;
545 dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>,
546 <&dma JZ4780_DMA_MSC0_TX 0xffffffff>;
547 dma-names = "rx", "tx";
548
549 status = "disabled";
550 };
551
552 mmc1: mmc@13460000 {
553 compatible = "ingenic,jz4780-mmc";
554 reg = <0x13460000 0x1000>;
555
556 interrupt-parent = <&intc>;
557 interrupts = <36>;
558
559 clocks = <&cgu JZ4780_CLK_MSC1>;
560 clock-names = "mmc";
561
562 cap-sd-highspeed;
563 cap-mmc-highspeed;
564 cap-sdio-irq;
565 dmas = <&dma JZ4780_DMA_MSC1_RX 0xffffffff>,
566 <&dma JZ4780_DMA_MSC1_TX 0xffffffff>;
567 dma-names = "rx", "tx";
568
569 status = "disabled";
570 };
571
572 bch: bch@134d0000 {
573 compatible = "ingenic,jz4780-bch";
574 reg = <0x134d0000 0x10000>;
575
576 clocks = <&cgu JZ4780_CLK_BCH>;
577
578 status = "disabled";
579 };
580
581 otg: usb@13500000 {
582 compatible = "ingenic,jz4780-otg";
583 reg = <0x13500000 0x40000>;
584
585 interrupt-parent = <&intc>;
586 interrupts = <21>;
587
588 clocks = <&cgu JZ4780_CLK_UHC>;
589 clock-names = "otg";
590
591 phys = <&otg_phy>;
592 phy-names = "usb2-phy";
593
594 g-rx-fifo-size = <768>;
595 g-np-tx-fifo-size = <256>;
596 g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
597
598 status = "disabled";
599 };
600};