1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Copyright 2013 Gateworks Corporation
  4 */
  5
  6/dts-v1/;
  7#include "imx6q.dtsi"
  8#include "imx6qdl-gw54xx.dtsi"
  9#include <dt-bindings/media/tda1997x.h>
 10
 11/ {
 12	model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
 13	compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
 14
 15	sound-digital {
 16		compatible = "simple-audio-card";
 17		simple-audio-card,name = "tda1997x-audio";
 18		simple-audio-card,format = "i2s";
 19		simple-audio-card,bitclock-master = <&sound_codec>;
 20		simple-audio-card,frame-master = <&sound_codec>;
 21
 22		sound_cpu: simple-audio-card,cpu {
 23			sound-dai = <&ssi2>;
 24		};
 25
 26		sound_codec: simple-audio-card,codec {
 27			sound-dai = <&hdmi_receiver>;
 28		};
 29	};
 30};
 31
 32&i2c3 {
 33	adv7180: camera@20 {
 34		compatible = "adi,adv7180";
 35		pinctrl-names = "default";
 36		pinctrl-0 = <&pinctrl_adv7180>;
 37		reg = <0x20>;
 38		powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
 39		interrupt-parent = <&gpio3>;
 40		interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
 41
 42		port {
 43			adv7180_to_ipu2_csi1_mux: endpoint {
 44				remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
 45				bus-width = <8>;
 46			};
 47		};
 48	};
 49
 50	hdmi_receiver: hdmi-receiver@48 {
 51		compatible = "nxp,tda19971";
 52		pinctrl-names = "default";
 53		pinctrl-0 = <&pinctrl_tda1997x>;
 54		reg = <0x48>;
 55		interrupt-parent = <&gpio1>;
 56		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
 57		DOVDD-supply = <&reg_3p3v>;
 58		AVDD-supply = <&sw4_reg>;
 59		DVDD-supply = <&sw4_reg>;
 60		#sound-dai-cells = <0>;
 61		nxp,audout-format = "i2s";
 62		nxp,audout-layout = <0>;
 63		nxp,audout-width = <16>;
 64		nxp,audout-mclk-fs = <128>;
 65		/*
 66		 * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
 67		 * and Y[11:4] across 16bits in the same cycle
 68		 * which we map to VP[15:08]<->CSI_DATA[19:12]
 69		 */
 70		nxp,vidout-portcfg =
 71			/*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
 72			< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
 73			/*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
 74			< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
 75			/*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
 76			< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
 77			/*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
 78			< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
 79
 80		port {
 81			tda1997x_to_ipu1_csi0_mux: endpoint {
 82				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 83				bus-width = <16>;
 84				hsync-active = <1>;
 85				vsync-active = <1>;
 86				data-active = <1>;
 87			};
 88		};
 89	};
 90};
 91
 92&ipu1_csi0_from_ipu1_csi0_mux {
 93	bus-width = <16>;
 94};
 95
 96&ipu1_csi0_mux_from_parallel_sensor {
 97	remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
 98	bus-width = <16>;
 99};
100
101&ipu1_csi0 {
102	pinctrl-names = "default";
103	pinctrl-0 = <&pinctrl_ipu1_csi0>;
104};
105
106&ipu2_csi1_from_ipu2_csi1_mux {
107	bus-width = <8>;
108};
109
110&ipu2_csi1_mux_from_parallel_sensor {
111	remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
112	bus-width = <8>;
113};
114
115&ipu2_csi1 {
116	pinctrl-names = "default";
117	pinctrl-0 = <&pinctrl_ipu2_csi1>;
118};
119
120&sata {
121	status = "okay";
122};
123
124&iomuxc {
125	pinctrl_adv7180: adv7180grp {
126		fsl,pins = <
127			MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x0001b0b0
128			MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x4001b0b0
129		>;
130	};
131
132	pinctrl_ipu1_csi0: ipu1_csi0grp {
133		fsl,pins = <
134			MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04		0x1b0b0
135			MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05		0x1b0b0
136			MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06		0x1b0b0
137			MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07		0x1b0b0
138			MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08		0x1b0b0
139			MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09		0x1b0b0
140			MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10		0x1b0b0
141			MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11		0x1b0b0
142			MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12		0x1b0b0
143			MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13		0x1b0b0
144			MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14		0x1b0b0
145			MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15		0x1b0b0
146			MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16		0x1b0b0
147			MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17		0x1b0b0
148			MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18		0x1b0b0
149			MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19		0x1b0b0
150			MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC		0x1b0b0
151			MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK	0x1b0b0
152			MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC		0x1b0b0
153		>;
154	};
155
156	pinctrl_ipu2_csi1: ipu2_csi1grp {
157		fsl,pins = <
158			MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19    0x1b0b0
159			MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18    0x1b0b0
160			MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17    0x1b0b0
161			MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16    0x1b0b0
162			MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15    0x1b0b0
163			MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14    0x1b0b0
164			MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13    0x1b0b0
165			MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12    0x1b0b0
166			MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC     0x1b0b0
167			MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC     0x1b0b0
168			MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK    0x1b0b0
169		>;
170	};
171
172	pinctrl_tda1997x: tda1997xgrp {
173		fsl,pins = <
174			MX6QDL_PAD_GPIO_7__GPIO1_IO07	0x1b0b0
175		>;
176	};
177};