1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Samsung Exynos5420 SoC cpu device tree source
  4 *
  5 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
  6 *		http://www.samsung.com
  7 *
  8 * This file provides desired ordering for Exynos5420 and Exynos5800
  9 * boards: CPU[0123] being the A15.
 10 *
 11 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
 12 * but particular boards choose different booting order.
 13 *
 14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
 15 * booting cluster (big or LITTLE) is chosen by IROM code by reading
 16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
 17 * from the LITTLE: Cortex-A7.
 18 */
 19
 20/ {
 21	cpus {
 22		#address-cells = <1>;
 23		#size-cells = <0>;
 24
 25		cpu-map {
 26			cluster0 {
 27				core0 {
 28					cpu = <&cpu0>;
 29				};
 30				core1 {
 31					cpu = <&cpu1>;
 32				};
 33				core2 {
 34					cpu = <&cpu2>;
 35				};
 36				core3 {
 37					cpu = <&cpu3>;
 38				};
 39			};
 40
 41			cluster1 {
 42				core0 {
 43					cpu = <&cpu4>;
 44				};
 45				core1 {
 46					cpu = <&cpu5>;
 47				};
 48				core2 {
 49					cpu = <&cpu6>;
 50				};
 51				core3 {
 52					cpu = <&cpu7>;
 53				};
 54			};
 55		};
 56
 57		cpu0: cpu@0 {
 58			device_type = "cpu";
 59			compatible = "arm,cortex-a15";
 60			reg = <0x0>;
 61			clocks = <&clock CLK_ARM_CLK>;
 62			clock-frequency = <1800000000>;
 63			cci-control-port = <&cci_control1>;
 64			operating-points-v2 = <&cluster_a15_opp_table>;
 65			#cooling-cells = <2>; /* min followed by max */
 66			capacity-dmips-mhz = <1024>;
 67		};
 68
 69		cpu1: cpu@1 {
 70			device_type = "cpu";
 71			compatible = "arm,cortex-a15";
 72			reg = <0x1>;
 73			clocks = <&clock CLK_ARM_CLK>;
 74			clock-frequency = <1800000000>;
 75			cci-control-port = <&cci_control1>;
 76			operating-points-v2 = <&cluster_a15_opp_table>;
 77			#cooling-cells = <2>; /* min followed by max */
 78			capacity-dmips-mhz = <1024>;
 79		};
 80
 81		cpu2: cpu@2 {
 82			device_type = "cpu";
 83			compatible = "arm,cortex-a15";
 84			reg = <0x2>;
 85			clocks = <&clock CLK_ARM_CLK>;
 86			clock-frequency = <1800000000>;
 87			cci-control-port = <&cci_control1>;
 88			operating-points-v2 = <&cluster_a15_opp_table>;
 89			#cooling-cells = <2>; /* min followed by max */
 90			capacity-dmips-mhz = <1024>;
 91		};
 92
 93		cpu3: cpu@3 {
 94			device_type = "cpu";
 95			compatible = "arm,cortex-a15";
 96			reg = <0x3>;
 97			clocks = <&clock CLK_ARM_CLK>;
 98			clock-frequency = <1800000000>;
 99			cci-control-port = <&cci_control1>;
100			operating-points-v2 = <&cluster_a15_opp_table>;
101			#cooling-cells = <2>; /* min followed by max */
102			capacity-dmips-mhz = <1024>;
103		};
104
105		cpu4: cpu@100 {
106			device_type = "cpu";
107			compatible = "arm,cortex-a7";
108			reg = <0x100>;
109			clocks = <&clock CLK_KFC_CLK>;
110			clock-frequency = <1000000000>;
111			cci-control-port = <&cci_control0>;
112			operating-points-v2 = <&cluster_a7_opp_table>;
113			#cooling-cells = <2>; /* min followed by max */
114			capacity-dmips-mhz = <539>;
115		};
116
117		cpu5: cpu@101 {
118			device_type = "cpu";
119			compatible = "arm,cortex-a7";
120			reg = <0x101>;
121			clocks = <&clock CLK_KFC_CLK>;
122			clock-frequency = <1000000000>;
123			cci-control-port = <&cci_control0>;
124			operating-points-v2 = <&cluster_a7_opp_table>;
125			#cooling-cells = <2>; /* min followed by max */
126			capacity-dmips-mhz = <539>;
127		};
128
129		cpu6: cpu@102 {
130			device_type = "cpu";
131			compatible = "arm,cortex-a7";
132			reg = <0x102>;
133			clocks = <&clock CLK_KFC_CLK>;
134			clock-frequency = <1000000000>;
135			cci-control-port = <&cci_control0>;
136			operating-points-v2 = <&cluster_a7_opp_table>;
137			#cooling-cells = <2>; /* min followed by max */
138			capacity-dmips-mhz = <539>;
139		};
140
141		cpu7: cpu@103 {
142			device_type = "cpu";
143			compatible = "arm,cortex-a7";
144			reg = <0x103>;
145			clocks = <&clock CLK_KFC_CLK>;
146			clock-frequency = <1000000000>;
147			cci-control-port = <&cci_control0>;
148			operating-points-v2 = <&cluster_a7_opp_table>;
149			#cooling-cells = <2>; /* min followed by max */
150			capacity-dmips-mhz = <539>;
151		};
152	};
153};
154
155&arm_a7_pmu {
156	interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
157	status = "okay";
158};
159
160&arm_a15_pmu {
161	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
162	status = "okay";
163};