1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright 2022 Broadcom Ltd.
  4 */
  5
  6#include <dt-bindings/interrupt-controller/arm-gic.h>
  7#include <dt-bindings/interrupt-controller/irq.h>
  8
  9/ {
 10	compatible = "brcm,bcm6878", "brcm,bcmbca";
 11	#address-cells = <1>;
 12	#size-cells = <1>;
 13
 14	interrupt-parent = <&gic>;
 15
 16	cpus {
 17		#address-cells = <1>;
 18		#size-cells = <0>;
 19
 20		CA7_0: cpu@0 {
 21			device_type = "cpu";
 22			compatible = "arm,cortex-a7";
 23			reg = <0x0>;
 24			next-level-cache = <&L2_0>;
 25			enable-method = "psci";
 26		};
 27
 28		CA7_1: cpu@1 {
 29			device_type = "cpu";
 30			compatible = "arm,cortex-a7";
 31			reg = <0x1>;
 32			next-level-cache = <&L2_0>;
 33			enable-method = "psci";
 34		};
 35
 36		L2_0: l2-cache0 {
 37			compatible = "cache";
 38			cache-level = <2>;
 39		};
 40	};
 41
 42	timer {
 43		compatible = "arm,armv7-timer";
 44		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 45			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 46			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 47			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 48		arm,cpu-registers-not-fw-configured;
 49	};
 50
 51	pmu: pmu {
 52		compatible = "arm,cortex-a7-pmu";
 53		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 54			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 55		interrupt-affinity = <&CA7_0>, <&CA7_1>;
 56	};
 57
 58	clocks: clocks {
 59		periph_clk: periph-clk {
 60			compatible = "fixed-clock";
 61			#clock-cells = <0>;
 62			clock-frequency = <200000000>;
 63		};
 64		uart_clk: uart-clk {
 65			compatible = "fixed-factor-clock";
 66			#clock-cells = <0>;
 67			clocks = <&periph_clk>;
 68			clock-div = <4>;
 69			clock-mult = <1>;
 70		};
 71	};
 72
 73	psci {
 74		compatible = "arm,psci-0.2";
 75		method = "smc";
 76	};
 77
 78	axi@81000000 {
 79		compatible = "simple-bus";
 80		#address-cells = <1>;
 81		#size-cells = <1>;
 82		ranges = <0 0x81000000 0x8000>;
 83
 84		gic: interrupt-controller@1000 {
 85			compatible = "arm,cortex-a7-gic";
 86			#interrupt-cells = <3>;
 87			interrupt-controller;
 88			reg = <0x1000 0x1000>,
 89				<0x2000 0x2000>,
 90				<0x4000 0x2000>,
 91				<0x6000 0x2000>;
 92			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
 93					IRQ_TYPE_LEVEL_HIGH)>;
 94		};
 95	};
 96
 97	bus@ff800000 {
 98		compatible = "simple-bus";
 99		#address-cells = <1>;
100		#size-cells = <1>;
101		ranges = <0 0xff800000 0x800000>;
102
103		uart0: serial@12000 {
104			compatible = "arm,pl011", "arm,primecell";
105			reg = <0x12000 0x1000>;
106			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
107			clocks = <&uart_clk>, <&uart_clk>;
108			clock-names = "uartclk", "apb_pclk";
109			status = "disabled";
110		};
111	};
112};