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1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * PWM controller driver for Amlogic Meson SoCs.
4 *
5 * This PWM is only a set of Gates, Dividers and Counters:
6 * PWM output is achieved by calculating a clock that permits calculating
7 * two periods (low and high). The counter then has to be set to switch after
8 * N cycles for the first half period.
9 * The hardware has no "polarity" setting. This driver reverses the period
10 * cycles (the low length is inverted with the high length) for
11 * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
12 * from the hardware.
13 * Setting the duty cycle will disable and re-enable the PWM output.
14 * Disabling the PWM stops the output immediately (without waiting for the
15 * current period to complete first).
16 *
17 * The public S912 (GXM) datasheet contains some documentation for this PWM
18 * controller starting on page 543:
19 * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
20 * An updated version of this IP block is found in S922X (G12B) SoCs. The
21 * datasheet contains the description for this IP block revision starting at
22 * page 1084:
23 * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
24 *
25 * Copyright (c) 2016 BayLibre, SAS.
26 * Author: Neil Armstrong <narmstrong@baylibre.com>
27 * Copyright (C) 2014 Amlogic, Inc.
28 */
29
30#include <linux/bitfield.h>
31#include <linux/bits.h>
32#include <linux/clk.h>
33#include <linux/clk-provider.h>
34#include <linux/err.h>
35#include <linux/io.h>
36#include <linux/kernel.h>
37#include <linux/math64.h>
38#include <linux/module.h>
39#include <linux/of.h>
40#include <linux/of_device.h>
41#include <linux/platform_device.h>
42#include <linux/pwm.h>
43#include <linux/slab.h>
44#include <linux/spinlock.h>
45
46#define REG_PWM_A 0x0
47#define REG_PWM_B 0x4
48#define PWM_LOW_MASK GENMASK(15, 0)
49#define PWM_HIGH_MASK GENMASK(31, 16)
50
51#define REG_MISC_AB 0x8
52#define MISC_B_CLK_EN BIT(23)
53#define MISC_A_CLK_EN BIT(15)
54#define MISC_CLK_DIV_MASK 0x7f
55#define MISC_B_CLK_DIV_SHIFT 16
56#define MISC_A_CLK_DIV_SHIFT 8
57#define MISC_B_CLK_SEL_SHIFT 6
58#define MISC_A_CLK_SEL_SHIFT 4
59#define MISC_CLK_SEL_MASK 0x3
60#define MISC_B_EN BIT(1)
61#define MISC_A_EN BIT(0)
62
63#define MESON_NUM_PWMS 2
64
65static struct meson_pwm_channel_data {
66 u8 reg_offset;
67 u8 clk_sel_shift;
68 u8 clk_div_shift;
69 u32 clk_en_mask;
70 u32 pwm_en_mask;
71} meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
72 {
73 .reg_offset = REG_PWM_A,
74 .clk_sel_shift = MISC_A_CLK_SEL_SHIFT,
75 .clk_div_shift = MISC_A_CLK_DIV_SHIFT,
76 .clk_en_mask = MISC_A_CLK_EN,
77 .pwm_en_mask = MISC_A_EN,
78 },
79 {
80 .reg_offset = REG_PWM_B,
81 .clk_sel_shift = MISC_B_CLK_SEL_SHIFT,
82 .clk_div_shift = MISC_B_CLK_DIV_SHIFT,
83 .clk_en_mask = MISC_B_CLK_EN,
84 .pwm_en_mask = MISC_B_EN,
85 }
86};
87
88struct meson_pwm_channel {
89 unsigned int hi;
90 unsigned int lo;
91 u8 pre_div;
92
93 struct clk *clk_parent;
94 struct clk_mux mux;
95 struct clk *clk;
96};
97
98struct meson_pwm_data {
99 const char * const *parent_names;
100 unsigned int num_parents;
101};
102
103struct meson_pwm {
104 struct pwm_chip chip;
105 const struct meson_pwm_data *data;
106 struct meson_pwm_channel channels[MESON_NUM_PWMS];
107 void __iomem *base;
108 /*
109 * Protects register (write) access to the REG_MISC_AB register
110 * that is shared between the two PWMs.
111 */
112 spinlock_t lock;
113};
114
115static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
116{
117 return container_of(chip, struct meson_pwm, chip);
118}
119
120static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
121{
122 struct meson_pwm *meson = to_meson_pwm(chip);
123 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
124 struct device *dev = chip->dev;
125 int err;
126
127 if (channel->clk_parent) {
128 err = clk_set_parent(channel->clk, channel->clk_parent);
129 if (err < 0) {
130 dev_err(dev, "failed to set parent %s for %s: %d\n",
131 __clk_get_name(channel->clk_parent),
132 __clk_get_name(channel->clk), err);
133 return err;
134 }
135 }
136
137 err = clk_prepare_enable(channel->clk);
138 if (err < 0) {
139 dev_err(dev, "failed to enable clock %s: %d\n",
140 __clk_get_name(channel->clk), err);
141 return err;
142 }
143
144 return 0;
145}
146
147static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
148{
149 struct meson_pwm *meson = to_meson_pwm(chip);
150 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
151
152 clk_disable_unprepare(channel->clk);
153}
154
155static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm,
156 const struct pwm_state *state)
157{
158 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
159 unsigned int duty, period, pre_div, cnt, duty_cnt;
160 unsigned long fin_freq;
161
162 duty = state->duty_cycle;
163 period = state->period;
164
165 if (state->polarity == PWM_POLARITY_INVERSED)
166 duty = period - duty;
167
168 fin_freq = clk_get_rate(channel->clk);
169 if (fin_freq == 0) {
170 dev_err(meson->chip.dev, "invalid source clock frequency\n");
171 return -EINVAL;
172 }
173
174 dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
175
176 pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL);
177 if (pre_div > MISC_CLK_DIV_MASK) {
178 dev_err(meson->chip.dev, "unable to get period pre_div\n");
179 return -EINVAL;
180 }
181
182 cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1));
183 if (cnt > 0xffff) {
184 dev_err(meson->chip.dev, "unable to get period cnt\n");
185 return -EINVAL;
186 }
187
188 dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period,
189 pre_div, cnt);
190
191 if (duty == period) {
192 channel->pre_div = pre_div;
193 channel->hi = cnt;
194 channel->lo = 0;
195 } else if (duty == 0) {
196 channel->pre_div = pre_div;
197 channel->hi = 0;
198 channel->lo = cnt;
199 } else {
200 /* Then check is we can have the duty with the same pre_div */
201 duty_cnt = div64_u64(fin_freq * (u64)duty,
202 NSEC_PER_SEC * (pre_div + 1));
203 if (duty_cnt > 0xffff) {
204 dev_err(meson->chip.dev, "unable to get duty cycle\n");
205 return -EINVAL;
206 }
207
208 dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n",
209 duty, pre_div, duty_cnt);
210
211 channel->pre_div = pre_div;
212 channel->hi = duty_cnt;
213 channel->lo = cnt - duty_cnt;
214 }
215
216 return 0;
217}
218
219static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm)
220{
221 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
222 struct meson_pwm_channel_data *channel_data;
223 unsigned long flags;
224 u32 value;
225
226 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
227
228 spin_lock_irqsave(&meson->lock, flags);
229
230 value = readl(meson->base + REG_MISC_AB);
231 value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift);
232 value |= channel->pre_div << channel_data->clk_div_shift;
233 value |= channel_data->clk_en_mask;
234 writel(value, meson->base + REG_MISC_AB);
235
236 value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
237 FIELD_PREP(PWM_LOW_MASK, channel->lo);
238 writel(value, meson->base + channel_data->reg_offset);
239
240 value = readl(meson->base + REG_MISC_AB);
241 value |= channel_data->pwm_en_mask;
242 writel(value, meson->base + REG_MISC_AB);
243
244 spin_unlock_irqrestore(&meson->lock, flags);
245}
246
247static void meson_pwm_disable(struct meson_pwm *meson, struct pwm_device *pwm)
248{
249 unsigned long flags;
250 u32 value;
251
252 spin_lock_irqsave(&meson->lock, flags);
253
254 value = readl(meson->base + REG_MISC_AB);
255 value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
256 writel(value, meson->base + REG_MISC_AB);
257
258 spin_unlock_irqrestore(&meson->lock, flags);
259}
260
261static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
262 const struct pwm_state *state)
263{
264 struct meson_pwm *meson = to_meson_pwm(chip);
265 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
266 int err = 0;
267
268 if (!state->enabled) {
269 if (state->polarity == PWM_POLARITY_INVERSED) {
270 /*
271 * This IP block revision doesn't have an "always high"
272 * setting which we can use for "inverted disabled".
273 * Instead we achieve this using the same settings
274 * that we use a pre_div of 0 (to get the shortest
275 * possible duration for one "count") and
276 * "period == duty_cycle". This results in a signal
277 * which is LOW for one "count", while being HIGH for
278 * the rest of the (so the signal is HIGH for slightly
279 * less than 100% of the period, but this is the best
280 * we can achieve).
281 */
282 channel->pre_div = 0;
283 channel->hi = ~0;
284 channel->lo = 0;
285
286 meson_pwm_enable(meson, pwm);
287 } else {
288 meson_pwm_disable(meson, pwm);
289 }
290 } else {
291 err = meson_pwm_calc(meson, pwm, state);
292 if (err < 0)
293 return err;
294
295 meson_pwm_enable(meson, pwm);
296 }
297
298 return 0;
299}
300
301static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip,
302 struct pwm_device *pwm, u32 cnt)
303{
304 struct meson_pwm *meson = to_meson_pwm(chip);
305 struct meson_pwm_channel *channel;
306 unsigned long fin_freq;
307 u32 fin_ns;
308
309 /* to_meson_pwm() can only be used after .get_state() is called */
310 channel = &meson->channels[pwm->hwpwm];
311
312 fin_freq = clk_get_rate(channel->clk);
313 if (fin_freq == 0)
314 return 0;
315
316 fin_ns = div_u64(NSEC_PER_SEC, fin_freq);
317
318 return cnt * fin_ns * (channel->pre_div + 1);
319}
320
321static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
322 struct pwm_state *state)
323{
324 struct meson_pwm *meson = to_meson_pwm(chip);
325 struct meson_pwm_channel_data *channel_data;
326 struct meson_pwm_channel *channel;
327 u32 value, tmp;
328
329 if (!state)
330 return 0;
331
332 channel = &meson->channels[pwm->hwpwm];
333 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
334
335 value = readl(meson->base + REG_MISC_AB);
336
337 tmp = channel_data->pwm_en_mask | channel_data->clk_en_mask;
338 state->enabled = (value & tmp) == tmp;
339
340 tmp = value >> channel_data->clk_div_shift;
341 channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp);
342
343 value = readl(meson->base + channel_data->reg_offset);
344
345 channel->lo = FIELD_GET(PWM_LOW_MASK, value);
346 channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
347
348 if (channel->lo == 0) {
349 state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
350 state->duty_cycle = state->period;
351 } else if (channel->lo >= channel->hi) {
352 state->period = meson_pwm_cnt_to_ns(chip, pwm,
353 channel->lo + channel->hi);
354 state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm,
355 channel->hi);
356 } else {
357 state->period = 0;
358 state->duty_cycle = 0;
359 }
360
361 return 0;
362}
363
364static const struct pwm_ops meson_pwm_ops = {
365 .request = meson_pwm_request,
366 .free = meson_pwm_free,
367 .apply = meson_pwm_apply,
368 .get_state = meson_pwm_get_state,
369 .owner = THIS_MODULE,
370};
371
372static const char * const pwm_meson8b_parent_names[] = {
373 "xtal", "vid_pll", "fclk_div4", "fclk_div3"
374};
375
376static const struct meson_pwm_data pwm_meson8b_data = {
377 .parent_names = pwm_meson8b_parent_names,
378 .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
379};
380
381static const char * const pwm_gxbb_parent_names[] = {
382 "xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
383};
384
385static const struct meson_pwm_data pwm_gxbb_data = {
386 .parent_names = pwm_gxbb_parent_names,
387 .num_parents = ARRAY_SIZE(pwm_gxbb_parent_names),
388};
389
390/*
391 * Only the 2 first inputs of the GXBB AO PWMs are valid
392 * The last 2 are grounded
393 */
394static const char * const pwm_gxbb_ao_parent_names[] = {
395 "xtal", "clk81"
396};
397
398static const struct meson_pwm_data pwm_gxbb_ao_data = {
399 .parent_names = pwm_gxbb_ao_parent_names,
400 .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
401};
402
403static const char * const pwm_axg_ee_parent_names[] = {
404 "xtal", "fclk_div5", "fclk_div4", "fclk_div3"
405};
406
407static const struct meson_pwm_data pwm_axg_ee_data = {
408 .parent_names = pwm_axg_ee_parent_names,
409 .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
410};
411
412static const char * const pwm_axg_ao_parent_names[] = {
413 "aoclk81", "xtal", "fclk_div4", "fclk_div5"
414};
415
416static const struct meson_pwm_data pwm_axg_ao_data = {
417 .parent_names = pwm_axg_ao_parent_names,
418 .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
419};
420
421static const char * const pwm_g12a_ao_ab_parent_names[] = {
422 "xtal", "aoclk81", "fclk_div4", "fclk_div5"
423};
424
425static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
426 .parent_names = pwm_g12a_ao_ab_parent_names,
427 .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
428};
429
430static const char * const pwm_g12a_ao_cd_parent_names[] = {
431 "xtal", "aoclk81",
432};
433
434static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
435 .parent_names = pwm_g12a_ao_cd_parent_names,
436 .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
437};
438
439static const char * const pwm_g12a_ee_parent_names[] = {
440 "xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
441};
442
443static const struct meson_pwm_data pwm_g12a_ee_data = {
444 .parent_names = pwm_g12a_ee_parent_names,
445 .num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names),
446};
447
448static const struct of_device_id meson_pwm_matches[] = {
449 {
450 .compatible = "amlogic,meson8b-pwm",
451 .data = &pwm_meson8b_data
452 },
453 {
454 .compatible = "amlogic,meson-gxbb-pwm",
455 .data = &pwm_gxbb_data
456 },
457 {
458 .compatible = "amlogic,meson-gxbb-ao-pwm",
459 .data = &pwm_gxbb_ao_data
460 },
461 {
462 .compatible = "amlogic,meson-axg-ee-pwm",
463 .data = &pwm_axg_ee_data
464 },
465 {
466 .compatible = "amlogic,meson-axg-ao-pwm",
467 .data = &pwm_axg_ao_data
468 },
469 {
470 .compatible = "amlogic,meson-g12a-ee-pwm",
471 .data = &pwm_g12a_ee_data
472 },
473 {
474 .compatible = "amlogic,meson-g12a-ao-pwm-ab",
475 .data = &pwm_g12a_ao_ab_data
476 },
477 {
478 .compatible = "amlogic,meson-g12a-ao-pwm-cd",
479 .data = &pwm_g12a_ao_cd_data
480 },
481 {},
482};
483MODULE_DEVICE_TABLE(of, meson_pwm_matches);
484
485static int meson_pwm_init_channels(struct meson_pwm *meson)
486{
487 struct device *dev = meson->chip.dev;
488 struct clk_init_data init;
489 unsigned int i;
490 char name[255];
491 int err;
492
493 for (i = 0; i < meson->chip.npwm; i++) {
494 struct meson_pwm_channel *channel = &meson->channels[i];
495
496 snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
497
498 init.name = name;
499 init.ops = &clk_mux_ops;
500 init.flags = 0;
501 init.parent_names = meson->data->parent_names;
502 init.num_parents = meson->data->num_parents;
503
504 channel->mux.reg = meson->base + REG_MISC_AB;
505 channel->mux.shift =
506 meson_pwm_per_channel_data[i].clk_sel_shift;
507 channel->mux.mask = MISC_CLK_SEL_MASK;
508 channel->mux.flags = 0;
509 channel->mux.lock = &meson->lock;
510 channel->mux.table = NULL;
511 channel->mux.hw.init = &init;
512
513 channel->clk = devm_clk_register(dev, &channel->mux.hw);
514 if (IS_ERR(channel->clk)) {
515 err = PTR_ERR(channel->clk);
516 dev_err(dev, "failed to register %s: %d\n", name, err);
517 return err;
518 }
519
520 snprintf(name, sizeof(name), "clkin%u", i);
521
522 channel->clk_parent = devm_clk_get_optional(dev, name);
523 if (IS_ERR(channel->clk_parent))
524 return PTR_ERR(channel->clk_parent);
525 }
526
527 return 0;
528}
529
530static int meson_pwm_probe(struct platform_device *pdev)
531{
532 struct meson_pwm *meson;
533 int err;
534
535 meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
536 if (!meson)
537 return -ENOMEM;
538
539 meson->base = devm_platform_ioremap_resource(pdev, 0);
540 if (IS_ERR(meson->base))
541 return PTR_ERR(meson->base);
542
543 spin_lock_init(&meson->lock);
544 meson->chip.dev = &pdev->dev;
545 meson->chip.ops = &meson_pwm_ops;
546 meson->chip.npwm = MESON_NUM_PWMS;
547
548 meson->data = of_device_get_match_data(&pdev->dev);
549
550 err = meson_pwm_init_channels(meson);
551 if (err < 0)
552 return err;
553
554 err = devm_pwmchip_add(&pdev->dev, &meson->chip);
555 if (err < 0) {
556 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
557 return err;
558 }
559
560 return 0;
561}
562
563static struct platform_driver meson_pwm_driver = {
564 .driver = {
565 .name = "meson-pwm",
566 .of_match_table = meson_pwm_matches,
567 },
568 .probe = meson_pwm_probe,
569};
570module_platform_driver(meson_pwm_driver);
571
572MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
573MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
574MODULE_LICENSE("Dual BSD/GPL");
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * PWM controller driver for Amlogic Meson SoCs.
4 *
5 * This PWM is only a set of Gates, Dividers and Counters:
6 * PWM output is achieved by calculating a clock that permits calculating
7 * two periods (low and high). The counter then has to be set to switch after
8 * N cycles for the first half period.
9 * The hardware has no "polarity" setting. This driver reverses the period
10 * cycles (the low length is inverted with the high length) for
11 * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
12 * from the hardware.
13 * Setting the duty cycle will disable and re-enable the PWM output.
14 * Disabling the PWM stops the output immediately (without waiting for the
15 * current period to complete first).
16 *
17 * The public S912 (GXM) datasheet contains some documentation for this PWM
18 * controller starting on page 543:
19 * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
20 * An updated version of this IP block is found in S922X (G12B) SoCs. The
21 * datasheet contains the description for this IP block revision starting at
22 * page 1084:
23 * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
24 *
25 * Copyright (c) 2016 BayLibre, SAS.
26 * Author: Neil Armstrong <narmstrong@baylibre.com>
27 * Copyright (C) 2014 Amlogic, Inc.
28 */
29
30#include <linux/bitfield.h>
31#include <linux/bits.h>
32#include <linux/clk.h>
33#include <linux/clk-provider.h>
34#include <linux/err.h>
35#include <linux/io.h>
36#include <linux/kernel.h>
37#include <linux/math64.h>
38#include <linux/module.h>
39#include <linux/of.h>
40#include <linux/platform_device.h>
41#include <linux/pwm.h>
42#include <linux/slab.h>
43#include <linux/spinlock.h>
44
45#define REG_PWM_A 0x0
46#define REG_PWM_B 0x4
47#define PWM_LOW_MASK GENMASK(15, 0)
48#define PWM_HIGH_MASK GENMASK(31, 16)
49
50#define REG_MISC_AB 0x8
51#define MISC_B_CLK_EN_SHIFT 23
52#define MISC_A_CLK_EN_SHIFT 15
53#define MISC_CLK_DIV_WIDTH 7
54#define MISC_B_CLK_DIV_SHIFT 16
55#define MISC_A_CLK_DIV_SHIFT 8
56#define MISC_B_CLK_SEL_SHIFT 6
57#define MISC_A_CLK_SEL_SHIFT 4
58#define MISC_CLK_SEL_MASK 0x3
59#define MISC_B_EN BIT(1)
60#define MISC_A_EN BIT(0)
61
62#define MESON_NUM_PWMS 2
63#define MESON_NUM_MUX_PARENTS 4
64
65static struct meson_pwm_channel_data {
66 u8 reg_offset;
67 u8 clk_sel_shift;
68 u8 clk_div_shift;
69 u8 clk_en_shift;
70 u32 pwm_en_mask;
71} meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
72 {
73 .reg_offset = REG_PWM_A,
74 .clk_sel_shift = MISC_A_CLK_SEL_SHIFT,
75 .clk_div_shift = MISC_A_CLK_DIV_SHIFT,
76 .clk_en_shift = MISC_A_CLK_EN_SHIFT,
77 .pwm_en_mask = MISC_A_EN,
78 },
79 {
80 .reg_offset = REG_PWM_B,
81 .clk_sel_shift = MISC_B_CLK_SEL_SHIFT,
82 .clk_div_shift = MISC_B_CLK_DIV_SHIFT,
83 .clk_en_shift = MISC_B_CLK_EN_SHIFT,
84 .pwm_en_mask = MISC_B_EN,
85 }
86};
87
88struct meson_pwm_channel {
89 unsigned long rate;
90 unsigned int hi;
91 unsigned int lo;
92
93 struct clk_mux mux;
94 struct clk_divider div;
95 struct clk_gate gate;
96 struct clk *clk;
97};
98
99struct meson_pwm_data {
100 const char *const parent_names[MESON_NUM_MUX_PARENTS];
101};
102
103struct meson_pwm {
104 const struct meson_pwm_data *data;
105 struct meson_pwm_channel channels[MESON_NUM_PWMS];
106 void __iomem *base;
107 /*
108 * Protects register (write) access to the REG_MISC_AB register
109 * that is shared between the two PWMs.
110 */
111 spinlock_t lock;
112};
113
114static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
115{
116 return pwmchip_get_drvdata(chip);
117}
118
119static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
120{
121 struct meson_pwm *meson = to_meson_pwm(chip);
122 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
123 struct device *dev = pwmchip_parent(chip);
124 int err;
125
126 err = clk_prepare_enable(channel->clk);
127 if (err < 0) {
128 dev_err(dev, "failed to enable clock %s: %d\n",
129 __clk_get_name(channel->clk), err);
130 return err;
131 }
132
133 return 0;
134}
135
136static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
137{
138 struct meson_pwm *meson = to_meson_pwm(chip);
139 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
140
141 clk_disable_unprepare(channel->clk);
142}
143
144static int meson_pwm_calc(struct pwm_chip *chip, struct pwm_device *pwm,
145 const struct pwm_state *state)
146{
147 struct meson_pwm *meson = to_meson_pwm(chip);
148 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
149 unsigned int cnt, duty_cnt;
150 long fin_freq;
151 u64 duty, period, freq;
152
153 duty = state->duty_cycle;
154 period = state->period;
155
156 /*
157 * Note this is wrong. The result is an output wave that isn't really
158 * inverted and so is wrongly identified by .get_state as normal.
159 * Fixing this needs some care however as some machines might rely on
160 * this.
161 */
162 if (state->polarity == PWM_POLARITY_INVERSED)
163 duty = period - duty;
164
165 freq = div64_u64(NSEC_PER_SEC * 0xffffULL, period);
166 if (freq > ULONG_MAX)
167 freq = ULONG_MAX;
168
169 fin_freq = clk_round_rate(channel->clk, freq);
170 if (fin_freq <= 0) {
171 dev_err(pwmchip_parent(chip),
172 "invalid source clock frequency %llu\n", freq);
173 return fin_freq ? fin_freq : -EINVAL;
174 }
175
176 dev_dbg(pwmchip_parent(chip), "fin_freq: %ld Hz\n", fin_freq);
177
178 cnt = mul_u64_u64_div_u64(fin_freq, period, NSEC_PER_SEC);
179 if (cnt > 0xffff) {
180 dev_err(pwmchip_parent(chip), "unable to get period cnt\n");
181 return -EINVAL;
182 }
183
184 dev_dbg(pwmchip_parent(chip), "period=%llu cnt=%u\n", period, cnt);
185
186 if (duty == period) {
187 channel->hi = cnt;
188 channel->lo = 0;
189 } else if (duty == 0) {
190 channel->hi = 0;
191 channel->lo = cnt;
192 } else {
193 duty_cnt = mul_u64_u64_div_u64(fin_freq, duty, NSEC_PER_SEC);
194
195 dev_dbg(pwmchip_parent(chip), "duty=%llu duty_cnt=%u\n", duty, duty_cnt);
196
197 channel->hi = duty_cnt;
198 channel->lo = cnt - duty_cnt;
199 }
200
201 channel->rate = fin_freq;
202
203 return 0;
204}
205
206static void meson_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
207{
208 struct meson_pwm *meson = to_meson_pwm(chip);
209 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
210 struct meson_pwm_channel_data *channel_data;
211 unsigned long flags;
212 u32 value;
213 int err;
214
215 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
216
217 err = clk_set_rate(channel->clk, channel->rate);
218 if (err)
219 dev_err(pwmchip_parent(chip), "setting clock rate failed\n");
220
221 spin_lock_irqsave(&meson->lock, flags);
222
223 value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
224 FIELD_PREP(PWM_LOW_MASK, channel->lo);
225 writel(value, meson->base + channel_data->reg_offset);
226
227 value = readl(meson->base + REG_MISC_AB);
228 value |= channel_data->pwm_en_mask;
229 writel(value, meson->base + REG_MISC_AB);
230
231 spin_unlock_irqrestore(&meson->lock, flags);
232}
233
234static void meson_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
235{
236 struct meson_pwm *meson = to_meson_pwm(chip);
237 unsigned long flags;
238 u32 value;
239
240 spin_lock_irqsave(&meson->lock, flags);
241
242 value = readl(meson->base + REG_MISC_AB);
243 value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
244 writel(value, meson->base + REG_MISC_AB);
245
246 spin_unlock_irqrestore(&meson->lock, flags);
247}
248
249static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
250 const struct pwm_state *state)
251{
252 struct meson_pwm *meson = to_meson_pwm(chip);
253 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
254 int err = 0;
255
256 if (!state->enabled) {
257 if (state->polarity == PWM_POLARITY_INVERSED) {
258 /*
259 * This IP block revision doesn't have an "always high"
260 * setting which we can use for "inverted disabled".
261 * Instead we achieve this by setting mux parent with
262 * highest rate and minimum divider value, resulting
263 * in the shortest possible duration for one "count"
264 * and "period == duty_cycle". This results in a signal
265 * which is LOW for one "count", while being HIGH for
266 * the rest of the (so the signal is HIGH for slightly
267 * less than 100% of the period, but this is the best
268 * we can achieve).
269 */
270 channel->rate = ULONG_MAX;
271 channel->hi = ~0;
272 channel->lo = 0;
273
274 meson_pwm_enable(chip, pwm);
275 } else {
276 meson_pwm_disable(chip, pwm);
277 }
278 } else {
279 err = meson_pwm_calc(chip, pwm, state);
280 if (err < 0)
281 return err;
282
283 meson_pwm_enable(chip, pwm);
284 }
285
286 return 0;
287}
288
289static u64 meson_pwm_cnt_to_ns(struct pwm_chip *chip, struct pwm_device *pwm,
290 u32 cnt)
291{
292 struct meson_pwm *meson = to_meson_pwm(chip);
293 struct meson_pwm_channel *channel;
294 unsigned long fin_freq;
295
296 /* to_meson_pwm() can only be used after .get_state() is called */
297 channel = &meson->channels[pwm->hwpwm];
298
299 fin_freq = clk_get_rate(channel->clk);
300 if (fin_freq == 0)
301 return 0;
302
303 return div64_ul(NSEC_PER_SEC * (u64)cnt, fin_freq);
304}
305
306static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
307 struct pwm_state *state)
308{
309 struct meson_pwm *meson = to_meson_pwm(chip);
310 struct meson_pwm_channel_data *channel_data;
311 struct meson_pwm_channel *channel;
312 u32 value;
313
314 if (!state)
315 return 0;
316
317 channel = &meson->channels[pwm->hwpwm];
318 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
319
320 value = readl(meson->base + REG_MISC_AB);
321 state->enabled = value & channel_data->pwm_en_mask;
322
323 value = readl(meson->base + channel_data->reg_offset);
324 channel->lo = FIELD_GET(PWM_LOW_MASK, value);
325 channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
326
327 state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->lo + channel->hi);
328 state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
329
330 state->polarity = PWM_POLARITY_NORMAL;
331
332 return 0;
333}
334
335static const struct pwm_ops meson_pwm_ops = {
336 .request = meson_pwm_request,
337 .free = meson_pwm_free,
338 .apply = meson_pwm_apply,
339 .get_state = meson_pwm_get_state,
340};
341
342static const struct meson_pwm_data pwm_meson8b_data = {
343 .parent_names = { "xtal", NULL, "fclk_div4", "fclk_div3" },
344};
345
346/*
347 * Only the 2 first inputs of the GXBB AO PWMs are valid
348 * The last 2 are grounded
349 */
350static const struct meson_pwm_data pwm_gxbb_ao_data = {
351 .parent_names = { "xtal", "clk81", NULL, NULL },
352};
353
354static const struct meson_pwm_data pwm_axg_ee_data = {
355 .parent_names = { "xtal", "fclk_div5", "fclk_div4", "fclk_div3" },
356};
357
358static const struct meson_pwm_data pwm_axg_ao_data = {
359 .parent_names = { "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" },
360};
361
362static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
363 .parent_names = { "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" },
364};
365
366static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
367 .parent_names = { "xtal", "g12a_ao_clk81", NULL, NULL },
368};
369
370static const struct of_device_id meson_pwm_matches[] = {
371 {
372 .compatible = "amlogic,meson8b-pwm",
373 .data = &pwm_meson8b_data
374 },
375 {
376 .compatible = "amlogic,meson-gxbb-pwm",
377 .data = &pwm_meson8b_data
378 },
379 {
380 .compatible = "amlogic,meson-gxbb-ao-pwm",
381 .data = &pwm_gxbb_ao_data
382 },
383 {
384 .compatible = "amlogic,meson-axg-ee-pwm",
385 .data = &pwm_axg_ee_data
386 },
387 {
388 .compatible = "amlogic,meson-axg-ao-pwm",
389 .data = &pwm_axg_ao_data
390 },
391 {
392 .compatible = "amlogic,meson-g12a-ee-pwm",
393 .data = &pwm_meson8b_data
394 },
395 {
396 .compatible = "amlogic,meson-g12a-ao-pwm-ab",
397 .data = &pwm_g12a_ao_ab_data
398 },
399 {
400 .compatible = "amlogic,meson-g12a-ao-pwm-cd",
401 .data = &pwm_g12a_ao_cd_data
402 },
403 {},
404};
405MODULE_DEVICE_TABLE(of, meson_pwm_matches);
406
407static int meson_pwm_init_channels(struct pwm_chip *chip)
408{
409 struct meson_pwm *meson = to_meson_pwm(chip);
410 struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] = {};
411 struct device *dev = pwmchip_parent(chip);
412 unsigned int i;
413 char name[255];
414 int err;
415
416 for (i = 0; i < MESON_NUM_MUX_PARENTS; i++) {
417 mux_parent_data[i].index = -1;
418 mux_parent_data[i].name = meson->data->parent_names[i];
419 }
420
421 for (i = 0; i < chip->npwm; i++) {
422 struct meson_pwm_channel *channel = &meson->channels[i];
423 struct clk_parent_data div_parent = {}, gate_parent = {};
424 struct clk_init_data init = {};
425
426 snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
427
428 init.name = name;
429 init.ops = &clk_mux_ops;
430 init.flags = 0;
431 init.parent_data = mux_parent_data;
432 init.num_parents = MESON_NUM_MUX_PARENTS;
433
434 channel->mux.reg = meson->base + REG_MISC_AB;
435 channel->mux.shift =
436 meson_pwm_per_channel_data[i].clk_sel_shift;
437 channel->mux.mask = MISC_CLK_SEL_MASK;
438 channel->mux.flags = 0;
439 channel->mux.lock = &meson->lock;
440 channel->mux.table = NULL;
441 channel->mux.hw.init = &init;
442
443 err = devm_clk_hw_register(dev, &channel->mux.hw);
444 if (err)
445 return dev_err_probe(dev, err,
446 "failed to register %s\n", name);
447
448 snprintf(name, sizeof(name), "%s#div%u", dev_name(dev), i);
449
450 init.name = name;
451 init.ops = &clk_divider_ops;
452 init.flags = CLK_SET_RATE_PARENT;
453 div_parent.index = -1;
454 div_parent.hw = &channel->mux.hw;
455 init.parent_data = &div_parent;
456 init.num_parents = 1;
457
458 channel->div.reg = meson->base + REG_MISC_AB;
459 channel->div.shift = meson_pwm_per_channel_data[i].clk_div_shift;
460 channel->div.width = MISC_CLK_DIV_WIDTH;
461 channel->div.hw.init = &init;
462 channel->div.flags = 0;
463 channel->div.lock = &meson->lock;
464
465 err = devm_clk_hw_register(dev, &channel->div.hw);
466 if (err)
467 return dev_err_probe(dev, err,
468 "failed to register %s\n", name);
469
470 snprintf(name, sizeof(name), "%s#gate%u", dev_name(dev), i);
471
472 init.name = name;
473 init.ops = &clk_gate_ops;
474 init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED;
475 gate_parent.index = -1;
476 gate_parent.hw = &channel->div.hw;
477 init.parent_data = &gate_parent;
478 init.num_parents = 1;
479
480 channel->gate.reg = meson->base + REG_MISC_AB;
481 channel->gate.bit_idx = meson_pwm_per_channel_data[i].clk_en_shift;
482 channel->gate.hw.init = &init;
483 channel->gate.flags = 0;
484 channel->gate.lock = &meson->lock;
485
486 err = devm_clk_hw_register(dev, &channel->gate.hw);
487 if (err)
488 return dev_err_probe(dev, err, "failed to register %s\n", name);
489
490 channel->clk = devm_clk_hw_get_clk(dev, &channel->gate.hw, NULL);
491 if (IS_ERR(channel->clk))
492 return dev_err_probe(dev, PTR_ERR(channel->clk),
493 "failed to register %s\n", name);
494 }
495
496 return 0;
497}
498
499static int meson_pwm_probe(struct platform_device *pdev)
500{
501 struct pwm_chip *chip;
502 struct meson_pwm *meson;
503 int err;
504
505 chip = devm_pwmchip_alloc(&pdev->dev, MESON_NUM_PWMS, sizeof(*meson));
506 if (IS_ERR(chip))
507 return PTR_ERR(chip);
508 meson = to_meson_pwm(chip);
509
510 meson->base = devm_platform_ioremap_resource(pdev, 0);
511 if (IS_ERR(meson->base))
512 return PTR_ERR(meson->base);
513
514 spin_lock_init(&meson->lock);
515 chip->ops = &meson_pwm_ops;
516
517 meson->data = of_device_get_match_data(&pdev->dev);
518
519 err = meson_pwm_init_channels(chip);
520 if (err < 0)
521 return err;
522
523 err = devm_pwmchip_add(&pdev->dev, chip);
524 if (err < 0)
525 return dev_err_probe(&pdev->dev, err,
526 "failed to register PWM chip\n");
527
528 return 0;
529}
530
531static struct platform_driver meson_pwm_driver = {
532 .driver = {
533 .name = "meson-pwm",
534 .of_match_table = meson_pwm_matches,
535 },
536 .probe = meson_pwm_probe,
537};
538module_platform_driver(meson_pwm_driver);
539
540MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
541MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
542MODULE_LICENSE("Dual BSD/GPL");