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1// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2/*
3 * Mellanox platform driver
4 *
5 * Copyright (C) 2016-2018 Mellanox Technologies
6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com>
7 */
8
9#include <linux/device.h>
10#include <linux/dmi.h>
11#include <linux/i2c.h>
12#include <linux/i2c-mux.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/platform_data/i2c-mux-reg.h>
17#include <linux/platform_data/mlxreg.h>
18#include <linux/regmap.h>
19
20#define MLX_PLAT_DEVICE_NAME "mlxplat"
21
22/* LPC bus IO offsets */
23#define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000
24#define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500
25#define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00
26#define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01
27#define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02
28#define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03
29#define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET 0x04
30#define MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET 0x05
31#define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0x06
32#define MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET 0x07
33#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0x08
34#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET 0x09
35#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a
36#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0x0b
37#define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET 0x19
38#define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c
39#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
40#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e
41#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f
42#define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20
43#define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21
44#define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22
45#define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23
46#define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24
47#define MLXPLAT_CPLD_LPC_REG_LED6_OFFSET 0x25
48#define MLXPLAT_CPLD_LPC_REG_LED7_OFFSET 0x26
49#define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a
50#define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b
51#define MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET 0x2d
52#define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e
53#define MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET 0x2f
54#define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30
55#define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31
56#define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32
57#define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33
58#define MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE 0x34
59#define MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET 0x35
60#define MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET 0x36
61#define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37
62#define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a
63#define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b
64#define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
65#define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41
66#define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42
67#define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43
68#define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44
69#define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45
70#define MLXPLAT_CPLD_LPC_REG_GWP_OFFSET 0x4a
71#define MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET 0x4b
72#define MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET 0x4c
73#define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50
74#define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51
75#define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52
76#define MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET 0x53
77#define MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET 0x54
78#define MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET 0x55
79#define MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET 0x56
80#define MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET 0x57
81#define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58
82#define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59
83#define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a
84#define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64
85#define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65
86#define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66
87#define MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET 0x70
88#define MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET 0x71
89#define MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET 0x72
90#define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88
91#define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89
92#define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a
93#define MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET 0x9a
94#define MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET 0x9b
95#define MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET 0x9c
96#define MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET 0x9d
97#define MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET 0x9e
98#define MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET 0x9f
99#define MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET 0xa0
100#define MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET 0xa1
101#define MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET 0xa2
102#define MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET 0xa3
103#define MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET 0xa4
104#define MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET 0xa5
105#define MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET 0xa6
106#define MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET 0xa7
107#define MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET 0xa8
108#define MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET 0xa9
109#define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa
110#define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab
111#define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2
112#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7
113#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8
114#define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9
115#define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0xcb
116#define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0xcd
117#define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0xce
118#define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0xcf
119#define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1
120#define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2
121#define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3
122#define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde
123#define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf
124#define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0
125#define MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET 0xe1
126#define MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET 0xe2
127#define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3
128#define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4
129#define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5
130#define MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET 0xe6
131#define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7
132#define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8
133#define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9
134#define MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET 0xea
135#define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xeb
136#define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xec
137#define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xed
138#define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee
139#define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef
140#define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0
141#define MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET 0xf1
142#define MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET 0xf2
143#define MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET 0xf3
144#define MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET 0xf4
145#define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5
146#define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6
147#define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7
148#define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0xf8
149#define MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET 0xf9
150#define MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET 0xfa
151#define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb
152#define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc
153#define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd
154#define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
155#define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
156#define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
157#define MLXPLAT_CPLD_LPC_I2C_CH3_OFF 0xdc
158#define MLXPLAT_CPLD_LPC_I2C_CH4_OFF 0xdd
159
160#define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL
161#define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
162 MLXPLAT_CPLD_LPC_I2C_CH1_OFF) | \
163 MLXPLAT_CPLD_LPC_PIO_OFFSET)
164#define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
165 MLXPLAT_CPLD_LPC_I2C_CH2_OFF) | \
166 MLXPLAT_CPLD_LPC_PIO_OFFSET)
167#define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
168 MLXPLAT_CPLD_LPC_I2C_CH3_OFF) | \
169 MLXPLAT_CPLD_LPC_PIO_OFFSET)
170#define MLXPLAT_CPLD_LPC_REG4 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
171 MLXPLAT_CPLD_LPC_I2C_CH4_OFF) | \
172 MLXPLAT_CPLD_LPC_PIO_OFFSET)
173
174/* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */
175#define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0x04
176#define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0x08
177#define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0x08
178#define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40
179#define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \
180 MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \
181 MLXPLAT_CPLD_AGGR_FAN_MASK_DEF)
182#define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01
183#define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04
184#define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0)
185#define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3)
186#define MLXPLAT_CPLD_AGGR_MASK_MODULAR (MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \
187 MLXPLAT_CPLD_AGGR_MASK_COMEX | \
188 MLXPLAT_CPLD_AGGR_MASK_LC)
189#define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0)
190#define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1)
191#define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2)
192#define MLXPLAT_CPLD_AGGR_MASK_LC_SCRD BIT(3)
193#define MLXPLAT_CPLD_AGGR_MASK_LC_SYNC BIT(4)
194#define MLXPLAT_CPLD_AGGR_MASK_LC_ACT BIT(5)
195#define MLXPLAT_CPLD_AGGR_MASK_LC_SDWN BIT(6)
196#define MLXPLAT_CPLD_AGGR_MASK_LC_LOW (MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT | \
197 MLXPLAT_CPLD_AGGR_MASK_LC_RDY | \
198 MLXPLAT_CPLD_AGGR_MASK_LC_PG | \
199 MLXPLAT_CPLD_AGGR_MASK_LC_SCRD | \
200 MLXPLAT_CPLD_AGGR_MASK_LC_SYNC | \
201 MLXPLAT_CPLD_AGGR_MASK_LC_ACT | \
202 MLXPLAT_CPLD_AGGR_MASK_LC_SDWN)
203#define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1
204#define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2)
205#define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6)
206#define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0)
207#define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)
208#define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0)
209#define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0)
210#define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0)
211#define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0)
212#define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(6, 0)
213#define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4)
214#define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0)
215#define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4)
216#define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0)
217#define MLXPLAT_CPLD_I2C_CAP_BIT 0x04
218#define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT)
219
220/* Masks for aggregation for comex carriers */
221#define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1)
222#define MLXPLAT_CPLD_AGGR_MASK_CARR_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \
223 MLXPLAT_CPLD_AGGR_MASK_CARRIER)
224#define MLXPLAT_CPLD_LOW_AGGRCX_MASK 0xc1
225
226/* Masks for aggregation for modular systems */
227#define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0)
228
229/* Default I2C parent bus number */
230#define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1
231
232/* Maximum number of possible physical buses equipped on system */
233#define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16
234#define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24
235
236/* Number of channels in group */
237#define MLXPLAT_CPLD_GRP_CHNL_NUM 8
238
239/* Start channel numbers */
240#define MLXPLAT_CPLD_CH1 2
241#define MLXPLAT_CPLD_CH2 10
242#define MLXPLAT_CPLD_CH3 18
243#define MLXPLAT_CPLD_CH2_ETH_MODULAR 3
244#define MLXPLAT_CPLD_CH3_ETH_MODULAR 43
245#define MLXPLAT_CPLD_CH4_ETH_MODULAR 51
246
247/* Number of LPC attached MUX platform devices */
248#define MLXPLAT_CPLD_LPC_MUX_DEVS 4
249
250/* Hotplug devices adapter numbers */
251#define MLXPLAT_CPLD_NR_NONE -1
252#define MLXPLAT_CPLD_PSU_DEFAULT_NR 10
253#define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4
254#define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11
255#define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12
256#define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13
257#define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14
258#define MLXPLAT_CPLD_NR_ASIC 3
259#define MLXPLAT_CPLD_NR_LC_BASE 34
260
261#define MLXPLAT_CPLD_NR_LC_SET(nr) (MLXPLAT_CPLD_NR_LC_BASE + (nr))
262#define MLXPLAT_CPLD_LC_ADDR 0x32
263
264/* Masks and default values for watchdogs */
265#define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1)
266#define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1))
267
268#define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4)
269#define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0
270#define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1)
271#define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4))
272#define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7))
273#define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7, 0) & ~BIT(6))
274#define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30
275#define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600
276#define MLXPLAT_CPLD_WD_MAX_DEVS 2
277
278#define MLXPLAT_CPLD_LPC_SYSIRQ 17
279
280/* Minimum power required for turning on Ethernet modular system (WATT) */
281#define MLXPLAT_CPLD_ETH_MODULAR_PWR_MIN 50
282
283/* mlxplat_priv - platform private data
284 * @pdev_i2c - i2c controller platform device
285 * @pdev_mux - array of mux platform devices
286 * @pdev_hotplug - hotplug platform devices
287 * @pdev_led - led platform devices
288 * @pdev_io_regs - register access platform devices
289 * @pdev_fan - FAN platform devices
290 * @pdev_wd - array of watchdog platform devices
291 * @regmap: device register map
292 */
293struct mlxplat_priv {
294 struct platform_device *pdev_i2c;
295 struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS];
296 struct platform_device *pdev_hotplug;
297 struct platform_device *pdev_led;
298 struct platform_device *pdev_io_regs;
299 struct platform_device *pdev_fan;
300 struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS];
301 void *regmap;
302};
303
304/* Regions for LPC I2C controller and LPC base register space */
305static const struct resource mlxplat_lpc_resources[] = {
306 [0] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_I2C_BASE_ADRR,
307 MLXPLAT_CPLD_LPC_IO_RANGE,
308 "mlxplat_cpld_lpc_i2c_ctrl", IORESOURCE_IO),
309 [1] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_REG_BASE_ADRR,
310 MLXPLAT_CPLD_LPC_IO_RANGE,
311 "mlxplat_cpld_lpc_regs",
312 IORESOURCE_IO),
313};
314
315/* Platform i2c next generation systems data */
316static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = {
317 {
318 .reg = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
319 .mask = MLXPLAT_CPLD_I2C_CAP_MASK,
320 .bit = MLXPLAT_CPLD_I2C_CAP_BIT,
321 },
322};
323
324static struct mlxreg_core_item mlxplat_mlxcpld_i2c_ng_items[] = {
325 {
326 .data = mlxplat_mlxcpld_i2c_ng_items_data,
327 },
328};
329
330/* Platform next generation systems i2c data */
331static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = {
332 .items = mlxplat_mlxcpld_i2c_ng_items,
333 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
334 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX,
335 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET,
336 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_I2C,
337};
338
339/* Platform default channels */
340static const int mlxplat_default_channels[][MLXPLAT_CPLD_GRP_CHNL_NUM] = {
341 {
342 MLXPLAT_CPLD_CH1, MLXPLAT_CPLD_CH1 + 1, MLXPLAT_CPLD_CH1 + 2,
343 MLXPLAT_CPLD_CH1 + 3, MLXPLAT_CPLD_CH1 + 4, MLXPLAT_CPLD_CH1 +
344 5, MLXPLAT_CPLD_CH1 + 6, MLXPLAT_CPLD_CH1 + 7
345 },
346 {
347 MLXPLAT_CPLD_CH2, MLXPLAT_CPLD_CH2 + 1, MLXPLAT_CPLD_CH2 + 2,
348 MLXPLAT_CPLD_CH2 + 3, MLXPLAT_CPLD_CH2 + 4, MLXPLAT_CPLD_CH2 +
349 5, MLXPLAT_CPLD_CH2 + 6, MLXPLAT_CPLD_CH2 + 7
350 },
351};
352
353/* Platform channels for MSN21xx system family */
354static const int mlxplat_msn21xx_channels[] = { 1, 2, 3, 4, 5, 6, 7, 8 };
355
356/* Platform mux data */
357static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = {
358 {
359 .parent = 1,
360 .base_nr = MLXPLAT_CPLD_CH1,
361 .write_only = 1,
362 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
363 .reg_size = 1,
364 .idle_in_use = 1,
365 },
366 {
367 .parent = 1,
368 .base_nr = MLXPLAT_CPLD_CH2,
369 .write_only = 1,
370 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
371 .reg_size = 1,
372 .idle_in_use = 1,
373 },
374
375};
376
377/* Platform mux configuration variables */
378static int mlxplat_max_adap_num;
379static int mlxplat_mux_num;
380static struct i2c_mux_reg_platform_data *mlxplat_mux_data;
381
382/* Platform extended mux data */
383static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = {
384 {
385 .parent = 1,
386 .base_nr = MLXPLAT_CPLD_CH1,
387 .write_only = 1,
388 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
389 .reg_size = 1,
390 .idle_in_use = 1,
391 },
392 {
393 .parent = 1,
394 .base_nr = MLXPLAT_CPLD_CH2,
395 .write_only = 1,
396 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3,
397 .reg_size = 1,
398 .idle_in_use = 1,
399 },
400 {
401 .parent = 1,
402 .base_nr = MLXPLAT_CPLD_CH3,
403 .write_only = 1,
404 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
405 .reg_size = 1,
406 .idle_in_use = 1,
407 },
408
409};
410
411/* Platform channels for modular system family */
412static const int mlxplat_modular_upper_channel[] = { 1 };
413static const int mlxplat_modular_channels[] = {
414 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
415 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37,
416 38, 39, 40
417};
418
419/* Platform modular mux data */
420static struct i2c_mux_reg_platform_data mlxplat_modular_mux_data[] = {
421 {
422 .parent = 1,
423 .base_nr = MLXPLAT_CPLD_CH1,
424 .write_only = 1,
425 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG4,
426 .reg_size = 1,
427 .idle_in_use = 1,
428 .values = mlxplat_modular_upper_channel,
429 .n_values = ARRAY_SIZE(mlxplat_modular_upper_channel),
430 },
431 {
432 .parent = 1,
433 .base_nr = MLXPLAT_CPLD_CH2_ETH_MODULAR,
434 .write_only = 1,
435 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
436 .reg_size = 1,
437 .idle_in_use = 1,
438 .values = mlxplat_modular_channels,
439 .n_values = ARRAY_SIZE(mlxplat_modular_channels),
440 },
441 {
442 .parent = MLXPLAT_CPLD_CH1,
443 .base_nr = MLXPLAT_CPLD_CH3_ETH_MODULAR,
444 .write_only = 1,
445 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3,
446 .reg_size = 1,
447 .idle_in_use = 1,
448 .values = mlxplat_msn21xx_channels,
449 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels),
450 },
451 {
452 .parent = 1,
453 .base_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR,
454 .write_only = 1,
455 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
456 .reg_size = 1,
457 .idle_in_use = 1,
458 .values = mlxplat_msn21xx_channels,
459 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels),
460 },
461};
462
463/* Platform hotplug devices */
464static struct i2c_board_info mlxplat_mlxcpld_pwr[] = {
465 {
466 I2C_BOARD_INFO("dps460", 0x59),
467 },
468 {
469 I2C_BOARD_INFO("dps460", 0x58),
470 },
471};
472
473static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = {
474 {
475 I2C_BOARD_INFO("dps460", 0x5b),
476 },
477 {
478 I2C_BOARD_INFO("dps460", 0x5a),
479 },
480};
481
482static struct i2c_board_info mlxplat_mlxcpld_fan[] = {
483 {
484 I2C_BOARD_INFO("24c32", 0x50),
485 },
486 {
487 I2C_BOARD_INFO("24c32", 0x50),
488 },
489 {
490 I2C_BOARD_INFO("24c32", 0x50),
491 },
492 {
493 I2C_BOARD_INFO("24c32", 0x50),
494 },
495};
496
497/* Platform hotplug comex carrier system family data */
498static struct mlxreg_core_data mlxplat_mlxcpld_comex_psu_items_data[] = {
499 {
500 .label = "psu1",
501 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
502 .mask = BIT(0),
503 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
504 },
505 {
506 .label = "psu2",
507 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
508 .mask = BIT(1),
509 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
510 },
511};
512
513/* Platform hotplug default data */
514static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = {
515 {
516 .label = "psu1",
517 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
518 .mask = BIT(0),
519 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
520 },
521 {
522 .label = "psu2",
523 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
524 .mask = BIT(1),
525 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
526 },
527};
528
529static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = {
530 {
531 .label = "pwr1",
532 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
533 .mask = BIT(0),
534 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
535 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR,
536 },
537 {
538 .label = "pwr2",
539 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
540 .mask = BIT(1),
541 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
542 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR,
543 },
544};
545
546static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_wc_items_data[] = {
547 {
548 .label = "pwr1",
549 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
550 .mask = BIT(0),
551 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
552 },
553 {
554 .label = "pwr2",
555 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
556 .mask = BIT(1),
557 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
558 },
559};
560
561static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = {
562 {
563 .label = "fan1",
564 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
565 .mask = BIT(0),
566 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[0],
567 .hpdev.nr = MLXPLAT_CPLD_FAN1_DEFAULT_NR,
568 },
569 {
570 .label = "fan2",
571 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
572 .mask = BIT(1),
573 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[1],
574 .hpdev.nr = MLXPLAT_CPLD_FAN2_DEFAULT_NR,
575 },
576 {
577 .label = "fan3",
578 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
579 .mask = BIT(2),
580 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[2],
581 .hpdev.nr = MLXPLAT_CPLD_FAN3_DEFAULT_NR,
582 },
583 {
584 .label = "fan4",
585 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
586 .mask = BIT(3),
587 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[3],
588 .hpdev.nr = MLXPLAT_CPLD_FAN4_DEFAULT_NR,
589 },
590};
591
592static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = {
593 {
594 .label = "asic1",
595 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
596 .mask = MLXPLAT_CPLD_ASIC_MASK,
597 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
598 },
599};
600
601static struct mlxreg_core_data mlxplat_mlxcpld_default_asic2_items_data[] = {
602 {
603 .label = "asic2",
604 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,
605 .mask = MLXPLAT_CPLD_ASIC_MASK,
606 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
607 },
608};
609
610static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = {
611 {
612 .data = mlxplat_mlxcpld_default_psu_items_data,
613 .aggr_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF,
614 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
615 .mask = MLXPLAT_CPLD_PSU_MASK,
616 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data),
617 .inversed = 1,
618 .health = false,
619 },
620 {
621 .data = mlxplat_mlxcpld_default_pwr_items_data,
622 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF,
623 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
624 .mask = MLXPLAT_CPLD_PWR_MASK,
625 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data),
626 .inversed = 0,
627 .health = false,
628 },
629 {
630 .data = mlxplat_mlxcpld_default_fan_items_data,
631 .aggr_mask = MLXPLAT_CPLD_AGGR_FAN_MASK_DEF,
632 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
633 .mask = MLXPLAT_CPLD_FAN_MASK,
634 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data),
635 .inversed = 1,
636 .health = false,
637 },
638 {
639 .data = mlxplat_mlxcpld_default_asic_items_data,
640 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
641 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
642 .mask = MLXPLAT_CPLD_ASIC_MASK,
643 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
644 .inversed = 0,
645 .health = true,
646 },
647};
648
649static struct mlxreg_core_item mlxplat_mlxcpld_comex_items[] = {
650 {
651 .data = mlxplat_mlxcpld_comex_psu_items_data,
652 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
653 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
654 .mask = MLXPLAT_CPLD_PSU_MASK,
655 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data),
656 .inversed = 1,
657 .health = false,
658 },
659 {
660 .data = mlxplat_mlxcpld_default_pwr_items_data,
661 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
662 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
663 .mask = MLXPLAT_CPLD_PWR_MASK,
664 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data),
665 .inversed = 0,
666 .health = false,
667 },
668 {
669 .data = mlxplat_mlxcpld_default_fan_items_data,
670 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
671 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
672 .mask = MLXPLAT_CPLD_FAN_MASK,
673 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data),
674 .inversed = 1,
675 .health = false,
676 },
677 {
678 .data = mlxplat_mlxcpld_default_asic_items_data,
679 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
680 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
681 .mask = MLXPLAT_CPLD_ASIC_MASK,
682 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
683 .inversed = 0,
684 .health = true,
685 },
686};
687
688static
689struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = {
690 .items = mlxplat_mlxcpld_default_items,
691 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_items),
692 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
693 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
694 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
695 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
696};
697
698static struct mlxreg_core_item mlxplat_mlxcpld_default_wc_items[] = {
699 {
700 .data = mlxplat_mlxcpld_comex_psu_items_data,
701 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
702 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
703 .mask = MLXPLAT_CPLD_PSU_MASK,
704 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data),
705 .inversed = 1,
706 .health = false,
707 },
708 {
709 .data = mlxplat_mlxcpld_default_pwr_wc_items_data,
710 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
711 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
712 .mask = MLXPLAT_CPLD_PWR_MASK,
713 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data),
714 .inversed = 0,
715 .health = false,
716 },
717 {
718 .data = mlxplat_mlxcpld_default_asic_items_data,
719 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
720 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
721 .mask = MLXPLAT_CPLD_ASIC_MASK,
722 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
723 .inversed = 0,
724 .health = true,
725 },
726};
727
728static
729struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_wc_data = {
730 .items = mlxplat_mlxcpld_default_wc_items,
731 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_wc_items),
732 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
733 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
734 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
735 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
736};
737
738static
739struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = {
740 .items = mlxplat_mlxcpld_comex_items,
741 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_items),
742 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
743 .mask = MLXPLAT_CPLD_AGGR_MASK_CARR_DEF,
744 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET,
745 .mask_low = MLXPLAT_CPLD_LOW_AGGRCX_MASK,
746};
747
748static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = {
749 {
750 .label = "pwr1",
751 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
752 .mask = BIT(0),
753 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
754 },
755 {
756 .label = "pwr2",
757 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
758 .mask = BIT(1),
759 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
760 },
761};
762
763/* Platform hotplug MSN21xx system family data */
764static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = {
765 {
766 .data = mlxplat_mlxcpld_msn21xx_pwr_items_data,
767 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF,
768 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
769 .mask = MLXPLAT_CPLD_PWR_MASK,
770 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_pwr_items_data),
771 .inversed = 0,
772 .health = false,
773 },
774 {
775 .data = mlxplat_mlxcpld_default_asic_items_data,
776 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
777 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
778 .mask = MLXPLAT_CPLD_ASIC_MASK,
779 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
780 .inversed = 0,
781 .health = true,
782 },
783};
784
785static
786struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = {
787 .items = mlxplat_mlxcpld_msn21xx_items,
788 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items),
789 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
790 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
791 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
792 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
793};
794
795/* Platform hotplug msn274x system family data */
796static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_psu_items_data[] = {
797 {
798 .label = "psu1",
799 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
800 .mask = BIT(0),
801 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
802 },
803 {
804 .label = "psu2",
805 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
806 .mask = BIT(1),
807 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
808 },
809};
810
811static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_pwr_items_data[] = {
812 {
813 .label = "pwr1",
814 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
815 .mask = BIT(0),
816 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
817 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
818 },
819 {
820 .label = "pwr2",
821 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
822 .mask = BIT(1),
823 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
824 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
825 },
826};
827
828static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_fan_items_data[] = {
829 {
830 .label = "fan1",
831 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
832 .mask = BIT(0),
833 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
834 },
835 {
836 .label = "fan2",
837 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
838 .mask = BIT(1),
839 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
840 },
841 {
842 .label = "fan3",
843 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
844 .mask = BIT(2),
845 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
846 },
847 {
848 .label = "fan4",
849 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
850 .mask = BIT(3),
851 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
852 },
853};
854
855static struct mlxreg_core_item mlxplat_mlxcpld_msn274x_items[] = {
856 {
857 .data = mlxplat_mlxcpld_msn274x_psu_items_data,
858 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
859 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
860 .mask = MLXPLAT_CPLD_PSU_MASK,
861 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_psu_items_data),
862 .inversed = 1,
863 .health = false,
864 },
865 {
866 .data = mlxplat_mlxcpld_default_ng_pwr_items_data,
867 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
868 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
869 .mask = MLXPLAT_CPLD_PWR_MASK,
870 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data),
871 .inversed = 0,
872 .health = false,
873 },
874 {
875 .data = mlxplat_mlxcpld_msn274x_fan_items_data,
876 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
877 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
878 .mask = MLXPLAT_CPLD_FAN_MASK,
879 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_fan_items_data),
880 .inversed = 1,
881 .health = false,
882 },
883 {
884 .data = mlxplat_mlxcpld_default_asic_items_data,
885 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
886 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
887 .mask = MLXPLAT_CPLD_ASIC_MASK,
888 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
889 .inversed = 0,
890 .health = true,
891 },
892};
893
894static
895struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn274x_data = {
896 .items = mlxplat_mlxcpld_msn274x_items,
897 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_items),
898 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
899 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
900 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
901 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
902};
903
904/* Platform hotplug MSN201x system family data */
905static struct mlxreg_core_data mlxplat_mlxcpld_msn201x_pwr_items_data[] = {
906 {
907 .label = "pwr1",
908 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
909 .mask = BIT(0),
910 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
911 },
912 {
913 .label = "pwr2",
914 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
915 .mask = BIT(1),
916 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
917 },
918};
919
920static struct mlxreg_core_item mlxplat_mlxcpld_msn201x_items[] = {
921 {
922 .data = mlxplat_mlxcpld_msn201x_pwr_items_data,
923 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF,
924 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
925 .mask = MLXPLAT_CPLD_PWR_MASK,
926 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_pwr_items_data),
927 .inversed = 0,
928 .health = false,
929 },
930 {
931 .data = mlxplat_mlxcpld_default_asic_items_data,
932 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
933 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
934 .mask = MLXPLAT_CPLD_ASIC_MASK,
935 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
936 .inversed = 0,
937 .health = true,
938 },
939};
940
941static
942struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn201x_data = {
943 .items = mlxplat_mlxcpld_msn201x_items,
944 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_items),
945 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
946 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
947 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
948 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
949};
950
951/* Platform hotplug next generation system family data */
952static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_psu_items_data[] = {
953 {
954 .label = "psu1",
955 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
956 .mask = BIT(0),
957 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
958 },
959 {
960 .label = "psu2",
961 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
962 .mask = BIT(1),
963 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
964 },
965};
966
967static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = {
968 {
969 .label = "fan1",
970 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
971 .mask = BIT(0),
972 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
973 .bit = BIT(0),
974 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
975 },
976 {
977 .label = "fan2",
978 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
979 .mask = BIT(1),
980 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
981 .bit = BIT(1),
982 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
983 },
984 {
985 .label = "fan3",
986 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
987 .mask = BIT(2),
988 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
989 .bit = BIT(2),
990 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
991 },
992 {
993 .label = "fan4",
994 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
995 .mask = BIT(3),
996 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
997 .bit = BIT(3),
998 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
999 },
1000 {
1001 .label = "fan5",
1002 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1003 .mask = BIT(4),
1004 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1005 .bit = BIT(4),
1006 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1007 },
1008 {
1009 .label = "fan6",
1010 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1011 .mask = BIT(5),
1012 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1013 .bit = BIT(5),
1014 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1015 },
1016 {
1017 .label = "fan7",
1018 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1019 .mask = BIT(6),
1020 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1021 .bit = BIT(6),
1022 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1023 },
1024};
1025
1026static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = {
1027 {
1028 .data = mlxplat_mlxcpld_default_ng_psu_items_data,
1029 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1030 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1031 .mask = MLXPLAT_CPLD_PSU_MASK,
1032 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data),
1033 .inversed = 1,
1034 .health = false,
1035 },
1036 {
1037 .data = mlxplat_mlxcpld_default_ng_pwr_items_data,
1038 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1039 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1040 .mask = MLXPLAT_CPLD_PWR_MASK,
1041 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data),
1042 .inversed = 0,
1043 .health = false,
1044 },
1045 {
1046 .data = mlxplat_mlxcpld_default_ng_fan_items_data,
1047 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1048 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1049 .mask = MLXPLAT_CPLD_FAN_NG_MASK,
1050 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
1051 .inversed = 1,
1052 .health = false,
1053 },
1054 {
1055 .data = mlxplat_mlxcpld_default_asic_items_data,
1056 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1057 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1058 .mask = MLXPLAT_CPLD_ASIC_MASK,
1059 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
1060 .inversed = 0,
1061 .health = true,
1062 },
1063};
1064
1065static
1066struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_ng_data = {
1067 .items = mlxplat_mlxcpld_default_ng_items,
1068 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_items),
1069 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
1070 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
1071 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
1072 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
1073};
1074
1075/* Platform hotplug extended system family data */
1076static struct mlxreg_core_data mlxplat_mlxcpld_ext_psu_items_data[] = {
1077 {
1078 .label = "psu1",
1079 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1080 .mask = BIT(0),
1081 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1082 },
1083 {
1084 .label = "psu2",
1085 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1086 .mask = BIT(1),
1087 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1088 },
1089 {
1090 .label = "psu3",
1091 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1092 .mask = BIT(2),
1093 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1094 },
1095 {
1096 .label = "psu4",
1097 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1098 .mask = BIT(3),
1099 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1100 },
1101};
1102
1103static struct mlxreg_core_data mlxplat_mlxcpld_ext_pwr_items_data[] = {
1104 {
1105 .label = "pwr1",
1106 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1107 .mask = BIT(0),
1108 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
1109 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
1110 },
1111 {
1112 .label = "pwr2",
1113 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1114 .mask = BIT(1),
1115 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
1116 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
1117 },
1118 {
1119 .label = "pwr3",
1120 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1121 .mask = BIT(2),
1122 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0],
1123 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
1124 },
1125 {
1126 .label = "pwr4",
1127 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1128 .mask = BIT(3),
1129 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1],
1130 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
1131 },
1132};
1133
1134static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = {
1135 {
1136 .data = mlxplat_mlxcpld_ext_psu_items_data,
1137 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1138 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1139 .mask = MLXPLAT_CPLD_PSU_EXT_MASK,
1140 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
1141 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data),
1142 .inversed = 1,
1143 .health = false,
1144 },
1145 {
1146 .data = mlxplat_mlxcpld_ext_pwr_items_data,
1147 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1148 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1149 .mask = MLXPLAT_CPLD_PWR_EXT_MASK,
1150 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
1151 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data),
1152 .inversed = 0,
1153 .health = false,
1154 },
1155 {
1156 .data = mlxplat_mlxcpld_default_ng_fan_items_data,
1157 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1158 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1159 .mask = MLXPLAT_CPLD_FAN_NG_MASK,
1160 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
1161 .inversed = 1,
1162 .health = false,
1163 },
1164 {
1165 .data = mlxplat_mlxcpld_default_asic_items_data,
1166 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1167 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1168 .mask = MLXPLAT_CPLD_ASIC_MASK,
1169 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
1170 .inversed = 0,
1171 .health = true,
1172 },
1173 {
1174 .data = mlxplat_mlxcpld_default_asic2_items_data,
1175 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1176 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,
1177 .mask = MLXPLAT_CPLD_ASIC_MASK,
1178 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic2_items_data),
1179 .inversed = 0,
1180 .health = true,
1181 }
1182};
1183
1184static
1185struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = {
1186 .items = mlxplat_mlxcpld_ext_items,
1187 .counter = ARRAY_SIZE(mlxplat_mlxcpld_ext_items),
1188 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
1189 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
1190 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
1191 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2,
1192};
1193
1194static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = {
1195 {
1196 .label = "pwr1",
1197 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1198 .mask = BIT(0),
1199 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
1200 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
1201 },
1202 {
1203 .label = "pwr2",
1204 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1205 .mask = BIT(1),
1206 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
1207 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
1208 },
1209 {
1210 .label = "pwr3",
1211 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1212 .mask = BIT(2),
1213 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0],
1214 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
1215 },
1216 {
1217 .label = "pwr4",
1218 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1219 .mask = BIT(3),
1220 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1],
1221 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
1222 },
1223};
1224
1225static
1226struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_lc_act = {
1227 .irq = MLXPLAT_CPLD_LPC_SYSIRQ,
1228};
1229
1230static struct mlxreg_core_data mlxplat_mlxcpld_modular_asic_items_data[] = {
1231 {
1232 .label = "asic1",
1233 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1234 .mask = MLXPLAT_CPLD_ASIC_MASK,
1235 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1236 },
1237};
1238
1239static struct i2c_board_info mlxplat_mlxcpld_lc_i2c_dev[] = {
1240 {
1241 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1242 .platform_data = &mlxplat_mlxcpld_lc_act,
1243 },
1244 {
1245 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1246 .platform_data = &mlxplat_mlxcpld_lc_act,
1247 },
1248 {
1249 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1250 .platform_data = &mlxplat_mlxcpld_lc_act,
1251 },
1252 {
1253 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1254 .platform_data = &mlxplat_mlxcpld_lc_act,
1255 },
1256 {
1257 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1258 .platform_data = &mlxplat_mlxcpld_lc_act,
1259 },
1260 {
1261 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1262 .platform_data = &mlxplat_mlxcpld_lc_act,
1263 },
1264 {
1265 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1266 .platform_data = &mlxplat_mlxcpld_lc_act,
1267 },
1268 {
1269 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1270 .platform_data = &mlxplat_mlxcpld_lc_act,
1271 },
1272};
1273
1274static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_modular_lc_notifier[] = {
1275 {
1276 .identity = "lc1",
1277 },
1278 {
1279 .identity = "lc2",
1280 },
1281 {
1282 .identity = "lc3",
1283 },
1284 {
1285 .identity = "lc4",
1286 },
1287 {
1288 .identity = "lc5",
1289 },
1290 {
1291 .identity = "lc6",
1292 },
1293 {
1294 .identity = "lc7",
1295 },
1296 {
1297 .identity = "lc8",
1298 },
1299};
1300
1301static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = {
1302 {
1303 .label = "lc1_present",
1304 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1305 .mask = BIT(0),
1306 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0],
1307 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0),
1308 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1309 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0],
1310 .slot = 1,
1311 },
1312 {
1313 .label = "lc2_present",
1314 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1315 .mask = BIT(1),
1316 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1],
1317 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1),
1318 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1319 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1],
1320 .slot = 2,
1321 },
1322 {
1323 .label = "lc3_present",
1324 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1325 .mask = BIT(2),
1326 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2],
1327 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2),
1328 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1329 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2],
1330 .slot = 3,
1331 },
1332 {
1333 .label = "lc4_present",
1334 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1335 .mask = BIT(3),
1336 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3],
1337 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3),
1338 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1339 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3],
1340 .slot = 4,
1341 },
1342 {
1343 .label = "lc5_present",
1344 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1345 .mask = BIT(4),
1346 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4],
1347 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4),
1348 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1349 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4],
1350 .slot = 5,
1351 },
1352 {
1353 .label = "lc6_present",
1354 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1355 .mask = BIT(5),
1356 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5],
1357 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5),
1358 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1359 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5],
1360 .slot = 6,
1361 },
1362 {
1363 .label = "lc7_present",
1364 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1365 .mask = BIT(6),
1366 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6],
1367 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6),
1368 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1369 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6],
1370 .slot = 7,
1371 },
1372 {
1373 .label = "lc8_present",
1374 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1375 .mask = BIT(7),
1376 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1377 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1378 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1379 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1380 .slot = 8,
1381 },
1382};
1383
1384static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = {
1385 {
1386 .label = "lc1_verified",
1387 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1388 .mask = BIT(0),
1389 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1390 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1391 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
1392 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
1393 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0],
1394 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0),
1395 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION,
1396 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0],
1397 .slot = 1,
1398 },
1399 {
1400 .label = "lc2_verified",
1401 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1402 .mask = BIT(1),
1403 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1404 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1405 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
1406 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
1407 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1],
1408 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1),
1409 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION,
1410 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1],
1411 .slot = 2,
1412 },
1413 {
1414 .label = "lc3_verified",
1415 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1416 .mask = BIT(2),
1417 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1418 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1419 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
1420 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
1421 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2],
1422 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2),
1423 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION,
1424 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2],
1425 .slot = 3,
1426 },
1427 {
1428 .label = "lc4_verified",
1429 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1430 .mask = BIT(3),
1431 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1432 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1433 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
1434 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
1435 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3],
1436 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3),
1437 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION,
1438 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3],
1439 .slot = 4,
1440 },
1441 {
1442 .label = "lc5_verified",
1443 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1444 .mask = BIT(4),
1445 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1446 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1447 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
1448 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
1449 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4],
1450 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4),
1451 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION,
1452 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4],
1453 .slot = 5,
1454 },
1455 {
1456 .label = "lc6_verified",
1457 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1458 .mask = BIT(5),
1459 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1460 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1461 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
1462 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
1463 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5],
1464 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5),
1465 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION,
1466 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5],
1467 .slot = 6,
1468 },
1469 {
1470 .label = "lc7_verified",
1471 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1472 .mask = BIT(6),
1473 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1474 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1475 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
1476 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
1477 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6],
1478 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6),
1479 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION,
1480 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6],
1481 .slot = 7,
1482 },
1483 {
1484 .label = "lc8_verified",
1485 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1486 .mask = BIT(7),
1487 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1488 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1489 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
1490 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
1491 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1492 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1493 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION,
1494 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1495 .slot = 8,
1496 },
1497};
1498
1499static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = {
1500 {
1501 .label = "lc1_powered",
1502 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1503 .mask = BIT(0),
1504 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0],
1505 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0),
1506 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1507 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0],
1508 .slot = 1,
1509 },
1510 {
1511 .label = "lc2_powered",
1512 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1513 .mask = BIT(1),
1514 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1],
1515 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1),
1516 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1517 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1],
1518 .slot = 2,
1519 },
1520 {
1521 .label = "lc3_powered",
1522 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1523 .mask = BIT(2),
1524 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2],
1525 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2),
1526 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1527 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2],
1528 .slot = 3,
1529 },
1530 {
1531 .label = "lc4_powered",
1532 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1533 .mask = BIT(3),
1534 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3],
1535 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3),
1536 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1537 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3],
1538 .slot = 4,
1539 },
1540 {
1541 .label = "lc5_powered",
1542 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1543 .mask = BIT(4),
1544 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4],
1545 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4),
1546 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1547 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4],
1548 .slot = 5,
1549 },
1550 {
1551 .label = "lc6_powered",
1552 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1553 .mask = BIT(5),
1554 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5],
1555 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5),
1556 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1557 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5],
1558 .slot = 6,
1559 },
1560 {
1561 .label = "lc7_powered",
1562 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1563 .mask = BIT(6),
1564 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6],
1565 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6),
1566 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1567 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6],
1568 .slot = 7,
1569 },
1570 {
1571 .label = "lc8_powered",
1572 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1573 .mask = BIT(7),
1574 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1575 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1576 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1577 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1578 .slot = 8,
1579 },
1580};
1581
1582static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = {
1583 {
1584 .label = "lc1_ready",
1585 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1586 .mask = BIT(0),
1587 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0],
1588 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0),
1589 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1590 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0],
1591 .slot = 1,
1592 },
1593 {
1594 .label = "lc2_ready",
1595 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1596 .mask = BIT(1),
1597 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1],
1598 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1),
1599 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1600 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1],
1601 .slot = 2,
1602 },
1603 {
1604 .label = "lc3_ready",
1605 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1606 .mask = BIT(2),
1607 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2],
1608 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2),
1609 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1610 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2],
1611 .slot = 3,
1612 },
1613 {
1614 .label = "lc4_ready",
1615 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1616 .mask = BIT(3),
1617 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3],
1618 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3),
1619 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1620 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3],
1621 .slot = 4,
1622 },
1623 {
1624 .label = "lc5_ready",
1625 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1626 .mask = BIT(4),
1627 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4],
1628 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4),
1629 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1630 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4],
1631 .slot = 5,
1632 },
1633 {
1634 .label = "lc6_ready",
1635 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1636 .mask = BIT(5),
1637 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5],
1638 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5),
1639 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1640 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5],
1641 .slot = 6,
1642 },
1643 {
1644 .label = "lc7_ready",
1645 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1646 .mask = BIT(6),
1647 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6],
1648 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6),
1649 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1650 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6],
1651 .slot = 7,
1652 },
1653 {
1654 .label = "lc8_ready",
1655 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1656 .mask = BIT(7),
1657 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1658 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1659 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1660 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1661 .slot = 8,
1662 },
1663};
1664
1665static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = {
1666 {
1667 .label = "lc1_synced",
1668 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1669 .mask = BIT(0),
1670 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0],
1671 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0),
1672 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1673 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0],
1674 .slot = 1,
1675 },
1676 {
1677 .label = "lc2_synced",
1678 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1679 .mask = BIT(1),
1680 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1],
1681 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1),
1682 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1683 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1],
1684 .slot = 2,
1685 },
1686 {
1687 .label = "lc3_synced",
1688 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1689 .mask = BIT(2),
1690 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2],
1691 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2),
1692 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1693 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2],
1694 .slot = 3,
1695 },
1696 {
1697 .label = "lc4_synced",
1698 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1699 .mask = BIT(3),
1700 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3],
1701 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3),
1702 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1703 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3],
1704 .slot = 4,
1705 },
1706 {
1707 .label = "lc5_synced",
1708 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1709 .mask = BIT(4),
1710 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4],
1711 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4),
1712 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1713 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4],
1714 .slot = 5,
1715 },
1716 {
1717 .label = "lc6_synced",
1718 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1719 .mask = BIT(5),
1720 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5],
1721 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5),
1722 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1723 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5],
1724 .slot = 6,
1725 },
1726 {
1727 .label = "lc7_synced",
1728 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1729 .mask = BIT(6),
1730 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6],
1731 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6),
1732 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1733 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6],
1734 .slot = 7,
1735 },
1736 {
1737 .label = "lc8_synced",
1738 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1739 .mask = BIT(7),
1740 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1741 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1742 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1743 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1744 .slot = 8,
1745 },
1746};
1747
1748static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = {
1749 {
1750 .label = "lc1_active",
1751 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
1752 .mask = BIT(0),
1753 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0],
1754 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0),
1755 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1756 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0],
1757 .slot = 1,
1758 },
1759 {
1760 .label = "lc2_active",
1761 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
1762 .mask = BIT(1),
1763 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1],
1764 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1),
1765 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1766 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1],
1767 .slot = 2,
1768 },
1769 {
1770 .label = "lc3_active",
1771 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
1772 .mask = BIT(2),
1773 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2],
1774 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2),
1775 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1776 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2],
1777 .slot = 3,
1778 },
1779 {
1780 .label = "lc4_active",
1781 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
1782 .mask = BIT(3),
1783 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3],
1784 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3),
1785 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1786 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3],
1787 .slot = 4,
1788 },
1789 {
1790 .label = "lc5_active",
1791 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
1792 .mask = BIT(4),
1793 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4],
1794 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4),
1795 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1796 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4],
1797 .slot = 5,
1798 },
1799 {
1800 .label = "lc6_active",
1801 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
1802 .mask = BIT(5),
1803 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5],
1804 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5),
1805 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1806 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5],
1807 .slot = 6,
1808 },
1809 {
1810 .label = "lc7_active",
1811 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
1812 .mask = BIT(6),
1813 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6],
1814 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6),
1815 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1816 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6],
1817 .slot = 7,
1818 },
1819 {
1820 .label = "lc8_active",
1821 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
1822 .mask = BIT(7),
1823 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1824 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1825 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1826 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1827 .slot = 8,
1828 },
1829};
1830
1831static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = {
1832 {
1833 .label = "lc1_shutdown",
1834 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
1835 .mask = BIT(0),
1836 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0],
1837 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0),
1838 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1839 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0],
1840 .slot = 1,
1841 },
1842 {
1843 .label = "lc2_shutdown",
1844 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
1845 .mask = BIT(1),
1846 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1],
1847 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1),
1848 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1849 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1],
1850 .slot = 2,
1851 },
1852 {
1853 .label = "lc3_shutdown",
1854 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
1855 .mask = BIT(2),
1856 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2],
1857 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2),
1858 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1859 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2],
1860 .slot = 3,
1861 },
1862 {
1863 .label = "lc4_shutdown",
1864 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
1865 .mask = BIT(3),
1866 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3],
1867 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3),
1868 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1869 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3],
1870 .slot = 4,
1871 },
1872 {
1873 .label = "lc5_shutdown",
1874 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
1875 .mask = BIT(4),
1876 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4],
1877 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4),
1878 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1879 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4],
1880 .slot = 5,
1881 },
1882 {
1883 .label = "lc6_shutdown",
1884 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
1885 .mask = BIT(5),
1886 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5],
1887 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5),
1888 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1889 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5],
1890 .slot = 6,
1891 },
1892 {
1893 .label = "lc7_shutdown",
1894 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
1895 .mask = BIT(6),
1896 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6],
1897 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6),
1898 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1899 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6],
1900 .slot = 7,
1901 },
1902 {
1903 .label = "lc8_shutdown",
1904 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
1905 .mask = BIT(7),
1906 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1907 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1908 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1909 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1910 .slot = 8,
1911 },
1912};
1913
1914static struct mlxreg_core_item mlxplat_mlxcpld_modular_items[] = {
1915 {
1916 .data = mlxplat_mlxcpld_ext_psu_items_data,
1917 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1918 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1919 .mask = MLXPLAT_CPLD_PSU_EXT_MASK,
1920 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
1921 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data),
1922 .inversed = 1,
1923 .health = false,
1924 },
1925 {
1926 .data = mlxplat_mlxcpld_modular_pwr_items_data,
1927 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1928 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1929 .mask = MLXPLAT_CPLD_PWR_EXT_MASK,
1930 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
1931 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data),
1932 .inversed = 0,
1933 .health = false,
1934 },
1935 {
1936 .data = mlxplat_mlxcpld_default_ng_fan_items_data,
1937 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1938 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1939 .mask = MLXPLAT_CPLD_FAN_NG_MASK,
1940 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
1941 .inversed = 1,
1942 .health = false,
1943 },
1944 {
1945 .data = mlxplat_mlxcpld_modular_asic_items_data,
1946 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1947 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1948 .mask = MLXPLAT_CPLD_ASIC_MASK,
1949 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_asic_items_data),
1950 .inversed = 0,
1951 .health = true,
1952 },
1953 {
1954 .data = mlxplat_mlxcpld_modular_lc_pr_items_data,
1955 .kind = MLXREG_HOTPLUG_LC_PRESENT,
1956 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC,
1957 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1958 .mask = MLXPLAT_CPLD_LPC_LC_MASK,
1959 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pr_items_data),
1960 .inversed = 1,
1961 .health = false,
1962 },
1963 {
1964 .data = mlxplat_mlxcpld_modular_lc_ver_items_data,
1965 .kind = MLXREG_HOTPLUG_LC_VERIFIED,
1966 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC,
1967 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1968 .mask = MLXPLAT_CPLD_LPC_LC_MASK,
1969 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ver_items_data),
1970 .inversed = 0,
1971 .health = false,
1972 },
1973 {
1974 .data = mlxplat_mlxcpld_modular_lc_pg_data,
1975 .kind = MLXREG_HOTPLUG_LC_POWERED,
1976 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC,
1977 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1978 .mask = MLXPLAT_CPLD_LPC_LC_MASK,
1979 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pg_data),
1980 .inversed = 0,
1981 .health = false,
1982 },
1983 {
1984 .data = mlxplat_mlxcpld_modular_lc_ready_data,
1985 .kind = MLXREG_HOTPLUG_LC_READY,
1986 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC,
1987 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1988 .mask = MLXPLAT_CPLD_LPC_LC_MASK,
1989 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ready_data),
1990 .inversed = 0,
1991 .health = false,
1992 },
1993 {
1994 .data = mlxplat_mlxcpld_modular_lc_synced_data,
1995 .kind = MLXREG_HOTPLUG_LC_SYNCED,
1996 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC,
1997 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1998 .mask = MLXPLAT_CPLD_LPC_LC_MASK,
1999 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_synced_data),
2000 .inversed = 0,
2001 .health = false,
2002 },
2003 {
2004 .data = mlxplat_mlxcpld_modular_lc_act_data,
2005 .kind = MLXREG_HOTPLUG_LC_ACTIVE,
2006 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC,
2007 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
2008 .mask = MLXPLAT_CPLD_LPC_LC_MASK,
2009 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_act_data),
2010 .inversed = 0,
2011 .health = false,
2012 },
2013 {
2014 .data = mlxplat_mlxcpld_modular_lc_sd_data,
2015 .kind = MLXREG_HOTPLUG_LC_THERMAL,
2016 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC,
2017 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2018 .mask = MLXPLAT_CPLD_LPC_LC_MASK,
2019 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_sd_data),
2020 .inversed = 0,
2021 .health = false,
2022 },
2023};
2024
2025static
2026struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = {
2027 .items = mlxplat_mlxcpld_modular_items,
2028 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_items),
2029 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
2030 .mask = MLXPLAT_CPLD_AGGR_MASK_MODULAR,
2031 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
2032 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
2033};
2034
2035/* Platform hotplug for NVLink blade systems family data */
2036static struct mlxreg_core_data mlxplat_mlxcpld_global_wp_items_data[] = {
2037 {
2038 .label = "global_wp_grant",
2039 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET,
2040 .mask = MLXPLAT_CPLD_GWP_MASK,
2041 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
2042 },
2043};
2044
2045static struct mlxreg_core_item mlxplat_mlxcpld_nvlink_blade_items[] = {
2046 {
2047 .data = mlxplat_mlxcpld_global_wp_items_data,
2048 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2049 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET,
2050 .mask = MLXPLAT_CPLD_GWP_MASK,
2051 .count = ARRAY_SIZE(mlxplat_mlxcpld_global_wp_items_data),
2052 .inversed = 0,
2053 .health = false,
2054 },
2055};
2056
2057static
2058struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_nvlink_blade_data = {
2059 .items = mlxplat_mlxcpld_nvlink_blade_items,
2060 .counter = ARRAY_SIZE(mlxplat_mlxcpld_nvlink_blade_items),
2061 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
2062 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX,
2063 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
2064 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
2065};
2066
2067/* Platform led default data */
2068static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = {
2069 {
2070 .label = "status:green",
2071 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2072 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2073 },
2074 {
2075 .label = "status:red",
2076 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2077 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
2078 },
2079 {
2080 .label = "psu:green",
2081 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2082 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2083 },
2084 {
2085 .label = "psu:red",
2086 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2087 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2088 },
2089 {
2090 .label = "fan1:green",
2091 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2092 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2093 },
2094 {
2095 .label = "fan1:red",
2096 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2097 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2098 },
2099 {
2100 .label = "fan2:green",
2101 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2102 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2103 },
2104 {
2105 .label = "fan2:red",
2106 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2107 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2108 },
2109 {
2110 .label = "fan3:green",
2111 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2112 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2113 },
2114 {
2115 .label = "fan3:red",
2116 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2117 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2118 },
2119 {
2120 .label = "fan4:green",
2121 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2122 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2123 },
2124 {
2125 .label = "fan4:red",
2126 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2127 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2128 },
2129};
2130
2131static struct mlxreg_core_platform_data mlxplat_default_led_data = {
2132 .data = mlxplat_mlxcpld_default_led_data,
2133 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data),
2134};
2135
2136/* Platform led default data for water cooling */
2137static struct mlxreg_core_data mlxplat_mlxcpld_default_led_wc_data[] = {
2138 {
2139 .label = "status:green",
2140 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2141 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2142 },
2143 {
2144 .label = "status:red",
2145 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2146 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
2147 },
2148 {
2149 .label = "psu:green",
2150 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2151 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2152 },
2153 {
2154 .label = "psu:red",
2155 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2156 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2157 },
2158};
2159
2160static struct mlxreg_core_platform_data mlxplat_default_led_wc_data = {
2161 .data = mlxplat_mlxcpld_default_led_wc_data,
2162 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_wc_data),
2163};
2164
2165/* Platform led default data for water cooling Ethernet switch blade */
2166static struct mlxreg_core_data mlxplat_mlxcpld_default_led_eth_wc_blade_data[] = {
2167 {
2168 .label = "status:green",
2169 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2170 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2171 },
2172 {
2173 .label = "status:red",
2174 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2175 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
2176 },
2177};
2178
2179static struct mlxreg_core_platform_data mlxplat_default_led_eth_wc_blade_data = {
2180 .data = mlxplat_mlxcpld_default_led_eth_wc_blade_data,
2181 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_eth_wc_blade_data),
2182};
2183
2184/* Platform led MSN21xx system family data */
2185static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = {
2186 {
2187 .label = "status:green",
2188 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2189 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2190 },
2191 {
2192 .label = "status:red",
2193 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2194 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
2195 },
2196 {
2197 .label = "fan:green",
2198 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2199 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2200 },
2201 {
2202 .label = "fan:red",
2203 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2204 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2205 },
2206 {
2207 .label = "psu1:green",
2208 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2209 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2210 },
2211 {
2212 .label = "psu1:red",
2213 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2214 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2215 },
2216 {
2217 .label = "psu2:green",
2218 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2219 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2220 },
2221 {
2222 .label = "psu2:red",
2223 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2224 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2225 },
2226 {
2227 .label = "uid:blue",
2228 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
2229 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2230 },
2231};
2232
2233static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = {
2234 .data = mlxplat_mlxcpld_msn21xx_led_data,
2235 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data),
2236};
2237
2238/* Platform led for default data for 200GbE systems */
2239static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = {
2240 {
2241 .label = "status:green",
2242 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2243 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2244 },
2245 {
2246 .label = "status:orange",
2247 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2248 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
2249 },
2250 {
2251 .label = "psu:green",
2252 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2253 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2254 },
2255 {
2256 .label = "psu:orange",
2257 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2258 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2259 },
2260 {
2261 .label = "fan1:green",
2262 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2263 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2264 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2265 .bit = BIT(0),
2266 },
2267 {
2268 .label = "fan1:orange",
2269 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2270 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2271 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2272 .bit = BIT(0),
2273 },
2274 {
2275 .label = "fan2:green",
2276 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2277 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2278 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2279 .bit = BIT(1),
2280 },
2281 {
2282 .label = "fan2:orange",
2283 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2284 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2285 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2286 .bit = BIT(1),
2287 },
2288 {
2289 .label = "fan3:green",
2290 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2291 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2292 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2293 .bit = BIT(2),
2294 },
2295 {
2296 .label = "fan3:orange",
2297 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2298 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2299 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2300 .bit = BIT(2),
2301 },
2302 {
2303 .label = "fan4:green",
2304 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2305 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2306 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2307 .bit = BIT(3),
2308 },
2309 {
2310 .label = "fan4:orange",
2311 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2312 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2313 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2314 .bit = BIT(3),
2315 },
2316 {
2317 .label = "fan5:green",
2318 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2319 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2320 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2321 .bit = BIT(4),
2322 },
2323 {
2324 .label = "fan5:orange",
2325 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2326 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2327 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2328 .bit = BIT(4),
2329 },
2330 {
2331 .label = "fan6:green",
2332 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2333 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2334 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2335 .bit = BIT(5),
2336 },
2337 {
2338 .label = "fan6:orange",
2339 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2340 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2341 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2342 .bit = BIT(5),
2343 },
2344 {
2345 .label = "fan7:green",
2346 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
2347 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2348 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2349 .bit = BIT(6),
2350 },
2351 {
2352 .label = "fan7:orange",
2353 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
2354 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2355 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2356 .bit = BIT(6),
2357 },
2358 {
2359 .label = "uid:blue",
2360 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
2361 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2362 },
2363};
2364
2365static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = {
2366 .data = mlxplat_mlxcpld_default_ng_led_data,
2367 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data),
2368};
2369
2370/* Platform led for Comex based 100GbE systems */
2371static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = {
2372 {
2373 .label = "status:green",
2374 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2375 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2376 },
2377 {
2378 .label = "status:red",
2379 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2380 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
2381 },
2382 {
2383 .label = "psu:green",
2384 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2385 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2386 },
2387 {
2388 .label = "psu:red",
2389 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2390 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2391 },
2392 {
2393 .label = "fan1:green",
2394 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2395 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2396 },
2397 {
2398 .label = "fan1:red",
2399 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2400 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2401 },
2402 {
2403 .label = "fan2:green",
2404 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2405 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2406 },
2407 {
2408 .label = "fan2:red",
2409 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2410 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2411 },
2412 {
2413 .label = "fan3:green",
2414 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2415 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2416 },
2417 {
2418 .label = "fan3:red",
2419 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2420 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2421 },
2422 {
2423 .label = "fan4:green",
2424 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2425 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2426 },
2427 {
2428 .label = "fan4:red",
2429 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2430 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2431 },
2432 {
2433 .label = "uid:blue",
2434 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
2435 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2436 },
2437};
2438
2439static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = {
2440 .data = mlxplat_mlxcpld_comex_100G_led_data,
2441 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data),
2442};
2443
2444/* Platform led for data for modular systems */
2445static struct mlxreg_core_data mlxplat_mlxcpld_modular_led_data[] = {
2446 {
2447 .label = "status:green",
2448 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2449 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2450 },
2451 {
2452 .label = "status:orange",
2453 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2454 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
2455 },
2456 {
2457 .label = "psu:green",
2458 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2459 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2460 },
2461 {
2462 .label = "psu:orange",
2463 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2464 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2465 },
2466 {
2467 .label = "fan1:green",
2468 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2469 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2470 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2471 .bit = BIT(0),
2472 },
2473 {
2474 .label = "fan1:orange",
2475 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2476 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2477 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2478 .bit = BIT(0),
2479 },
2480 {
2481 .label = "fan2:green",
2482 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2483 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2484 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2485 .bit = BIT(1),
2486 },
2487 {
2488 .label = "fan2:orange",
2489 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2490 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2491 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2492 .bit = BIT(1),
2493 },
2494 {
2495 .label = "fan3:green",
2496 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2497 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2498 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2499 .bit = BIT(2),
2500 },
2501 {
2502 .label = "fan3:orange",
2503 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2504 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2505 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2506 .bit = BIT(2),
2507 },
2508 {
2509 .label = "fan4:green",
2510 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2511 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2512 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2513 .bit = BIT(3),
2514 },
2515 {
2516 .label = "fan4:orange",
2517 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2518 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2519 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2520 .bit = BIT(3),
2521 },
2522 {
2523 .label = "fan5:green",
2524 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2525 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2526 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2527 .bit = BIT(4),
2528 },
2529 {
2530 .label = "fan5:orange",
2531 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2532 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2533 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2534 .bit = BIT(4),
2535 },
2536 {
2537 .label = "fan6:green",
2538 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2539 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2540 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2541 .bit = BIT(5),
2542 },
2543 {
2544 .label = "fan6:orange",
2545 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2546 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2547 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2548 .bit = BIT(5),
2549 },
2550 {
2551 .label = "fan7:green",
2552 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
2553 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2554 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2555 .bit = BIT(6),
2556 },
2557 {
2558 .label = "fan7:orange",
2559 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
2560 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2561 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2562 .bit = BIT(6),
2563 },
2564 {
2565 .label = "uid:blue",
2566 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
2567 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2568 },
2569 {
2570 .label = "fan_front:green",
2571 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
2572 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2573 },
2574 {
2575 .label = "fan_front:orange",
2576 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
2577 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2578 },
2579 {
2580 .label = "mgmt:green",
2581 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET,
2582 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2583 },
2584 {
2585 .label = "mgmt:orange",
2586 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET,
2587 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2588 },
2589};
2590
2591static struct mlxreg_core_platform_data mlxplat_modular_led_data = {
2592 .data = mlxplat_mlxcpld_modular_led_data,
2593 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_led_data),
2594};
2595
2596/* Platform register access default */
2597static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = {
2598 {
2599 .label = "cpld1_version",
2600 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
2601 .bit = GENMASK(7, 0),
2602 .mode = 0444,
2603 },
2604 {
2605 .label = "cpld2_version",
2606 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
2607 .bit = GENMASK(7, 0),
2608 .mode = 0444,
2609 },
2610 {
2611 .label = "cpld1_pn",
2612 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
2613 .bit = GENMASK(15, 0),
2614 .mode = 0444,
2615 .regnum = 2,
2616 },
2617 {
2618 .label = "cpld2_pn",
2619 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
2620 .bit = GENMASK(15, 0),
2621 .mode = 0444,
2622 .regnum = 2,
2623 },
2624 {
2625 .label = "cpld1_version_min",
2626 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
2627 .bit = GENMASK(7, 0),
2628 .mode = 0444,
2629 },
2630 {
2631 .label = "cpld2_version_min",
2632 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
2633 .bit = GENMASK(7, 0),
2634 .mode = 0444,
2635 },
2636 {
2637 .label = "reset_long_pb",
2638 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2639 .mask = GENMASK(7, 0) & ~BIT(0),
2640 .mode = 0444,
2641 },
2642 {
2643 .label = "reset_short_pb",
2644 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2645 .mask = GENMASK(7, 0) & ~BIT(1),
2646 .mode = 0444,
2647 },
2648 {
2649 .label = "reset_aux_pwr_or_ref",
2650 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2651 .mask = GENMASK(7, 0) & ~BIT(2),
2652 .mode = 0444,
2653 },
2654 {
2655 .label = "reset_main_pwr_fail",
2656 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2657 .mask = GENMASK(7, 0) & ~BIT(3),
2658 .mode = 0444,
2659 },
2660 {
2661 .label = "reset_sw_reset",
2662 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2663 .mask = GENMASK(7, 0) & ~BIT(4),
2664 .mode = 0444,
2665 },
2666 {
2667 .label = "reset_fw_reset",
2668 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2669 .mask = GENMASK(7, 0) & ~BIT(5),
2670 .mode = 0444,
2671 },
2672 {
2673 .label = "reset_hotswap_or_wd",
2674 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2675 .mask = GENMASK(7, 0) & ~BIT(6),
2676 .mode = 0444,
2677 },
2678 {
2679 .label = "reset_asic_thermal",
2680 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2681 .mask = GENMASK(7, 0) & ~BIT(7),
2682 .mode = 0444,
2683 },
2684 {
2685 .label = "psu1_on",
2686 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
2687 .mask = GENMASK(7, 0) & ~BIT(0),
2688 .mode = 0200,
2689 },
2690 {
2691 .label = "psu2_on",
2692 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
2693 .mask = GENMASK(7, 0) & ~BIT(1),
2694 .mode = 0200,
2695 },
2696 {
2697 .label = "pwr_cycle",
2698 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
2699 .mask = GENMASK(7, 0) & ~BIT(2),
2700 .mode = 0200,
2701 },
2702 {
2703 .label = "pwr_down",
2704 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
2705 .mask = GENMASK(7, 0) & ~BIT(3),
2706 .mode = 0200,
2707 },
2708 {
2709 .label = "select_iio",
2710 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
2711 .mask = GENMASK(7, 0) & ~BIT(6),
2712 .mode = 0644,
2713 },
2714 {
2715 .label = "asic_health",
2716 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
2717 .mask = MLXPLAT_CPLD_ASIC_MASK,
2718 .bit = 1,
2719 .mode = 0444,
2720 },
2721};
2722
2723static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = {
2724 .data = mlxplat_mlxcpld_default_regs_io_data,
2725 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data),
2726};
2727
2728/* Platform register access MSN21xx, MSN201x, MSN274x systems families data */
2729static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = {
2730 {
2731 .label = "cpld1_version",
2732 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
2733 .bit = GENMASK(7, 0),
2734 .mode = 0444,
2735 },
2736 {
2737 .label = "cpld2_version",
2738 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
2739 .bit = GENMASK(7, 0),
2740 .mode = 0444,
2741 },
2742 {
2743 .label = "cpld1_pn",
2744 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
2745 .bit = GENMASK(15, 0),
2746 .mode = 0444,
2747 .regnum = 2,
2748 },
2749 {
2750 .label = "cpld2_pn",
2751 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
2752 .bit = GENMASK(15, 0),
2753 .mode = 0444,
2754 .regnum = 2,
2755 },
2756 {
2757 .label = "cpld1_version_min",
2758 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
2759 .bit = GENMASK(7, 0),
2760 .mode = 0444,
2761 },
2762 {
2763 .label = "cpld2_version_min",
2764 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
2765 .bit = GENMASK(7, 0),
2766 .mode = 0444,
2767 },
2768 {
2769 .label = "reset_long_pb",
2770 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2771 .mask = GENMASK(7, 0) & ~BIT(0),
2772 .mode = 0444,
2773 },
2774 {
2775 .label = "reset_short_pb",
2776 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2777 .mask = GENMASK(7, 0) & ~BIT(1),
2778 .mode = 0444,
2779 },
2780 {
2781 .label = "reset_aux_pwr_or_ref",
2782 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2783 .mask = GENMASK(7, 0) & ~BIT(2),
2784 .mode = 0444,
2785 },
2786 {
2787 .label = "reset_sw_reset",
2788 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2789 .mask = GENMASK(7, 0) & ~BIT(3),
2790 .mode = 0444,
2791 },
2792 {
2793 .label = "reset_main_pwr_fail",
2794 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2795 .mask = GENMASK(7, 0) & ~BIT(4),
2796 .mode = 0444,
2797 },
2798 {
2799 .label = "reset_asic_thermal",
2800 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2801 .mask = GENMASK(7, 0) & ~BIT(5),
2802 .mode = 0444,
2803 },
2804 {
2805 .label = "reset_hotswap_or_halt",
2806 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2807 .mask = GENMASK(7, 0) & ~BIT(6),
2808 .mode = 0444,
2809 },
2810 {
2811 .label = "reset_sff_wd",
2812 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
2813 .mask = GENMASK(7, 0) & ~BIT(6),
2814 .mode = 0444,
2815 },
2816 {
2817 .label = "psu1_on",
2818 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
2819 .mask = GENMASK(7, 0) & ~BIT(0),
2820 .mode = 0200,
2821 },
2822 {
2823 .label = "psu2_on",
2824 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
2825 .mask = GENMASK(7, 0) & ~BIT(1),
2826 .mode = 0200,
2827 },
2828 {
2829 .label = "pwr_cycle",
2830 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
2831 .mask = GENMASK(7, 0) & ~BIT(2),
2832 .mode = 0200,
2833 },
2834 {
2835 .label = "pwr_down",
2836 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
2837 .mask = GENMASK(7, 0) & ~BIT(3),
2838 .mode = 0200,
2839 },
2840 {
2841 .label = "select_iio",
2842 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
2843 .mask = GENMASK(7, 0) & ~BIT(6),
2844 .mode = 0644,
2845 },
2846 {
2847 .label = "asic_health",
2848 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
2849 .mask = MLXPLAT_CPLD_ASIC_MASK,
2850 .bit = 1,
2851 .mode = 0444,
2852 },
2853};
2854
2855static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = {
2856 .data = mlxplat_mlxcpld_msn21xx_regs_io_data,
2857 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data),
2858};
2859
2860/* Platform register access for next generation systems families data */
2861static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
2862 {
2863 .label = "cpld1_version",
2864 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
2865 .bit = GENMASK(7, 0),
2866 .mode = 0444,
2867 },
2868 {
2869 .label = "cpld2_version",
2870 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
2871 .bit = GENMASK(7, 0),
2872 .mode = 0444,
2873 },
2874 {
2875 .label = "cpld3_version",
2876 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET,
2877 .bit = GENMASK(7, 0),
2878 .mode = 0444,
2879 },
2880 {
2881 .label = "cpld4_version",
2882 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET,
2883 .bit = GENMASK(7, 0),
2884 .mode = 0444,
2885 },
2886 {
2887 .label = "cpld1_pn",
2888 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
2889 .bit = GENMASK(15, 0),
2890 .mode = 0444,
2891 .regnum = 2,
2892 },
2893 {
2894 .label = "cpld2_pn",
2895 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
2896 .bit = GENMASK(15, 0),
2897 .mode = 0444,
2898 .regnum = 2,
2899 },
2900 {
2901 .label = "cpld3_pn",
2902 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET,
2903 .bit = GENMASK(15, 0),
2904 .mode = 0444,
2905 .regnum = 2,
2906 },
2907 {
2908 .label = "cpld4_pn",
2909 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET,
2910 .bit = GENMASK(15, 0),
2911 .mode = 0444,
2912 .regnum = 2,
2913 },
2914 {
2915 .label = "cpld1_version_min",
2916 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
2917 .bit = GENMASK(7, 0),
2918 .mode = 0444,
2919 },
2920 {
2921 .label = "cpld2_version_min",
2922 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
2923 .bit = GENMASK(7, 0),
2924 .mode = 0444,
2925 },
2926 {
2927 .label = "cpld3_version_min",
2928 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET,
2929 .bit = GENMASK(7, 0),
2930 .mode = 0444,
2931 },
2932 {
2933 .label = "cpld4_version_min",
2934 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET,
2935 .bit = GENMASK(7, 0),
2936 .mode = 0444,
2937 },
2938 {
2939 .label = "asic_reset",
2940 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
2941 .mask = GENMASK(7, 0) & ~BIT(3),
2942 .mode = 0200,
2943 },
2944 {
2945 .label = "asic2_reset",
2946 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
2947 .mask = GENMASK(7, 0) & ~BIT(2),
2948 .mode = 0200,
2949 },
2950 {
2951 .label = "reset_long_pb",
2952 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2953 .mask = GENMASK(7, 0) & ~BIT(0),
2954 .mode = 0444,
2955 },
2956 {
2957 .label = "reset_short_pb",
2958 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2959 .mask = GENMASK(7, 0) & ~BIT(1),
2960 .mode = 0444,
2961 },
2962 {
2963 .label = "reset_aux_pwr_or_ref",
2964 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2965 .mask = GENMASK(7, 0) & ~BIT(2),
2966 .mode = 0444,
2967 },
2968 {
2969 .label = "reset_from_comex",
2970 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2971 .mask = GENMASK(7, 0) & ~BIT(4),
2972 .mode = 0444,
2973 },
2974 {
2975 .label = "reset_from_asic",
2976 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2977 .mask = GENMASK(7, 0) & ~BIT(5),
2978 .mode = 0444,
2979 },
2980 {
2981 .label = "reset_swb_wd",
2982 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2983 .mask = GENMASK(7, 0) & ~BIT(6),
2984 .mode = 0444,
2985 },
2986 {
2987 .label = "reset_asic_thermal",
2988 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
2989 .mask = GENMASK(7, 0) & ~BIT(7),
2990 .mode = 0444,
2991 },
2992 {
2993 .label = "reset_comex_pwr_fail",
2994 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
2995 .mask = GENMASK(7, 0) & ~BIT(3),
2996 .mode = 0444,
2997 },
2998 {
2999 .label = "reset_platform",
3000 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3001 .mask = GENMASK(7, 0) & ~BIT(4),
3002 .mode = 0444,
3003 },
3004 {
3005 .label = "reset_soc",
3006 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3007 .mask = GENMASK(7, 0) & ~BIT(5),
3008 .mode = 0444,
3009 },
3010 {
3011 .label = "reset_comex_wd",
3012 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3013 .mask = GENMASK(7, 0) & ~BIT(6),
3014 .mode = 0444,
3015 },
3016 {
3017 .label = "reset_voltmon_upgrade_fail",
3018 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3019 .mask = GENMASK(7, 0) & ~BIT(0),
3020 .mode = 0444,
3021 },
3022 {
3023 .label = "reset_system",
3024 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3025 .mask = GENMASK(7, 0) & ~BIT(1),
3026 .mode = 0444,
3027 },
3028 {
3029 .label = "reset_sw_pwr_off",
3030 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3031 .mask = GENMASK(7, 0) & ~BIT(2),
3032 .mode = 0444,
3033 },
3034 {
3035 .label = "reset_comex_thermal",
3036 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3037 .mask = GENMASK(7, 0) & ~BIT(3),
3038 .mode = 0444,
3039 },
3040 {
3041 .label = "reset_reload_bios",
3042 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3043 .mask = GENMASK(7, 0) & ~BIT(5),
3044 .mode = 0444,
3045 },
3046 {
3047 .label = "reset_ac_pwr_fail",
3048 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3049 .mask = GENMASK(7, 0) & ~BIT(6),
3050 .mode = 0444,
3051 },
3052 {
3053 .label = "psu1_on",
3054 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3055 .mask = GENMASK(7, 0) & ~BIT(0),
3056 .mode = 0200,
3057 },
3058 {
3059 .label = "psu2_on",
3060 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3061 .mask = GENMASK(7, 0) & ~BIT(1),
3062 .mode = 0200,
3063 },
3064 {
3065 .label = "pwr_cycle",
3066 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3067 .mask = GENMASK(7, 0) & ~BIT(2),
3068 .mode = 0200,
3069 },
3070 {
3071 .label = "pwr_down",
3072 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3073 .mask = GENMASK(7, 0) & ~BIT(3),
3074 .mode = 0200,
3075 },
3076 {
3077 .label = "jtag_enable",
3078 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
3079 .mask = GENMASK(7, 0) & ~BIT(4),
3080 .mode = 0644,
3081 },
3082 {
3083 .label = "asic_health",
3084 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
3085 .mask = MLXPLAT_CPLD_ASIC_MASK,
3086 .bit = 1,
3087 .mode = 0444,
3088 },
3089 {
3090 .label = "asic2_health",
3091 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,
3092 .mask = MLXPLAT_CPLD_ASIC_MASK,
3093 .bit = 1,
3094 .mode = 0444,
3095 },
3096 {
3097 .label = "fan_dir",
3098 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
3099 .bit = GENMASK(7, 0),
3100 .mode = 0444,
3101 },
3102 {
3103 .label = "bios_safe_mode",
3104 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3105 .mask = GENMASK(7, 0) & ~BIT(4),
3106 .mode = 0444,
3107 },
3108 {
3109 .label = "bios_active_image",
3110 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3111 .mask = GENMASK(7, 0) & ~BIT(5),
3112 .mode = 0444,
3113 },
3114 {
3115 .label = "bios_auth_fail",
3116 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3117 .mask = GENMASK(7, 0) & ~BIT(6),
3118 .mode = 0444,
3119 },
3120 {
3121 .label = "bios_upgrade_fail",
3122 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3123 .mask = GENMASK(7, 0) & ~BIT(7),
3124 .mode = 0444,
3125 },
3126 {
3127 .label = "voltreg_update_status",
3128 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET,
3129 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK,
3130 .bit = 5,
3131 .mode = 0444,
3132 },
3133 {
3134 .label = "vpd_wp",
3135 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
3136 .mask = GENMASK(7, 0) & ~BIT(3),
3137 .mode = 0644,
3138 },
3139 {
3140 .label = "pcie_asic_reset_dis",
3141 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
3142 .mask = GENMASK(7, 0) & ~BIT(4),
3143 .mode = 0644,
3144 },
3145 {
3146 .label = "config1",
3147 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET,
3148 .bit = GENMASK(7, 0),
3149 .mode = 0444,
3150 },
3151 {
3152 .label = "config2",
3153 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET,
3154 .bit = GENMASK(7, 0),
3155 .mode = 0444,
3156 },
3157 {
3158 .label = "config3",
3159 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET,
3160 .bit = GENMASK(7, 0),
3161 .mode = 0444,
3162 },
3163 {
3164 .label = "ufm_version",
3165 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET,
3166 .bit = GENMASK(7, 0),
3167 .mode = 0444,
3168 },
3169};
3170
3171static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = {
3172 .data = mlxplat_mlxcpld_default_ng_regs_io_data,
3173 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data),
3174};
3175
3176/* Platform register access for modular systems families data */
3177static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = {
3178 {
3179 .label = "cpld1_version",
3180 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
3181 .bit = GENMASK(7, 0),
3182 .mode = 0444,
3183 },
3184 {
3185 .label = "cpld2_version",
3186 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
3187 .bit = GENMASK(7, 0),
3188 .mode = 0444,
3189 },
3190 {
3191 .label = "cpld3_version",
3192 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET,
3193 .bit = GENMASK(7, 0),
3194 .mode = 0444,
3195 },
3196 {
3197 .label = "cpld4_version",
3198 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET,
3199 .bit = GENMASK(7, 0),
3200 .mode = 0444,
3201 },
3202 {
3203 .label = "cpld1_pn",
3204 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
3205 .bit = GENMASK(15, 0),
3206 .mode = 0444,
3207 .regnum = 2,
3208 },
3209 {
3210 .label = "cpld2_pn",
3211 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
3212 .bit = GENMASK(15, 0),
3213 .mode = 0444,
3214 .regnum = 2,
3215 },
3216 {
3217 .label = "cpld3_pn",
3218 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET,
3219 .bit = GENMASK(15, 0),
3220 .mode = 0444,
3221 .regnum = 2,
3222 },
3223 {
3224 .label = "cpld4_pn",
3225 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET,
3226 .bit = GENMASK(15, 0),
3227 .mode = 0444,
3228 .regnum = 2,
3229 },
3230 {
3231 .label = "cpld1_version_min",
3232 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
3233 .bit = GENMASK(7, 0),
3234 .mode = 0444,
3235 },
3236 {
3237 .label = "cpld2_version_min",
3238 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
3239 .bit = GENMASK(7, 0),
3240 .mode = 0444,
3241 },
3242 {
3243 .label = "cpld3_version_min",
3244 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET,
3245 .bit = GENMASK(7, 0),
3246 .mode = 0444,
3247 },
3248 {
3249 .label = "cpld4_version_min",
3250 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET,
3251 .bit = GENMASK(7, 0),
3252 .mode = 0444,
3253 },
3254 {
3255 .label = "lc1_enable",
3256 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
3257 .mask = GENMASK(7, 0) & ~BIT(0),
3258 .mode = 0644,
3259 },
3260 {
3261 .label = "lc2_enable",
3262 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
3263 .mask = GENMASK(7, 0) & ~BIT(1),
3264 .mode = 0644,
3265 },
3266 {
3267 .label = "lc3_enable",
3268 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
3269 .mask = GENMASK(7, 0) & ~BIT(2),
3270 .mode = 0644,
3271 },
3272 {
3273 .label = "lc4_enable",
3274 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
3275 .mask = GENMASK(7, 0) & ~BIT(3),
3276 .mode = 0644,
3277 },
3278 {
3279 .label = "lc5_enable",
3280 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
3281 .mask = GENMASK(7, 0) & ~BIT(4),
3282 .mode = 0644,
3283 },
3284 {
3285 .label = "lc6_enable",
3286 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
3287 .mask = GENMASK(7, 0) & ~BIT(5),
3288 .mode = 0644,
3289 },
3290 {
3291 .label = "lc7_enable",
3292 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
3293 .mask = GENMASK(7, 0) & ~BIT(6),
3294 .mode = 0644,
3295 },
3296 {
3297 .label = "lc8_enable",
3298 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
3299 .mask = GENMASK(7, 0) & ~BIT(7),
3300 .mode = 0644,
3301 },
3302 {
3303 .label = "reset_long_pb",
3304 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3305 .mask = GENMASK(7, 0) & ~BIT(0),
3306 .mode = 0444,
3307 },
3308 {
3309 .label = "reset_short_pb",
3310 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3311 .mask = GENMASK(7, 0) & ~BIT(1),
3312 .mode = 0444,
3313 },
3314 {
3315 .label = "reset_aux_pwr_or_fu",
3316 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3317 .mask = GENMASK(7, 0) & ~BIT(2),
3318 .mode = 0444,
3319 },
3320 {
3321 .label = "reset_mgmt_dc_dc_pwr_fail",
3322 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3323 .mask = GENMASK(7, 0) & ~BIT(3),
3324 .mode = 0444,
3325 },
3326 {
3327 .label = "reset_sys_comex_bios",
3328 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3329 .mask = GENMASK(7, 0) & ~BIT(5),
3330 .mode = 0444,
3331 },
3332 {
3333 .label = "reset_sw_reset",
3334 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3335 .mask = GENMASK(7, 0) & ~BIT(0),
3336 .mode = 0444,
3337 },
3338 {
3339 .label = "reset_aux_pwr_or_reload",
3340 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3341 .mask = GENMASK(7, 0) & ~BIT(2),
3342 .mode = 0444,
3343 },
3344 {
3345 .label = "reset_comex_pwr_fail",
3346 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3347 .mask = GENMASK(7, 0) & ~BIT(3),
3348 .mode = 0444,
3349 },
3350 {
3351 .label = "reset_platform",
3352 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3353 .mask = GENMASK(7, 0) & ~BIT(4),
3354 .mode = 0444,
3355 },
3356 {
3357 .label = "reset_soc",
3358 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3359 .mask = GENMASK(7, 0) & ~BIT(5),
3360 .mode = 0444,
3361 },
3362 {
3363 .label = "reset_pwr_off_from_carrier",
3364 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3365 .mask = GENMASK(7, 0) & ~BIT(7),
3366 .mode = 0444,
3367 },
3368 {
3369 .label = "reset_swb_wd",
3370 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3371 .mask = GENMASK(7, 0) & ~BIT(0),
3372 .mode = 0444,
3373 },
3374 {
3375 .label = "reset_swb_aux_pwr_or_fu",
3376 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3377 .mask = GENMASK(7, 0) & ~BIT(2),
3378 .mode = 0444,
3379 },
3380 {
3381 .label = "reset_swb_dc_dc_pwr_fail",
3382 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3383 .mask = GENMASK(7, 0) & ~BIT(3),
3384 .mode = 0444,
3385 },
3386 {
3387 .label = "reset_swb_12v_fail",
3388 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3389 .mask = GENMASK(7, 0) & ~BIT(4),
3390 .mode = 0444,
3391 },
3392 {
3393 .label = "reset_system",
3394 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3395 .mask = GENMASK(7, 0) & ~BIT(5),
3396 .mode = 0444,
3397 },
3398 {
3399 .label = "reset_thermal_spc_or_pciesw",
3400 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3401 .mask = GENMASK(7, 0) & ~BIT(7),
3402 .mode = 0444,
3403 },
3404 {
3405 .label = "bios_safe_mode",
3406 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3407 .mask = GENMASK(7, 0) & ~BIT(4),
3408 .mode = 0444,
3409 },
3410 {
3411 .label = "bios_active_image",
3412 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3413 .mask = GENMASK(7, 0) & ~BIT(5),
3414 .mode = 0444,
3415 },
3416 {
3417 .label = "bios_auth_fail",
3418 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3419 .mask = GENMASK(7, 0) & ~BIT(6),
3420 .mode = 0444,
3421 },
3422 {
3423 .label = "bios_upgrade_fail",
3424 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3425 .mask = GENMASK(7, 0) & ~BIT(7),
3426 .mode = 0444,
3427 },
3428 {
3429 .label = "voltreg_update_status",
3430 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET,
3431 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK,
3432 .bit = 5,
3433 .mode = 0444,
3434 },
3435 {
3436 .label = "vpd_wp",
3437 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
3438 .mask = GENMASK(7, 0) & ~BIT(3),
3439 .mode = 0644,
3440 },
3441 {
3442 .label = "pcie_asic_reset_dis",
3443 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
3444 .mask = GENMASK(7, 0) & ~BIT(4),
3445 .mode = 0644,
3446 },
3447 {
3448 .label = "shutdown_unlock",
3449 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
3450 .mask = GENMASK(7, 0) & ~BIT(5),
3451 .mode = 0644,
3452 },
3453 {
3454 .label = "lc1_rst_mask",
3455 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
3456 .mask = GENMASK(7, 0) & ~BIT(0),
3457 .mode = 0200,
3458 },
3459 {
3460 .label = "lc2_rst_mask",
3461 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
3462 .mask = GENMASK(7, 0) & ~BIT(1),
3463 .mode = 0200,
3464 },
3465 {
3466 .label = "lc3_rst_mask",
3467 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
3468 .mask = GENMASK(7, 0) & ~BIT(2),
3469 .mode = 0200,
3470 },
3471 {
3472 .label = "lc4_rst_mask",
3473 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
3474 .mask = GENMASK(7, 0) & ~BIT(3),
3475 .mode = 0200,
3476 },
3477 {
3478 .label = "lc5_rst_mask",
3479 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
3480 .mask = GENMASK(7, 0) & ~BIT(4),
3481 .mode = 0200,
3482 },
3483 {
3484 .label = "lc6_rst_mask",
3485 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
3486 .mask = GENMASK(7, 0) & ~BIT(5),
3487 .mode = 0200,
3488 },
3489 {
3490 .label = "lc7_rst_mask",
3491 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
3492 .mask = GENMASK(7, 0) & ~BIT(6),
3493 .mode = 0200,
3494 },
3495 {
3496 .label = "lc8_rst_mask",
3497 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
3498 .mask = GENMASK(7, 0) & ~BIT(7),
3499 .mode = 0200,
3500 },
3501 {
3502 .label = "psu1_on",
3503 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3504 .mask = GENMASK(7, 0) & ~BIT(0),
3505 .mode = 0200,
3506 },
3507 {
3508 .label = "psu2_on",
3509 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3510 .mask = GENMASK(7, 0) & ~BIT(1),
3511 .mode = 0200,
3512 },
3513 {
3514 .label = "pwr_cycle",
3515 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3516 .mask = GENMASK(7, 0) & ~BIT(2),
3517 .mode = 0200,
3518 },
3519 {
3520 .label = "pwr_down",
3521 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3522 .mask = GENMASK(7, 0) & ~BIT(3),
3523 .mode = 0200,
3524 },
3525 {
3526 .label = "psu3_on",
3527 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3528 .mask = GENMASK(7, 0) & ~BIT(4),
3529 .mode = 0200,
3530 },
3531 {
3532 .label = "psu4_on",
3533 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3534 .mask = GENMASK(7, 0) & ~BIT(5),
3535 .mode = 0200,
3536 },
3537 {
3538 .label = "auto_power_mode",
3539 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3540 .mask = GENMASK(7, 0) & ~BIT(6),
3541 .mode = 0644,
3542 },
3543 {
3544 .label = "pm_mgmt_en",
3545 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3546 .mask = GENMASK(7, 0) & ~BIT(7),
3547 .mode = 0644,
3548 },
3549 {
3550 .label = "jtag_enable",
3551 .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE,
3552 .mask = GENMASK(3, 0),
3553 .bit = 1,
3554 .mode = 0644,
3555 },
3556 {
3557 .label = "safe_bios_dis",
3558 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET,
3559 .mask = GENMASK(7, 0) & ~BIT(5),
3560 .mode = 0644,
3561 },
3562 {
3563 .label = "safe_bios_dis_wp",
3564 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET,
3565 .mask = GENMASK(7, 0) & ~BIT(5),
3566 .mode = 0644,
3567 },
3568 {
3569 .label = "asic_health",
3570 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
3571 .mask = MLXPLAT_CPLD_ASIC_MASK,
3572 .bit = 1,
3573 .mode = 0444,
3574 },
3575 {
3576 .label = "fan_dir",
3577 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
3578 .bit = GENMASK(7, 0),
3579 .mode = 0444,
3580 },
3581 {
3582 .label = "lc1_pwr",
3583 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
3584 .mask = GENMASK(7, 0) & ~BIT(0),
3585 .mode = 0644,
3586 },
3587 {
3588 .label = "lc2_pwr",
3589 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
3590 .mask = GENMASK(7, 0) & ~BIT(1),
3591 .mode = 0644,
3592 },
3593 {
3594 .label = "lc3_pwr",
3595 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
3596 .mask = GENMASK(7, 0) & ~BIT(2),
3597 .mode = 0644,
3598 },
3599 {
3600 .label = "lc4_pwr",
3601 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
3602 .mask = GENMASK(7, 0) & ~BIT(3),
3603 .mode = 0644,
3604 },
3605 {
3606 .label = "lc5_pwr",
3607 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
3608 .mask = GENMASK(7, 0) & ~BIT(4),
3609 .mode = 0644,
3610 },
3611 {
3612 .label = "lc6_pwr",
3613 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
3614 .mask = GENMASK(7, 0) & ~BIT(5),
3615 .mode = 0644,
3616 },
3617 {
3618 .label = "lc7_pwr",
3619 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
3620 .mask = GENMASK(7, 0) & ~BIT(6),
3621 .mode = 0644,
3622 },
3623 {
3624 .label = "lc8_pwr",
3625 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
3626 .mask = GENMASK(7, 0) & ~BIT(7),
3627 .mode = 0644,
3628 },
3629 {
3630 .label = "config1",
3631 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET,
3632 .bit = GENMASK(7, 0),
3633 .mode = 0444,
3634 },
3635 {
3636 .label = "config2",
3637 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET,
3638 .bit = GENMASK(7, 0),
3639 .mode = 0444,
3640 },
3641 {
3642 .label = "config3",
3643 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET,
3644 .bit = GENMASK(7, 0),
3645 .mode = 0444,
3646 },
3647 {
3648 .label = "ufm_version",
3649 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET,
3650 .bit = GENMASK(7, 0),
3651 .mode = 0444,
3652 },
3653};
3654
3655static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = {
3656 .data = mlxplat_mlxcpld_modular_regs_io_data,
3657 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data),
3658};
3659
3660/* Platform register access for NVLink blade systems family data */
3661static struct mlxreg_core_data mlxplat_mlxcpld_nvlink_blade_regs_io_data[] = {
3662 {
3663 .label = "cpld1_version",
3664 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
3665 .bit = GENMASK(7, 0),
3666 .mode = 0444,
3667 },
3668 {
3669 .label = "cpld1_pn",
3670 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
3671 .bit = GENMASK(15, 0),
3672 .mode = 0444,
3673 .regnum = 2,
3674 },
3675 {
3676 .label = "cpld1_version_min",
3677 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
3678 .bit = GENMASK(7, 0),
3679 .mode = 0444,
3680 },
3681 {
3682 .label = "reset_aux_pwr_or_ref",
3683 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3684 .mask = GENMASK(7, 0) & ~BIT(2),
3685 .mode = 0444,
3686 },
3687 {
3688 .label = "reset_from_comex",
3689 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3690 .mask = GENMASK(7, 0) & ~BIT(4),
3691 .mode = 0444,
3692 },
3693 {
3694 .label = "reset_comex_pwr_fail",
3695 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3696 .mask = GENMASK(7, 0) & ~BIT(3),
3697 .mode = 0444,
3698 },
3699 {
3700 .label = "reset_platform",
3701 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3702 .mask = GENMASK(7, 0) & ~BIT(4),
3703 .mode = 0444,
3704 },
3705 {
3706 .label = "reset_soc",
3707 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3708 .mask = GENMASK(7, 0) & ~BIT(5),
3709 .mode = 0444,
3710 },
3711 {
3712 .label = "reset_comex_wd",
3713 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3714 .mask = GENMASK(7, 0) & ~BIT(6),
3715 .mode = 0444,
3716 },
3717 {
3718 .label = "reset_voltmon_upgrade_fail",
3719 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3720 .mask = GENMASK(7, 0) & ~BIT(0),
3721 .mode = 0444,
3722 },
3723 {
3724 .label = "reset_system",
3725 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3726 .mask = GENMASK(7, 0) & ~BIT(1),
3727 .mode = 0444,
3728 },
3729 {
3730 .label = "reset_sw_pwr_off",
3731 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3732 .mask = GENMASK(7, 0) & ~BIT(2),
3733 .mode = 0444,
3734 },
3735 {
3736 .label = "reset_comex_thermal",
3737 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3738 .mask = GENMASK(7, 0) & ~BIT(3),
3739 .mode = 0444,
3740 },
3741 {
3742 .label = "reset_reload_bios",
3743 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3744 .mask = GENMASK(7, 0) & ~BIT(5),
3745 .mode = 0444,
3746 },
3747 {
3748 .label = "reset_ac_pwr_fail",
3749 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3750 .mask = GENMASK(7, 0) & ~BIT(6),
3751 .mode = 0444,
3752 },
3753 {
3754 .label = "pwr_cycle",
3755 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3756 .mask = GENMASK(7, 0) & ~BIT(2),
3757 .mode = 0200,
3758 },
3759 {
3760 .label = "pwr_down",
3761 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3762 .mask = GENMASK(7, 0) & ~BIT(3),
3763 .mode = 0200,
3764 },
3765 {
3766 .label = "global_wp_request",
3767 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
3768 .mask = GENMASK(7, 0) & ~BIT(0),
3769 .mode = 0644,
3770 },
3771 {
3772 .label = "jtag_enable",
3773 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
3774 .mask = GENMASK(7, 0) & ~BIT(4),
3775 .mode = 0644,
3776 },
3777 {
3778 .label = "comm_chnl_ready",
3779 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
3780 .mask = GENMASK(7, 0) & ~BIT(6),
3781 .mode = 0200,
3782 },
3783 {
3784 .label = "bios_safe_mode",
3785 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3786 .mask = GENMASK(7, 0) & ~BIT(4),
3787 .mode = 0444,
3788 },
3789 {
3790 .label = "bios_active_image",
3791 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3792 .mask = GENMASK(7, 0) & ~BIT(5),
3793 .mode = 0444,
3794 },
3795 {
3796 .label = "bios_auth_fail",
3797 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3798 .mask = GENMASK(7, 0) & ~BIT(6),
3799 .mode = 0444,
3800 },
3801 {
3802 .label = "bios_upgrade_fail",
3803 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3804 .mask = GENMASK(7, 0) & ~BIT(7),
3805 .mode = 0444,
3806 },
3807 {
3808 .label = "voltreg_update_status",
3809 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET,
3810 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK,
3811 .bit = 5,
3812 .mode = 0444,
3813 },
3814 {
3815 .label = "vpd_wp",
3816 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
3817 .mask = GENMASK(7, 0) & ~BIT(3),
3818 .mode = 0644,
3819 },
3820 {
3821 .label = "pcie_asic_reset_dis",
3822 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
3823 .mask = GENMASK(7, 0) & ~BIT(4),
3824 .mode = 0644,
3825 },
3826 {
3827 .label = "global_wp_response",
3828 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET,
3829 .mask = GENMASK(7, 0) & ~BIT(0),
3830 .mode = 0444,
3831 },
3832 {
3833 .label = "config1",
3834 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET,
3835 .bit = GENMASK(7, 0),
3836 .mode = 0444,
3837 },
3838 {
3839 .label = "config2",
3840 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET,
3841 .bit = GENMASK(7, 0),
3842 .mode = 0444,
3843 },
3844 {
3845 .label = "config3",
3846 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET,
3847 .bit = GENMASK(7, 0),
3848 .mode = 0444,
3849 },
3850 {
3851 .label = "ufm_version",
3852 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET,
3853 .bit = GENMASK(7, 0),
3854 .mode = 0444,
3855 },
3856};
3857
3858static struct mlxreg_core_platform_data mlxplat_nvlink_blade_regs_io_data = {
3859 .data = mlxplat_mlxcpld_nvlink_blade_regs_io_data,
3860 .counter = ARRAY_SIZE(mlxplat_mlxcpld_nvlink_blade_regs_io_data),
3861};
3862
3863/* Platform FAN default */
3864static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
3865 {
3866 .label = "pwm1",
3867 .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET,
3868 },
3869 {
3870 .label = "pwm2",
3871 .reg = MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET,
3872 },
3873 {
3874 .label = "pwm3",
3875 .reg = MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET,
3876 },
3877 {
3878 .label = "pwm4",
3879 .reg = MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET,
3880 },
3881 {
3882 .label = "tacho1",
3883 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET,
3884 .mask = GENMASK(7, 0),
3885 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
3886 .bit = BIT(0),
3887 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
3888
3889 },
3890 {
3891 .label = "tacho2",
3892 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET,
3893 .mask = GENMASK(7, 0),
3894 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
3895 .bit = BIT(1),
3896 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
3897 },
3898 {
3899 .label = "tacho3",
3900 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET,
3901 .mask = GENMASK(7, 0),
3902 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
3903 .bit = BIT(2),
3904 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
3905 },
3906 {
3907 .label = "tacho4",
3908 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET,
3909 .mask = GENMASK(7, 0),
3910 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
3911 .bit = BIT(3),
3912 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
3913 },
3914 {
3915 .label = "tacho5",
3916 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET,
3917 .mask = GENMASK(7, 0),
3918 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
3919 .bit = BIT(4),
3920 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
3921 },
3922 {
3923 .label = "tacho6",
3924 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET,
3925 .mask = GENMASK(7, 0),
3926 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
3927 .bit = BIT(5),
3928 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
3929 },
3930 {
3931 .label = "tacho7",
3932 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET,
3933 .mask = GENMASK(7, 0),
3934 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
3935 .bit = BIT(6),
3936 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
3937 },
3938 {
3939 .label = "tacho8",
3940 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET,
3941 .mask = GENMASK(7, 0),
3942 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
3943 .bit = BIT(7),
3944 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
3945 },
3946 {
3947 .label = "tacho9",
3948 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET,
3949 .mask = GENMASK(7, 0),
3950 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
3951 .bit = BIT(0),
3952 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
3953 },
3954 {
3955 .label = "tacho10",
3956 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET,
3957 .mask = GENMASK(7, 0),
3958 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
3959 .bit = BIT(1),
3960 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
3961 },
3962 {
3963 .label = "tacho11",
3964 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET,
3965 .mask = GENMASK(7, 0),
3966 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
3967 .bit = BIT(2),
3968 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
3969 },
3970 {
3971 .label = "tacho12",
3972 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET,
3973 .mask = GENMASK(7, 0),
3974 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
3975 .bit = BIT(3),
3976 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
3977 },
3978 {
3979 .label = "tacho13",
3980 .reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET,
3981 .mask = GENMASK(7, 0),
3982 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
3983 .bit = BIT(4),
3984 },
3985 {
3986 .label = "tacho14",
3987 .reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET,
3988 .mask = GENMASK(7, 0),
3989 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
3990 .bit = BIT(5),
3991 },
3992 {
3993 .label = "conf",
3994 .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET,
3995 },
3996};
3997
3998static struct mlxreg_core_platform_data mlxplat_default_fan_data = {
3999 .data = mlxplat_mlxcpld_default_fan_data,
4000 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data),
4001 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
4002};
4003
4004/* Watchdog type1: hardware implementation version1
4005 * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems).
4006 */
4007static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = {
4008 {
4009 .label = "action",
4010 .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET,
4011 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
4012 .bit = 0,
4013 },
4014 {
4015 .label = "timeout",
4016 .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET,
4017 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK,
4018 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
4019 },
4020 {
4021 .label = "ping",
4022 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET,
4023 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK,
4024 .bit = 0,
4025 },
4026 {
4027 .label = "reset",
4028 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4029 .mask = GENMASK(7, 0) & ~BIT(6),
4030 .bit = 6,
4031 },
4032};
4033
4034static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = {
4035 {
4036 .label = "action",
4037 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
4038 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
4039 .bit = 4,
4040 },
4041 {
4042 .label = "timeout",
4043 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
4044 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK,
4045 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
4046 },
4047 {
4048 .label = "ping",
4049 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET,
4050 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK,
4051 .bit = 1,
4052 },
4053};
4054
4055static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = {
4056 {
4057 .data = mlxplat_mlxcpld_wd_main_regs_type1,
4058 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type1),
4059 .version = MLX_WDT_TYPE1,
4060 .identity = "mlx-wdt-main",
4061 },
4062 {
4063 .data = mlxplat_mlxcpld_wd_aux_regs_type1,
4064 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type1),
4065 .version = MLX_WDT_TYPE1,
4066 .identity = "mlx-wdt-aux",
4067 },
4068};
4069
4070/* Watchdog type2: hardware implementation version 2
4071 * (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140).
4072 */
4073static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = {
4074 {
4075 .label = "action",
4076 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
4077 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
4078 .bit = 0,
4079 },
4080 {
4081 .label = "timeout",
4082 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
4083 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
4084 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
4085 },
4086 {
4087 .label = "timeleft",
4088 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET,
4089 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
4090 },
4091 {
4092 .label = "ping",
4093 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
4094 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
4095 .bit = 0,
4096 },
4097 {
4098 .label = "reset",
4099 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4100 .mask = GENMASK(7, 0) & ~BIT(6),
4101 .bit = 6,
4102 },
4103};
4104
4105static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = {
4106 {
4107 .label = "action",
4108 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
4109 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
4110 .bit = 4,
4111 },
4112 {
4113 .label = "timeout",
4114 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
4115 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
4116 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
4117 },
4118 {
4119 .label = "timeleft",
4120 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET,
4121 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
4122 },
4123 {
4124 .label = "ping",
4125 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
4126 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
4127 .bit = 4,
4128 },
4129};
4130
4131static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = {
4132 {
4133 .data = mlxplat_mlxcpld_wd_main_regs_type2,
4134 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type2),
4135 .version = MLX_WDT_TYPE2,
4136 .identity = "mlx-wdt-main",
4137 },
4138 {
4139 .data = mlxplat_mlxcpld_wd_aux_regs_type2,
4140 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type2),
4141 .version = MLX_WDT_TYPE2,
4142 .identity = "mlx-wdt-aux",
4143 },
4144};
4145
4146/* Watchdog type3: hardware implementation version 3
4147 * Can be on all systems. It's differentiated by WD capability bit.
4148 * Old systems (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140)
4149 * still have only one main watchdog.
4150 */
4151static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type3[] = {
4152 {
4153 .label = "action",
4154 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
4155 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
4156 .bit = 0,
4157 },
4158 {
4159 .label = "timeout",
4160 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
4161 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
4162 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT,
4163 },
4164 {
4165 .label = "timeleft",
4166 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
4167 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
4168 },
4169 {
4170 .label = "ping",
4171 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
4172 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
4173 .bit = 0,
4174 },
4175 {
4176 .label = "reset",
4177 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4178 .mask = GENMASK(7, 0) & ~BIT(6),
4179 .bit = 6,
4180 },
4181};
4182
4183static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type3[] = {
4184 {
4185 .label = "action",
4186 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
4187 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
4188 .bit = 4,
4189 },
4190 {
4191 .label = "timeout",
4192 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
4193 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
4194 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT,
4195 },
4196 {
4197 .label = "timeleft",
4198 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
4199 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
4200 },
4201 {
4202 .label = "ping",
4203 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
4204 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
4205 .bit = 4,
4206 },
4207};
4208
4209static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type3[] = {
4210 {
4211 .data = mlxplat_mlxcpld_wd_main_regs_type3,
4212 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type3),
4213 .version = MLX_WDT_TYPE3,
4214 .identity = "mlx-wdt-main",
4215 },
4216 {
4217 .data = mlxplat_mlxcpld_wd_aux_regs_type3,
4218 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type3),
4219 .version = MLX_WDT_TYPE3,
4220 .identity = "mlx-wdt-aux",
4221 },
4222};
4223
4224static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
4225{
4226 switch (reg) {
4227 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:
4228 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
4229 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
4230 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
4231 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
4232 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
4233 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:
4234 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:
4235 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:
4236 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET:
4237 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
4238 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
4239 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
4240 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:
4241 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE:
4242 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET:
4243 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
4244 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
4245 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
4246 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
4247 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
4248 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET:
4249 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET:
4250 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
4251 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
4252 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:
4253 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:
4254 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
4255 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
4256 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:
4257 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:
4258 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
4259 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
4260 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET:
4261 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET:
4262 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET:
4263 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET:
4264 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET:
4265 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET:
4266 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET:
4267 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET:
4268 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET:
4269 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET:
4270 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET:
4271 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET:
4272 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET:
4273 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET:
4274 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:
4275 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:
4276 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:
4277 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
4278 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:
4279 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
4280 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:
4281 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
4282 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
4283 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:
4284 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
4285 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
4286 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
4287 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
4288 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET:
4289 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET:
4290 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET:
4291 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
4292 return true;
4293 }
4294 return false;
4295}
4296
4297static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
4298{
4299 switch (reg) {
4300 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
4301 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
4302 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
4303 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
4304 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
4305 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET:
4306 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
4307 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET:
4308 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:
4309 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET:
4310 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
4311 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET:
4312 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:
4313 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
4314 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
4315 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
4316 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
4317 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
4318 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
4319 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
4320 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
4321 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:
4322 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:
4323 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
4324 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:
4325 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET:
4326 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:
4327 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET:
4328 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
4329 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
4330 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
4331 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:
4332 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE:
4333 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET:
4334 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
4335 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
4336 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
4337 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
4338 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
4339 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET:
4340 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
4341 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET:
4342 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
4343 case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET:
4344 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET:
4345 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET:
4346 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
4347 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
4348 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
4349 case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET:
4350 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:
4351 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:
4352 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
4353 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
4354 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
4355 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET:
4356 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:
4357 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:
4358 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
4359 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
4360 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
4361 case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET:
4362 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET:
4363 case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET:
4364 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET:
4365 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET:
4366 case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET:
4367 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET:
4368 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET:
4369 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET:
4370 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET:
4371 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET:
4372 case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET:
4373 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET:
4374 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET:
4375 case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET:
4376 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET:
4377 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET:
4378 case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET:
4379 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET:
4380 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET:
4381 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET:
4382 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:
4383 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:
4384 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:
4385 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
4386 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:
4387 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
4388 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:
4389 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
4390 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
4391 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:
4392 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
4393 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
4394 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
4395 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET:
4396 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:
4397 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
4398 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:
4399 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
4400 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET:
4401 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET:
4402 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET:
4403 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
4404 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
4405 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET:
4406 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET:
4407 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET:
4408 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET:
4409 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET:
4410 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET:
4411 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET:
4412 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET:
4413 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
4414 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
4415 case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET:
4416 case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET:
4417 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
4418 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
4419 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
4420 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
4421 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET:
4422 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET:
4423 case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET:
4424 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET:
4425 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET:
4426 case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET:
4427 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET:
4428 return true;
4429 }
4430 return false;
4431}
4432
4433static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
4434{
4435 switch (reg) {
4436 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
4437 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
4438 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
4439 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
4440 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
4441 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET:
4442 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
4443 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET:
4444 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:
4445 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET:
4446 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
4447 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET:
4448 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:
4449 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
4450 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
4451 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
4452 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
4453 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
4454 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
4455 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
4456 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
4457 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:
4458 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:
4459 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
4460 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:
4461 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET:
4462 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:
4463 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET:
4464 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
4465 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
4466 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE:
4467 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET:
4468 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
4469 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
4470 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
4471 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
4472 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
4473 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET:
4474 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
4475 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET:
4476 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
4477 case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET:
4478 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET:
4479 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET:
4480 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
4481 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
4482 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
4483 case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET:
4484 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:
4485 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:
4486 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
4487 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
4488 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
4489 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET:
4490 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:
4491 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:
4492 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
4493 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
4494 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
4495 case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET:
4496 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET:
4497 case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET:
4498 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET:
4499 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET:
4500 case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET:
4501 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET:
4502 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET:
4503 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET:
4504 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET:
4505 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET:
4506 case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET:
4507 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET:
4508 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET:
4509 case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET:
4510 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET:
4511 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET:
4512 case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET:
4513 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET:
4514 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET:
4515 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET:
4516 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:
4517 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:
4518 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:
4519 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
4520 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
4521 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
4522 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
4523 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET:
4524 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:
4525 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
4526 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:
4527 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
4528 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET:
4529 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET:
4530 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET:
4531 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
4532 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
4533 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET:
4534 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET:
4535 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET:
4536 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET:
4537 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET:
4538 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET:
4539 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET:
4540 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET:
4541 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
4542 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
4543 case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET:
4544 case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET:
4545 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
4546 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
4547 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
4548 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
4549 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET:
4550 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET:
4551 case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET:
4552 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET:
4553 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET:
4554 case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET:
4555 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET:
4556 return true;
4557 }
4558 return false;
4559}
4560
4561static const struct reg_default mlxplat_mlxcpld_regmap_default[] = {
4562 { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 },
4563 { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 },
4564 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
4565 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 },
4566};
4567
4568static const struct reg_default mlxplat_mlxcpld_regmap_ng[] = {
4569 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
4570 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 },
4571};
4572
4573static const struct reg_default mlxplat_mlxcpld_regmap_comex_default[] = {
4574 { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET,
4575 MLXPLAT_CPLD_LOW_AGGRCX_MASK },
4576 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
4577};
4578
4579static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = {
4580 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
4581 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 },
4582 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 },
4583 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 },
4584};
4585
4586static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = {
4587 { MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 0x61 },
4588 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
4589 { MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, 0x00 },
4590 { MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, 0x00 },
4591 { MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, 0x00 },
4592 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 },
4593 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 },
4594 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 },
4595 { MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET,
4596 MLXPLAT_CPLD_AGGR_MASK_LC_LOW },
4597};
4598
4599struct mlxplat_mlxcpld_regmap_context {
4600 void __iomem *base;
4601};
4602
4603static struct mlxplat_mlxcpld_regmap_context mlxplat_mlxcpld_regmap_ctx;
4604
4605static int
4606mlxplat_mlxcpld_reg_read(void *context, unsigned int reg, unsigned int *val)
4607{
4608 struct mlxplat_mlxcpld_regmap_context *ctx = context;
4609
4610 *val = ioread8(ctx->base + reg);
4611 return 0;
4612}
4613
4614static int
4615mlxplat_mlxcpld_reg_write(void *context, unsigned int reg, unsigned int val)
4616{
4617 struct mlxplat_mlxcpld_regmap_context *ctx = context;
4618
4619 iowrite8(val, ctx->base + reg);
4620 return 0;
4621}
4622
4623static const struct regmap_config mlxplat_mlxcpld_regmap_config = {
4624 .reg_bits = 8,
4625 .val_bits = 8,
4626 .max_register = 255,
4627 .cache_type = REGCACHE_FLAT,
4628 .writeable_reg = mlxplat_mlxcpld_writeable_reg,
4629 .readable_reg = mlxplat_mlxcpld_readable_reg,
4630 .volatile_reg = mlxplat_mlxcpld_volatile_reg,
4631 .reg_defaults = mlxplat_mlxcpld_regmap_default,
4632 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_default),
4633 .reg_read = mlxplat_mlxcpld_reg_read,
4634 .reg_write = mlxplat_mlxcpld_reg_write,
4635};
4636
4637static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng = {
4638 .reg_bits = 8,
4639 .val_bits = 8,
4640 .max_register = 255,
4641 .cache_type = REGCACHE_FLAT,
4642 .writeable_reg = mlxplat_mlxcpld_writeable_reg,
4643 .readable_reg = mlxplat_mlxcpld_readable_reg,
4644 .volatile_reg = mlxplat_mlxcpld_volatile_reg,
4645 .reg_defaults = mlxplat_mlxcpld_regmap_ng,
4646 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng),
4647 .reg_read = mlxplat_mlxcpld_reg_read,
4648 .reg_write = mlxplat_mlxcpld_reg_write,
4649};
4650
4651static const struct regmap_config mlxplat_mlxcpld_regmap_config_comex = {
4652 .reg_bits = 8,
4653 .val_bits = 8,
4654 .max_register = 255,
4655 .cache_type = REGCACHE_FLAT,
4656 .writeable_reg = mlxplat_mlxcpld_writeable_reg,
4657 .readable_reg = mlxplat_mlxcpld_readable_reg,
4658 .volatile_reg = mlxplat_mlxcpld_volatile_reg,
4659 .reg_defaults = mlxplat_mlxcpld_regmap_comex_default,
4660 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_comex_default),
4661 .reg_read = mlxplat_mlxcpld_reg_read,
4662 .reg_write = mlxplat_mlxcpld_reg_write,
4663};
4664
4665static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = {
4666 .reg_bits = 8,
4667 .val_bits = 8,
4668 .max_register = 255,
4669 .cache_type = REGCACHE_FLAT,
4670 .writeable_reg = mlxplat_mlxcpld_writeable_reg,
4671 .readable_reg = mlxplat_mlxcpld_readable_reg,
4672 .volatile_reg = mlxplat_mlxcpld_volatile_reg,
4673 .reg_defaults = mlxplat_mlxcpld_regmap_ng400,
4674 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng400),
4675 .reg_read = mlxplat_mlxcpld_reg_read,
4676 .reg_write = mlxplat_mlxcpld_reg_write,
4677};
4678
4679static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = {
4680 .reg_bits = 8,
4681 .val_bits = 8,
4682 .max_register = 255,
4683 .cache_type = REGCACHE_FLAT,
4684 .writeable_reg = mlxplat_mlxcpld_writeable_reg,
4685 .readable_reg = mlxplat_mlxcpld_readable_reg,
4686 .volatile_reg = mlxplat_mlxcpld_volatile_reg,
4687 .reg_defaults = mlxplat_mlxcpld_regmap_eth_modular,
4688 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_eth_modular),
4689 .reg_read = mlxplat_mlxcpld_reg_read,
4690 .reg_write = mlxplat_mlxcpld_reg_write,
4691};
4692
4693static struct resource mlxplat_mlxcpld_resources[] = {
4694 [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"),
4695};
4696
4697static struct platform_device *mlxplat_dev;
4698static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c;
4699static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug;
4700static struct mlxreg_core_platform_data *mlxplat_led;
4701static struct mlxreg_core_platform_data *mlxplat_regs_io;
4702static struct mlxreg_core_platform_data *mlxplat_fan;
4703static struct mlxreg_core_platform_data
4704 *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS];
4705static const struct regmap_config *mlxplat_regmap_config;
4706
4707static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
4708{
4709 int i;
4710
4711 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
4712 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
4713 mlxplat_mux_data = mlxplat_default_mux_data;
4714 for (i = 0; i < mlxplat_mux_num; i++) {
4715 mlxplat_mux_data[i].values = mlxplat_default_channels[i];
4716 mlxplat_mux_data[i].n_values =
4717 ARRAY_SIZE(mlxplat_default_channels[i]);
4718 }
4719 mlxplat_hotplug = &mlxplat_mlxcpld_default_data;
4720 mlxplat_hotplug->deferred_nr =
4721 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
4722 mlxplat_led = &mlxplat_default_led_data;
4723 mlxplat_regs_io = &mlxplat_default_regs_io_data;
4724 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
4725
4726 return 1;
4727}
4728
4729static int __init mlxplat_dmi_default_wc_matched(const struct dmi_system_id *dmi)
4730{
4731 int i;
4732
4733 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
4734 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
4735 mlxplat_mux_data = mlxplat_default_mux_data;
4736 for (i = 0; i < mlxplat_mux_num; i++) {
4737 mlxplat_mux_data[i].values = mlxplat_default_channels[i];
4738 mlxplat_mux_data[i].n_values =
4739 ARRAY_SIZE(mlxplat_default_channels[i]);
4740 }
4741 mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data;
4742 mlxplat_hotplug->deferred_nr =
4743 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
4744 mlxplat_led = &mlxplat_default_led_wc_data;
4745 mlxplat_regs_io = &mlxplat_default_regs_io_data;
4746 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
4747
4748 return 1;
4749}
4750
4751static int __init mlxplat_dmi_default_eth_wc_blade_matched(const struct dmi_system_id *dmi)
4752{
4753 int i;
4754
4755 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
4756 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
4757 mlxplat_mux_data = mlxplat_default_mux_data;
4758 for (i = 0; i < mlxplat_mux_num; i++) {
4759 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
4760 mlxplat_mux_data[i].n_values =
4761 ARRAY_SIZE(mlxplat_msn21xx_channels);
4762 }
4763 mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data;
4764 mlxplat_hotplug->deferred_nr =
4765 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
4766 mlxplat_led = &mlxplat_default_led_eth_wc_blade_data;
4767 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
4768 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
4769 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
4770 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
4771 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng;
4772
4773 return 1;
4774}
4775
4776static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi)
4777{
4778 int i;
4779
4780 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
4781 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
4782 mlxplat_mux_data = mlxplat_default_mux_data;
4783 for (i = 0; i < mlxplat_mux_num; i++) {
4784 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
4785 mlxplat_mux_data[i].n_values =
4786 ARRAY_SIZE(mlxplat_msn21xx_channels);
4787 }
4788 mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data;
4789 mlxplat_hotplug->deferred_nr =
4790 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
4791 mlxplat_led = &mlxplat_msn21xx_led_data;
4792 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
4793 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
4794
4795 return 1;
4796}
4797
4798static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi)
4799{
4800 int i;
4801
4802 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
4803 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
4804 mlxplat_mux_data = mlxplat_default_mux_data;
4805 for (i = 0; i < mlxplat_mux_num; i++) {
4806 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
4807 mlxplat_mux_data[i].n_values =
4808 ARRAY_SIZE(mlxplat_msn21xx_channels);
4809 }
4810 mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data;
4811 mlxplat_hotplug->deferred_nr =
4812 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
4813 mlxplat_led = &mlxplat_default_led_data;
4814 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
4815 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
4816
4817 return 1;
4818}
4819
4820static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi)
4821{
4822 int i;
4823
4824 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
4825 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
4826 mlxplat_mux_data = mlxplat_default_mux_data;
4827 for (i = 0; i < mlxplat_mux_num; i++) {
4828 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
4829 mlxplat_mux_data[i].n_values =
4830 ARRAY_SIZE(mlxplat_msn21xx_channels);
4831 }
4832 mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data;
4833 mlxplat_hotplug->deferred_nr =
4834 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
4835 mlxplat_led = &mlxplat_msn21xx_led_data;
4836 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
4837 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
4838
4839 return 1;
4840}
4841
4842static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi)
4843{
4844 int i;
4845
4846 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
4847 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
4848 mlxplat_mux_data = mlxplat_default_mux_data;
4849 for (i = 0; i < mlxplat_mux_num; i++) {
4850 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
4851 mlxplat_mux_data[i].n_values =
4852 ARRAY_SIZE(mlxplat_msn21xx_channels);
4853 }
4854 mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data;
4855 mlxplat_hotplug->deferred_nr =
4856 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
4857 mlxplat_led = &mlxplat_default_ng_led_data;
4858 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
4859 mlxplat_fan = &mlxplat_default_fan_data;
4860 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
4861 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
4862 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
4863 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng;
4864
4865 return 1;
4866}
4867
4868static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi)
4869{
4870 int i;
4871
4872 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM;
4873 mlxplat_mux_num = ARRAY_SIZE(mlxplat_extended_mux_data);
4874 mlxplat_mux_data = mlxplat_extended_mux_data;
4875 for (i = 0; i < mlxplat_mux_num; i++) {
4876 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
4877 mlxplat_mux_data[i].n_values =
4878 ARRAY_SIZE(mlxplat_msn21xx_channels);
4879 }
4880 mlxplat_hotplug = &mlxplat_mlxcpld_comex_data;
4881 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM;
4882 mlxplat_led = &mlxplat_comex_100G_led_data;
4883 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
4884 mlxplat_fan = &mlxplat_default_fan_data;
4885 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
4886 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
4887 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex;
4888
4889 return 1;
4890}
4891
4892static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi)
4893{
4894 int i;
4895
4896 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
4897 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
4898 mlxplat_mux_data = mlxplat_default_mux_data;
4899 for (i = 0; i < mlxplat_mux_num; i++) {
4900 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
4901 mlxplat_mux_data[i].n_values =
4902 ARRAY_SIZE(mlxplat_msn21xx_channels);
4903 }
4904 mlxplat_hotplug = &mlxplat_mlxcpld_ext_data;
4905 mlxplat_hotplug->deferred_nr =
4906 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
4907 mlxplat_led = &mlxplat_default_ng_led_data;
4908 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
4909 mlxplat_fan = &mlxplat_default_fan_data;
4910 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
4911 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
4912 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
4913 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400;
4914
4915 return 1;
4916}
4917
4918static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi)
4919{
4920 int i;
4921
4922 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
4923 mlxplat_mux_num = ARRAY_SIZE(mlxplat_modular_mux_data);
4924 mlxplat_mux_data = mlxplat_modular_mux_data;
4925 mlxplat_hotplug = &mlxplat_mlxcpld_modular_data;
4926 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR;
4927 mlxplat_led = &mlxplat_modular_led_data;
4928 mlxplat_regs_io = &mlxplat_modular_regs_io_data;
4929 mlxplat_fan = &mlxplat_default_fan_data;
4930 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
4931 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
4932 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
4933 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_eth_modular;
4934
4935 return 1;
4936}
4937
4938static int __init mlxplat_dmi_nvlink_blade_matched(const struct dmi_system_id *dmi)
4939{
4940 int i;
4941
4942 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
4943 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
4944 mlxplat_mux_data = mlxplat_default_mux_data;
4945 mlxplat_hotplug = &mlxplat_mlxcpld_nvlink_blade_data;
4946 mlxplat_hotplug->deferred_nr =
4947 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
4948 for (i = 0; i < mlxplat_mux_num; i++) {
4949 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
4950 mlxplat_mux_data[i].n_values =
4951 ARRAY_SIZE(mlxplat_msn21xx_channels);
4952 }
4953 mlxplat_regs_io = &mlxplat_nvlink_blade_regs_io_data;
4954 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
4955 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400;
4956
4957 return 1;
4958}
4959
4960static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
4961 {
4962 .callback = mlxplat_dmi_default_wc_matched,
4963 .matches = {
4964 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"),
4965 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI138"),
4966 },
4967 },
4968 {
4969 .callback = mlxplat_dmi_default_matched,
4970 .matches = {
4971 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"),
4972 },
4973 },
4974 {
4975 .callback = mlxplat_dmi_msn21xx_matched,
4976 .matches = {
4977 DMI_MATCH(DMI_BOARD_NAME, "VMOD0002"),
4978 },
4979 },
4980 {
4981 .callback = mlxplat_dmi_msn274x_matched,
4982 .matches = {
4983 DMI_MATCH(DMI_BOARD_NAME, "VMOD0003"),
4984 },
4985 },
4986 {
4987 .callback = mlxplat_dmi_msn201x_matched,
4988 .matches = {
4989 DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"),
4990 },
4991 },
4992 {
4993 .callback = mlxplat_dmi_default_eth_wc_blade_matched,
4994 .matches = {
4995 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"),
4996 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI139"),
4997 },
4998 },
4999 {
5000 .callback = mlxplat_dmi_qmb7xx_matched,
5001 .matches = {
5002 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"),
5003 },
5004 },
5005 {
5006 .callback = mlxplat_dmi_qmb7xx_matched,
5007 .matches = {
5008 DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"),
5009 },
5010 },
5011 {
5012 .callback = mlxplat_dmi_comex_matched,
5013 .matches = {
5014 DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"),
5015 },
5016 },
5017 {
5018 .callback = mlxplat_dmi_ng400_matched,
5019 .matches = {
5020 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"),
5021 },
5022 },
5023 {
5024 .callback = mlxplat_dmi_modular_matched,
5025 .matches = {
5026 DMI_MATCH(DMI_BOARD_NAME, "VMOD0011"),
5027 },
5028 },
5029 {
5030 .callback = mlxplat_dmi_nvlink_blade_matched,
5031 .matches = {
5032 DMI_MATCH(DMI_BOARD_NAME, "VMOD0015"),
5033 },
5034 },
5035 {
5036 .callback = mlxplat_dmi_msn274x_matched,
5037 .matches = {
5038 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
5039 DMI_MATCH(DMI_PRODUCT_NAME, "MSN274"),
5040 },
5041 },
5042 {
5043 .callback = mlxplat_dmi_default_matched,
5044 .matches = {
5045 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
5046 DMI_MATCH(DMI_PRODUCT_NAME, "MSN24"),
5047 },
5048 },
5049 {
5050 .callback = mlxplat_dmi_default_matched,
5051 .matches = {
5052 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
5053 DMI_MATCH(DMI_PRODUCT_NAME, "MSN27"),
5054 },
5055 },
5056 {
5057 .callback = mlxplat_dmi_default_matched,
5058 .matches = {
5059 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
5060 DMI_MATCH(DMI_PRODUCT_NAME, "MSB"),
5061 },
5062 },
5063 {
5064 .callback = mlxplat_dmi_default_matched,
5065 .matches = {
5066 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
5067 DMI_MATCH(DMI_PRODUCT_NAME, "MSX"),
5068 },
5069 },
5070 {
5071 .callback = mlxplat_dmi_msn21xx_matched,
5072 .matches = {
5073 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
5074 DMI_MATCH(DMI_PRODUCT_NAME, "MSN21"),
5075 },
5076 },
5077 {
5078 .callback = mlxplat_dmi_msn201x_matched,
5079 .matches = {
5080 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
5081 DMI_MATCH(DMI_PRODUCT_NAME, "MSN201"),
5082 },
5083 },
5084 {
5085 .callback = mlxplat_dmi_qmb7xx_matched,
5086 .matches = {
5087 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
5088 DMI_MATCH(DMI_PRODUCT_NAME, "MQM87"),
5089 },
5090 },
5091 {
5092 .callback = mlxplat_dmi_qmb7xx_matched,
5093 .matches = {
5094 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
5095 DMI_MATCH(DMI_PRODUCT_NAME, "MSN37"),
5096 },
5097 },
5098 {
5099 .callback = mlxplat_dmi_qmb7xx_matched,
5100 .matches = {
5101 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
5102 DMI_MATCH(DMI_PRODUCT_NAME, "MSN34"),
5103 },
5104 },
5105 {
5106 .callback = mlxplat_dmi_qmb7xx_matched,
5107 .matches = {
5108 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
5109 DMI_MATCH(DMI_PRODUCT_NAME, "MSN38"),
5110 },
5111 },
5112 { }
5113};
5114
5115MODULE_DEVICE_TABLE(dmi, mlxplat_dmi_table);
5116
5117static int mlxplat_mlxcpld_verify_bus_topology(int *nr)
5118{
5119 struct i2c_adapter *search_adap;
5120 int shift, i;
5121
5122 /* Scan adapters from expected id to verify it is free. */
5123 *nr = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR;
5124 for (i = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; i <
5125 mlxplat_max_adap_num; i++) {
5126 search_adap = i2c_get_adapter(i);
5127 if (search_adap) {
5128 i2c_put_adapter(search_adap);
5129 continue;
5130 }
5131
5132 /* Return if expected parent adapter is free. */
5133 if (i == MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR)
5134 return 0;
5135 break;
5136 }
5137
5138 /* Return with error if free id for adapter is not found. */
5139 if (i == mlxplat_max_adap_num)
5140 return -ENODEV;
5141
5142 /* Shift adapter ids, since expected parent adapter is not free. */
5143 *nr = i;
5144 for (i = 0; i < mlxplat_mux_num; i++) {
5145 shift = *nr - mlxplat_mux_data[i].parent;
5146 mlxplat_mux_data[i].parent = *nr;
5147 mlxplat_mux_data[i].base_nr += shift;
5148 if (shift > 0)
5149 mlxplat_hotplug->shift_nr = shift;
5150 }
5151
5152 return 0;
5153}
5154
5155static int mlxplat_mlxcpld_check_wd_capability(void *regmap)
5156{
5157 u32 regval;
5158 int i, rc;
5159
5160 rc = regmap_read(regmap, MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
5161 ®val);
5162 if (rc)
5163 return rc;
5164
5165 if (!(regval & ~MLXPLAT_CPLD_WD_CPBLTY_MASK)) {
5166 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) {
5167 if (mlxplat_wd_data[i])
5168 mlxplat_wd_data[i] =
5169 &mlxplat_mlxcpld_wd_set_type3[i];
5170 }
5171 }
5172
5173 return 0;
5174}
5175
5176static int __init mlxplat_init(void)
5177{
5178 struct mlxplat_priv *priv;
5179 int i, j, nr, err;
5180
5181 if (!dmi_check_system(mlxplat_dmi_table))
5182 return -ENODEV;
5183
5184 mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, PLATFORM_DEVID_NONE,
5185 mlxplat_lpc_resources,
5186 ARRAY_SIZE(mlxplat_lpc_resources));
5187
5188 if (IS_ERR(mlxplat_dev))
5189 return PTR_ERR(mlxplat_dev);
5190
5191 priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv),
5192 GFP_KERNEL);
5193 if (!priv) {
5194 err = -ENOMEM;
5195 goto fail_alloc;
5196 }
5197 platform_set_drvdata(mlxplat_dev, priv);
5198
5199 mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev,
5200 mlxplat_lpc_resources[1].start, 1);
5201 if (!mlxplat_mlxcpld_regmap_ctx.base) {
5202 err = -ENOMEM;
5203 goto fail_alloc;
5204 }
5205
5206 if (!mlxplat_regmap_config)
5207 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config;
5208
5209 priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL,
5210 &mlxplat_mlxcpld_regmap_ctx,
5211 mlxplat_regmap_config);
5212 if (IS_ERR(priv->regmap)) {
5213 err = PTR_ERR(priv->regmap);
5214 goto fail_alloc;
5215 }
5216
5217 err = mlxplat_mlxcpld_verify_bus_topology(&nr);
5218 if (nr < 0)
5219 goto fail_alloc;
5220
5221 nr = (nr == mlxplat_max_adap_num) ? -1 : nr;
5222 if (mlxplat_i2c)
5223 mlxplat_i2c->regmap = priv->regmap;
5224 priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld",
5225 nr, mlxplat_mlxcpld_resources,
5226 ARRAY_SIZE(mlxplat_mlxcpld_resources),
5227 mlxplat_i2c, sizeof(*mlxplat_i2c));
5228 if (IS_ERR(priv->pdev_i2c)) {
5229 err = PTR_ERR(priv->pdev_i2c);
5230 goto fail_alloc;
5231 }
5232
5233 for (i = 0; i < mlxplat_mux_num; i++) {
5234 priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev,
5235 "i2c-mux-reg", i, NULL, 0,
5236 &mlxplat_mux_data[i],
5237 sizeof(mlxplat_mux_data[i]));
5238 if (IS_ERR(priv->pdev_mux[i])) {
5239 err = PTR_ERR(priv->pdev_mux[i]);
5240 goto fail_platform_mux_register;
5241 }
5242 }
5243
5244 /* Add hotplug driver */
5245 if (mlxplat_hotplug) {
5246 mlxplat_hotplug->regmap = priv->regmap;
5247 priv->pdev_hotplug =
5248 platform_device_register_resndata(&mlxplat_dev->dev,
5249 "mlxreg-hotplug", PLATFORM_DEVID_NONE,
5250 mlxplat_mlxcpld_resources,
5251 ARRAY_SIZE(mlxplat_mlxcpld_resources),
5252 mlxplat_hotplug, sizeof(*mlxplat_hotplug));
5253 if (IS_ERR(priv->pdev_hotplug)) {
5254 err = PTR_ERR(priv->pdev_hotplug);
5255 goto fail_platform_mux_register;
5256 }
5257 }
5258
5259 /* Set default registers. */
5260 for (j = 0; j < mlxplat_regmap_config->num_reg_defaults; j++) {
5261 err = regmap_write(priv->regmap,
5262 mlxplat_regmap_config->reg_defaults[j].reg,
5263 mlxplat_regmap_config->reg_defaults[j].def);
5264 if (err)
5265 goto fail_platform_mux_register;
5266 }
5267
5268 /* Add LED driver. */
5269 if (mlxplat_led) {
5270 mlxplat_led->regmap = priv->regmap;
5271 priv->pdev_led =
5272 platform_device_register_resndata(&mlxplat_dev->dev, "leds-mlxreg",
5273 PLATFORM_DEVID_NONE, NULL, 0, mlxplat_led,
5274 sizeof(*mlxplat_led));
5275 if (IS_ERR(priv->pdev_led)) {
5276 err = PTR_ERR(priv->pdev_led);
5277 goto fail_platform_hotplug_register;
5278 }
5279 }
5280
5281 /* Add registers io access driver. */
5282 if (mlxplat_regs_io) {
5283 mlxplat_regs_io->regmap = priv->regmap;
5284 priv->pdev_io_regs = platform_device_register_resndata(&mlxplat_dev->dev,
5285 "mlxreg-io",
5286 PLATFORM_DEVID_NONE, NULL,
5287 0, mlxplat_regs_io,
5288 sizeof(*mlxplat_regs_io));
5289 if (IS_ERR(priv->pdev_io_regs)) {
5290 err = PTR_ERR(priv->pdev_io_regs);
5291 goto fail_platform_led_register;
5292 }
5293 }
5294
5295 /* Add FAN driver. */
5296 if (mlxplat_fan) {
5297 mlxplat_fan->regmap = priv->regmap;
5298 priv->pdev_fan = platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-fan",
5299 PLATFORM_DEVID_NONE, NULL, 0,
5300 mlxplat_fan,
5301 sizeof(*mlxplat_fan));
5302 if (IS_ERR(priv->pdev_fan)) {
5303 err = PTR_ERR(priv->pdev_fan);
5304 goto fail_platform_io_regs_register;
5305 }
5306 }
5307
5308 /* Add WD drivers. */
5309 err = mlxplat_mlxcpld_check_wd_capability(priv->regmap);
5310 if (err)
5311 goto fail_platform_wd_register;
5312 for (j = 0; j < MLXPLAT_CPLD_WD_MAX_DEVS; j++) {
5313 if (mlxplat_wd_data[j]) {
5314 mlxplat_wd_data[j]->regmap = priv->regmap;
5315 priv->pdev_wd[j] =
5316 platform_device_register_resndata(&mlxplat_dev->dev, "mlx-wdt", j,
5317 NULL, 0, mlxplat_wd_data[j],
5318 sizeof(*mlxplat_wd_data[j]));
5319 if (IS_ERR(priv->pdev_wd[j])) {
5320 err = PTR_ERR(priv->pdev_wd[j]);
5321 goto fail_platform_wd_register;
5322 }
5323 }
5324 }
5325
5326 /* Sync registers with hardware. */
5327 regcache_mark_dirty(priv->regmap);
5328 err = regcache_sync(priv->regmap);
5329 if (err)
5330 goto fail_platform_wd_register;
5331
5332 return 0;
5333
5334fail_platform_wd_register:
5335 while (--j >= 0)
5336 platform_device_unregister(priv->pdev_wd[j]);
5337 if (mlxplat_fan)
5338 platform_device_unregister(priv->pdev_fan);
5339fail_platform_io_regs_register:
5340 if (mlxplat_regs_io)
5341 platform_device_unregister(priv->pdev_io_regs);
5342fail_platform_led_register:
5343 if (mlxplat_led)
5344 platform_device_unregister(priv->pdev_led);
5345fail_platform_hotplug_register:
5346 if (mlxplat_hotplug)
5347 platform_device_unregister(priv->pdev_hotplug);
5348fail_platform_mux_register:
5349 while (--i >= 0)
5350 platform_device_unregister(priv->pdev_mux[i]);
5351 platform_device_unregister(priv->pdev_i2c);
5352fail_alloc:
5353 platform_device_unregister(mlxplat_dev);
5354
5355 return err;
5356}
5357module_init(mlxplat_init);
5358
5359static void __exit mlxplat_exit(void)
5360{
5361 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
5362 int i;
5363
5364 for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--)
5365 platform_device_unregister(priv->pdev_wd[i]);
5366 if (priv->pdev_fan)
5367 platform_device_unregister(priv->pdev_fan);
5368 if (priv->pdev_io_regs)
5369 platform_device_unregister(priv->pdev_io_regs);
5370 if (priv->pdev_led)
5371 platform_device_unregister(priv->pdev_led);
5372 if (priv->pdev_hotplug)
5373 platform_device_unregister(priv->pdev_hotplug);
5374
5375 for (i = mlxplat_mux_num - 1; i >= 0 ; i--)
5376 platform_device_unregister(priv->pdev_mux[i]);
5377
5378 platform_device_unregister(priv->pdev_i2c);
5379 platform_device_unregister(mlxplat_dev);
5380}
5381module_exit(mlxplat_exit);
5382
5383MODULE_AUTHOR("Vadim Pasternak (vadimp@mellanox.com)");
5384MODULE_DESCRIPTION("Mellanox platform driver");
5385MODULE_LICENSE("Dual BSD/GPL");
1// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2/*
3 * Mellanox platform driver
4 *
5 * Copyright (C) 2016-2018 Mellanox Technologies
6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com>
7 */
8
9#include <linux/device.h>
10#include <linux/dmi.h>
11#include <linux/i2c.h>
12#include <linux/i2c-mux.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/pci.h>
16#include <linux/platform_device.h>
17#include <linux/platform_data/i2c-mux-reg.h>
18#include <linux/platform_data/mlxreg.h>
19#include <linux/reboot.h>
20#include <linux/regmap.h>
21
22#define MLX_PLAT_DEVICE_NAME "mlxplat"
23
24/* LPC bus IO offsets */
25#define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000
26#define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500
27#define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00
28#define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01
29#define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02
30#define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03
31#define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET 0x04
32#define MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET 0x05
33#define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0x06
34#define MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET 0x07
35#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0x08
36#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET 0x09
37#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a
38#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0x0b
39#define MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET 0x17
40#define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET 0x19
41#define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c
42#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
43#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e
44#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f
45#define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20
46#define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21
47#define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22
48#define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23
49#define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24
50#define MLXPLAT_CPLD_LPC_REG_LED6_OFFSET 0x25
51#define MLXPLAT_CPLD_LPC_REG_LED7_OFFSET 0x26
52#define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a
53#define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b
54#define MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET 0x2d
55#define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e
56#define MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET 0x2f
57#define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30
58#define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31
59#define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32
60#define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33
61#define MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE 0x34
62#define MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET 0x35
63#define MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET 0x36
64#define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37
65#define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a
66#define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b
67#define MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET 0x3c
68#define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
69#define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41
70#define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42
71#define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43
72#define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44
73#define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45
74#define MLXPLAT_CPLD_LPC_REG_BRD_OFFSET 0x47
75#define MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET 0x48
76#define MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET 0x49
77#define MLXPLAT_CPLD_LPC_REG_GWP_OFFSET 0x4a
78#define MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET 0x4b
79#define MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET 0x4c
80#define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50
81#define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51
82#define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52
83#define MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET 0x53
84#define MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET 0x54
85#define MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET 0x55
86#define MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET 0x56
87#define MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET 0x57
88#define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58
89#define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59
90#define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a
91#define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64
92#define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65
93#define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66
94#define MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET 0x70
95#define MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET 0x71
96#define MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET 0x72
97#define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88
98#define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89
99#define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a
100#define MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET 0x8e
101#define MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET 0x8f
102#define MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET 0x90
103#define MLXPLAT_CPLD_LPC_REG_EROT_OFFSET 0x91
104#define MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET 0x92
105#define MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET 0x93
106#define MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET 0x94
107#define MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET 0x95
108#define MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET 0x96
109#define MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET 0x97
110#define MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET 0x98
111#define MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET 0x99
112#define MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET 0x9a
113#define MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET 0x9b
114#define MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET 0x9c
115#define MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET 0x9d
116#define MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET 0x9e
117#define MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET 0x9f
118#define MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET 0xa0
119#define MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET 0xa1
120#define MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET 0xa2
121#define MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET 0xa3
122#define MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET 0xa4
123#define MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET 0xa5
124#define MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET 0xa6
125#define MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET 0xa7
126#define MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET 0xa8
127#define MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET 0xa9
128#define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa
129#define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab
130#define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2
131#define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0xb6
132#define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0xb7
133#define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0xb8
134#define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0xb9
135#define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2
136#define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3
137#define MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET 0xc4
138#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7
139#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8
140#define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9
141#define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0xcb
142#define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0xcd
143#define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0xce
144#define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0xcf
145#define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1
146#define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2
147#define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3
148#define MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET 0xd9
149#define MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET 0xdb
150#define MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET 0xda
151#define MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET 0xdc
152#define MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET 0xdd
153#define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde
154#define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf
155#define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0
156#define MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET 0xe1
157#define MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET 0xe2
158#define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3
159#define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4
160#define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5
161#define MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET 0xe6
162#define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7
163#define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8
164#define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9
165#define MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET 0xea
166#define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xeb
167#define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xec
168#define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xed
169#define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee
170#define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef
171#define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0
172#define MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET 0xf1
173#define MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET 0xf2
174#define MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET 0xf3
175#define MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET 0xf4
176#define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5
177#define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6
178#define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7
179#define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0xf8
180#define MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET 0xf9
181#define MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET 0xfa
182#define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb
183#define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc
184#define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd
185#define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
186
187#define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL
188#define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
189 MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET) | \
190 MLXPLAT_CPLD_LPC_PIO_OFFSET)
191#define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
192 MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET) | \
193 MLXPLAT_CPLD_LPC_PIO_OFFSET)
194#define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
195 MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET) | \
196 MLXPLAT_CPLD_LPC_PIO_OFFSET)
197#define MLXPLAT_CPLD_LPC_REG4 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
198 MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET) | \
199 MLXPLAT_CPLD_LPC_PIO_OFFSET)
200
201/* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */
202#define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0x04
203#define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0x08
204#define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0x08
205#define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40
206#define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \
207 MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \
208 MLXPLAT_CPLD_AGGR_FAN_MASK_DEF)
209#define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01
210#define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04
211#define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0)
212#define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3)
213#define MLXPLAT_CPLD_AGGR_MASK_MODULAR (MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \
214 MLXPLAT_CPLD_AGGR_MASK_COMEX | \
215 MLXPLAT_CPLD_AGGR_MASK_LC)
216#define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0)
217#define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1)
218#define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2)
219#define MLXPLAT_CPLD_AGGR_MASK_LC_SCRD BIT(3)
220#define MLXPLAT_CPLD_AGGR_MASK_LC_SYNC BIT(4)
221#define MLXPLAT_CPLD_AGGR_MASK_LC_ACT BIT(5)
222#define MLXPLAT_CPLD_AGGR_MASK_LC_SDWN BIT(6)
223#define MLXPLAT_CPLD_AGGR_MASK_LC_LOW (MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT | \
224 MLXPLAT_CPLD_AGGR_MASK_LC_RDY | \
225 MLXPLAT_CPLD_AGGR_MASK_LC_PG | \
226 MLXPLAT_CPLD_AGGR_MASK_LC_SCRD | \
227 MLXPLAT_CPLD_AGGR_MASK_LC_SYNC | \
228 MLXPLAT_CPLD_AGGR_MASK_LC_ACT | \
229 MLXPLAT_CPLD_AGGR_MASK_LC_SDWN)
230#define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1
231#define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2)
232#define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT GENMASK(5, 4)
233#define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6)
234#define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0)
235#define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)
236#define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0)
237#define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0)
238#define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0)
239#define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0)
240#define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(6, 0)
241#define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4)
242#define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0)
243#define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4)
244#define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0)
245#define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0)
246#define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1, 0)
247#define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0)
248#define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6)
249#define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3)
250#define MLXPLAT_CPLD_THERMAL2_PDB_MASK BIT(4)
251#define MLXPLAT_CPLD_INTRUSION_MASK BIT(6)
252#define MLXPLAT_CPLD_PWM_PG_MASK BIT(7)
253#define MLXPLAT_CPLD_L1_CHA_HEALTH_MASK (MLXPLAT_CPLD_THERMAL1_PDB_MASK | \
254 MLXPLAT_CPLD_THERMAL2_PDB_MASK | \
255 MLXPLAT_CPLD_INTRUSION_MASK |\
256 MLXPLAT_CPLD_PWM_PG_MASK)
257#define MLXPLAT_CPLD_I2C_CAP_BIT 0x04
258#define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT)
259#define MLXPLAT_CPLD_SYS_RESET_MASK BIT(0)
260
261/* Masks for aggregation for comex carriers */
262#define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1)
263#define MLXPLAT_CPLD_AGGR_MASK_CARR_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \
264 MLXPLAT_CPLD_AGGR_MASK_CARRIER)
265#define MLXPLAT_CPLD_LOW_AGGRCX_MASK 0xc1
266
267/* Masks for aggregation for modular systems */
268#define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0)
269
270#define MLXPLAT_CPLD_HALT_MASK BIT(3)
271#define MLXPLAT_CPLD_RESET_MASK GENMASK(7, 1)
272
273/* Default I2C parent bus number */
274#define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1
275
276/* Maximum number of possible physical buses equipped on system */
277#define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16
278#define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24
279
280/* Number of channels in group */
281#define MLXPLAT_CPLD_GRP_CHNL_NUM 8
282
283/* Start channel numbers */
284#define MLXPLAT_CPLD_CH1 2
285#define MLXPLAT_CPLD_CH2 10
286#define MLXPLAT_CPLD_CH3 18
287#define MLXPLAT_CPLD_CH2_ETH_MODULAR 3
288#define MLXPLAT_CPLD_CH3_ETH_MODULAR 43
289#define MLXPLAT_CPLD_CH4_ETH_MODULAR 51
290#define MLXPLAT_CPLD_CH2_RACK_SWITCH 18
291#define MLXPLAT_CPLD_CH2_NG800 34
292
293/* Number of LPC attached MUX platform devices */
294#define MLXPLAT_CPLD_LPC_MUX_DEVS 4
295
296/* Hotplug devices adapter numbers */
297#define MLXPLAT_CPLD_NR_NONE -1
298#define MLXPLAT_CPLD_PSU_DEFAULT_NR 10
299#define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4
300#define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11
301#define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12
302#define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13
303#define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14
304#define MLXPLAT_CPLD_NR_ASIC 3
305#define MLXPLAT_CPLD_NR_LC_BASE 34
306
307#define MLXPLAT_CPLD_NR_LC_SET(nr) (MLXPLAT_CPLD_NR_LC_BASE + (nr))
308#define MLXPLAT_CPLD_LC_ADDR 0x32
309
310/* Masks and default values for watchdogs */
311#define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1)
312#define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1))
313
314#define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4)
315#define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0
316#define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1)
317#define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4))
318#define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7))
319#define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7, 0) & ~BIT(6))
320#define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30
321#define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600
322#define MLXPLAT_CPLD_WD_MAX_DEVS 2
323
324#define MLXPLAT_CPLD_LPC_SYSIRQ 17
325
326/* Minimum power required for turning on Ethernet modular system (WATT) */
327#define MLXPLAT_CPLD_ETH_MODULAR_PWR_MIN 50
328
329/* Default value for PWM control register for rack switch system */
330#define MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT 0xf4
331
332#define MLXPLAT_I2C_MAIN_BUS_NOTIFIED 0x01
333#define MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED 0x02
334
335/* Lattice FPGA PCI configuration */
336#define PCI_VENDOR_ID_LATTICE 0x1204
337#define PCI_DEVICE_ID_LATTICE_I2C_BRIDGE 0x9c2f
338#define PCI_DEVICE_ID_LATTICE_JTAG_BRIDGE 0x9c30
339#define PCI_DEVICE_ID_LATTICE_LPC_BRIDGE 0x9c32
340
341/* mlxplat_priv - platform private data
342 * @pdev_i2c - i2c controller platform device
343 * @pdev_mux - array of mux platform devices
344 * @pdev_hotplug - hotplug platform devices
345 * @pdev_led - led platform devices
346 * @pdev_io_regs - register access platform devices
347 * @pdev_fan - FAN platform devices
348 * @pdev_wd - array of watchdog platform devices
349 * @regmap: device register map
350 * @hotplug_resources: system hotplug resources
351 * @hotplug_resources_size: size of system hotplug resources
352 * @hi2c_main_init_status: init status of I2C main bus
353 * @irq_fpga: FPGA IRQ number
354 */
355struct mlxplat_priv {
356 struct platform_device *pdev_i2c;
357 struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS];
358 struct platform_device *pdev_hotplug;
359 struct platform_device *pdev_led;
360 struct platform_device *pdev_io_regs;
361 struct platform_device *pdev_fan;
362 struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS];
363 void *regmap;
364 struct resource *hotplug_resources;
365 unsigned int hotplug_resources_size;
366 u8 i2c_main_init_status;
367 int irq_fpga;
368};
369
370static struct platform_device *mlxplat_dev;
371static int mlxplat_i2c_main_completion_notify(void *handle, int id);
372static void __iomem *i2c_bridge_addr, *jtag_bridge_addr;
373
374/* Regions for LPC I2C controller and LPC base register space */
375static const struct resource mlxplat_lpc_resources[] = {
376 [0] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_I2C_BASE_ADRR,
377 MLXPLAT_CPLD_LPC_IO_RANGE,
378 "mlxplat_cpld_lpc_i2c_ctrl", IORESOURCE_IO),
379 [1] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_REG_BASE_ADRR,
380 MLXPLAT_CPLD_LPC_IO_RANGE,
381 "mlxplat_cpld_lpc_regs",
382 IORESOURCE_IO),
383};
384
385/* Platform systems default i2c data */
386static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_default_data = {
387 .completion_notify = mlxplat_i2c_main_completion_notify,
388};
389
390/* Platform i2c next generation systems data */
391static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = {
392 {
393 .reg = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
394 .mask = MLXPLAT_CPLD_I2C_CAP_MASK,
395 .bit = MLXPLAT_CPLD_I2C_CAP_BIT,
396 },
397};
398
399static struct mlxreg_core_item mlxplat_mlxcpld_i2c_ng_items[] = {
400 {
401 .data = mlxplat_mlxcpld_i2c_ng_items_data,
402 },
403};
404
405/* Platform next generation systems i2c data */
406static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = {
407 .items = mlxplat_mlxcpld_i2c_ng_items,
408 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
409 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX,
410 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET,
411 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_I2C,
412 .completion_notify = mlxplat_i2c_main_completion_notify,
413};
414
415/* Platform default channels */
416static const int mlxplat_default_channels[][MLXPLAT_CPLD_GRP_CHNL_NUM] = {
417 {
418 MLXPLAT_CPLD_CH1, MLXPLAT_CPLD_CH1 + 1, MLXPLAT_CPLD_CH1 + 2,
419 MLXPLAT_CPLD_CH1 + 3, MLXPLAT_CPLD_CH1 + 4, MLXPLAT_CPLD_CH1 +
420 5, MLXPLAT_CPLD_CH1 + 6, MLXPLAT_CPLD_CH1 + 7
421 },
422 {
423 MLXPLAT_CPLD_CH2, MLXPLAT_CPLD_CH2 + 1, MLXPLAT_CPLD_CH2 + 2,
424 MLXPLAT_CPLD_CH2 + 3, MLXPLAT_CPLD_CH2 + 4, MLXPLAT_CPLD_CH2 +
425 5, MLXPLAT_CPLD_CH2 + 6, MLXPLAT_CPLD_CH2 + 7
426 },
427};
428
429/* Platform channels for MSN21xx system family */
430static const int mlxplat_msn21xx_channels[] = { 1, 2, 3, 4, 5, 6, 7, 8 };
431
432/* Platform mux data */
433static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = {
434 {
435 .parent = 1,
436 .base_nr = MLXPLAT_CPLD_CH1,
437 .write_only = 1,
438 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
439 .reg_size = 1,
440 .idle_in_use = 1,
441 },
442 {
443 .parent = 1,
444 .base_nr = MLXPLAT_CPLD_CH2,
445 .write_only = 1,
446 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
447 .reg_size = 1,
448 .idle_in_use = 1,
449 },
450
451};
452
453/* Platform mux configuration variables */
454static int mlxplat_max_adap_num;
455static int mlxplat_mux_num;
456static struct i2c_mux_reg_platform_data *mlxplat_mux_data;
457static struct notifier_block *mlxplat_reboot_nb;
458
459/* Platform extended mux data */
460static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = {
461 {
462 .parent = 1,
463 .base_nr = MLXPLAT_CPLD_CH1,
464 .write_only = 1,
465 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
466 .reg_size = 1,
467 .idle_in_use = 1,
468 },
469 {
470 .parent = 1,
471 .base_nr = MLXPLAT_CPLD_CH2,
472 .write_only = 1,
473 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3,
474 .reg_size = 1,
475 .idle_in_use = 1,
476 },
477 {
478 .parent = 1,
479 .base_nr = MLXPLAT_CPLD_CH3,
480 .write_only = 1,
481 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
482 .reg_size = 1,
483 .idle_in_use = 1,
484 },
485
486};
487
488/* Platform channels for modular system family */
489static const int mlxplat_modular_upper_channel[] = { 1 };
490static const int mlxplat_modular_channels[] = {
491 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
492 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37,
493 38, 39, 40
494};
495
496/* Platform modular mux data */
497static struct i2c_mux_reg_platform_data mlxplat_modular_mux_data[] = {
498 {
499 .parent = 1,
500 .base_nr = MLXPLAT_CPLD_CH1,
501 .write_only = 1,
502 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG4,
503 .reg_size = 1,
504 .idle_in_use = 1,
505 .values = mlxplat_modular_upper_channel,
506 .n_values = ARRAY_SIZE(mlxplat_modular_upper_channel),
507 },
508 {
509 .parent = 1,
510 .base_nr = MLXPLAT_CPLD_CH2_ETH_MODULAR,
511 .write_only = 1,
512 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
513 .reg_size = 1,
514 .idle_in_use = 1,
515 .values = mlxplat_modular_channels,
516 .n_values = ARRAY_SIZE(mlxplat_modular_channels),
517 },
518 {
519 .parent = MLXPLAT_CPLD_CH1,
520 .base_nr = MLXPLAT_CPLD_CH3_ETH_MODULAR,
521 .write_only = 1,
522 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3,
523 .reg_size = 1,
524 .idle_in_use = 1,
525 .values = mlxplat_msn21xx_channels,
526 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels),
527 },
528 {
529 .parent = 1,
530 .base_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR,
531 .write_only = 1,
532 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
533 .reg_size = 1,
534 .idle_in_use = 1,
535 .values = mlxplat_msn21xx_channels,
536 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels),
537 },
538};
539
540/* Platform channels for rack switch system family */
541static const int mlxplat_rack_switch_channels[] = {
542 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
543};
544
545/* Platform rack switch mux data */
546static struct i2c_mux_reg_platform_data mlxplat_rack_switch_mux_data[] = {
547 {
548 .parent = 1,
549 .base_nr = MLXPLAT_CPLD_CH1,
550 .write_only = 1,
551 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
552 .reg_size = 1,
553 .idle_in_use = 1,
554 .values = mlxplat_rack_switch_channels,
555 .n_values = ARRAY_SIZE(mlxplat_rack_switch_channels),
556 },
557 {
558 .parent = 1,
559 .base_nr = MLXPLAT_CPLD_CH2_RACK_SWITCH,
560 .write_only = 1,
561 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
562 .reg_size = 1,
563 .idle_in_use = 1,
564 .values = mlxplat_msn21xx_channels,
565 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels),
566 },
567
568};
569
570/* Platform channels for ng800 system family */
571static const int mlxplat_ng800_channels[] = {
572 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
573 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32
574};
575
576/* Platform ng800 mux data */
577static struct i2c_mux_reg_platform_data mlxplat_ng800_mux_data[] = {
578 {
579 .parent = 1,
580 .base_nr = MLXPLAT_CPLD_CH1,
581 .write_only = 1,
582 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
583 .reg_size = 1,
584 .idle_in_use = 1,
585 .values = mlxplat_ng800_channels,
586 .n_values = ARRAY_SIZE(mlxplat_ng800_channels),
587 },
588 {
589 .parent = 1,
590 .base_nr = MLXPLAT_CPLD_CH2_NG800,
591 .write_only = 1,
592 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
593 .reg_size = 1,
594 .idle_in_use = 1,
595 .values = mlxplat_msn21xx_channels,
596 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels),
597 },
598
599};
600
601/* Platform hotplug devices */
602static struct i2c_board_info mlxplat_mlxcpld_pwr[] = {
603 {
604 I2C_BOARD_INFO("dps460", 0x59),
605 },
606 {
607 I2C_BOARD_INFO("dps460", 0x58),
608 },
609};
610
611static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = {
612 {
613 I2C_BOARD_INFO("dps460", 0x5b),
614 },
615 {
616 I2C_BOARD_INFO("dps460", 0x5a),
617 },
618};
619
620static struct i2c_board_info mlxplat_mlxcpld_pwr_ng800[] = {
621 {
622 I2C_BOARD_INFO("dps460", 0x59),
623 },
624 {
625 I2C_BOARD_INFO("dps460", 0x5a),
626 },
627};
628
629static struct i2c_board_info mlxplat_mlxcpld_fan[] = {
630 {
631 I2C_BOARD_INFO("24c32", 0x50),
632 },
633 {
634 I2C_BOARD_INFO("24c32", 0x50),
635 },
636 {
637 I2C_BOARD_INFO("24c32", 0x50),
638 },
639 {
640 I2C_BOARD_INFO("24c32", 0x50),
641 },
642};
643
644/* Platform hotplug comex carrier system family data */
645static struct mlxreg_core_data mlxplat_mlxcpld_comex_psu_items_data[] = {
646 {
647 .label = "psu1",
648 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
649 .mask = BIT(0),
650 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
651 },
652 {
653 .label = "psu2",
654 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
655 .mask = BIT(1),
656 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
657 },
658};
659
660/* Platform hotplug default data */
661static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = {
662 {
663 .label = "psu1",
664 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
665 .mask = BIT(0),
666 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
667 },
668 {
669 .label = "psu2",
670 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
671 .mask = BIT(1),
672 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
673 },
674};
675
676static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = {
677 {
678 .label = "pwr1",
679 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
680 .mask = BIT(0),
681 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
682 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR,
683 },
684 {
685 .label = "pwr2",
686 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
687 .mask = BIT(1),
688 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
689 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR,
690 },
691};
692
693static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_wc_items_data[] = {
694 {
695 .label = "pwr1",
696 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
697 .mask = BIT(0),
698 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
699 },
700 {
701 .label = "pwr2",
702 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
703 .mask = BIT(1),
704 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
705 },
706};
707
708static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_ng800_items_data[] = {
709 {
710 .label = "pwr1",
711 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
712 .mask = BIT(0),
713 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[0],
714 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
715 },
716 {
717 .label = "pwr2",
718 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
719 .mask = BIT(1),
720 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[1],
721 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
722 },
723};
724
725static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = {
726 {
727 .label = "fan1",
728 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
729 .mask = BIT(0),
730 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[0],
731 .hpdev.nr = MLXPLAT_CPLD_FAN1_DEFAULT_NR,
732 },
733 {
734 .label = "fan2",
735 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
736 .mask = BIT(1),
737 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[1],
738 .hpdev.nr = MLXPLAT_CPLD_FAN2_DEFAULT_NR,
739 },
740 {
741 .label = "fan3",
742 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
743 .mask = BIT(2),
744 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[2],
745 .hpdev.nr = MLXPLAT_CPLD_FAN3_DEFAULT_NR,
746 },
747 {
748 .label = "fan4",
749 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
750 .mask = BIT(3),
751 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[3],
752 .hpdev.nr = MLXPLAT_CPLD_FAN4_DEFAULT_NR,
753 },
754};
755
756static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = {
757 {
758 .label = "asic1",
759 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
760 .mask = MLXPLAT_CPLD_ASIC_MASK,
761 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
762 },
763};
764
765static struct mlxreg_core_data mlxplat_mlxcpld_default_asic2_items_data[] = {
766 {
767 .label = "asic2",
768 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,
769 .mask = MLXPLAT_CPLD_ASIC_MASK,
770 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
771 },
772};
773
774static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = {
775 {
776 .data = mlxplat_mlxcpld_default_psu_items_data,
777 .aggr_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF,
778 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
779 .mask = MLXPLAT_CPLD_PSU_MASK,
780 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data),
781 .inversed = 1,
782 .health = false,
783 },
784 {
785 .data = mlxplat_mlxcpld_default_pwr_items_data,
786 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF,
787 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
788 .mask = MLXPLAT_CPLD_PWR_MASK,
789 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data),
790 .inversed = 0,
791 .health = false,
792 },
793 {
794 .data = mlxplat_mlxcpld_default_fan_items_data,
795 .aggr_mask = MLXPLAT_CPLD_AGGR_FAN_MASK_DEF,
796 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
797 .mask = MLXPLAT_CPLD_FAN_MASK,
798 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data),
799 .inversed = 1,
800 .health = false,
801 },
802 {
803 .data = mlxplat_mlxcpld_default_asic_items_data,
804 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
805 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
806 .mask = MLXPLAT_CPLD_ASIC_MASK,
807 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
808 .inversed = 0,
809 .health = true,
810 },
811};
812
813static struct mlxreg_core_item mlxplat_mlxcpld_comex_items[] = {
814 {
815 .data = mlxplat_mlxcpld_comex_psu_items_data,
816 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
817 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
818 .mask = MLXPLAT_CPLD_PSU_MASK,
819 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data),
820 .inversed = 1,
821 .health = false,
822 },
823 {
824 .data = mlxplat_mlxcpld_default_pwr_items_data,
825 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
826 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
827 .mask = MLXPLAT_CPLD_PWR_MASK,
828 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data),
829 .inversed = 0,
830 .health = false,
831 },
832 {
833 .data = mlxplat_mlxcpld_default_fan_items_data,
834 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
835 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
836 .mask = MLXPLAT_CPLD_FAN_MASK,
837 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data),
838 .inversed = 1,
839 .health = false,
840 },
841 {
842 .data = mlxplat_mlxcpld_default_asic_items_data,
843 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
844 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
845 .mask = MLXPLAT_CPLD_ASIC_MASK,
846 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
847 .inversed = 0,
848 .health = true,
849 },
850};
851
852static
853struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = {
854 .items = mlxplat_mlxcpld_default_items,
855 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_items),
856 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
857 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
858 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
859 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
860};
861
862static struct mlxreg_core_item mlxplat_mlxcpld_default_wc_items[] = {
863 {
864 .data = mlxplat_mlxcpld_comex_psu_items_data,
865 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
866 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
867 .mask = MLXPLAT_CPLD_PSU_MASK,
868 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data),
869 .inversed = 1,
870 .health = false,
871 },
872 {
873 .data = mlxplat_mlxcpld_default_pwr_wc_items_data,
874 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER,
875 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
876 .mask = MLXPLAT_CPLD_PWR_MASK,
877 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data),
878 .inversed = 0,
879 .health = false,
880 },
881 {
882 .data = mlxplat_mlxcpld_default_asic_items_data,
883 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
884 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
885 .mask = MLXPLAT_CPLD_ASIC_MASK,
886 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
887 .inversed = 0,
888 .health = true,
889 },
890};
891
892static
893struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_wc_data = {
894 .items = mlxplat_mlxcpld_default_wc_items,
895 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_wc_items),
896 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
897 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
898 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
899 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
900};
901
902static
903struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = {
904 .items = mlxplat_mlxcpld_comex_items,
905 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_items),
906 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
907 .mask = MLXPLAT_CPLD_AGGR_MASK_CARR_DEF,
908 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET,
909 .mask_low = MLXPLAT_CPLD_LOW_AGGRCX_MASK,
910};
911
912static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = {
913 {
914 .label = "pwr1",
915 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
916 .mask = BIT(0),
917 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
918 },
919 {
920 .label = "pwr2",
921 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
922 .mask = BIT(1),
923 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
924 },
925};
926
927/* Platform hotplug MSN21xx system family data */
928static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = {
929 {
930 .data = mlxplat_mlxcpld_msn21xx_pwr_items_data,
931 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF,
932 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
933 .mask = MLXPLAT_CPLD_PWR_MASK,
934 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_pwr_items_data),
935 .inversed = 0,
936 .health = false,
937 },
938 {
939 .data = mlxplat_mlxcpld_default_asic_items_data,
940 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
941 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
942 .mask = MLXPLAT_CPLD_ASIC_MASK,
943 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
944 .inversed = 0,
945 .health = true,
946 },
947};
948
949static
950struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = {
951 .items = mlxplat_mlxcpld_msn21xx_items,
952 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items),
953 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
954 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
955 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
956 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
957};
958
959/* Platform hotplug msn274x system family data */
960static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_psu_items_data[] = {
961 {
962 .label = "psu1",
963 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
964 .mask = BIT(0),
965 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
966 },
967 {
968 .label = "psu2",
969 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
970 .mask = BIT(1),
971 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
972 },
973};
974
975static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_pwr_items_data[] = {
976 {
977 .label = "pwr1",
978 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
979 .mask = BIT(0),
980 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
981 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
982 },
983 {
984 .label = "pwr2",
985 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
986 .mask = BIT(1),
987 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
988 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
989 },
990};
991
992static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_fan_items_data[] = {
993 {
994 .label = "fan1",
995 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
996 .mask = BIT(0),
997 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
998 },
999 {
1000 .label = "fan2",
1001 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1002 .mask = BIT(1),
1003 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1004 },
1005 {
1006 .label = "fan3",
1007 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1008 .mask = BIT(2),
1009 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1010 },
1011 {
1012 .label = "fan4",
1013 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1014 .mask = BIT(3),
1015 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1016 },
1017};
1018
1019static struct mlxreg_core_item mlxplat_mlxcpld_msn274x_items[] = {
1020 {
1021 .data = mlxplat_mlxcpld_msn274x_psu_items_data,
1022 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1023 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1024 .mask = MLXPLAT_CPLD_PSU_MASK,
1025 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_psu_items_data),
1026 .inversed = 1,
1027 .health = false,
1028 },
1029 {
1030 .data = mlxplat_mlxcpld_default_ng_pwr_items_data,
1031 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1032 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1033 .mask = MLXPLAT_CPLD_PWR_MASK,
1034 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data),
1035 .inversed = 0,
1036 .health = false,
1037 },
1038 {
1039 .data = mlxplat_mlxcpld_msn274x_fan_items_data,
1040 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1041 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1042 .mask = MLXPLAT_CPLD_FAN_MASK,
1043 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_fan_items_data),
1044 .inversed = 1,
1045 .health = false,
1046 },
1047 {
1048 .data = mlxplat_mlxcpld_default_asic_items_data,
1049 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1050 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1051 .mask = MLXPLAT_CPLD_ASIC_MASK,
1052 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
1053 .inversed = 0,
1054 .health = true,
1055 },
1056};
1057
1058static
1059struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn274x_data = {
1060 .items = mlxplat_mlxcpld_msn274x_items,
1061 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_items),
1062 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
1063 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1064 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
1065 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
1066};
1067
1068/* Platform hotplug MSN201x system family data */
1069static struct mlxreg_core_data mlxplat_mlxcpld_msn201x_pwr_items_data[] = {
1070 {
1071 .label = "pwr1",
1072 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1073 .mask = BIT(0),
1074 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1075 },
1076 {
1077 .label = "pwr2",
1078 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1079 .mask = BIT(1),
1080 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1081 },
1082};
1083
1084static struct mlxreg_core_item mlxplat_mlxcpld_msn201x_items[] = {
1085 {
1086 .data = mlxplat_mlxcpld_msn201x_pwr_items_data,
1087 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF,
1088 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1089 .mask = MLXPLAT_CPLD_PWR_MASK,
1090 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_pwr_items_data),
1091 .inversed = 0,
1092 .health = false,
1093 },
1094 {
1095 .data = mlxplat_mlxcpld_default_asic_items_data,
1096 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF,
1097 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1098 .mask = MLXPLAT_CPLD_ASIC_MASK,
1099 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
1100 .inversed = 0,
1101 .health = true,
1102 },
1103};
1104
1105static
1106struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn201x_data = {
1107 .items = mlxplat_mlxcpld_msn201x_items,
1108 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_items),
1109 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
1110 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
1111 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
1112 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
1113};
1114
1115/* Platform hotplug next generation system family data */
1116static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_psu_items_data[] = {
1117 {
1118 .label = "psu1",
1119 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1120 .mask = BIT(0),
1121 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1122 },
1123 {
1124 .label = "psu2",
1125 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1126 .mask = BIT(1),
1127 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1128 },
1129};
1130
1131static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = {
1132 {
1133 .label = "fan1",
1134 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1135 .mask = BIT(0),
1136 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1137 .bit = BIT(0),
1138 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1139 },
1140 {
1141 .label = "fan2",
1142 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1143 .mask = BIT(1),
1144 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1145 .bit = BIT(1),
1146 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1147 },
1148 {
1149 .label = "fan3",
1150 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1151 .mask = BIT(2),
1152 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1153 .bit = BIT(2),
1154 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1155 },
1156 {
1157 .label = "fan4",
1158 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1159 .mask = BIT(3),
1160 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1161 .bit = BIT(3),
1162 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1163 },
1164 {
1165 .label = "fan5",
1166 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1167 .mask = BIT(4),
1168 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1169 .bit = BIT(4),
1170 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1171 },
1172 {
1173 .label = "fan6",
1174 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1175 .mask = BIT(5),
1176 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1177 .bit = BIT(5),
1178 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1179 },
1180 {
1181 .label = "fan7",
1182 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1183 .mask = BIT(6),
1184 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
1185 .bit = BIT(6),
1186 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1187 },
1188};
1189
1190static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = {
1191 {
1192 .data = mlxplat_mlxcpld_default_ng_psu_items_data,
1193 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1194 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1195 .mask = MLXPLAT_CPLD_PSU_MASK,
1196 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data),
1197 .inversed = 1,
1198 .health = false,
1199 },
1200 {
1201 .data = mlxplat_mlxcpld_default_ng_pwr_items_data,
1202 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1203 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1204 .mask = MLXPLAT_CPLD_PWR_MASK,
1205 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data),
1206 .inversed = 0,
1207 .health = false,
1208 },
1209 {
1210 .data = mlxplat_mlxcpld_default_ng_fan_items_data,
1211 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1212 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1213 .mask = MLXPLAT_CPLD_FAN_NG_MASK,
1214 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
1215 .inversed = 1,
1216 .health = false,
1217 },
1218 {
1219 .data = mlxplat_mlxcpld_default_asic_items_data,
1220 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1221 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1222 .mask = MLXPLAT_CPLD_ASIC_MASK,
1223 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
1224 .inversed = 0,
1225 .health = true,
1226 },
1227};
1228
1229static
1230struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_ng_data = {
1231 .items = mlxplat_mlxcpld_default_ng_items,
1232 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_items),
1233 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
1234 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
1235 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
1236 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
1237};
1238
1239/* Platform hotplug extended system family data */
1240static struct mlxreg_core_data mlxplat_mlxcpld_ext_psu_items_data[] = {
1241 {
1242 .label = "psu1",
1243 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1244 .mask = BIT(0),
1245 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1246 },
1247 {
1248 .label = "psu2",
1249 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1250 .mask = BIT(1),
1251 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1252 },
1253 {
1254 .label = "psu3",
1255 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1256 .mask = BIT(2),
1257 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1258 },
1259 {
1260 .label = "psu4",
1261 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1262 .mask = BIT(3),
1263 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1264 },
1265};
1266
1267static struct mlxreg_core_data mlxplat_mlxcpld_ext_pwr_items_data[] = {
1268 {
1269 .label = "pwr1",
1270 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1271 .mask = BIT(0),
1272 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
1273 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
1274 },
1275 {
1276 .label = "pwr2",
1277 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1278 .mask = BIT(1),
1279 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
1280 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
1281 },
1282 {
1283 .label = "pwr3",
1284 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1285 .mask = BIT(2),
1286 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0],
1287 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
1288 },
1289 {
1290 .label = "pwr4",
1291 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1292 .mask = BIT(3),
1293 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1],
1294 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
1295 },
1296};
1297
1298static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = {
1299 {
1300 .data = mlxplat_mlxcpld_ext_psu_items_data,
1301 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1302 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1303 .mask = MLXPLAT_CPLD_PSU_EXT_MASK,
1304 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
1305 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data),
1306 .inversed = 1,
1307 .health = false,
1308 },
1309 {
1310 .data = mlxplat_mlxcpld_ext_pwr_items_data,
1311 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1312 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1313 .mask = MLXPLAT_CPLD_PWR_EXT_MASK,
1314 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
1315 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data),
1316 .inversed = 0,
1317 .health = false,
1318 },
1319 {
1320 .data = mlxplat_mlxcpld_default_ng_fan_items_data,
1321 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1322 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1323 .mask = MLXPLAT_CPLD_FAN_NG_MASK,
1324 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
1325 .inversed = 1,
1326 .health = false,
1327 },
1328 {
1329 .data = mlxplat_mlxcpld_default_asic_items_data,
1330 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1331 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1332 .mask = MLXPLAT_CPLD_ASIC_MASK,
1333 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
1334 .inversed = 0,
1335 .health = true,
1336 },
1337 {
1338 .data = mlxplat_mlxcpld_default_asic2_items_data,
1339 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1340 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,
1341 .mask = MLXPLAT_CPLD_ASIC_MASK,
1342 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic2_items_data),
1343 .inversed = 0,
1344 .health = true,
1345 }
1346};
1347
1348static struct mlxreg_core_item mlxplat_mlxcpld_ng800_items[] = {
1349 {
1350 .data = mlxplat_mlxcpld_default_ng_psu_items_data,
1351 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1352 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1353 .mask = MLXPLAT_CPLD_PSU_EXT_MASK,
1354 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
1355 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data),
1356 .inversed = 1,
1357 .health = false,
1358 },
1359 {
1360 .data = mlxplat_mlxcpld_default_pwr_ng800_items_data,
1361 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1362 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1363 .mask = MLXPLAT_CPLD_PWR_EXT_MASK,
1364 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
1365 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_ng800_items_data),
1366 .inversed = 0,
1367 .health = false,
1368 },
1369 {
1370 .data = mlxplat_mlxcpld_default_ng_fan_items_data,
1371 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1372 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1373 .mask = MLXPLAT_CPLD_FAN_NG_MASK,
1374 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
1375 .inversed = 1,
1376 .health = false,
1377 },
1378 {
1379 .data = mlxplat_mlxcpld_default_asic_items_data,
1380 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1381 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1382 .mask = MLXPLAT_CPLD_ASIC_MASK,
1383 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
1384 .inversed = 0,
1385 .health = true,
1386 },
1387};
1388
1389static
1390struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = {
1391 .items = mlxplat_mlxcpld_ext_items,
1392 .counter = ARRAY_SIZE(mlxplat_mlxcpld_ext_items),
1393 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
1394 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
1395 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
1396 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2,
1397};
1398
1399static
1400struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_data = {
1401 .items = mlxplat_mlxcpld_ng800_items,
1402 .counter = ARRAY_SIZE(mlxplat_mlxcpld_ng800_items),
1403 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
1404 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
1405 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
1406 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2,
1407};
1408
1409static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = {
1410 {
1411 .label = "pwr1",
1412 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1413 .mask = BIT(0),
1414 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
1415 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
1416 },
1417 {
1418 .label = "pwr2",
1419 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1420 .mask = BIT(1),
1421 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
1422 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
1423 },
1424 {
1425 .label = "pwr3",
1426 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1427 .mask = BIT(2),
1428 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0],
1429 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
1430 },
1431 {
1432 .label = "pwr4",
1433 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1434 .mask = BIT(3),
1435 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1],
1436 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
1437 },
1438};
1439
1440static
1441struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_lc_act = {
1442 .irq = MLXPLAT_CPLD_LPC_SYSIRQ,
1443};
1444
1445static struct mlxreg_core_data mlxplat_mlxcpld_modular_asic_items_data[] = {
1446 {
1447 .label = "asic1",
1448 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1449 .mask = MLXPLAT_CPLD_ASIC_MASK,
1450 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
1451 },
1452};
1453
1454static struct i2c_board_info mlxplat_mlxcpld_lc_i2c_dev[] = {
1455 {
1456 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1457 .platform_data = &mlxplat_mlxcpld_lc_act,
1458 },
1459 {
1460 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1461 .platform_data = &mlxplat_mlxcpld_lc_act,
1462 },
1463 {
1464 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1465 .platform_data = &mlxplat_mlxcpld_lc_act,
1466 },
1467 {
1468 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1469 .platform_data = &mlxplat_mlxcpld_lc_act,
1470 },
1471 {
1472 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1473 .platform_data = &mlxplat_mlxcpld_lc_act,
1474 },
1475 {
1476 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1477 .platform_data = &mlxplat_mlxcpld_lc_act,
1478 },
1479 {
1480 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1481 .platform_data = &mlxplat_mlxcpld_lc_act,
1482 },
1483 {
1484 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR),
1485 .platform_data = &mlxplat_mlxcpld_lc_act,
1486 },
1487};
1488
1489static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_modular_lc_notifier[] = {
1490 {
1491 .identity = "lc1",
1492 },
1493 {
1494 .identity = "lc2",
1495 },
1496 {
1497 .identity = "lc3",
1498 },
1499 {
1500 .identity = "lc4",
1501 },
1502 {
1503 .identity = "lc5",
1504 },
1505 {
1506 .identity = "lc6",
1507 },
1508 {
1509 .identity = "lc7",
1510 },
1511 {
1512 .identity = "lc8",
1513 },
1514};
1515
1516static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = {
1517 {
1518 .label = "lc1_present",
1519 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1520 .mask = BIT(0),
1521 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0],
1522 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0),
1523 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1524 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0],
1525 .slot = 1,
1526 },
1527 {
1528 .label = "lc2_present",
1529 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1530 .mask = BIT(1),
1531 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1],
1532 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1),
1533 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1534 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1],
1535 .slot = 2,
1536 },
1537 {
1538 .label = "lc3_present",
1539 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1540 .mask = BIT(2),
1541 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2],
1542 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2),
1543 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1544 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2],
1545 .slot = 3,
1546 },
1547 {
1548 .label = "lc4_present",
1549 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1550 .mask = BIT(3),
1551 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3],
1552 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3),
1553 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1554 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3],
1555 .slot = 4,
1556 },
1557 {
1558 .label = "lc5_present",
1559 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1560 .mask = BIT(4),
1561 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4],
1562 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4),
1563 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1564 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4],
1565 .slot = 5,
1566 },
1567 {
1568 .label = "lc6_present",
1569 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1570 .mask = BIT(5),
1571 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5],
1572 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5),
1573 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1574 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5],
1575 .slot = 6,
1576 },
1577 {
1578 .label = "lc7_present",
1579 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1580 .mask = BIT(6),
1581 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6],
1582 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6),
1583 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1584 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6],
1585 .slot = 7,
1586 },
1587 {
1588 .label = "lc8_present",
1589 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
1590 .mask = BIT(7),
1591 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1592 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1593 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1594 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1595 .slot = 8,
1596 },
1597};
1598
1599static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = {
1600 {
1601 .label = "lc1_verified",
1602 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1603 .mask = BIT(0),
1604 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1605 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1606 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
1607 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
1608 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0],
1609 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0),
1610 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION,
1611 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0],
1612 .slot = 1,
1613 },
1614 {
1615 .label = "lc2_verified",
1616 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1617 .mask = BIT(1),
1618 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1619 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1620 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
1621 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
1622 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1],
1623 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1),
1624 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION,
1625 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1],
1626 .slot = 2,
1627 },
1628 {
1629 .label = "lc3_verified",
1630 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1631 .mask = BIT(2),
1632 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1633 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1634 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
1635 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
1636 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2],
1637 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2),
1638 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION,
1639 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2],
1640 .slot = 3,
1641 },
1642 {
1643 .label = "lc4_verified",
1644 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1645 .mask = BIT(3),
1646 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1647 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1648 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
1649 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
1650 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3],
1651 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3),
1652 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION,
1653 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3],
1654 .slot = 4,
1655 },
1656 {
1657 .label = "lc5_verified",
1658 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1659 .mask = BIT(4),
1660 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1661 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1662 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
1663 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
1664 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4],
1665 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4),
1666 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION,
1667 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4],
1668 .slot = 5,
1669 },
1670 {
1671 .label = "lc6_verified",
1672 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1673 .mask = BIT(5),
1674 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1675 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1676 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
1677 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
1678 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5],
1679 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5),
1680 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION,
1681 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5],
1682 .slot = 6,
1683 },
1684 {
1685 .label = "lc7_verified",
1686 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1687 .mask = BIT(6),
1688 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1689 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1690 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
1691 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
1692 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6],
1693 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6),
1694 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION,
1695 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6],
1696 .slot = 7,
1697 },
1698 {
1699 .label = "lc8_verified",
1700 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
1701 .mask = BIT(7),
1702 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1703 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1704 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
1705 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
1706 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1707 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1708 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION,
1709 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1710 .slot = 8,
1711 },
1712};
1713
1714static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = {
1715 {
1716 .label = "lc1_powered",
1717 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1718 .mask = BIT(0),
1719 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0],
1720 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0),
1721 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1722 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0],
1723 .slot = 1,
1724 },
1725 {
1726 .label = "lc2_powered",
1727 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1728 .mask = BIT(1),
1729 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1],
1730 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1),
1731 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1732 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1],
1733 .slot = 2,
1734 },
1735 {
1736 .label = "lc3_powered",
1737 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1738 .mask = BIT(2),
1739 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2],
1740 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2),
1741 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1742 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2],
1743 .slot = 3,
1744 },
1745 {
1746 .label = "lc4_powered",
1747 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1748 .mask = BIT(3),
1749 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3],
1750 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3),
1751 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1752 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3],
1753 .slot = 4,
1754 },
1755 {
1756 .label = "lc5_powered",
1757 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1758 .mask = BIT(4),
1759 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4],
1760 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4),
1761 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1762 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4],
1763 .slot = 5,
1764 },
1765 {
1766 .label = "lc6_powered",
1767 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1768 .mask = BIT(5),
1769 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5],
1770 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5),
1771 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1772 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5],
1773 .slot = 6,
1774 },
1775 {
1776 .label = "lc7_powered",
1777 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1778 .mask = BIT(6),
1779 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6],
1780 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6),
1781 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1782 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6],
1783 .slot = 7,
1784 },
1785 {
1786 .label = "lc8_powered",
1787 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
1788 .mask = BIT(7),
1789 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1790 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1791 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1792 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1793 .slot = 8,
1794 },
1795};
1796
1797static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = {
1798 {
1799 .label = "lc1_ready",
1800 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1801 .mask = BIT(0),
1802 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0],
1803 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0),
1804 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1805 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0],
1806 .slot = 1,
1807 },
1808 {
1809 .label = "lc2_ready",
1810 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1811 .mask = BIT(1),
1812 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1],
1813 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1),
1814 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1815 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1],
1816 .slot = 2,
1817 },
1818 {
1819 .label = "lc3_ready",
1820 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1821 .mask = BIT(2),
1822 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2],
1823 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2),
1824 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1825 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2],
1826 .slot = 3,
1827 },
1828 {
1829 .label = "lc4_ready",
1830 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1831 .mask = BIT(3),
1832 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3],
1833 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3),
1834 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1835 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3],
1836 .slot = 4,
1837 },
1838 {
1839 .label = "lc5_ready",
1840 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1841 .mask = BIT(4),
1842 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4],
1843 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4),
1844 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1845 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4],
1846 .slot = 5,
1847 },
1848 {
1849 .label = "lc6_ready",
1850 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1851 .mask = BIT(5),
1852 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5],
1853 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5),
1854 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1855 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5],
1856 .slot = 6,
1857 },
1858 {
1859 .label = "lc7_ready",
1860 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1861 .mask = BIT(6),
1862 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6],
1863 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6),
1864 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1865 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6],
1866 .slot = 7,
1867 },
1868 {
1869 .label = "lc8_ready",
1870 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
1871 .mask = BIT(7),
1872 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1873 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1874 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1875 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1876 .slot = 8,
1877 },
1878};
1879
1880static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = {
1881 {
1882 .label = "lc1_synced",
1883 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1884 .mask = BIT(0),
1885 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0],
1886 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0),
1887 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1888 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0],
1889 .slot = 1,
1890 },
1891 {
1892 .label = "lc2_synced",
1893 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1894 .mask = BIT(1),
1895 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1],
1896 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1),
1897 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1898 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1],
1899 .slot = 2,
1900 },
1901 {
1902 .label = "lc3_synced",
1903 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1904 .mask = BIT(2),
1905 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2],
1906 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2),
1907 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1908 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2],
1909 .slot = 3,
1910 },
1911 {
1912 .label = "lc4_synced",
1913 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1914 .mask = BIT(3),
1915 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3],
1916 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3),
1917 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1918 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3],
1919 .slot = 4,
1920 },
1921 {
1922 .label = "lc5_synced",
1923 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1924 .mask = BIT(4),
1925 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4],
1926 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4),
1927 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1928 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4],
1929 .slot = 5,
1930 },
1931 {
1932 .label = "lc6_synced",
1933 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1934 .mask = BIT(5),
1935 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5],
1936 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5),
1937 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1938 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5],
1939 .slot = 6,
1940 },
1941 {
1942 .label = "lc7_synced",
1943 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1944 .mask = BIT(6),
1945 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6],
1946 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6),
1947 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1948 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6],
1949 .slot = 7,
1950 },
1951 {
1952 .label = "lc8_synced",
1953 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
1954 .mask = BIT(7),
1955 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
1956 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
1957 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1958 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
1959 .slot = 8,
1960 },
1961};
1962
1963static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = {
1964 {
1965 .label = "lc1_active",
1966 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
1967 .mask = BIT(0),
1968 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0],
1969 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0),
1970 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1971 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0],
1972 .slot = 1,
1973 },
1974 {
1975 .label = "lc2_active",
1976 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
1977 .mask = BIT(1),
1978 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1],
1979 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1),
1980 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1981 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1],
1982 .slot = 2,
1983 },
1984 {
1985 .label = "lc3_active",
1986 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
1987 .mask = BIT(2),
1988 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2],
1989 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2),
1990 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
1991 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2],
1992 .slot = 3,
1993 },
1994 {
1995 .label = "lc4_active",
1996 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
1997 .mask = BIT(3),
1998 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3],
1999 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3),
2000 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
2001 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3],
2002 .slot = 4,
2003 },
2004 {
2005 .label = "lc5_active",
2006 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
2007 .mask = BIT(4),
2008 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4],
2009 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4),
2010 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
2011 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4],
2012 .slot = 5,
2013 },
2014 {
2015 .label = "lc6_active",
2016 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
2017 .mask = BIT(5),
2018 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5],
2019 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5),
2020 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
2021 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5],
2022 .slot = 6,
2023 },
2024 {
2025 .label = "lc7_active",
2026 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
2027 .mask = BIT(6),
2028 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6],
2029 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6),
2030 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
2031 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6],
2032 .slot = 7,
2033 },
2034 {
2035 .label = "lc8_active",
2036 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
2037 .mask = BIT(7),
2038 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
2039 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
2040 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
2041 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
2042 .slot = 8,
2043 },
2044};
2045
2046static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = {
2047 {
2048 .label = "lc1_shutdown",
2049 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2050 .mask = BIT(0),
2051 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0],
2052 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0),
2053 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
2054 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0],
2055 .slot = 1,
2056 },
2057 {
2058 .label = "lc2_shutdown",
2059 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2060 .mask = BIT(1),
2061 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1],
2062 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1),
2063 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
2064 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1],
2065 .slot = 2,
2066 },
2067 {
2068 .label = "lc3_shutdown",
2069 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2070 .mask = BIT(2),
2071 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2],
2072 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2),
2073 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
2074 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2],
2075 .slot = 3,
2076 },
2077 {
2078 .label = "lc4_shutdown",
2079 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2080 .mask = BIT(3),
2081 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3],
2082 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3),
2083 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
2084 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3],
2085 .slot = 4,
2086 },
2087 {
2088 .label = "lc5_shutdown",
2089 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2090 .mask = BIT(4),
2091 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4],
2092 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4),
2093 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
2094 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4],
2095 .slot = 5,
2096 },
2097 {
2098 .label = "lc6_shutdown",
2099 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2100 .mask = BIT(5),
2101 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5],
2102 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5),
2103 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
2104 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5],
2105 .slot = 6,
2106 },
2107 {
2108 .label = "lc7_shutdown",
2109 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2110 .mask = BIT(6),
2111 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6],
2112 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6),
2113 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
2114 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6],
2115 .slot = 7,
2116 },
2117 {
2118 .label = "lc8_shutdown",
2119 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2120 .mask = BIT(7),
2121 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7],
2122 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7),
2123 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
2124 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7],
2125 .slot = 8,
2126 },
2127};
2128
2129static struct mlxreg_core_item mlxplat_mlxcpld_modular_items[] = {
2130 {
2131 .data = mlxplat_mlxcpld_ext_psu_items_data,
2132 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2133 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
2134 .mask = MLXPLAT_CPLD_PSU_EXT_MASK,
2135 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
2136 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data),
2137 .inversed = 1,
2138 .health = false,
2139 },
2140 {
2141 .data = mlxplat_mlxcpld_modular_pwr_items_data,
2142 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2143 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
2144 .mask = MLXPLAT_CPLD_PWR_EXT_MASK,
2145 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
2146 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data),
2147 .inversed = 0,
2148 .health = false,
2149 },
2150 {
2151 .data = mlxplat_mlxcpld_default_ng_fan_items_data,
2152 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2153 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
2154 .mask = MLXPLAT_CPLD_FAN_NG_MASK,
2155 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
2156 .inversed = 1,
2157 .health = false,
2158 },
2159 {
2160 .data = mlxplat_mlxcpld_modular_asic_items_data,
2161 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2162 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
2163 .mask = MLXPLAT_CPLD_ASIC_MASK,
2164 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_asic_items_data),
2165 .inversed = 0,
2166 .health = true,
2167 },
2168 {
2169 .data = mlxplat_mlxcpld_modular_lc_pr_items_data,
2170 .kind = MLXREG_HOTPLUG_LC_PRESENT,
2171 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC,
2172 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET,
2173 .mask = MLXPLAT_CPLD_LPC_LC_MASK,
2174 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pr_items_data),
2175 .inversed = 1,
2176 .health = false,
2177 },
2178 {
2179 .data = mlxplat_mlxcpld_modular_lc_ver_items_data,
2180 .kind = MLXREG_HOTPLUG_LC_VERIFIED,
2181 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC,
2182 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET,
2183 .mask = MLXPLAT_CPLD_LPC_LC_MASK,
2184 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ver_items_data),
2185 .inversed = 0,
2186 .health = false,
2187 },
2188 {
2189 .data = mlxplat_mlxcpld_modular_lc_pg_data,
2190 .kind = MLXREG_HOTPLUG_LC_POWERED,
2191 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC,
2192 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET,
2193 .mask = MLXPLAT_CPLD_LPC_LC_MASK,
2194 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pg_data),
2195 .inversed = 0,
2196 .health = false,
2197 },
2198 {
2199 .data = mlxplat_mlxcpld_modular_lc_ready_data,
2200 .kind = MLXREG_HOTPLUG_LC_READY,
2201 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC,
2202 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET,
2203 .mask = MLXPLAT_CPLD_LPC_LC_MASK,
2204 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ready_data),
2205 .inversed = 0,
2206 .health = false,
2207 },
2208 {
2209 .data = mlxplat_mlxcpld_modular_lc_synced_data,
2210 .kind = MLXREG_HOTPLUG_LC_SYNCED,
2211 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC,
2212 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET,
2213 .mask = MLXPLAT_CPLD_LPC_LC_MASK,
2214 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_synced_data),
2215 .inversed = 0,
2216 .health = false,
2217 },
2218 {
2219 .data = mlxplat_mlxcpld_modular_lc_act_data,
2220 .kind = MLXREG_HOTPLUG_LC_ACTIVE,
2221 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC,
2222 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET,
2223 .mask = MLXPLAT_CPLD_LPC_LC_MASK,
2224 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_act_data),
2225 .inversed = 0,
2226 .health = false,
2227 },
2228 {
2229 .data = mlxplat_mlxcpld_modular_lc_sd_data,
2230 .kind = MLXREG_HOTPLUG_LC_THERMAL,
2231 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC,
2232 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET,
2233 .mask = MLXPLAT_CPLD_LPC_LC_MASK,
2234 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_sd_data),
2235 .inversed = 0,
2236 .health = false,
2237 },
2238};
2239
2240static
2241struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = {
2242 .items = mlxplat_mlxcpld_modular_items,
2243 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_items),
2244 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
2245 .mask = MLXPLAT_CPLD_AGGR_MASK_MODULAR,
2246 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
2247 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
2248};
2249
2250/* Platform hotplug for NVLink blade systems family data */
2251static struct mlxreg_core_data mlxplat_mlxcpld_global_wp_items_data[] = {
2252 {
2253 .label = "global_wp_grant",
2254 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET,
2255 .mask = MLXPLAT_CPLD_GWP_MASK,
2256 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
2257 },
2258};
2259
2260static struct mlxreg_core_item mlxplat_mlxcpld_chassis_blade_items[] = {
2261 {
2262 .data = mlxplat_mlxcpld_global_wp_items_data,
2263 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2264 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET,
2265 .mask = MLXPLAT_CPLD_GWP_MASK,
2266 .count = ARRAY_SIZE(mlxplat_mlxcpld_global_wp_items_data),
2267 .inversed = 0,
2268 .health = false,
2269 },
2270};
2271
2272static
2273struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_chassis_blade_data = {
2274 .items = mlxplat_mlxcpld_chassis_blade_items,
2275 .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_items),
2276 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
2277 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX,
2278 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
2279 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
2280};
2281
2282/* Platform hotplug for switch systems family data */
2283static struct mlxreg_core_data mlxplat_mlxcpld_erot_ap_items_data[] = {
2284 {
2285 .label = "erot1_ap",
2286 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET,
2287 .mask = BIT(0),
2288 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
2289 },
2290 {
2291 .label = "erot2_ap",
2292 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET,
2293 .mask = BIT(1),
2294 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
2295 },
2296};
2297
2298static struct mlxreg_core_data mlxplat_mlxcpld_erot_error_items_data[] = {
2299 {
2300 .label = "erot1_error",
2301 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET,
2302 .mask = BIT(0),
2303 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
2304 },
2305 {
2306 .label = "erot2_error",
2307 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET,
2308 .mask = BIT(1),
2309 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
2310 },
2311};
2312
2313static struct mlxreg_core_item mlxplat_mlxcpld_rack_switch_items[] = {
2314 {
2315 .data = mlxplat_mlxcpld_ext_psu_items_data,
2316 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2317 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
2318 .mask = MLXPLAT_CPLD_PSU_EXT_MASK,
2319 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
2320 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data),
2321 .inversed = 1,
2322 .health = false,
2323 },
2324 {
2325 .data = mlxplat_mlxcpld_ext_pwr_items_data,
2326 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2327 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
2328 .mask = MLXPLAT_CPLD_PWR_EXT_MASK,
2329 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
2330 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data),
2331 .inversed = 0,
2332 .health = false,
2333 },
2334 {
2335 .data = mlxplat_mlxcpld_default_ng_fan_items_data,
2336 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2337 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
2338 .mask = MLXPLAT_CPLD_FAN_NG_MASK,
2339 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
2340 .inversed = 1,
2341 .health = false,
2342 },
2343 {
2344 .data = mlxplat_mlxcpld_erot_ap_items_data,
2345 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2346 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET,
2347 .mask = MLXPLAT_CPLD_EROT_MASK,
2348 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data),
2349 .inversed = 1,
2350 .health = false,
2351 },
2352 {
2353 .data = mlxplat_mlxcpld_erot_error_items_data,
2354 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2355 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET,
2356 .mask = MLXPLAT_CPLD_EROT_MASK,
2357 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data),
2358 .inversed = 1,
2359 .health = false,
2360 },
2361};
2362
2363static
2364struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_rack_switch_data = {
2365 .items = mlxplat_mlxcpld_rack_switch_items,
2366 .counter = ARRAY_SIZE(mlxplat_mlxcpld_rack_switch_items),
2367 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
2368 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
2369 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
2370 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
2371};
2372
2373/* Callback performs graceful shutdown after notification about power button event */
2374static int
2375mlxplat_mlxcpld_l1_switch_pwr_events_handler(void *handle, enum mlxreg_hotplug_kind kind,
2376 u8 action)
2377{
2378 if (action) {
2379 dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button");
2380 kernel_power_off();
2381 }
2382
2383 return 0;
2384}
2385
2386static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_pwr_events_notifier = {
2387 .user_handler = mlxplat_mlxcpld_l1_switch_pwr_events_handler,
2388};
2389
2390/* Platform hotplug for l1 switch systems family data */
2391static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_pwr_events_items_data[] = {
2392 {
2393 .label = "power_button",
2394 .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET,
2395 .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK,
2396 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
2397 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
2398 .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_pwr_events_notifier,
2399 },
2400};
2401
2402/* Callback activates latch reset flow after notification about intrusion event */
2403static int
2404mlxplat_mlxcpld_l1_switch_intrusion_events_handler(void *handle, enum mlxreg_hotplug_kind kind,
2405 u8 action)
2406{
2407 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
2408 u32 regval;
2409 int err;
2410
2411 err = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ®val);
2412 if (err)
2413 goto fail_regmap_read;
2414
2415 if (action) {
2416 dev_info(&mlxplat_dev->dev, "Detected intrusion - system latch is opened");
2417 err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
2418 regval | MLXPLAT_CPLD_LATCH_RST_MASK);
2419 } else {
2420 dev_info(&mlxplat_dev->dev, "System latch is properly closed");
2421 err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
2422 regval & ~MLXPLAT_CPLD_LATCH_RST_MASK);
2423 }
2424
2425 if (err)
2426 goto fail_regmap_write;
2427
2428 return 0;
2429
2430fail_regmap_read:
2431fail_regmap_write:
2432 dev_err(&mlxplat_dev->dev, "Register access failed");
2433 return err;
2434}
2435
2436static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_intrusion_events_notifier = {
2437 .user_handler = mlxplat_mlxcpld_l1_switch_intrusion_events_handler,
2438};
2439
2440static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_health_events_items_data[] = {
2441 {
2442 .label = "thermal1_pdb",
2443 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET,
2444 .mask = MLXPLAT_CPLD_THERMAL1_PDB_MASK,
2445 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
2446 },
2447 {
2448 .label = "thermal2_pdb",
2449 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET,
2450 .mask = MLXPLAT_CPLD_THERMAL2_PDB_MASK,
2451 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
2452 },
2453 {
2454 .label = "intrusion",
2455 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET,
2456 .mask = MLXPLAT_CPLD_INTRUSION_MASK,
2457 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
2458 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION,
2459 .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_intrusion_events_notifier,
2460 },
2461 {
2462 .label = "pwm_pg",
2463 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET,
2464 .mask = MLXPLAT_CPLD_PWM_PG_MASK,
2465 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
2466 },
2467};
2468
2469static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = {
2470 {
2471 .data = mlxplat_mlxcpld_default_ng_fan_items_data,
2472 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2473 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
2474 .mask = MLXPLAT_CPLD_FAN_NG_MASK,
2475 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
2476 .inversed = 1,
2477 .health = false,
2478 },
2479 {
2480 .data = mlxplat_mlxcpld_erot_ap_items_data,
2481 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2482 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET,
2483 .mask = MLXPLAT_CPLD_EROT_MASK,
2484 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data),
2485 .inversed = 1,
2486 .health = false,
2487 },
2488 {
2489 .data = mlxplat_mlxcpld_erot_error_items_data,
2490 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2491 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET,
2492 .mask = MLXPLAT_CPLD_EROT_MASK,
2493 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data),
2494 .inversed = 1,
2495 .health = false,
2496 },
2497 {
2498 .data = mlxplat_mlxcpld_l1_switch_pwr_events_items_data,
2499 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2500 .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET,
2501 .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK,
2502 .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_pwr_events_items_data),
2503 .inversed = 1,
2504 .health = false,
2505 },
2506 {
2507 .data = mlxplat_mlxcpld_l1_switch_health_events_items_data,
2508 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
2509 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET,
2510 .mask = MLXPLAT_CPLD_L1_CHA_HEALTH_MASK,
2511 .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_health_events_items_data),
2512 .inversed = 1,
2513 .health = false,
2514 .ind = 8,
2515 },
2516};
2517
2518static
2519struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = {
2520 .items = mlxplat_mlxcpld_l1_switch_events_items,
2521 .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_events_items),
2522 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
2523 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
2524 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
2525 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT,
2526};
2527
2528/* Platform led default data */
2529static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = {
2530 {
2531 .label = "status:green",
2532 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2533 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2534 },
2535 {
2536 .label = "status:red",
2537 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2538 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
2539 },
2540 {
2541 .label = "psu:green",
2542 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2543 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2544 },
2545 {
2546 .label = "psu:red",
2547 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2548 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2549 },
2550 {
2551 .label = "fan1:green",
2552 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2553 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2554 },
2555 {
2556 .label = "fan1:red",
2557 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2558 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2559 },
2560 {
2561 .label = "fan2:green",
2562 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2563 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2564 },
2565 {
2566 .label = "fan2:red",
2567 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2568 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2569 },
2570 {
2571 .label = "fan3:green",
2572 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2573 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2574 },
2575 {
2576 .label = "fan3:red",
2577 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2578 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2579 },
2580 {
2581 .label = "fan4:green",
2582 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2583 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2584 },
2585 {
2586 .label = "fan4:red",
2587 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2588 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2589 },
2590};
2591
2592static struct mlxreg_core_platform_data mlxplat_default_led_data = {
2593 .data = mlxplat_mlxcpld_default_led_data,
2594 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data),
2595};
2596
2597/* Platform led default data for water cooling */
2598static struct mlxreg_core_data mlxplat_mlxcpld_default_led_wc_data[] = {
2599 {
2600 .label = "status:green",
2601 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2602 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2603 },
2604 {
2605 .label = "status:red",
2606 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2607 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
2608 },
2609 {
2610 .label = "psu:green",
2611 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2612 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2613 },
2614 {
2615 .label = "psu:red",
2616 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2617 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2618 },
2619};
2620
2621static struct mlxreg_core_platform_data mlxplat_default_led_wc_data = {
2622 .data = mlxplat_mlxcpld_default_led_wc_data,
2623 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_wc_data),
2624};
2625
2626/* Platform led default data for water cooling Ethernet switch blade */
2627static struct mlxreg_core_data mlxplat_mlxcpld_default_led_eth_wc_blade_data[] = {
2628 {
2629 .label = "status:green",
2630 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2631 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2632 },
2633 {
2634 .label = "status:red",
2635 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2636 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
2637 },
2638};
2639
2640static struct mlxreg_core_platform_data mlxplat_default_led_eth_wc_blade_data = {
2641 .data = mlxplat_mlxcpld_default_led_eth_wc_blade_data,
2642 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_eth_wc_blade_data),
2643};
2644
2645/* Platform led MSN21xx system family data */
2646static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = {
2647 {
2648 .label = "status:green",
2649 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2650 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2651 },
2652 {
2653 .label = "status:red",
2654 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2655 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
2656 },
2657 {
2658 .label = "fan:green",
2659 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2660 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2661 },
2662 {
2663 .label = "fan:red",
2664 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2665 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2666 },
2667 {
2668 .label = "psu1:green",
2669 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2670 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2671 },
2672 {
2673 .label = "psu1:red",
2674 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2675 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2676 },
2677 {
2678 .label = "psu2:green",
2679 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2680 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2681 },
2682 {
2683 .label = "psu2:red",
2684 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2685 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2686 },
2687 {
2688 .label = "uid:blue",
2689 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
2690 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2691 },
2692};
2693
2694static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = {
2695 .data = mlxplat_mlxcpld_msn21xx_led_data,
2696 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data),
2697};
2698
2699/* Platform led for default data for 200GbE systems */
2700static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = {
2701 {
2702 .label = "status:green",
2703 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2704 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2705 },
2706 {
2707 .label = "status:orange",
2708 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2709 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
2710 },
2711 {
2712 .label = "psu:green",
2713 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2714 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2715 },
2716 {
2717 .label = "psu:orange",
2718 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2719 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2720 },
2721 {
2722 .label = "fan1:green",
2723 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2724 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2725 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2726 .bit = BIT(0),
2727 },
2728 {
2729 .label = "fan1:orange",
2730 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2731 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2732 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2733 .bit = BIT(0),
2734 },
2735 {
2736 .label = "fan2:green",
2737 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2738 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2739 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2740 .bit = BIT(1),
2741 },
2742 {
2743 .label = "fan2:orange",
2744 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2745 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2746 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2747 .bit = BIT(1),
2748 },
2749 {
2750 .label = "fan3:green",
2751 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2752 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2753 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2754 .bit = BIT(2),
2755 },
2756 {
2757 .label = "fan3:orange",
2758 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2759 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2760 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2761 .bit = BIT(2),
2762 },
2763 {
2764 .label = "fan4:green",
2765 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2766 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2767 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2768 .bit = BIT(3),
2769 },
2770 {
2771 .label = "fan4:orange",
2772 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2773 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2774 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2775 .bit = BIT(3),
2776 },
2777 {
2778 .label = "fan5:green",
2779 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2780 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2781 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2782 .bit = BIT(4),
2783 },
2784 {
2785 .label = "fan5:orange",
2786 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2787 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2788 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2789 .bit = BIT(4),
2790 },
2791 {
2792 .label = "fan6:green",
2793 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2794 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2795 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2796 .bit = BIT(5),
2797 },
2798 {
2799 .label = "fan6:orange",
2800 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2801 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2802 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2803 .bit = BIT(5),
2804 },
2805 {
2806 .label = "fan7:green",
2807 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
2808 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2809 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2810 .bit = BIT(6),
2811 },
2812 {
2813 .label = "fan7:orange",
2814 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
2815 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2816 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2817 .bit = BIT(6),
2818 },
2819 {
2820 .label = "uid:blue",
2821 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
2822 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2823 },
2824};
2825
2826static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = {
2827 .data = mlxplat_mlxcpld_default_ng_led_data,
2828 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data),
2829};
2830
2831/* Platform led for Comex based 100GbE systems */
2832static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = {
2833 {
2834 .label = "status:green",
2835 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2836 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2837 },
2838 {
2839 .label = "status:red",
2840 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2841 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
2842 },
2843 {
2844 .label = "psu:green",
2845 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2846 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2847 },
2848 {
2849 .label = "psu:red",
2850 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2851 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2852 },
2853 {
2854 .label = "fan1:green",
2855 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2856 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2857 },
2858 {
2859 .label = "fan1:red",
2860 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2861 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2862 },
2863 {
2864 .label = "fan2:green",
2865 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2866 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2867 },
2868 {
2869 .label = "fan2:red",
2870 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2871 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2872 },
2873 {
2874 .label = "fan3:green",
2875 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2876 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2877 },
2878 {
2879 .label = "fan3:red",
2880 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2881 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2882 },
2883 {
2884 .label = "fan4:green",
2885 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2886 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2887 },
2888 {
2889 .label = "fan4:red",
2890 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2891 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2892 },
2893 {
2894 .label = "uid:blue",
2895 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
2896 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2897 },
2898};
2899
2900static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = {
2901 .data = mlxplat_mlxcpld_comex_100G_led_data,
2902 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data),
2903};
2904
2905/* Platform led for data for modular systems */
2906static struct mlxreg_core_data mlxplat_mlxcpld_modular_led_data[] = {
2907 {
2908 .label = "status:green",
2909 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2910 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2911 },
2912 {
2913 .label = "status:orange",
2914 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2915 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
2916 },
2917 {
2918 .label = "psu:green",
2919 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2920 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2921 },
2922 {
2923 .label = "psu:orange",
2924 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
2925 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2926 },
2927 {
2928 .label = "fan1:green",
2929 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2930 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2931 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2932 .bit = BIT(0),
2933 },
2934 {
2935 .label = "fan1:orange",
2936 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2937 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2938 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2939 .bit = BIT(0),
2940 },
2941 {
2942 .label = "fan2:green",
2943 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2944 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2945 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2946 .bit = BIT(1),
2947 },
2948 {
2949 .label = "fan2:orange",
2950 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
2951 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2952 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2953 .bit = BIT(1),
2954 },
2955 {
2956 .label = "fan3:green",
2957 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2958 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2959 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2960 .bit = BIT(2),
2961 },
2962 {
2963 .label = "fan3:orange",
2964 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2965 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2966 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2967 .bit = BIT(2),
2968 },
2969 {
2970 .label = "fan4:green",
2971 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2972 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2973 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2974 .bit = BIT(3),
2975 },
2976 {
2977 .label = "fan4:orange",
2978 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
2979 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
2980 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2981 .bit = BIT(3),
2982 },
2983 {
2984 .label = "fan5:green",
2985 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2986 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2987 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2988 .bit = BIT(4),
2989 },
2990 {
2991 .label = "fan5:orange",
2992 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
2993 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
2994 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
2995 .bit = BIT(4),
2996 },
2997 {
2998 .label = "fan6:green",
2999 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
3000 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
3001 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
3002 .bit = BIT(5),
3003 },
3004 {
3005 .label = "fan6:orange",
3006 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
3007 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
3008 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
3009 .bit = BIT(5),
3010 },
3011 {
3012 .label = "fan7:green",
3013 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
3014 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
3015 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
3016 .bit = BIT(6),
3017 },
3018 {
3019 .label = "fan7:orange",
3020 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
3021 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
3022 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
3023 .bit = BIT(6),
3024 },
3025 {
3026 .label = "uid:blue",
3027 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
3028 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
3029 },
3030 {
3031 .label = "fan_front:green",
3032 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
3033 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
3034 },
3035 {
3036 .label = "fan_front:orange",
3037 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET,
3038 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
3039 },
3040 {
3041 .label = "mgmt:green",
3042 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET,
3043 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
3044 },
3045 {
3046 .label = "mgmt:orange",
3047 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET,
3048 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
3049 },
3050};
3051
3052static struct mlxreg_core_platform_data mlxplat_modular_led_data = {
3053 .data = mlxplat_mlxcpld_modular_led_data,
3054 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_led_data),
3055};
3056
3057/* Platform led data for chassis system */
3058static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = {
3059 {
3060 .label = "status:green",
3061 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
3062 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
3063 },
3064 {
3065 .label = "status:orange",
3066 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET,
3067 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK
3068 },
3069 {
3070 .label = "fan1:green",
3071 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
3072 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
3073 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
3074 .bit = BIT(0),
3075 },
3076 {
3077 .label = "fan1:orange",
3078 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
3079 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
3080 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
3081 .bit = BIT(0),
3082 },
3083 {
3084 .label = "fan2:green",
3085 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
3086 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
3087 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
3088 .bit = BIT(1),
3089 },
3090 {
3091 .label = "fan2:orange",
3092 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
3093 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
3094 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
3095 .bit = BIT(1),
3096 },
3097 {
3098 .label = "fan3:green",
3099 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
3100 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
3101 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
3102 .bit = BIT(2),
3103 },
3104 {
3105 .label = "fan3:orange",
3106 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
3107 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
3108 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
3109 .bit = BIT(2),
3110 },
3111 {
3112 .label = "fan4:green",
3113 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
3114 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
3115 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
3116 .bit = BIT(3),
3117 },
3118 {
3119 .label = "fan4:orange",
3120 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
3121 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
3122 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
3123 .bit = BIT(3),
3124 },
3125 {
3126 .label = "fan5:green",
3127 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
3128 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
3129 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
3130 .bit = BIT(4),
3131 },
3132 {
3133 .label = "fan5:orange",
3134 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
3135 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
3136 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
3137 .bit = BIT(4),
3138 },
3139 {
3140 .label = "fan6:green",
3141 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
3142 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
3143 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
3144 .bit = BIT(5),
3145 },
3146 {
3147 .label = "fan6:orange",
3148 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
3149 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
3150 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
3151 .bit = BIT(5),
3152 },
3153 {
3154 .label = "uid:blue",
3155 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
3156 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
3157 },
3158};
3159
3160static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = {
3161 .data = mlxplat_mlxcpld_l1_switch_led_data,
3162 .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_led_data),
3163};
3164
3165/* Platform register access default */
3166static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = {
3167 {
3168 .label = "cpld1_version",
3169 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
3170 .bit = GENMASK(7, 0),
3171 .mode = 0444,
3172 },
3173 {
3174 .label = "cpld2_version",
3175 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
3176 .bit = GENMASK(7, 0),
3177 .mode = 0444,
3178 },
3179 {
3180 .label = "cpld1_pn",
3181 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
3182 .bit = GENMASK(15, 0),
3183 .mode = 0444,
3184 .regnum = 2,
3185 },
3186 {
3187 .label = "cpld2_pn",
3188 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
3189 .bit = GENMASK(15, 0),
3190 .mode = 0444,
3191 .regnum = 2,
3192 },
3193 {
3194 .label = "cpld1_version_min",
3195 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
3196 .bit = GENMASK(7, 0),
3197 .mode = 0444,
3198 },
3199 {
3200 .label = "cpld2_version_min",
3201 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
3202 .bit = GENMASK(7, 0),
3203 .mode = 0444,
3204 },
3205 {
3206 .label = "reset_long_pb",
3207 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3208 .mask = GENMASK(7, 0) & ~BIT(0),
3209 .mode = 0444,
3210 },
3211 {
3212 .label = "reset_short_pb",
3213 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3214 .mask = GENMASK(7, 0) & ~BIT(1),
3215 .mode = 0444,
3216 },
3217 {
3218 .label = "reset_aux_pwr_or_ref",
3219 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3220 .mask = GENMASK(7, 0) & ~BIT(2),
3221 .mode = 0444,
3222 },
3223 {
3224 .label = "reset_main_pwr_fail",
3225 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3226 .mask = GENMASK(7, 0) & ~BIT(3),
3227 .mode = 0444,
3228 },
3229 {
3230 .label = "reset_sw_reset",
3231 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3232 .mask = GENMASK(7, 0) & ~BIT(4),
3233 .mode = 0444,
3234 },
3235 {
3236 .label = "reset_fw_reset",
3237 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3238 .mask = GENMASK(7, 0) & ~BIT(5),
3239 .mode = 0444,
3240 },
3241 {
3242 .label = "reset_hotswap_or_wd",
3243 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3244 .mask = GENMASK(7, 0) & ~BIT(6),
3245 .mode = 0444,
3246 },
3247 {
3248 .label = "reset_asic_thermal",
3249 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3250 .mask = GENMASK(7, 0) & ~BIT(7),
3251 .mode = 0444,
3252 },
3253 {
3254 .label = "psu1_on",
3255 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3256 .mask = GENMASK(7, 0) & ~BIT(0),
3257 .mode = 0200,
3258 },
3259 {
3260 .label = "psu2_on",
3261 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3262 .mask = GENMASK(7, 0) & ~BIT(1),
3263 .mode = 0200,
3264 },
3265 {
3266 .label = "pwr_cycle",
3267 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3268 .mask = GENMASK(7, 0) & ~BIT(2),
3269 .mode = 0200,
3270 },
3271 {
3272 .label = "pwr_down",
3273 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3274 .mask = GENMASK(7, 0) & ~BIT(3),
3275 .mode = 0200,
3276 },
3277 {
3278 .label = "select_iio",
3279 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
3280 .mask = GENMASK(7, 0) & ~BIT(6),
3281 .mode = 0644,
3282 },
3283 {
3284 .label = "asic_health",
3285 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
3286 .mask = MLXPLAT_CPLD_ASIC_MASK,
3287 .bit = 1,
3288 .mode = 0444,
3289 },
3290};
3291
3292static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = {
3293 .data = mlxplat_mlxcpld_default_regs_io_data,
3294 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data),
3295};
3296
3297/* Platform register access MSN21xx, MSN201x, MSN274x systems families data */
3298static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = {
3299 {
3300 .label = "cpld1_version",
3301 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
3302 .bit = GENMASK(7, 0),
3303 .mode = 0444,
3304 },
3305 {
3306 .label = "cpld2_version",
3307 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
3308 .bit = GENMASK(7, 0),
3309 .mode = 0444,
3310 },
3311 {
3312 .label = "cpld1_pn",
3313 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
3314 .bit = GENMASK(15, 0),
3315 .mode = 0444,
3316 .regnum = 2,
3317 },
3318 {
3319 .label = "cpld2_pn",
3320 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
3321 .bit = GENMASK(15, 0),
3322 .mode = 0444,
3323 .regnum = 2,
3324 },
3325 {
3326 .label = "cpld1_version_min",
3327 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
3328 .bit = GENMASK(7, 0),
3329 .mode = 0444,
3330 },
3331 {
3332 .label = "cpld2_version_min",
3333 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
3334 .bit = GENMASK(7, 0),
3335 .mode = 0444,
3336 },
3337 {
3338 .label = "reset_long_pb",
3339 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3340 .mask = GENMASK(7, 0) & ~BIT(0),
3341 .mode = 0444,
3342 },
3343 {
3344 .label = "reset_short_pb",
3345 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3346 .mask = GENMASK(7, 0) & ~BIT(1),
3347 .mode = 0444,
3348 },
3349 {
3350 .label = "reset_aux_pwr_or_ref",
3351 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3352 .mask = GENMASK(7, 0) & ~BIT(2),
3353 .mode = 0444,
3354 },
3355 {
3356 .label = "reset_sw_reset",
3357 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3358 .mask = GENMASK(7, 0) & ~BIT(3),
3359 .mode = 0444,
3360 },
3361 {
3362 .label = "reset_main_pwr_fail",
3363 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3364 .mask = GENMASK(7, 0) & ~BIT(4),
3365 .mode = 0444,
3366 },
3367 {
3368 .label = "reset_asic_thermal",
3369 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3370 .mask = GENMASK(7, 0) & ~BIT(5),
3371 .mode = 0444,
3372 },
3373 {
3374 .label = "reset_hotswap_or_halt",
3375 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3376 .mask = GENMASK(7, 0) & ~BIT(6),
3377 .mode = 0444,
3378 },
3379 {
3380 .label = "reset_sff_wd",
3381 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3382 .mask = GENMASK(7, 0) & ~BIT(6),
3383 .mode = 0444,
3384 },
3385 {
3386 .label = "psu1_on",
3387 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3388 .mask = GENMASK(7, 0) & ~BIT(0),
3389 .mode = 0200,
3390 },
3391 {
3392 .label = "psu2_on",
3393 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3394 .mask = GENMASK(7, 0) & ~BIT(1),
3395 .mode = 0200,
3396 },
3397 {
3398 .label = "pwr_cycle",
3399 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3400 .mask = GENMASK(7, 0) & ~BIT(2),
3401 .mode = 0200,
3402 },
3403 {
3404 .label = "pwr_down",
3405 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3406 .mask = GENMASK(7, 0) & ~BIT(3),
3407 .mode = 0200,
3408 },
3409 {
3410 .label = "select_iio",
3411 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
3412 .mask = GENMASK(7, 0) & ~BIT(6),
3413 .mode = 0644,
3414 },
3415 {
3416 .label = "asic_health",
3417 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
3418 .mask = MLXPLAT_CPLD_ASIC_MASK,
3419 .bit = 1,
3420 .mode = 0444,
3421 },
3422};
3423
3424static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = {
3425 .data = mlxplat_mlxcpld_msn21xx_regs_io_data,
3426 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data),
3427};
3428
3429/* Platform register access for next generation systems families data */
3430static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
3431 {
3432 .label = "cpld1_version",
3433 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
3434 .bit = GENMASK(7, 0),
3435 .mode = 0444,
3436 },
3437 {
3438 .label = "cpld2_version",
3439 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
3440 .bit = GENMASK(7, 0),
3441 .mode = 0444,
3442 },
3443 {
3444 .label = "cpld3_version",
3445 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET,
3446 .bit = GENMASK(7, 0),
3447 .mode = 0444,
3448 },
3449 {
3450 .label = "cpld4_version",
3451 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET,
3452 .bit = GENMASK(7, 0),
3453 .mode = 0444,
3454 },
3455 {
3456 .label = "cpld5_version",
3457 .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET,
3458 .bit = GENMASK(7, 0),
3459 .mode = 0444,
3460 },
3461 {
3462 .label = "cpld1_pn",
3463 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
3464 .bit = GENMASK(15, 0),
3465 .mode = 0444,
3466 .regnum = 2,
3467 },
3468 {
3469 .label = "cpld2_pn",
3470 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
3471 .bit = GENMASK(15, 0),
3472 .mode = 0444,
3473 .regnum = 2,
3474 },
3475 {
3476 .label = "cpld3_pn",
3477 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET,
3478 .bit = GENMASK(15, 0),
3479 .mode = 0444,
3480 .regnum = 2,
3481 },
3482 {
3483 .label = "cpld4_pn",
3484 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET,
3485 .bit = GENMASK(15, 0),
3486 .mode = 0444,
3487 .regnum = 2,
3488 },
3489 {
3490 .label = "cpld5_pn",
3491 .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET,
3492 .bit = GENMASK(15, 0),
3493 .mode = 0444,
3494 .regnum = 2,
3495 },
3496 {
3497 .label = "cpld1_version_min",
3498 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
3499 .bit = GENMASK(7, 0),
3500 .mode = 0444,
3501 },
3502 {
3503 .label = "cpld2_version_min",
3504 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
3505 .bit = GENMASK(7, 0),
3506 .mode = 0444,
3507 },
3508 {
3509 .label = "cpld3_version_min",
3510 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET,
3511 .bit = GENMASK(7, 0),
3512 .mode = 0444,
3513 },
3514 {
3515 .label = "cpld4_version_min",
3516 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET,
3517 .bit = GENMASK(7, 0),
3518 .mode = 0444,
3519 },
3520 {
3521 .label = "cpld5_version_min",
3522 .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET,
3523 .bit = GENMASK(7, 0),
3524 .mode = 0444,
3525 },
3526 {
3527 .label = "asic_reset",
3528 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
3529 .mask = GENMASK(7, 0) & ~BIT(3),
3530 .mode = 0200,
3531 },
3532 {
3533 .label = "asic2_reset",
3534 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
3535 .mask = GENMASK(7, 0) & ~BIT(2),
3536 .mode = 0200,
3537 },
3538 {
3539 .label = "erot1_reset",
3540 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
3541 .mask = GENMASK(7, 0) & ~BIT(6),
3542 .mode = 0644,
3543 },
3544 {
3545 .label = "erot2_reset",
3546 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
3547 .mask = GENMASK(7, 0) & ~BIT(7),
3548 .mode = 0644,
3549 },
3550 {
3551 .label = "clk_brd_prog_en",
3552 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
3553 .mask = GENMASK(7, 0) & ~BIT(1),
3554 .mode = 0644,
3555 .secured = 1,
3556 },
3557 {
3558 .label = "erot1_recovery",
3559 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
3560 .mask = GENMASK(7, 0) & ~BIT(6),
3561 .mode = 0644,
3562 },
3563 {
3564 .label = "erot2_recovery",
3565 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
3566 .mask = GENMASK(7, 0) & ~BIT(7),
3567 .mode = 0644,
3568 },
3569 {
3570 .label = "erot1_wp",
3571 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
3572 .mask = GENMASK(7, 0) & ~BIT(4),
3573 .mode = 0644,
3574 .secured = 1,
3575 },
3576 {
3577 .label = "erot2_wp",
3578 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET,
3579 .mask = GENMASK(7, 0) & ~BIT(5),
3580 .mode = 0644,
3581 .secured = 1,
3582 },
3583 {
3584 .label = "reset_long_pb",
3585 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3586 .mask = GENMASK(7, 0) & ~BIT(0),
3587 .mode = 0444,
3588 },
3589 {
3590 .label = "reset_short_pb",
3591 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3592 .mask = GENMASK(7, 0) & ~BIT(1),
3593 .mode = 0444,
3594 },
3595 {
3596 .label = "reset_aux_pwr_or_ref",
3597 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3598 .mask = GENMASK(7, 0) & ~BIT(2),
3599 .mode = 0444,
3600 },
3601 {
3602 .label = "reset_swb_dc_dc_pwr_fail",
3603 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3604 .mask = GENMASK(7, 0) & ~BIT(3),
3605 .mode = 0444,
3606 },
3607 {
3608 .label = "reset_from_asic",
3609 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3610 .mask = GENMASK(7, 0) & ~BIT(5),
3611 .mode = 0444,
3612 },
3613 {
3614 .label = "reset_swb_wd",
3615 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3616 .mask = GENMASK(7, 0) & ~BIT(6),
3617 .mode = 0444,
3618 },
3619 {
3620 .label = "reset_asic_thermal",
3621 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
3622 .mask = GENMASK(7, 0) & ~BIT(7),
3623 .mode = 0444,
3624 },
3625 {
3626 .label = "reset_sw_reset",
3627 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3628 .mask = GENMASK(7, 0) & ~BIT(0),
3629 .mode = 0444,
3630 },
3631 {
3632 .label = "reset_comex_pwr_fail",
3633 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3634 .mask = GENMASK(7, 0) & ~BIT(3),
3635 .mode = 0444,
3636 },
3637 {
3638 .label = "reset_platform",
3639 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3640 .mask = GENMASK(7, 0) & ~BIT(4),
3641 .mode = 0444,
3642 },
3643 {
3644 .label = "reset_soc",
3645 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3646 .mask = GENMASK(7, 0) & ~BIT(5),
3647 .mode = 0444,
3648 },
3649 {
3650 .label = "reset_comex_wd",
3651 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
3652 .mask = GENMASK(7, 0) & ~BIT(6),
3653 .mode = 0444,
3654 },
3655 {
3656 .label = "reset_pwr_converter_fail",
3657 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3658 .mask = GENMASK(7, 0) & ~BIT(0),
3659 .mode = 0444,
3660 },
3661 {
3662 .label = "reset_system",
3663 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3664 .mask = GENMASK(7, 0) & ~BIT(1),
3665 .mode = 0444,
3666 },
3667 {
3668 .label = "reset_sw_pwr_off",
3669 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3670 .mask = GENMASK(7, 0) & ~BIT(2),
3671 .mode = 0444,
3672 },
3673 {
3674 .label = "reset_comex_thermal",
3675 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3676 .mask = GENMASK(7, 0) & ~BIT(3),
3677 .mode = 0444,
3678 },
3679 {
3680 .label = "reset_reload_bios",
3681 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3682 .mask = GENMASK(7, 0) & ~BIT(5),
3683 .mode = 0444,
3684 },
3685 {
3686 .label = "reset_ac_pwr_fail",
3687 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3688 .mask = GENMASK(7, 0) & ~BIT(6),
3689 .mode = 0444,
3690 },
3691 {
3692 .label = "reset_ac_ok_fail",
3693 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
3694 .mask = GENMASK(7, 0) & ~BIT(7),
3695 .mode = 0444,
3696 },
3697 {
3698 .label = "psu1_on",
3699 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3700 .mask = GENMASK(7, 0) & ~BIT(0),
3701 .mode = 0200,
3702 },
3703 {
3704 .label = "psu2_on",
3705 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3706 .mask = GENMASK(7, 0) & ~BIT(1),
3707 .mode = 0200,
3708 },
3709 {
3710 .label = "pwr_cycle",
3711 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3712 .mask = GENMASK(7, 0) & ~BIT(2),
3713 .mode = 0200,
3714 },
3715 {
3716 .label = "pwr_down",
3717 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3718 .mask = GENMASK(7, 0) & ~BIT(3),
3719 .mode = 0200,
3720 },
3721 {
3722 .label = "deep_pwr_cycle",
3723 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3724 .mask = GENMASK(7, 0) & ~BIT(5),
3725 .mode = 0200,
3726 },
3727 {
3728 .label = "latch_reset",
3729 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
3730 .mask = GENMASK(7, 0) & ~BIT(6),
3731 .mode = 0200,
3732 },
3733 {
3734 .label = "jtag_cap",
3735 .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET,
3736 .mask = MLXPLAT_CPLD_FU_CAP_MASK,
3737 .bit = 1,
3738 .mode = 0444,
3739 },
3740 {
3741 .label = "jtag_enable",
3742 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
3743 .mask = GENMASK(7, 0) & ~BIT(4),
3744 .mode = 0644,
3745 },
3746 {
3747 .label = "dbg1",
3748 .reg = MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET,
3749 .bit = GENMASK(7, 0),
3750 .mode = 0644,
3751 },
3752 {
3753 .label = "dbg2",
3754 .reg = MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET,
3755 .bit = GENMASK(7, 0),
3756 .mode = 0644,
3757 },
3758 {
3759 .label = "dbg3",
3760 .reg = MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET,
3761 .bit = GENMASK(7, 0),
3762 .mode = 0644,
3763 },
3764 {
3765 .label = "dbg4",
3766 .reg = MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET,
3767 .bit = GENMASK(7, 0),
3768 .mode = 0644,
3769 },
3770 {
3771 .label = "asic_health",
3772 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
3773 .mask = MLXPLAT_CPLD_ASIC_MASK,
3774 .bit = 1,
3775 .mode = 0444,
3776 },
3777 {
3778 .label = "asic2_health",
3779 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET,
3780 .mask = MLXPLAT_CPLD_ASIC_MASK,
3781 .bit = 1,
3782 .mode = 0444,
3783 },
3784 {
3785 .label = "fan_dir",
3786 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
3787 .bit = GENMASK(7, 0),
3788 .mode = 0444,
3789 },
3790 {
3791 .label = "bios_safe_mode",
3792 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3793 .mask = GENMASK(7, 0) & ~BIT(4),
3794 .mode = 0444,
3795 },
3796 {
3797 .label = "bios_active_image",
3798 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3799 .mask = GENMASK(7, 0) & ~BIT(5),
3800 .mode = 0444,
3801 },
3802 {
3803 .label = "bios_auth_fail",
3804 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3805 .mask = GENMASK(7, 0) & ~BIT(6),
3806 .mode = 0444,
3807 },
3808 {
3809 .label = "bios_upgrade_fail",
3810 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
3811 .mask = GENMASK(7, 0) & ~BIT(7),
3812 .mode = 0444,
3813 },
3814 {
3815 .label = "voltreg_update_status",
3816 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET,
3817 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK,
3818 .bit = 5,
3819 .mode = 0444,
3820 },
3821 {
3822 .label = "pwr_converter_prog_en",
3823 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
3824 .mask = GENMASK(7, 0) & ~BIT(0),
3825 .mode = 0644,
3826 .secured = 1,
3827 },
3828 {
3829 .label = "vpd_wp",
3830 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
3831 .mask = GENMASK(7, 0) & ~BIT(3),
3832 .mode = 0644,
3833 },
3834 {
3835 .label = "pcie_asic_reset_dis",
3836 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
3837 .mask = GENMASK(7, 0) & ~BIT(4),
3838 .mode = 0644,
3839 },
3840 {
3841 .label = "erot1_ap_reset",
3842 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3843 .mask = GENMASK(7, 0) & ~BIT(0),
3844 .mode = 0444,
3845 },
3846 {
3847 .label = "erot2_ap_reset",
3848 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3849 .mask = GENMASK(7, 0) & ~BIT(1),
3850 .mode = 0444,
3851 },
3852 {
3853 .label = "lid_open",
3854 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3855 .mask = GENMASK(7, 0) & ~BIT(2),
3856 .mode = 0444,
3857 },
3858 {
3859 .label = "clk_brd1_boot_fail",
3860 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3861 .mask = GENMASK(7, 0) & ~BIT(4),
3862 .mode = 0444,
3863 },
3864 {
3865 .label = "clk_brd2_boot_fail",
3866 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3867 .mask = GENMASK(7, 0) & ~BIT(5),
3868 .mode = 0444,
3869 },
3870 {
3871 .label = "clk_brd_fail",
3872 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3873 .mask = GENMASK(7, 0) & ~BIT(6),
3874 .mode = 0444,
3875 },
3876 {
3877 .label = "asic_pg_fail",
3878 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET,
3879 .mask = GENMASK(7, 0) & ~BIT(7),
3880 .mode = 0444,
3881 },
3882 {
3883 .label = "spi_chnl_select",
3884 .reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT,
3885 .mask = GENMASK(7, 0),
3886 .bit = 1,
3887 .mode = 0644,
3888 },
3889 {
3890 .label = "config1",
3891 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET,
3892 .bit = GENMASK(7, 0),
3893 .mode = 0444,
3894 },
3895 {
3896 .label = "config2",
3897 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET,
3898 .bit = GENMASK(7, 0),
3899 .mode = 0444,
3900 },
3901 {
3902 .label = "config3",
3903 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET,
3904 .bit = GENMASK(7, 0),
3905 .mode = 0444,
3906 },
3907 {
3908 .label = "ufm_version",
3909 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET,
3910 .bit = GENMASK(7, 0),
3911 .mode = 0444,
3912 },
3913};
3914
3915static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = {
3916 .data = mlxplat_mlxcpld_default_ng_regs_io_data,
3917 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data),
3918};
3919
3920/* Platform register access for modular systems families data */
3921static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = {
3922 {
3923 .label = "cpld1_version",
3924 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
3925 .bit = GENMASK(7, 0),
3926 .mode = 0444,
3927 },
3928 {
3929 .label = "cpld2_version",
3930 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
3931 .bit = GENMASK(7, 0),
3932 .mode = 0444,
3933 },
3934 {
3935 .label = "cpld3_version",
3936 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET,
3937 .bit = GENMASK(7, 0),
3938 .mode = 0444,
3939 },
3940 {
3941 .label = "cpld4_version",
3942 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET,
3943 .bit = GENMASK(7, 0),
3944 .mode = 0444,
3945 },
3946 {
3947 .label = "cpld1_pn",
3948 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
3949 .bit = GENMASK(15, 0),
3950 .mode = 0444,
3951 .regnum = 2,
3952 },
3953 {
3954 .label = "cpld2_pn",
3955 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
3956 .bit = GENMASK(15, 0),
3957 .mode = 0444,
3958 .regnum = 2,
3959 },
3960 {
3961 .label = "cpld3_pn",
3962 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET,
3963 .bit = GENMASK(15, 0),
3964 .mode = 0444,
3965 .regnum = 2,
3966 },
3967 {
3968 .label = "cpld4_pn",
3969 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET,
3970 .bit = GENMASK(15, 0),
3971 .mode = 0444,
3972 .regnum = 2,
3973 },
3974 {
3975 .label = "cpld1_version_min",
3976 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
3977 .bit = GENMASK(7, 0),
3978 .mode = 0444,
3979 },
3980 {
3981 .label = "cpld2_version_min",
3982 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
3983 .bit = GENMASK(7, 0),
3984 .mode = 0444,
3985 },
3986 {
3987 .label = "cpld3_version_min",
3988 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET,
3989 .bit = GENMASK(7, 0),
3990 .mode = 0444,
3991 },
3992 {
3993 .label = "cpld4_version_min",
3994 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET,
3995 .bit = GENMASK(7, 0),
3996 .mode = 0444,
3997 },
3998 {
3999 .label = "lc1_enable",
4000 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
4001 .mask = GENMASK(7, 0) & ~BIT(0),
4002 .mode = 0644,
4003 },
4004 {
4005 .label = "lc2_enable",
4006 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
4007 .mask = GENMASK(7, 0) & ~BIT(1),
4008 .mode = 0644,
4009 },
4010 {
4011 .label = "lc3_enable",
4012 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
4013 .mask = GENMASK(7, 0) & ~BIT(2),
4014 .mode = 0644,
4015 },
4016 {
4017 .label = "lc4_enable",
4018 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
4019 .mask = GENMASK(7, 0) & ~BIT(3),
4020 .mode = 0644,
4021 },
4022 {
4023 .label = "lc5_enable",
4024 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
4025 .mask = GENMASK(7, 0) & ~BIT(4),
4026 .mode = 0644,
4027 },
4028 {
4029 .label = "lc6_enable",
4030 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
4031 .mask = GENMASK(7, 0) & ~BIT(5),
4032 .mode = 0644,
4033 },
4034 {
4035 .label = "lc7_enable",
4036 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
4037 .mask = GENMASK(7, 0) & ~BIT(6),
4038 .mode = 0644,
4039 },
4040 {
4041 .label = "lc8_enable",
4042 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET,
4043 .mask = GENMASK(7, 0) & ~BIT(7),
4044 .mode = 0644,
4045 },
4046 {
4047 .label = "reset_long_pb",
4048 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4049 .mask = GENMASK(7, 0) & ~BIT(0),
4050 .mode = 0444,
4051 },
4052 {
4053 .label = "reset_short_pb",
4054 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4055 .mask = GENMASK(7, 0) & ~BIT(1),
4056 .mode = 0444,
4057 },
4058 {
4059 .label = "reset_aux_pwr_or_fu",
4060 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4061 .mask = GENMASK(7, 0) & ~BIT(2),
4062 .mode = 0444,
4063 },
4064 {
4065 .label = "reset_mgmt_dc_dc_pwr_fail",
4066 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4067 .mask = GENMASK(7, 0) & ~BIT(3),
4068 .mode = 0444,
4069 },
4070 {
4071 .label = "reset_sys_comex_bios",
4072 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4073 .mask = GENMASK(7, 0) & ~BIT(5),
4074 .mode = 0444,
4075 },
4076 {
4077 .label = "reset_sw_reset",
4078 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4079 .mask = GENMASK(7, 0) & ~BIT(0),
4080 .mode = 0444,
4081 },
4082 {
4083 .label = "reset_aux_pwr_or_reload",
4084 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4085 .mask = GENMASK(7, 0) & ~BIT(2),
4086 .mode = 0444,
4087 },
4088 {
4089 .label = "reset_comex_pwr_fail",
4090 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4091 .mask = GENMASK(7, 0) & ~BIT(3),
4092 .mode = 0444,
4093 },
4094 {
4095 .label = "reset_platform",
4096 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4097 .mask = GENMASK(7, 0) & ~BIT(4),
4098 .mode = 0444,
4099 },
4100 {
4101 .label = "reset_soc",
4102 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4103 .mask = GENMASK(7, 0) & ~BIT(5),
4104 .mode = 0444,
4105 },
4106 {
4107 .label = "reset_pwr_off_from_carrier",
4108 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4109 .mask = GENMASK(7, 0) & ~BIT(7),
4110 .mode = 0444,
4111 },
4112 {
4113 .label = "reset_swb_wd",
4114 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4115 .mask = GENMASK(7, 0) & ~BIT(0),
4116 .mode = 0444,
4117 },
4118 {
4119 .label = "reset_swb_aux_pwr_or_fu",
4120 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4121 .mask = GENMASK(7, 0) & ~BIT(2),
4122 .mode = 0444,
4123 },
4124 {
4125 .label = "reset_swb_dc_dc_pwr_fail",
4126 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4127 .mask = GENMASK(7, 0) & ~BIT(3),
4128 .mode = 0444,
4129 },
4130 {
4131 .label = "reset_swb_12v_fail",
4132 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4133 .mask = GENMASK(7, 0) & ~BIT(4),
4134 .mode = 0444,
4135 },
4136 {
4137 .label = "reset_system",
4138 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4139 .mask = GENMASK(7, 0) & ~BIT(5),
4140 .mode = 0444,
4141 },
4142 {
4143 .label = "reset_thermal_spc_or_pciesw",
4144 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4145 .mask = GENMASK(7, 0) & ~BIT(7),
4146 .mode = 0444,
4147 },
4148 {
4149 .label = "bios_safe_mode",
4150 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4151 .mask = GENMASK(7, 0) & ~BIT(4),
4152 .mode = 0444,
4153 },
4154 {
4155 .label = "bios_active_image",
4156 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4157 .mask = GENMASK(7, 0) & ~BIT(5),
4158 .mode = 0444,
4159 },
4160 {
4161 .label = "bios_auth_fail",
4162 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4163 .mask = GENMASK(7, 0) & ~BIT(6),
4164 .mode = 0444,
4165 },
4166 {
4167 .label = "bios_upgrade_fail",
4168 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4169 .mask = GENMASK(7, 0) & ~BIT(7),
4170 .mode = 0444,
4171 },
4172 {
4173 .label = "voltreg_update_status",
4174 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET,
4175 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK,
4176 .bit = 5,
4177 .mode = 0444,
4178 },
4179 {
4180 .label = "vpd_wp",
4181 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
4182 .mask = GENMASK(7, 0) & ~BIT(3),
4183 .mode = 0644,
4184 },
4185 {
4186 .label = "pcie_asic_reset_dis",
4187 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
4188 .mask = GENMASK(7, 0) & ~BIT(4),
4189 .mode = 0644,
4190 },
4191 {
4192 .label = "shutdown_unlock",
4193 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
4194 .mask = GENMASK(7, 0) & ~BIT(5),
4195 .mode = 0644,
4196 },
4197 {
4198 .label = "lc1_rst_mask",
4199 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
4200 .mask = GENMASK(7, 0) & ~BIT(0),
4201 .mode = 0200,
4202 },
4203 {
4204 .label = "lc2_rst_mask",
4205 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
4206 .mask = GENMASK(7, 0) & ~BIT(1),
4207 .mode = 0200,
4208 },
4209 {
4210 .label = "lc3_rst_mask",
4211 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
4212 .mask = GENMASK(7, 0) & ~BIT(2),
4213 .mode = 0200,
4214 },
4215 {
4216 .label = "lc4_rst_mask",
4217 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
4218 .mask = GENMASK(7, 0) & ~BIT(3),
4219 .mode = 0200,
4220 },
4221 {
4222 .label = "lc5_rst_mask",
4223 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
4224 .mask = GENMASK(7, 0) & ~BIT(4),
4225 .mode = 0200,
4226 },
4227 {
4228 .label = "lc6_rst_mask",
4229 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
4230 .mask = GENMASK(7, 0) & ~BIT(5),
4231 .mode = 0200,
4232 },
4233 {
4234 .label = "lc7_rst_mask",
4235 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
4236 .mask = GENMASK(7, 0) & ~BIT(6),
4237 .mode = 0200,
4238 },
4239 {
4240 .label = "lc8_rst_mask",
4241 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET,
4242 .mask = GENMASK(7, 0) & ~BIT(7),
4243 .mode = 0200,
4244 },
4245 {
4246 .label = "psu1_on",
4247 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4248 .mask = GENMASK(7, 0) & ~BIT(0),
4249 .mode = 0200,
4250 },
4251 {
4252 .label = "psu2_on",
4253 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4254 .mask = GENMASK(7, 0) & ~BIT(1),
4255 .mode = 0200,
4256 },
4257 {
4258 .label = "pwr_cycle",
4259 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4260 .mask = GENMASK(7, 0) & ~BIT(2),
4261 .mode = 0200,
4262 },
4263 {
4264 .label = "pwr_down",
4265 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4266 .mask = GENMASK(7, 0) & ~BIT(3),
4267 .mode = 0200,
4268 },
4269 {
4270 .label = "psu3_on",
4271 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4272 .mask = GENMASK(7, 0) & ~BIT(4),
4273 .mode = 0200,
4274 },
4275 {
4276 .label = "psu4_on",
4277 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4278 .mask = GENMASK(7, 0) & ~BIT(5),
4279 .mode = 0200,
4280 },
4281 {
4282 .label = "auto_power_mode",
4283 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4284 .mask = GENMASK(7, 0) & ~BIT(6),
4285 .mode = 0644,
4286 },
4287 {
4288 .label = "pm_mgmt_en",
4289 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4290 .mask = GENMASK(7, 0) & ~BIT(7),
4291 .mode = 0644,
4292 },
4293 {
4294 .label = "jtag_enable",
4295 .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE,
4296 .mask = GENMASK(3, 0),
4297 .bit = 1,
4298 .mode = 0644,
4299 },
4300 {
4301 .label = "safe_bios_dis",
4302 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET,
4303 .mask = GENMASK(7, 0) & ~BIT(5),
4304 .mode = 0644,
4305 },
4306 {
4307 .label = "safe_bios_dis_wp",
4308 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET,
4309 .mask = GENMASK(7, 0) & ~BIT(5),
4310 .mode = 0644,
4311 },
4312 {
4313 .label = "asic_health",
4314 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
4315 .mask = MLXPLAT_CPLD_ASIC_MASK,
4316 .bit = 1,
4317 .mode = 0444,
4318 },
4319 {
4320 .label = "fan_dir",
4321 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
4322 .bit = GENMASK(7, 0),
4323 .mode = 0444,
4324 },
4325 {
4326 .label = "lc1_pwr",
4327 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
4328 .mask = GENMASK(7, 0) & ~BIT(0),
4329 .mode = 0644,
4330 },
4331 {
4332 .label = "lc2_pwr",
4333 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
4334 .mask = GENMASK(7, 0) & ~BIT(1),
4335 .mode = 0644,
4336 },
4337 {
4338 .label = "lc3_pwr",
4339 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
4340 .mask = GENMASK(7, 0) & ~BIT(2),
4341 .mode = 0644,
4342 },
4343 {
4344 .label = "lc4_pwr",
4345 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
4346 .mask = GENMASK(7, 0) & ~BIT(3),
4347 .mode = 0644,
4348 },
4349 {
4350 .label = "lc5_pwr",
4351 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
4352 .mask = GENMASK(7, 0) & ~BIT(4),
4353 .mode = 0644,
4354 },
4355 {
4356 .label = "lc6_pwr",
4357 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
4358 .mask = GENMASK(7, 0) & ~BIT(5),
4359 .mode = 0644,
4360 },
4361 {
4362 .label = "lc7_pwr",
4363 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
4364 .mask = GENMASK(7, 0) & ~BIT(6),
4365 .mode = 0644,
4366 },
4367 {
4368 .label = "lc8_pwr",
4369 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON,
4370 .mask = GENMASK(7, 0) & ~BIT(7),
4371 .mode = 0644,
4372 },
4373 {
4374 .label = "config1",
4375 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET,
4376 .bit = GENMASK(7, 0),
4377 .mode = 0444,
4378 },
4379 {
4380 .label = "config2",
4381 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET,
4382 .bit = GENMASK(7, 0),
4383 .mode = 0444,
4384 },
4385 {
4386 .label = "config3",
4387 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET,
4388 .bit = GENMASK(7, 0),
4389 .mode = 0444,
4390 },
4391 {
4392 .label = "ufm_version",
4393 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET,
4394 .bit = GENMASK(7, 0),
4395 .mode = 0444,
4396 },
4397};
4398
4399static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = {
4400 .data = mlxplat_mlxcpld_modular_regs_io_data,
4401 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data),
4402};
4403
4404/* Platform register access for chassis blade systems family data */
4405static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = {
4406 {
4407 .label = "cpld1_version",
4408 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
4409 .bit = GENMASK(7, 0),
4410 .mode = 0444,
4411 },
4412 {
4413 .label = "cpld1_pn",
4414 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
4415 .bit = GENMASK(15, 0),
4416 .mode = 0444,
4417 .regnum = 2,
4418 },
4419 {
4420 .label = "cpld1_version_min",
4421 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
4422 .bit = GENMASK(7, 0),
4423 .mode = 0444,
4424 },
4425 {
4426 .label = "reset_aux_pwr_or_ref",
4427 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4428 .mask = GENMASK(7, 0) & ~BIT(2),
4429 .mode = 0444,
4430 },
4431 {
4432 .label = "reset_from_comex",
4433 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4434 .mask = GENMASK(7, 0) & ~BIT(4),
4435 .mode = 0444,
4436 },
4437 {
4438 .label = "reset_comex_pwr_fail",
4439 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4440 .mask = GENMASK(7, 0) & ~BIT(3),
4441 .mode = 0444,
4442 },
4443 {
4444 .label = "reset_platform",
4445 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4446 .mask = GENMASK(7, 0) & ~BIT(4),
4447 .mode = 0444,
4448 },
4449 {
4450 .label = "reset_soc",
4451 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4452 .mask = GENMASK(7, 0) & ~BIT(5),
4453 .mode = 0444,
4454 },
4455 {
4456 .label = "reset_comex_wd",
4457 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4458 .mask = GENMASK(7, 0) & ~BIT(6),
4459 .mode = 0444,
4460 },
4461 {
4462 .label = "reset_voltmon_upgrade_fail",
4463 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4464 .mask = GENMASK(7, 0) & ~BIT(0),
4465 .mode = 0444,
4466 },
4467 {
4468 .label = "reset_system",
4469 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4470 .mask = GENMASK(7, 0) & ~BIT(1),
4471 .mode = 0444,
4472 },
4473 {
4474 .label = "reset_sw_pwr_off",
4475 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4476 .mask = GENMASK(7, 0) & ~BIT(2),
4477 .mode = 0444,
4478 },
4479 {
4480 .label = "reset_comex_thermal",
4481 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4482 .mask = GENMASK(7, 0) & ~BIT(3),
4483 .mode = 0444,
4484 },
4485 {
4486 .label = "reset_reload_bios",
4487 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4488 .mask = GENMASK(7, 0) & ~BIT(5),
4489 .mode = 0444,
4490 },
4491 {
4492 .label = "reset_ac_pwr_fail",
4493 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4494 .mask = GENMASK(7, 0) & ~BIT(6),
4495 .mode = 0444,
4496 },
4497 {
4498 .label = "reset_long_pwr_pb",
4499 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4500 .mask = GENMASK(7, 0) & ~BIT(7),
4501 .mode = 0444,
4502 },
4503 {
4504 .label = "pwr_cycle",
4505 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4506 .mask = GENMASK(7, 0) & ~BIT(2),
4507 .mode = 0200,
4508 },
4509 {
4510 .label = "pwr_down",
4511 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4512 .mask = GENMASK(7, 0) & ~BIT(3),
4513 .mode = 0200,
4514 },
4515 {
4516 .label = "global_wp_request",
4517 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
4518 .mask = GENMASK(7, 0) & ~BIT(0),
4519 .mode = 0644,
4520 },
4521 {
4522 .label = "jtag_enable",
4523 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
4524 .mask = GENMASK(7, 0) & ~BIT(4),
4525 .mode = 0644,
4526 },
4527 {
4528 .label = "comm_chnl_ready",
4529 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
4530 .mask = GENMASK(7, 0) & ~BIT(6),
4531 .mode = 0200,
4532 },
4533 {
4534 .label = "bios_safe_mode",
4535 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4536 .mask = GENMASK(7, 0) & ~BIT(4),
4537 .mode = 0444,
4538 },
4539 {
4540 .label = "bios_active_image",
4541 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4542 .mask = GENMASK(7, 0) & ~BIT(5),
4543 .mode = 0444,
4544 },
4545 {
4546 .label = "bios_auth_fail",
4547 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4548 .mask = GENMASK(7, 0) & ~BIT(6),
4549 .mode = 0444,
4550 },
4551 {
4552 .label = "bios_upgrade_fail",
4553 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4554 .mask = GENMASK(7, 0) & ~BIT(7),
4555 .mode = 0444,
4556 },
4557 {
4558 .label = "voltreg_update_status",
4559 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET,
4560 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK,
4561 .bit = 5,
4562 .mode = 0444,
4563 },
4564 {
4565 .label = "vpd_wp",
4566 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
4567 .mask = GENMASK(7, 0) & ~BIT(3),
4568 .mode = 0644,
4569 },
4570 {
4571 .label = "pcie_asic_reset_dis",
4572 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
4573 .mask = GENMASK(7, 0) & ~BIT(4),
4574 .mode = 0644,
4575 },
4576 {
4577 .label = "global_wp_response",
4578 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET,
4579 .mask = GENMASK(7, 0) & ~BIT(0),
4580 .mode = 0444,
4581 },
4582 {
4583 .label = "config1",
4584 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET,
4585 .bit = GENMASK(7, 0),
4586 .mode = 0444,
4587 },
4588 {
4589 .label = "config2",
4590 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET,
4591 .bit = GENMASK(7, 0),
4592 .mode = 0444,
4593 },
4594 {
4595 .label = "config3",
4596 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET,
4597 .bit = GENMASK(7, 0),
4598 .mode = 0444,
4599 },
4600 {
4601 .label = "ufm_version",
4602 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET,
4603 .bit = GENMASK(7, 0),
4604 .mode = 0444,
4605 },
4606};
4607
4608static struct mlxreg_core_platform_data mlxplat_chassis_blade_regs_io_data = {
4609 .data = mlxplat_mlxcpld_chassis_blade_regs_io_data,
4610 .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_regs_io_data),
4611};
4612
4613/* Platform FAN default */
4614static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
4615 {
4616 .label = "pwm1",
4617 .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET,
4618 },
4619 {
4620 .label = "pwm2",
4621 .reg = MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET,
4622 },
4623 {
4624 .label = "pwm3",
4625 .reg = MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET,
4626 },
4627 {
4628 .label = "pwm4",
4629 .reg = MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET,
4630 },
4631 {
4632 .label = "tacho1",
4633 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET,
4634 .mask = GENMASK(7, 0),
4635 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
4636 .bit = BIT(0),
4637 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
4638
4639 },
4640 {
4641 .label = "tacho2",
4642 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET,
4643 .mask = GENMASK(7, 0),
4644 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
4645 .bit = BIT(1),
4646 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
4647 },
4648 {
4649 .label = "tacho3",
4650 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET,
4651 .mask = GENMASK(7, 0),
4652 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
4653 .bit = BIT(2),
4654 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
4655 },
4656 {
4657 .label = "tacho4",
4658 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET,
4659 .mask = GENMASK(7, 0),
4660 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
4661 .bit = BIT(3),
4662 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
4663 },
4664 {
4665 .label = "tacho5",
4666 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET,
4667 .mask = GENMASK(7, 0),
4668 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
4669 .bit = BIT(4),
4670 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
4671 },
4672 {
4673 .label = "tacho6",
4674 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET,
4675 .mask = GENMASK(7, 0),
4676 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
4677 .bit = BIT(5),
4678 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
4679 },
4680 {
4681 .label = "tacho7",
4682 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET,
4683 .mask = GENMASK(7, 0),
4684 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
4685 .bit = BIT(6),
4686 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
4687 },
4688 {
4689 .label = "tacho8",
4690 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET,
4691 .mask = GENMASK(7, 0),
4692 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
4693 .bit = BIT(7),
4694 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
4695 },
4696 {
4697 .label = "tacho9",
4698 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET,
4699 .mask = GENMASK(7, 0),
4700 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
4701 .bit = BIT(0),
4702 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
4703 },
4704 {
4705 .label = "tacho10",
4706 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET,
4707 .mask = GENMASK(7, 0),
4708 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
4709 .bit = BIT(1),
4710 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
4711 },
4712 {
4713 .label = "tacho11",
4714 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET,
4715 .mask = GENMASK(7, 0),
4716 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
4717 .bit = BIT(2),
4718 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
4719 },
4720 {
4721 .label = "tacho12",
4722 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET,
4723 .mask = GENMASK(7, 0),
4724 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
4725 .bit = BIT(3),
4726 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
4727 },
4728 {
4729 .label = "tacho13",
4730 .reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET,
4731 .mask = GENMASK(7, 0),
4732 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
4733 .bit = BIT(4),
4734 },
4735 {
4736 .label = "tacho14",
4737 .reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET,
4738 .mask = GENMASK(7, 0),
4739 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
4740 .bit = BIT(5),
4741 },
4742 {
4743 .label = "conf",
4744 .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET,
4745 },
4746};
4747
4748static struct mlxreg_core_platform_data mlxplat_default_fan_data = {
4749 .data = mlxplat_mlxcpld_default_fan_data,
4750 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data),
4751 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
4752};
4753
4754/* Watchdog type1: hardware implementation version1
4755 * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems).
4756 */
4757static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = {
4758 {
4759 .label = "action",
4760 .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET,
4761 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
4762 .bit = 0,
4763 },
4764 {
4765 .label = "timeout",
4766 .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET,
4767 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK,
4768 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
4769 },
4770 {
4771 .label = "ping",
4772 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET,
4773 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK,
4774 .bit = 0,
4775 },
4776 {
4777 .label = "reset",
4778 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4779 .mask = GENMASK(7, 0) & ~BIT(6),
4780 .bit = 6,
4781 },
4782};
4783
4784static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = {
4785 {
4786 .label = "action",
4787 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
4788 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
4789 .bit = 4,
4790 },
4791 {
4792 .label = "timeout",
4793 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
4794 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK,
4795 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
4796 },
4797 {
4798 .label = "ping",
4799 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET,
4800 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK,
4801 .bit = 1,
4802 },
4803};
4804
4805static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = {
4806 {
4807 .data = mlxplat_mlxcpld_wd_main_regs_type1,
4808 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type1),
4809 .version = MLX_WDT_TYPE1,
4810 .identity = "mlx-wdt-main",
4811 },
4812 {
4813 .data = mlxplat_mlxcpld_wd_aux_regs_type1,
4814 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type1),
4815 .version = MLX_WDT_TYPE1,
4816 .identity = "mlx-wdt-aux",
4817 },
4818};
4819
4820/* Watchdog type2: hardware implementation version 2
4821 * (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140).
4822 */
4823static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = {
4824 {
4825 .label = "action",
4826 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
4827 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
4828 .bit = 0,
4829 },
4830 {
4831 .label = "timeout",
4832 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
4833 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
4834 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
4835 },
4836 {
4837 .label = "timeleft",
4838 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET,
4839 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
4840 },
4841 {
4842 .label = "ping",
4843 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
4844 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
4845 .bit = 0,
4846 },
4847 {
4848 .label = "reset",
4849 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4850 .mask = GENMASK(7, 0) & ~BIT(6),
4851 .bit = 6,
4852 },
4853};
4854
4855static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = {
4856 {
4857 .label = "action",
4858 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
4859 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
4860 .bit = 4,
4861 },
4862 {
4863 .label = "timeout",
4864 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
4865 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
4866 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT,
4867 },
4868 {
4869 .label = "timeleft",
4870 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET,
4871 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
4872 },
4873 {
4874 .label = "ping",
4875 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
4876 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
4877 .bit = 4,
4878 },
4879};
4880
4881static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = {
4882 {
4883 .data = mlxplat_mlxcpld_wd_main_regs_type2,
4884 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type2),
4885 .version = MLX_WDT_TYPE2,
4886 .identity = "mlx-wdt-main",
4887 },
4888 {
4889 .data = mlxplat_mlxcpld_wd_aux_regs_type2,
4890 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type2),
4891 .version = MLX_WDT_TYPE2,
4892 .identity = "mlx-wdt-aux",
4893 },
4894};
4895
4896/* Watchdog type3: hardware implementation version 3
4897 * Can be on all systems. It's differentiated by WD capability bit.
4898 * Old systems (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140)
4899 * still have only one main watchdog.
4900 */
4901static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type3[] = {
4902 {
4903 .label = "action",
4904 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
4905 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
4906 .bit = 0,
4907 },
4908 {
4909 .label = "timeout",
4910 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
4911 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
4912 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT,
4913 },
4914 {
4915 .label = "timeleft",
4916 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET,
4917 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
4918 },
4919 {
4920 .label = "ping",
4921 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET,
4922 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK,
4923 .bit = 0,
4924 },
4925 {
4926 .label = "reset",
4927 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4928 .mask = GENMASK(7, 0) & ~BIT(6),
4929 .bit = 6,
4930 },
4931};
4932
4933static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type3[] = {
4934 {
4935 .label = "action",
4936 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
4937 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
4938 .bit = 4,
4939 },
4940 {
4941 .label = "timeout",
4942 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
4943 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
4944 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT,
4945 },
4946 {
4947 .label = "timeleft",
4948 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET,
4949 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK,
4950 },
4951 {
4952 .label = "ping",
4953 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET,
4954 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK,
4955 .bit = 4,
4956 },
4957};
4958
4959static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type3[] = {
4960 {
4961 .data = mlxplat_mlxcpld_wd_main_regs_type3,
4962 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type3),
4963 .version = MLX_WDT_TYPE3,
4964 .identity = "mlx-wdt-main",
4965 },
4966 {
4967 .data = mlxplat_mlxcpld_wd_aux_regs_type3,
4968 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type3),
4969 .version = MLX_WDT_TYPE3,
4970 .identity = "mlx-wdt-aux",
4971 },
4972};
4973
4974static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
4975{
4976 switch (reg) {
4977 case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET:
4978 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:
4979 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
4980 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
4981 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
4982 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
4983 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
4984 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:
4985 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:
4986 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:
4987 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET:
4988 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
4989 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
4990 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
4991 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:
4992 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE:
4993 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET:
4994 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
4995 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
4996 case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET:
4997 case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET:
4998 case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET:
4999 case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET:
5000 case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET:
5001 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
5002 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
5003 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
5004 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET:
5005 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET:
5006 case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET:
5007 case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET:
5008 case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET:
5009 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
5010 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
5011 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:
5012 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:
5013 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
5014 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
5015 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:
5016 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:
5017 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
5018 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
5019 case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET:
5020 case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET:
5021 case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET:
5022 case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET:
5023 case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET:
5024 case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET:
5025 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET:
5026 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET:
5027 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET:
5028 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET:
5029 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET:
5030 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET:
5031 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET:
5032 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET:
5033 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET:
5034 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET:
5035 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET:
5036 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET:
5037 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET:
5038 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET:
5039 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:
5040 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:
5041 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:
5042 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT:
5043 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
5044 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:
5045 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
5046 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:
5047 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
5048 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
5049 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:
5050 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
5051 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
5052 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
5053 case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET:
5054 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET:
5055 case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET:
5056 case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET:
5057 case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET:
5058 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
5059 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET:
5060 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET:
5061 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET:
5062 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
5063 return true;
5064 }
5065 return false;
5066}
5067
5068static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
5069{
5070 switch (reg) {
5071 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
5072 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
5073 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
5074 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
5075 case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET:
5076 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
5077 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET:
5078 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
5079 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET:
5080 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:
5081 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET:
5082 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
5083 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET:
5084 case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET:
5085 case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET:
5086 case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET:
5087 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:
5088 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
5089 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
5090 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
5091 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
5092 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
5093 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
5094 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
5095 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
5096 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:
5097 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:
5098 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
5099 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:
5100 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET:
5101 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:
5102 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET:
5103 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
5104 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
5105 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
5106 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:
5107 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE:
5108 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET:
5109 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
5110 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
5111 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
5112 case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET:
5113 case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET:
5114 case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET:
5115 case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET:
5116 case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET:
5117 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
5118 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
5119 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET:
5120 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
5121 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET:
5122 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
5123 case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET:
5124 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET:
5125 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET:
5126 case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET:
5127 case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET:
5128 case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET:
5129 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
5130 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
5131 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
5132 case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET:
5133 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:
5134 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:
5135 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
5136 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
5137 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
5138 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET:
5139 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:
5140 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:
5141 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
5142 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
5143 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
5144 case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET:
5145 case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET:
5146 case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET:
5147 case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET:
5148 case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET:
5149 case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET:
5150 case MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET:
5151 case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET:
5152 case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET:
5153 case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET:
5154 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET:
5155 case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET:
5156 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET:
5157 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET:
5158 case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET:
5159 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET:
5160 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET:
5161 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET:
5162 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET:
5163 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET:
5164 case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET:
5165 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET:
5166 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET:
5167 case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET:
5168 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET:
5169 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET:
5170 case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET:
5171 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET:
5172 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET:
5173 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET:
5174 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:
5175 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:
5176 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:
5177 case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET:
5178 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT:
5179 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:
5180 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:
5181 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:
5182 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:
5183 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
5184 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
5185 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:
5186 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
5187 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
5188 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:
5189 case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET:
5190 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET:
5191 case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET:
5192 case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET:
5193 case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET:
5194 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET:
5195 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:
5196 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
5197 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:
5198 case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET:
5199 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
5200 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET:
5201 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET:
5202 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET:
5203 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
5204 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
5205 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET:
5206 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET:
5207 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET:
5208 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET:
5209 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET:
5210 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET:
5211 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET:
5212 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET:
5213 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
5214 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
5215 case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET:
5216 case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET:
5217 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
5218 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
5219 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
5220 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
5221 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET:
5222 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET:
5223 case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET:
5224 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET:
5225 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET:
5226 case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET:
5227 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET:
5228 return true;
5229 }
5230 return false;
5231}
5232
5233static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
5234{
5235 switch (reg) {
5236 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
5237 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
5238 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
5239 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
5240 case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET:
5241 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:
5242 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET:
5243 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:
5244 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET:
5245 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:
5246 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET:
5247 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
5248 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET:
5249 case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET:
5250 case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET:
5251 case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET:
5252 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:
5253 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
5254 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
5255 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
5256 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:
5257 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:
5258 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
5259 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
5260 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
5261 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:
5262 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:
5263 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
5264 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:
5265 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET:
5266 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:
5267 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET:
5268 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
5269 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
5270 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE:
5271 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET:
5272 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
5273 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
5274 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
5275 case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET:
5276 case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET:
5277 case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET:
5278 case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET:
5279 case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET:
5280 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:
5281 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:
5282 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET:
5283 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:
5284 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET:
5285 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:
5286 case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET:
5287 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET:
5288 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET:
5289 case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET:
5290 case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET:
5291 case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET:
5292 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:
5293 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:
5294 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:
5295 case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET:
5296 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:
5297 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:
5298 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:
5299 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:
5300 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:
5301 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET:
5302 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:
5303 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:
5304 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:
5305 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:
5306 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:
5307 case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET:
5308 case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET:
5309 case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET:
5310 case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET:
5311 case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET:
5312 case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET:
5313 case MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET:
5314 case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET:
5315 case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET:
5316 case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET:
5317 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET:
5318 case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET:
5319 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET:
5320 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET:
5321 case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET:
5322 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET:
5323 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET:
5324 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET:
5325 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET:
5326 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET:
5327 case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET:
5328 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET:
5329 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET:
5330 case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET:
5331 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET:
5332 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET:
5333 case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET:
5334 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET:
5335 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET:
5336 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET:
5337 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:
5338 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:
5339 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:
5340 case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET:
5341 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT:
5342 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:
5343 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:
5344 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:
5345 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:
5346 case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET:
5347 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET:
5348 case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET:
5349 case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET:
5350 case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET:
5351 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET:
5352 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:
5353 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:
5354 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:
5355 case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET:
5356 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:
5357 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET:
5358 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET:
5359 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET:
5360 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:
5361 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:
5362 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET:
5363 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET:
5364 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET:
5365 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET:
5366 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET:
5367 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET:
5368 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET:
5369 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET:
5370 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
5371 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
5372 case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET:
5373 case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET:
5374 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
5375 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
5376 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
5377 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
5378 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET:
5379 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET:
5380 case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET:
5381 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET:
5382 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET:
5383 case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET:
5384 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET:
5385 return true;
5386 }
5387 return false;
5388}
5389
5390static const struct reg_default mlxplat_mlxcpld_regmap_default[] = {
5391 { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 },
5392 { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 },
5393 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
5394 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 },
5395};
5396
5397static const struct reg_default mlxplat_mlxcpld_regmap_ng[] = {
5398 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
5399 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 },
5400};
5401
5402static const struct reg_default mlxplat_mlxcpld_regmap_comex_default[] = {
5403 { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET,
5404 MLXPLAT_CPLD_LOW_AGGRCX_MASK },
5405 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
5406};
5407
5408static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = {
5409 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
5410 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 },
5411 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 },
5412 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 },
5413};
5414
5415static const struct reg_default mlxplat_mlxcpld_regmap_rack_switch[] = {
5416 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT },
5417 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 },
5418 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 },
5419 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 },
5420};
5421
5422static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = {
5423 { MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 0x61 },
5424 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 },
5425 { MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, 0x00 },
5426 { MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, 0x00 },
5427 { MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, 0x00 },
5428 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 },
5429 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 },
5430 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 },
5431 { MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET,
5432 MLXPLAT_CPLD_AGGR_MASK_LC_LOW },
5433};
5434
5435struct mlxplat_mlxcpld_regmap_context {
5436 void __iomem *base;
5437};
5438
5439static struct mlxplat_mlxcpld_regmap_context mlxplat_mlxcpld_regmap_ctx;
5440
5441static int
5442mlxplat_mlxcpld_reg_read(void *context, unsigned int reg, unsigned int *val)
5443{
5444 struct mlxplat_mlxcpld_regmap_context *ctx = context;
5445
5446 *val = ioread8(ctx->base + reg);
5447 return 0;
5448}
5449
5450static int
5451mlxplat_mlxcpld_reg_write(void *context, unsigned int reg, unsigned int val)
5452{
5453 struct mlxplat_mlxcpld_regmap_context *ctx = context;
5454
5455 iowrite8(val, ctx->base + reg);
5456 return 0;
5457}
5458
5459static const struct regmap_config mlxplat_mlxcpld_regmap_config = {
5460 .reg_bits = 8,
5461 .val_bits = 8,
5462 .max_register = 255,
5463 .cache_type = REGCACHE_FLAT,
5464 .writeable_reg = mlxplat_mlxcpld_writeable_reg,
5465 .readable_reg = mlxplat_mlxcpld_readable_reg,
5466 .volatile_reg = mlxplat_mlxcpld_volatile_reg,
5467 .reg_defaults = mlxplat_mlxcpld_regmap_default,
5468 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_default),
5469 .reg_read = mlxplat_mlxcpld_reg_read,
5470 .reg_write = mlxplat_mlxcpld_reg_write,
5471};
5472
5473static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng = {
5474 .reg_bits = 8,
5475 .val_bits = 8,
5476 .max_register = 255,
5477 .cache_type = REGCACHE_FLAT,
5478 .writeable_reg = mlxplat_mlxcpld_writeable_reg,
5479 .readable_reg = mlxplat_mlxcpld_readable_reg,
5480 .volatile_reg = mlxplat_mlxcpld_volatile_reg,
5481 .reg_defaults = mlxplat_mlxcpld_regmap_ng,
5482 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng),
5483 .reg_read = mlxplat_mlxcpld_reg_read,
5484 .reg_write = mlxplat_mlxcpld_reg_write,
5485};
5486
5487static const struct regmap_config mlxplat_mlxcpld_regmap_config_comex = {
5488 .reg_bits = 8,
5489 .val_bits = 8,
5490 .max_register = 255,
5491 .cache_type = REGCACHE_FLAT,
5492 .writeable_reg = mlxplat_mlxcpld_writeable_reg,
5493 .readable_reg = mlxplat_mlxcpld_readable_reg,
5494 .volatile_reg = mlxplat_mlxcpld_volatile_reg,
5495 .reg_defaults = mlxplat_mlxcpld_regmap_comex_default,
5496 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_comex_default),
5497 .reg_read = mlxplat_mlxcpld_reg_read,
5498 .reg_write = mlxplat_mlxcpld_reg_write,
5499};
5500
5501static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = {
5502 .reg_bits = 8,
5503 .val_bits = 8,
5504 .max_register = 255,
5505 .cache_type = REGCACHE_FLAT,
5506 .writeable_reg = mlxplat_mlxcpld_writeable_reg,
5507 .readable_reg = mlxplat_mlxcpld_readable_reg,
5508 .volatile_reg = mlxplat_mlxcpld_volatile_reg,
5509 .reg_defaults = mlxplat_mlxcpld_regmap_ng400,
5510 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng400),
5511 .reg_read = mlxplat_mlxcpld_reg_read,
5512 .reg_write = mlxplat_mlxcpld_reg_write,
5513};
5514
5515static const struct regmap_config mlxplat_mlxcpld_regmap_config_rack_switch = {
5516 .reg_bits = 8,
5517 .val_bits = 8,
5518 .max_register = 255,
5519 .cache_type = REGCACHE_FLAT,
5520 .writeable_reg = mlxplat_mlxcpld_writeable_reg,
5521 .readable_reg = mlxplat_mlxcpld_readable_reg,
5522 .volatile_reg = mlxplat_mlxcpld_volatile_reg,
5523 .reg_defaults = mlxplat_mlxcpld_regmap_rack_switch,
5524 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_rack_switch),
5525 .reg_read = mlxplat_mlxcpld_reg_read,
5526 .reg_write = mlxplat_mlxcpld_reg_write,
5527};
5528
5529static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = {
5530 .reg_bits = 8,
5531 .val_bits = 8,
5532 .max_register = 255,
5533 .cache_type = REGCACHE_FLAT,
5534 .writeable_reg = mlxplat_mlxcpld_writeable_reg,
5535 .readable_reg = mlxplat_mlxcpld_readable_reg,
5536 .volatile_reg = mlxplat_mlxcpld_volatile_reg,
5537 .reg_defaults = mlxplat_mlxcpld_regmap_eth_modular,
5538 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_eth_modular),
5539 .reg_read = mlxplat_mlxcpld_reg_read,
5540 .reg_write = mlxplat_mlxcpld_reg_write,
5541};
5542
5543static struct resource mlxplat_mlxcpld_resources[] = {
5544 [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"),
5545};
5546
5547static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c;
5548static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug;
5549static struct mlxreg_core_platform_data *mlxplat_led;
5550static struct mlxreg_core_platform_data *mlxplat_regs_io;
5551static struct mlxreg_core_platform_data *mlxplat_fan;
5552static struct mlxreg_core_platform_data
5553 *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS];
5554static const struct regmap_config *mlxplat_regmap_config;
5555static struct pci_dev *lpc_bridge;
5556static struct pci_dev *i2c_bridge;
5557static struct pci_dev *jtag_bridge;
5558
5559/* Platform default reset function */
5560static int mlxplat_reboot_notifier(struct notifier_block *nb, unsigned long action, void *unused)
5561{
5562 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
5563 u32 regval;
5564 int ret;
5565
5566 ret = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, ®val);
5567
5568 if (action == SYS_RESTART && !ret && regval & MLXPLAT_CPLD_SYS_RESET_MASK)
5569 regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET,
5570 MLXPLAT_CPLD_RESET_MASK);
5571
5572 return NOTIFY_DONE;
5573}
5574
5575static struct notifier_block mlxplat_reboot_default_nb = {
5576 .notifier_call = mlxplat_reboot_notifier,
5577};
5578
5579/* Platform default poweroff function */
5580static void mlxplat_poweroff(void)
5581{
5582 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
5583
5584 if (mlxplat_reboot_nb)
5585 unregister_reboot_notifier(mlxplat_reboot_nb);
5586 regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, MLXPLAT_CPLD_HALT_MASK);
5587 kernel_halt();
5588}
5589
5590static int __init mlxplat_register_platform_device(void)
5591{
5592 mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1,
5593 mlxplat_lpc_resources,
5594 ARRAY_SIZE(mlxplat_lpc_resources));
5595 if (IS_ERR(mlxplat_dev))
5596 return PTR_ERR(mlxplat_dev);
5597 else
5598 return 1;
5599}
5600
5601static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
5602{
5603 int i;
5604
5605 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
5606 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
5607 mlxplat_mux_data = mlxplat_default_mux_data;
5608 for (i = 0; i < mlxplat_mux_num; i++) {
5609 mlxplat_mux_data[i].values = mlxplat_default_channels[i];
5610 mlxplat_mux_data[i].n_values =
5611 ARRAY_SIZE(mlxplat_default_channels[i]);
5612 }
5613 mlxplat_hotplug = &mlxplat_mlxcpld_default_data;
5614 mlxplat_hotplug->deferred_nr =
5615 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
5616 mlxplat_led = &mlxplat_default_led_data;
5617 mlxplat_regs_io = &mlxplat_default_regs_io_data;
5618 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
5619 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data;
5620
5621 return mlxplat_register_platform_device();
5622}
5623
5624static int __init mlxplat_dmi_default_wc_matched(const struct dmi_system_id *dmi)
5625{
5626 int i;
5627
5628 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
5629 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
5630 mlxplat_mux_data = mlxplat_default_mux_data;
5631 for (i = 0; i < mlxplat_mux_num; i++) {
5632 mlxplat_mux_data[i].values = mlxplat_default_channels[i];
5633 mlxplat_mux_data[i].n_values =
5634 ARRAY_SIZE(mlxplat_default_channels[i]);
5635 }
5636 mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data;
5637 mlxplat_hotplug->deferred_nr =
5638 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
5639 mlxplat_led = &mlxplat_default_led_wc_data;
5640 mlxplat_regs_io = &mlxplat_default_regs_io_data;
5641 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
5642 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data;
5643
5644 return mlxplat_register_platform_device();
5645}
5646
5647static int __init mlxplat_dmi_default_eth_wc_blade_matched(const struct dmi_system_id *dmi)
5648{
5649 int i;
5650
5651 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
5652 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
5653 mlxplat_mux_data = mlxplat_default_mux_data;
5654 for (i = 0; i < mlxplat_mux_num; i++) {
5655 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
5656 mlxplat_mux_data[i].n_values =
5657 ARRAY_SIZE(mlxplat_msn21xx_channels);
5658 }
5659 mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data;
5660 mlxplat_hotplug->deferred_nr =
5661 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
5662 mlxplat_led = &mlxplat_default_led_eth_wc_blade_data;
5663 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
5664 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
5665 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
5666 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
5667 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng;
5668
5669 return mlxplat_register_platform_device();
5670}
5671
5672static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi)
5673{
5674 int i;
5675
5676 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
5677 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
5678 mlxplat_mux_data = mlxplat_default_mux_data;
5679 for (i = 0; i < mlxplat_mux_num; i++) {
5680 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
5681 mlxplat_mux_data[i].n_values =
5682 ARRAY_SIZE(mlxplat_msn21xx_channels);
5683 }
5684 mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data;
5685 mlxplat_hotplug->deferred_nr =
5686 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
5687 mlxplat_led = &mlxplat_msn21xx_led_data;
5688 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
5689 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
5690 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data;
5691
5692 return mlxplat_register_platform_device();
5693}
5694
5695static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi)
5696{
5697 int i;
5698
5699 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
5700 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
5701 mlxplat_mux_data = mlxplat_default_mux_data;
5702 for (i = 0; i < mlxplat_mux_num; i++) {
5703 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
5704 mlxplat_mux_data[i].n_values =
5705 ARRAY_SIZE(mlxplat_msn21xx_channels);
5706 }
5707 mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data;
5708 mlxplat_hotplug->deferred_nr =
5709 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
5710 mlxplat_led = &mlxplat_default_led_data;
5711 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
5712 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
5713 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data;
5714
5715 return mlxplat_register_platform_device();
5716}
5717
5718static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi)
5719{
5720 int i;
5721
5722 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
5723 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
5724 mlxplat_mux_data = mlxplat_default_mux_data;
5725 for (i = 0; i < mlxplat_mux_num; i++) {
5726 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
5727 mlxplat_mux_data[i].n_values =
5728 ARRAY_SIZE(mlxplat_msn21xx_channels);
5729 }
5730 mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data;
5731 mlxplat_hotplug->deferred_nr =
5732 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
5733 mlxplat_led = &mlxplat_msn21xx_led_data;
5734 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data;
5735 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0];
5736 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data;
5737
5738 return mlxplat_register_platform_device();
5739}
5740
5741static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi)
5742{
5743 int i;
5744
5745 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
5746 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
5747 mlxplat_mux_data = mlxplat_default_mux_data;
5748 for (i = 0; i < mlxplat_mux_num; i++) {
5749 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
5750 mlxplat_mux_data[i].n_values =
5751 ARRAY_SIZE(mlxplat_msn21xx_channels);
5752 }
5753 mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data;
5754 mlxplat_hotplug->deferred_nr =
5755 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
5756 mlxplat_led = &mlxplat_default_ng_led_data;
5757 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
5758 mlxplat_fan = &mlxplat_default_fan_data;
5759 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
5760 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
5761 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
5762 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng;
5763
5764 return mlxplat_register_platform_device();
5765}
5766
5767static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi)
5768{
5769 int i;
5770
5771 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM;
5772 mlxplat_mux_num = ARRAY_SIZE(mlxplat_extended_mux_data);
5773 mlxplat_mux_data = mlxplat_extended_mux_data;
5774 for (i = 0; i < mlxplat_mux_num; i++) {
5775 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
5776 mlxplat_mux_data[i].n_values =
5777 ARRAY_SIZE(mlxplat_msn21xx_channels);
5778 }
5779 mlxplat_hotplug = &mlxplat_mlxcpld_comex_data;
5780 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM;
5781 mlxplat_led = &mlxplat_comex_100G_led_data;
5782 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
5783 mlxplat_fan = &mlxplat_default_fan_data;
5784 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
5785 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
5786 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data;
5787 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex;
5788
5789 return mlxplat_register_platform_device();
5790}
5791
5792static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi)
5793{
5794 int i;
5795
5796 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
5797 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
5798 mlxplat_mux_data = mlxplat_default_mux_data;
5799 for (i = 0; i < mlxplat_mux_num; i++) {
5800 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
5801 mlxplat_mux_data[i].n_values =
5802 ARRAY_SIZE(mlxplat_msn21xx_channels);
5803 }
5804 mlxplat_hotplug = &mlxplat_mlxcpld_ext_data;
5805 mlxplat_hotplug->deferred_nr =
5806 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
5807 mlxplat_led = &mlxplat_default_ng_led_data;
5808 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
5809 mlxplat_fan = &mlxplat_default_fan_data;
5810 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
5811 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
5812 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
5813 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400;
5814
5815 return mlxplat_register_platform_device();
5816}
5817
5818static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi)
5819{
5820 int i;
5821
5822 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
5823 mlxplat_mux_num = ARRAY_SIZE(mlxplat_modular_mux_data);
5824 mlxplat_mux_data = mlxplat_modular_mux_data;
5825 mlxplat_hotplug = &mlxplat_mlxcpld_modular_data;
5826 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR;
5827 mlxplat_led = &mlxplat_modular_led_data;
5828 mlxplat_regs_io = &mlxplat_modular_regs_io_data;
5829 mlxplat_fan = &mlxplat_default_fan_data;
5830 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
5831 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
5832 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
5833 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_eth_modular;
5834
5835 return mlxplat_register_platform_device();
5836}
5837
5838static int __init mlxplat_dmi_chassis_blade_matched(const struct dmi_system_id *dmi)
5839{
5840 int i;
5841
5842 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
5843 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
5844 mlxplat_mux_data = mlxplat_default_mux_data;
5845 mlxplat_hotplug = &mlxplat_mlxcpld_chassis_blade_data;
5846 mlxplat_hotplug->deferred_nr =
5847 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
5848 for (i = 0; i < mlxplat_mux_num; i++) {
5849 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
5850 mlxplat_mux_data[i].n_values =
5851 ARRAY_SIZE(mlxplat_msn21xx_channels);
5852 }
5853 mlxplat_regs_io = &mlxplat_chassis_blade_regs_io_data;
5854 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
5855 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400;
5856
5857 return mlxplat_register_platform_device();
5858}
5859
5860static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dmi)
5861{
5862 int i;
5863
5864 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
5865 mlxplat_mux_num = ARRAY_SIZE(mlxplat_rack_switch_mux_data);
5866 mlxplat_mux_data = mlxplat_rack_switch_mux_data;
5867 mlxplat_hotplug = &mlxplat_mlxcpld_rack_switch_data;
5868 mlxplat_hotplug->deferred_nr =
5869 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
5870 mlxplat_led = &mlxplat_default_ng_led_data;
5871 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
5872 mlxplat_fan = &mlxplat_default_fan_data;
5873 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
5874 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
5875 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
5876 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch;
5877
5878 return mlxplat_register_platform_device();
5879}
5880
5881static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi)
5882{
5883 int i;
5884
5885 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
5886 mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data);
5887 mlxplat_mux_data = mlxplat_ng800_mux_data;
5888 mlxplat_hotplug = &mlxplat_mlxcpld_ng800_data;
5889 mlxplat_hotplug->deferred_nr =
5890 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
5891 mlxplat_led = &mlxplat_default_ng_led_data;
5892 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
5893 mlxplat_fan = &mlxplat_default_fan_data;
5894 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
5895 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
5896 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
5897 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400;
5898
5899 return mlxplat_register_platform_device();
5900}
5901
5902static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi)
5903{
5904 int i;
5905
5906 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
5907 mlxplat_mux_num = ARRAY_SIZE(mlxplat_rack_switch_mux_data);
5908 mlxplat_mux_data = mlxplat_rack_switch_mux_data;
5909 mlxplat_hotplug = &mlxplat_mlxcpld_l1_switch_data;
5910 mlxplat_hotplug->deferred_nr =
5911 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
5912 mlxplat_led = &mlxplat_l1_switch_led_data;
5913 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data;
5914 mlxplat_fan = &mlxplat_default_fan_data;
5915 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
5916 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
5917 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
5918 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch;
5919 pm_power_off = mlxplat_poweroff;
5920 mlxplat_reboot_nb = &mlxplat_reboot_default_nb;
5921
5922 return mlxplat_register_platform_device();
5923}
5924
5925static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
5926 {
5927 .callback = mlxplat_dmi_default_wc_matched,
5928 .matches = {
5929 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"),
5930 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI138"),
5931 },
5932 },
5933 {
5934 .callback = mlxplat_dmi_default_matched,
5935 .matches = {
5936 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"),
5937 },
5938 },
5939 {
5940 .callback = mlxplat_dmi_msn21xx_matched,
5941 .matches = {
5942 DMI_MATCH(DMI_BOARD_NAME, "VMOD0002"),
5943 },
5944 },
5945 {
5946 .callback = mlxplat_dmi_msn274x_matched,
5947 .matches = {
5948 DMI_MATCH(DMI_BOARD_NAME, "VMOD0003"),
5949 },
5950 },
5951 {
5952 .callback = mlxplat_dmi_msn201x_matched,
5953 .matches = {
5954 DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"),
5955 },
5956 },
5957 {
5958 .callback = mlxplat_dmi_default_eth_wc_blade_matched,
5959 .matches = {
5960 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"),
5961 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI139"),
5962 },
5963 },
5964 {
5965 .callback = mlxplat_dmi_qmb7xx_matched,
5966 .matches = {
5967 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"),
5968 },
5969 },
5970 {
5971 .callback = mlxplat_dmi_qmb7xx_matched,
5972 .matches = {
5973 DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"),
5974 },
5975 },
5976 {
5977 .callback = mlxplat_dmi_comex_matched,
5978 .matches = {
5979 DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"),
5980 },
5981 },
5982 {
5983 .callback = mlxplat_dmi_rack_switch_matched,
5984 .matches = {
5985 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"),
5986 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI142"),
5987 },
5988 },
5989 {
5990 .callback = mlxplat_dmi_ng400_matched,
5991 .matches = {
5992 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"),
5993 },
5994 },
5995 {
5996 .callback = mlxplat_dmi_modular_matched,
5997 .matches = {
5998 DMI_MATCH(DMI_BOARD_NAME, "VMOD0011"),
5999 },
6000 },
6001 {
6002 .callback = mlxplat_dmi_ng800_matched,
6003 .matches = {
6004 DMI_MATCH(DMI_BOARD_NAME, "VMOD0013"),
6005 },
6006 },
6007 {
6008 .callback = mlxplat_dmi_chassis_blade_matched,
6009 .matches = {
6010 DMI_MATCH(DMI_BOARD_NAME, "VMOD0015"),
6011 },
6012 },
6013 {
6014 .callback = mlxplat_dmi_l1_switch_matched,
6015 .matches = {
6016 DMI_MATCH(DMI_BOARD_NAME, "VMOD0017"),
6017 },
6018 },
6019 {
6020 .callback = mlxplat_dmi_msn274x_matched,
6021 .matches = {
6022 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
6023 DMI_MATCH(DMI_PRODUCT_NAME, "MSN274"),
6024 },
6025 },
6026 {
6027 .callback = mlxplat_dmi_default_matched,
6028 .matches = {
6029 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
6030 DMI_MATCH(DMI_PRODUCT_NAME, "MSN24"),
6031 },
6032 },
6033 {
6034 .callback = mlxplat_dmi_default_matched,
6035 .matches = {
6036 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
6037 DMI_MATCH(DMI_PRODUCT_NAME, "MSN27"),
6038 },
6039 },
6040 {
6041 .callback = mlxplat_dmi_default_matched,
6042 .matches = {
6043 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
6044 DMI_MATCH(DMI_PRODUCT_NAME, "MSB"),
6045 },
6046 },
6047 {
6048 .callback = mlxplat_dmi_default_matched,
6049 .matches = {
6050 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
6051 DMI_MATCH(DMI_PRODUCT_NAME, "MSX"),
6052 },
6053 },
6054 {
6055 .callback = mlxplat_dmi_msn21xx_matched,
6056 .matches = {
6057 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
6058 DMI_MATCH(DMI_PRODUCT_NAME, "MSN21"),
6059 },
6060 },
6061 {
6062 .callback = mlxplat_dmi_msn201x_matched,
6063 .matches = {
6064 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
6065 DMI_MATCH(DMI_PRODUCT_NAME, "MSN201"),
6066 },
6067 },
6068 {
6069 .callback = mlxplat_dmi_qmb7xx_matched,
6070 .matches = {
6071 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
6072 DMI_MATCH(DMI_PRODUCT_NAME, "MQM87"),
6073 },
6074 },
6075 {
6076 .callback = mlxplat_dmi_qmb7xx_matched,
6077 .matches = {
6078 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
6079 DMI_MATCH(DMI_PRODUCT_NAME, "MSN37"),
6080 },
6081 },
6082 {
6083 .callback = mlxplat_dmi_qmb7xx_matched,
6084 .matches = {
6085 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
6086 DMI_MATCH(DMI_PRODUCT_NAME, "MSN34"),
6087 },
6088 },
6089 {
6090 .callback = mlxplat_dmi_qmb7xx_matched,
6091 .matches = {
6092 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
6093 DMI_MATCH(DMI_PRODUCT_NAME, "MSN38"),
6094 },
6095 },
6096 { }
6097};
6098
6099MODULE_DEVICE_TABLE(dmi, mlxplat_dmi_table);
6100
6101static int mlxplat_mlxcpld_verify_bus_topology(int *nr)
6102{
6103 struct i2c_adapter *search_adap;
6104 int i, shift = 0;
6105
6106 /* Scan adapters from expected id to verify it is free. */
6107 *nr = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR;
6108 for (i = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; i <
6109 mlxplat_max_adap_num; i++) {
6110 search_adap = i2c_get_adapter(i);
6111 if (search_adap) {
6112 i2c_put_adapter(search_adap);
6113 continue;
6114 }
6115
6116 /* Return if expected parent adapter is free. */
6117 if (i == MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR)
6118 return 0;
6119 break;
6120 }
6121
6122 /* Return with error if free id for adapter is not found. */
6123 if (i == mlxplat_max_adap_num)
6124 return -ENODEV;
6125
6126 /* Shift adapter ids, since expected parent adapter is not free. */
6127 *nr = i;
6128 for (i = 0; i < mlxplat_mux_num; i++) {
6129 shift = *nr - mlxplat_mux_data[i].parent;
6130 mlxplat_mux_data[i].parent = *nr;
6131 mlxplat_mux_data[i].base_nr += shift;
6132 }
6133
6134 if (shift > 0)
6135 mlxplat_hotplug->shift_nr = shift;
6136
6137 return 0;
6138}
6139
6140static int mlxplat_mlxcpld_check_wd_capability(void *regmap)
6141{
6142 u32 regval;
6143 int i, rc;
6144
6145 rc = regmap_read(regmap, MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET,
6146 ®val);
6147 if (rc)
6148 return rc;
6149
6150 if (!(regval & ~MLXPLAT_CPLD_WD_CPBLTY_MASK)) {
6151 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) {
6152 if (mlxplat_wd_data[i])
6153 mlxplat_wd_data[i] =
6154 &mlxplat_mlxcpld_wd_set_type3[i];
6155 }
6156 }
6157
6158 return 0;
6159}
6160
6161static int mlxplat_lpc_cpld_device_init(struct resource **hotplug_resources,
6162 unsigned int *hotplug_resources_size)
6163{
6164 int err;
6165
6166 mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev,
6167 mlxplat_lpc_resources[1].start, 1);
6168 if (!mlxplat_mlxcpld_regmap_ctx.base) {
6169 err = -ENOMEM;
6170 goto fail_devm_ioport_map;
6171 }
6172
6173 *hotplug_resources = mlxplat_mlxcpld_resources;
6174 *hotplug_resources_size = ARRAY_SIZE(mlxplat_mlxcpld_resources);
6175
6176 return 0;
6177
6178fail_devm_ioport_map:
6179 return err;
6180}
6181
6182static void mlxplat_lpc_cpld_device_exit(void)
6183{
6184}
6185
6186static int
6187mlxplat_pci_fpga_device_init(unsigned int device, const char *res_name, struct pci_dev **pci_bridge,
6188 void __iomem **pci_bridge_addr)
6189{
6190 void __iomem *pci_mem_addr;
6191 struct pci_dev *pci_dev;
6192 int err;
6193
6194 pci_dev = pci_get_device(PCI_VENDOR_ID_LATTICE, device, NULL);
6195 if (!pci_dev)
6196 return -ENODEV;
6197
6198 err = pci_enable_device(pci_dev);
6199 if (err) {
6200 dev_err(&pci_dev->dev, "pci_enable_device failed with error %d\n", err);
6201 goto fail_pci_enable_device;
6202 }
6203
6204 err = pci_request_region(pci_dev, 0, res_name);
6205 if (err) {
6206 dev_err(&pci_dev->dev, "pci_request_regions failed with error %d\n", err);
6207 goto fail_pci_request_regions;
6208 }
6209
6210 err = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(64));
6211 if (err) {
6212 err = dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32));
6213 if (err) {
6214 dev_err(&pci_dev->dev, "dma_set_mask failed with error %d\n", err);
6215 goto fail_pci_set_dma_mask;
6216 }
6217 }
6218
6219 pci_set_master(pci_dev);
6220
6221 pci_mem_addr = devm_ioremap(&pci_dev->dev, pci_resource_start(pci_dev, 0),
6222 pci_resource_len(pci_dev, 0));
6223 if (!pci_mem_addr) {
6224 dev_err(&mlxplat_dev->dev, "ioremap failed\n");
6225 err = -EIO;
6226 goto fail_ioremap;
6227 }
6228
6229 *pci_bridge = pci_dev;
6230 *pci_bridge_addr = pci_mem_addr;
6231
6232 return 0;
6233
6234fail_ioremap:
6235fail_pci_set_dma_mask:
6236 pci_release_regions(pci_dev);
6237fail_pci_request_regions:
6238 pci_disable_device(pci_dev);
6239fail_pci_enable_device:
6240 return err;
6241}
6242
6243static void
6244mlxplat_pci_fpga_device_exit(struct pci_dev *pci_bridge,
6245 void __iomem *pci_bridge_addr)
6246{
6247 iounmap(pci_bridge_addr);
6248 pci_release_regions(pci_bridge);
6249 pci_disable_device(pci_bridge);
6250}
6251
6252static int
6253mlxplat_pci_fpga_devices_init(struct resource **hotplug_resources,
6254 unsigned int *hotplug_resources_size)
6255{
6256 int err;
6257
6258 err = mlxplat_pci_fpga_device_init(PCI_DEVICE_ID_LATTICE_LPC_BRIDGE,
6259 "mlxplat_lpc_bridge", &lpc_bridge,
6260 &mlxplat_mlxcpld_regmap_ctx.base);
6261 if (err)
6262 goto mlxplat_pci_fpga_device_init_lpc_fail;
6263
6264 err = mlxplat_pci_fpga_device_init(PCI_DEVICE_ID_LATTICE_I2C_BRIDGE,
6265 "mlxplat_i2c_bridge", &i2c_bridge,
6266 &i2c_bridge_addr);
6267 if (err)
6268 goto mlxplat_pci_fpga_device_init_i2c_fail;
6269
6270 err = mlxplat_pci_fpga_device_init(PCI_DEVICE_ID_LATTICE_JTAG_BRIDGE,
6271 "mlxplat_jtag_bridge", &jtag_bridge,
6272 &jtag_bridge_addr);
6273 if (err)
6274 goto mlxplat_pci_fpga_device_init_jtag_fail;
6275
6276 return 0;
6277
6278mlxplat_pci_fpga_device_init_jtag_fail:
6279 mlxplat_pci_fpga_device_exit(i2c_bridge, i2c_bridge_addr);
6280mlxplat_pci_fpga_device_init_i2c_fail:
6281 mlxplat_pci_fpga_device_exit(lpc_bridge, mlxplat_mlxcpld_regmap_ctx.base);
6282mlxplat_pci_fpga_device_init_lpc_fail:
6283 return err;
6284}
6285
6286static void mlxplat_pci_fpga_devices_exit(void)
6287{
6288 mlxplat_pci_fpga_device_exit(jtag_bridge, jtag_bridge_addr);
6289 mlxplat_pci_fpga_device_exit(i2c_bridge, i2c_bridge_addr);
6290 mlxplat_pci_fpga_device_exit(lpc_bridge, mlxplat_mlxcpld_regmap_ctx.base);
6291}
6292
6293static int
6294mlxplat_logicdev_init(struct resource **hotplug_resources, unsigned int *hotplug_resources_size)
6295{
6296 int err;
6297
6298 err = mlxplat_pci_fpga_devices_init(hotplug_resources, hotplug_resources_size);
6299 if (err == -ENODEV)
6300 return mlxplat_lpc_cpld_device_init(hotplug_resources, hotplug_resources_size);
6301
6302 return err;
6303}
6304
6305static void mlxplat_logicdev_exit(void)
6306{
6307 if (lpc_bridge)
6308 mlxplat_pci_fpga_devices_exit();
6309 else
6310 mlxplat_lpc_cpld_device_exit();
6311}
6312
6313static int mlxplat_platdevs_init(struct mlxplat_priv *priv)
6314{
6315 int i = 0, err;
6316
6317 /* Add hotplug driver */
6318 if (mlxplat_hotplug) {
6319 mlxplat_hotplug->regmap = priv->regmap;
6320 if (priv->irq_fpga)
6321 mlxplat_hotplug->irq = priv->irq_fpga;
6322 priv->pdev_hotplug =
6323 platform_device_register_resndata(&mlxplat_dev->dev,
6324 "mlxreg-hotplug", PLATFORM_DEVID_NONE,
6325 priv->hotplug_resources,
6326 priv->hotplug_resources_size,
6327 mlxplat_hotplug, sizeof(*mlxplat_hotplug));
6328 if (IS_ERR(priv->pdev_hotplug)) {
6329 err = PTR_ERR(priv->pdev_hotplug);
6330 goto fail_platform_hotplug_register;
6331 }
6332 }
6333
6334 /* Add LED driver. */
6335 if (mlxplat_led) {
6336 mlxplat_led->regmap = priv->regmap;
6337 priv->pdev_led =
6338 platform_device_register_resndata(&mlxplat_dev->dev, "leds-mlxreg",
6339 PLATFORM_DEVID_NONE, NULL, 0, mlxplat_led,
6340 sizeof(*mlxplat_led));
6341 if (IS_ERR(priv->pdev_led)) {
6342 err = PTR_ERR(priv->pdev_led);
6343 goto fail_platform_leds_register;
6344 }
6345 }
6346
6347 /* Add registers io access driver. */
6348 if (mlxplat_regs_io) {
6349 mlxplat_regs_io->regmap = priv->regmap;
6350 priv->pdev_io_regs = platform_device_register_resndata(&mlxplat_dev->dev,
6351 "mlxreg-io",
6352 PLATFORM_DEVID_NONE, NULL,
6353 0, mlxplat_regs_io,
6354 sizeof(*mlxplat_regs_io));
6355 if (IS_ERR(priv->pdev_io_regs)) {
6356 err = PTR_ERR(priv->pdev_io_regs);
6357 goto fail_platform_io_register;
6358 }
6359 }
6360
6361 /* Add FAN driver. */
6362 if (mlxplat_fan) {
6363 mlxplat_fan->regmap = priv->regmap;
6364 priv->pdev_fan = platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-fan",
6365 PLATFORM_DEVID_NONE, NULL, 0,
6366 mlxplat_fan,
6367 sizeof(*mlxplat_fan));
6368 if (IS_ERR(priv->pdev_fan)) {
6369 err = PTR_ERR(priv->pdev_fan);
6370 goto fail_platform_fan_register;
6371 }
6372 }
6373
6374 /* Add WD drivers. */
6375 err = mlxplat_mlxcpld_check_wd_capability(priv->regmap);
6376 if (err)
6377 goto fail_platform_wd_register;
6378 for (i = 0; i < MLXPLAT_CPLD_WD_MAX_DEVS; i++) {
6379 if (mlxplat_wd_data[i]) {
6380 mlxplat_wd_data[i]->regmap = priv->regmap;
6381 priv->pdev_wd[i] =
6382 platform_device_register_resndata(&mlxplat_dev->dev, "mlx-wdt", i,
6383 NULL, 0, mlxplat_wd_data[i],
6384 sizeof(*mlxplat_wd_data[i]));
6385 if (IS_ERR(priv->pdev_wd[i])) {
6386 err = PTR_ERR(priv->pdev_wd[i]);
6387 goto fail_platform_wd_register;
6388 }
6389 }
6390 }
6391
6392 return 0;
6393
6394fail_platform_wd_register:
6395 while (--i >= 0)
6396 platform_device_unregister(priv->pdev_wd[i]);
6397fail_platform_fan_register:
6398 if (mlxplat_regs_io)
6399 platform_device_unregister(priv->pdev_io_regs);
6400fail_platform_io_register:
6401 if (mlxplat_led)
6402 platform_device_unregister(priv->pdev_led);
6403fail_platform_leds_register:
6404 if (mlxplat_hotplug)
6405 platform_device_unregister(priv->pdev_hotplug);
6406fail_platform_hotplug_register:
6407 return err;
6408}
6409
6410static void mlxplat_platdevs_exit(struct mlxplat_priv *priv)
6411{
6412 int i;
6413
6414 for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--)
6415 platform_device_unregister(priv->pdev_wd[i]);
6416 if (priv->pdev_fan)
6417 platform_device_unregister(priv->pdev_fan);
6418 if (priv->pdev_io_regs)
6419 platform_device_unregister(priv->pdev_io_regs);
6420 if (priv->pdev_led)
6421 platform_device_unregister(priv->pdev_led);
6422 if (priv->pdev_hotplug)
6423 platform_device_unregister(priv->pdev_hotplug);
6424}
6425
6426static int
6427mlxplat_i2c_mux_complition_notify(void *handle, struct i2c_adapter *parent,
6428 struct i2c_adapter *adapters[])
6429{
6430 struct mlxplat_priv *priv = handle;
6431
6432 return mlxplat_platdevs_init(priv);
6433}
6434
6435static int mlxplat_i2c_mux_topology_init(struct mlxplat_priv *priv)
6436{
6437 int i, err;
6438
6439 if (!priv->pdev_i2c) {
6440 priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_NOTIFIED;
6441 return 0;
6442 }
6443
6444 priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED;
6445 for (i = 0; i < mlxplat_mux_num; i++) {
6446 priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev,
6447 "i2c-mux-reg", i, NULL, 0,
6448 &mlxplat_mux_data[i],
6449 sizeof(mlxplat_mux_data[i]));
6450 if (IS_ERR(priv->pdev_mux[i])) {
6451 err = PTR_ERR(priv->pdev_mux[i]);
6452 goto fail_platform_mux_register;
6453 }
6454 }
6455
6456 return mlxplat_i2c_mux_complition_notify(priv, NULL, NULL);
6457
6458fail_platform_mux_register:
6459 while (--i >= 0)
6460 platform_device_unregister(priv->pdev_mux[i]);
6461 return err;
6462}
6463
6464static void mlxplat_i2c_mux_topology_exit(struct mlxplat_priv *priv)
6465{
6466 int i;
6467
6468 for (i = mlxplat_mux_num - 1; i >= 0 ; i--) {
6469 if (priv->pdev_mux[i])
6470 platform_device_unregister(priv->pdev_mux[i]);
6471 }
6472}
6473
6474static int mlxplat_i2c_main_completion_notify(void *handle, int id)
6475{
6476 struct mlxplat_priv *priv = handle;
6477
6478 return mlxplat_i2c_mux_topology_init(priv);
6479}
6480
6481static int mlxplat_i2c_main_init(struct mlxplat_priv *priv)
6482{
6483 int nr, err;
6484
6485 if (!mlxplat_i2c)
6486 return 0;
6487
6488 err = mlxplat_mlxcpld_verify_bus_topology(&nr);
6489 if (nr < 0)
6490 goto fail_mlxplat_mlxcpld_verify_bus_topology;
6491
6492 nr = (nr == mlxplat_max_adap_num) ? -1 : nr;
6493 mlxplat_i2c->regmap = priv->regmap;
6494 mlxplat_i2c->handle = priv;
6495
6496 /* Set mapped base address of I2C-LPC bridge over PCIe */
6497 if (lpc_bridge)
6498 mlxplat_i2c->addr = i2c_bridge_addr;
6499 priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld",
6500 nr, priv->hotplug_resources,
6501 priv->hotplug_resources_size,
6502 mlxplat_i2c, sizeof(*mlxplat_i2c));
6503 if (IS_ERR(priv->pdev_i2c)) {
6504 err = PTR_ERR(priv->pdev_i2c);
6505 goto fail_platform_i2c_register;
6506 }
6507
6508 if (priv->i2c_main_init_status == MLXPLAT_I2C_MAIN_BUS_NOTIFIED) {
6509 err = mlxplat_i2c_mux_topology_init(priv);
6510 if (err)
6511 goto fail_mlxplat_i2c_mux_topology_init;
6512 }
6513
6514 return 0;
6515
6516fail_mlxplat_i2c_mux_topology_init:
6517 platform_device_unregister(priv->pdev_i2c);
6518fail_platform_i2c_register:
6519fail_mlxplat_mlxcpld_verify_bus_topology:
6520 return err;
6521}
6522
6523static void mlxplat_i2c_main_exit(struct mlxplat_priv *priv)
6524{
6525 mlxplat_platdevs_exit(priv);
6526 mlxplat_i2c_mux_topology_exit(priv);
6527 if (priv->pdev_i2c)
6528 platform_device_unregister(priv->pdev_i2c);
6529}
6530
6531static int mlxplat_probe(struct platform_device *pdev)
6532{
6533 unsigned int hotplug_resources_size = 0;
6534 struct resource *hotplug_resources = NULL;
6535 struct acpi_device *acpi_dev;
6536 struct mlxplat_priv *priv;
6537 int irq_fpga = 0, i, err;
6538
6539 acpi_dev = ACPI_COMPANION(&pdev->dev);
6540 if (acpi_dev) {
6541 irq_fpga = acpi_dev_gpio_irq_get(acpi_dev, 0);
6542 if (irq_fpga < 0)
6543 return -ENODEV;
6544 mlxplat_dev = pdev;
6545 }
6546
6547 err = mlxplat_logicdev_init(&hotplug_resources, &hotplug_resources_size);
6548 if (err)
6549 return err;
6550
6551 priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv),
6552 GFP_KERNEL);
6553 if (!priv) {
6554 err = -ENOMEM;
6555 goto fail_alloc;
6556 }
6557 platform_set_drvdata(mlxplat_dev, priv);
6558 priv->hotplug_resources = hotplug_resources;
6559 priv->hotplug_resources_size = hotplug_resources_size;
6560 priv->irq_fpga = irq_fpga;
6561
6562 if (!mlxplat_regmap_config)
6563 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config;
6564
6565 priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL,
6566 &mlxplat_mlxcpld_regmap_ctx,
6567 mlxplat_regmap_config);
6568 if (IS_ERR(priv->regmap)) {
6569 err = PTR_ERR(priv->regmap);
6570 goto fail_alloc;
6571 }
6572
6573 /* Set default registers. */
6574 for (i = 0; i < mlxplat_regmap_config->num_reg_defaults; i++) {
6575 err = regmap_write(priv->regmap,
6576 mlxplat_regmap_config->reg_defaults[i].reg,
6577 mlxplat_regmap_config->reg_defaults[i].def);
6578 if (err)
6579 goto fail_regmap_write;
6580 }
6581
6582 err = mlxplat_i2c_main_init(priv);
6583 if (err)
6584 goto fail_mlxplat_i2c_main_init;
6585
6586 /* Sync registers with hardware. */
6587 regcache_mark_dirty(priv->regmap);
6588 err = regcache_sync(priv->regmap);
6589 if (err)
6590 goto fail_regcache_sync;
6591
6592 if (mlxplat_reboot_nb) {
6593 err = register_reboot_notifier(mlxplat_reboot_nb);
6594 if (err)
6595 goto fail_register_reboot_notifier;
6596 }
6597
6598 return 0;
6599
6600fail_register_reboot_notifier:
6601fail_regcache_sync:
6602 mlxplat_i2c_main_exit(priv);
6603fail_mlxplat_i2c_main_init:
6604fail_regmap_write:
6605fail_alloc:
6606 mlxplat_logicdev_exit();
6607
6608 return err;
6609}
6610
6611static void mlxplat_remove(struct platform_device *pdev)
6612{
6613 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
6614
6615 if (pm_power_off)
6616 pm_power_off = NULL;
6617 if (mlxplat_reboot_nb)
6618 unregister_reboot_notifier(mlxplat_reboot_nb);
6619 mlxplat_i2c_main_exit(priv);
6620 mlxplat_logicdev_exit();
6621}
6622
6623static const struct acpi_device_id mlxplat_acpi_table[] = {
6624 { "MLNXBF49", 0 },
6625 {}
6626};
6627MODULE_DEVICE_TABLE(acpi, mlxplat_acpi_table);
6628
6629static struct platform_driver mlxplat_driver = {
6630 .driver = {
6631 .name = "mlxplat",
6632 .acpi_match_table = mlxplat_acpi_table,
6633 .probe_type = PROBE_FORCE_SYNCHRONOUS,
6634 },
6635 .probe = mlxplat_probe,
6636 .remove_new = mlxplat_remove,
6637};
6638
6639static int __init mlxplat_init(void)
6640{
6641 int err;
6642
6643 if (!dmi_check_system(mlxplat_dmi_table))
6644 return -ENODEV;
6645
6646 err = platform_driver_register(&mlxplat_driver);
6647 if (err)
6648 return err;
6649 return 0;
6650}
6651module_init(mlxplat_init);
6652
6653static void __exit mlxplat_exit(void)
6654{
6655 if (mlxplat_dev)
6656 platform_device_unregister(mlxplat_dev);
6657
6658 platform_driver_unregister(&mlxplat_driver);
6659}
6660module_exit(mlxplat_exit);
6661
6662MODULE_AUTHOR("Vadim Pasternak <vadimp@mellanox.com>");
6663MODULE_DESCRIPTION("Mellanox platform driver");
6664MODULE_LICENSE("Dual BSD/GPL");