1/* SPDX-License-Identifier: GPL-2.0-or-later */
 2/*
 3 * AMD SoC Power Management Controller Driver
 4 *
 5 * Copyright (c) 2023, Advanced Micro Devices, Inc.
 6 * All Rights Reserved.
 7 *
 8 * Author: Mario Limonciello <mario.limonciello@amd.com>
 9 */
10
11#ifndef PMC_H
12#define PMC_H
13
14#include <linux/types.h>
15#include <linux/mutex.h>
16
17struct amd_pmc_dev {
18	void __iomem *regbase;
19	void __iomem *smu_virt_addr;
20	void __iomem *stb_virt_addr;
21	void __iomem *fch_virt_addr;
22	bool msg_port;
23	u32 base_addr;
24	u32 cpu_id;
25	u32 active_ips;
26	u32 dram_size;
27	u32 num_ips;
28	u32 s2d_msg_id;
29	u32 smu_msg;
30/* SMU version information */
31	u8 smu_program;
32	u8 major;
33	u8 minor;
34	u8 rev;
35	struct device *dev;
36	struct pci_dev *rdev;
37	struct mutex lock; /* generic mutex lock */
38	struct dentry *dbgfs_dir;
39	struct quirk_entry *quirks;
40	bool disable_8042_wakeup;
41};
42
43void amd_pmc_process_restore_quirks(struct amd_pmc_dev *dev);
44void amd_pmc_quirks_init(struct amd_pmc_dev *dev);
45
46/* List of supported CPU ids */
47#define AMD_CPU_ID_RV			0x15D0
48#define AMD_CPU_ID_RN			0x1630
49#define AMD_CPU_ID_PCO			AMD_CPU_ID_RV
50#define AMD_CPU_ID_CZN			AMD_CPU_ID_RN
51#define AMD_CPU_ID_YC			0x14B5
52#define AMD_CPU_ID_CB			0x14D8
53#define AMD_CPU_ID_PS			0x14E8
54#define AMD_CPU_ID_SP			0x14A4
55#define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
56
57#endif /* PMC_H */