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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Utility to set the DAVINCI MUX register from a table in mux.h
4 *
5 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * Based on linux/arch/arm/plat-omap/mux.c:
8 * Copyright (C) 2003 - 2005 Nokia Corporation
9 *
10 * Written by Tony Lindgren
11 *
12 * 2007 (c) MontaVista Software, Inc.
13 *
14 * Copyright (C) 2008 Texas Instruments.
15 */
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <linux/io.h>
20#include <linux/module.h>
21#include <linux/spinlock.h>
22
23#include "mux.h"
24#include "common.h"
25
26static void __iomem *pinmux_base;
27
28/*
29 * Sets the DAVINCI MUX register based on the table
30 */
31int davinci_cfg_reg(const unsigned long index)
32{
33 static DEFINE_SPINLOCK(mux_spin_lock);
34 struct davinci_soc_info *soc_info = &davinci_soc_info;
35 unsigned long flags;
36 const struct mux_config *cfg;
37 unsigned int reg_orig = 0, reg = 0;
38 unsigned int mask, warn = 0;
39
40 if (WARN_ON(!soc_info->pinmux_pins))
41 return -ENODEV;
42
43 if (!pinmux_base) {
44 pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
45 if (WARN_ON(!pinmux_base))
46 return -ENOMEM;
47 }
48
49 if (index >= soc_info->pinmux_pins_num) {
50 pr_err("Invalid pin mux index: %lu (%lu)\n",
51 index, soc_info->pinmux_pins_num);
52 dump_stack();
53 return -ENODEV;
54 }
55
56 cfg = &soc_info->pinmux_pins[index];
57
58 if (cfg->name == NULL) {
59 pr_err("No entry for the specified index\n");
60 return -ENODEV;
61 }
62
63 /* Update the mux register in question */
64 if (cfg->mask) {
65 unsigned tmp1, tmp2;
66
67 spin_lock_irqsave(&mux_spin_lock, flags);
68 reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);
69
70 mask = (cfg->mask << cfg->mask_offset);
71 tmp1 = reg_orig & mask;
72 reg = reg_orig & ~mask;
73
74 tmp2 = (cfg->mode << cfg->mask_offset);
75 reg |= tmp2;
76
77 if (tmp1 != tmp2)
78 warn = 1;
79
80 __raw_writel(reg, pinmux_base + cfg->mux_reg);
81 spin_unlock_irqrestore(&mux_spin_lock, flags);
82 }
83
84 if (warn) {
85#ifdef CONFIG_DAVINCI_MUX_WARNINGS
86 pr_warn("initialized %s\n", cfg->name);
87#endif
88 }
89
90#ifdef CONFIG_DAVINCI_MUX_DEBUG
91 if (cfg->debug || warn) {
92 pr_warn("Setting register %s\n", cfg->name);
93 pr_warn(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
94 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
95 }
96#endif
97
98 return 0;
99}
100EXPORT_SYMBOL(davinci_cfg_reg);
101
102int davinci_cfg_reg_list(const short pins[])
103{
104 int i, error = -EINVAL;
105
106 if (pins)
107 for (i = 0; pins[i] >= 0; i++) {
108 error = davinci_cfg_reg(pins[i]);
109 if (error)
110 break;
111 }
112
113 return error;
114}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Utility to set the DAVINCI MUX register from a table in mux.h
4 *
5 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * Based on linux/arch/arm/plat-omap/mux.c:
8 * Copyright (C) 2003 - 2005 Nokia Corporation
9 *
10 * Written by Tony Lindgren
11 *
12 * 2007 (c) MontaVista Software, Inc.
13 *
14 * Copyright (C) 2008 Texas Instruments.
15 */
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <linux/io.h>
20#include <linux/module.h>
21#include <linux/spinlock.h>
22
23#include "mux.h"
24#include "common.h"
25
26static void __iomem *pinmux_base;
27
28/*
29 * Sets the DAVINCI MUX register based on the table
30 */
31int davinci_cfg_reg(const unsigned long index)
32{
33 static DEFINE_SPINLOCK(mux_spin_lock);
34 struct davinci_soc_info *soc_info = &davinci_soc_info;
35 unsigned long flags;
36 const struct mux_config *cfg;
37 unsigned int reg_orig = 0, reg = 0;
38 unsigned int mask, warn = 0;
39
40 if (WARN_ON(!soc_info->pinmux_pins))
41 return -ENODEV;
42
43 if (!pinmux_base) {
44 pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
45 if (WARN_ON(!pinmux_base))
46 return -ENOMEM;
47 }
48
49 if (index >= soc_info->pinmux_pins_num) {
50 pr_err("Invalid pin mux index: %lu (%lu)\n",
51 index, soc_info->pinmux_pins_num);
52 dump_stack();
53 return -ENODEV;
54 }
55
56 cfg = &soc_info->pinmux_pins[index];
57
58 if (cfg->name == NULL) {
59 pr_err("No entry for the specified index\n");
60 return -ENODEV;
61 }
62
63 /* Update the mux register in question */
64 if (cfg->mask) {
65 unsigned tmp1, tmp2;
66
67 spin_lock_irqsave(&mux_spin_lock, flags);
68 reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);
69
70 mask = (cfg->mask << cfg->mask_offset);
71 tmp1 = reg_orig & mask;
72 reg = reg_orig & ~mask;
73
74 tmp2 = (cfg->mode << cfg->mask_offset);
75 reg |= tmp2;
76
77 if (tmp1 != tmp2)
78 warn = 1;
79
80 __raw_writel(reg, pinmux_base + cfg->mux_reg);
81 spin_unlock_irqrestore(&mux_spin_lock, flags);
82 }
83
84 if (warn) {
85#ifdef CONFIG_DAVINCI_MUX_WARNINGS
86 pr_warn("initialized %s\n", cfg->name);
87#endif
88 }
89
90#ifdef CONFIG_DAVINCI_MUX_DEBUG
91 if (cfg->debug || warn) {
92 pr_warn("Setting register %s\n", cfg->name);
93 pr_warn(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
94 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
95 }
96#endif
97
98 return 0;
99}