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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interconnect/qcom,msm8974.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8974.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/reset/qcom,gcc-msm8974.h>
10#include <dt-bindings/gpio/gpio.h>
11
12/ {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 interrupt-parent = <&intc>;
16
17 clocks {
18 xo_board: xo_board {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <19200000>;
22 };
23
24 sleep_clk: sleep_clk {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <32768>;
28 };
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
35
36 CPU0: cpu@0 {
37 compatible = "qcom,krait";
38 enable-method = "qcom,kpss-acc-v2";
39 device_type = "cpu";
40 reg = <0>;
41 next-level-cache = <&L2>;
42 qcom,acc = <&acc0>;
43 qcom,saw = <&saw0>;
44 cpu-idle-states = <&CPU_SPC>;
45 };
46
47 CPU1: cpu@1 {
48 compatible = "qcom,krait";
49 enable-method = "qcom,kpss-acc-v2";
50 device_type = "cpu";
51 reg = <1>;
52 next-level-cache = <&L2>;
53 qcom,acc = <&acc1>;
54 qcom,saw = <&saw1>;
55 cpu-idle-states = <&CPU_SPC>;
56 };
57
58 CPU2: cpu@2 {
59 compatible = "qcom,krait";
60 enable-method = "qcom,kpss-acc-v2";
61 device_type = "cpu";
62 reg = <2>;
63 next-level-cache = <&L2>;
64 qcom,acc = <&acc2>;
65 qcom,saw = <&saw2>;
66 cpu-idle-states = <&CPU_SPC>;
67 };
68
69 CPU3: cpu@3 {
70 compatible = "qcom,krait";
71 enable-method = "qcom,kpss-acc-v2";
72 device_type = "cpu";
73 reg = <3>;
74 next-level-cache = <&L2>;
75 qcom,acc = <&acc3>;
76 qcom,saw = <&saw3>;
77 cpu-idle-states = <&CPU_SPC>;
78 };
79
80 L2: l2-cache {
81 compatible = "cache";
82 cache-level = <2>;
83 cache-unified;
84 qcom,saw = <&saw_l2>;
85 };
86
87 idle-states {
88 CPU_SPC: spc {
89 compatible = "qcom,idle-state-spc",
90 "arm,idle-state";
91 entry-latency-us = <150>;
92 exit-latency-us = <200>;
93 min-residency-us = <2000>;
94 };
95 };
96 };
97
98 firmware {
99 scm {
100 compatible = "qcom,scm-msm8974", "qcom,scm";
101 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
102 clock-names = "core", "bus", "iface";
103 };
104 };
105
106 memory {
107 device_type = "memory";
108 reg = <0x0 0x0>;
109 };
110
111 pmu {
112 compatible = "qcom,krait-pmu";
113 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
114 };
115
116 rpm: remoteproc {
117 compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc";
118
119 master-stats {
120 compatible = "qcom,rpm-master-stats";
121 qcom,rpm-msg-ram = <&apss_master_stats>,
122 <&mpss_master_stats>,
123 <&lpss_master_stats>,
124 <&pronto_master_stats>;
125 qcom,master-names = "APSS",
126 "MPSS",
127 "LPSS",
128 "PRONTO";
129 };
130
131 smd-edge {
132 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
133 qcom,ipc = <&apcs 8 0>;
134 qcom,smd-edge = <15>;
135
136 rpm_requests: rpm-requests {
137 compatible = "qcom,rpm-msm8974";
138 qcom,smd-channels = "rpm_requests";
139
140 rpmcc: clock-controller {
141 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
142 #clock-cells = <1>;
143 clocks = <&xo_board>;
144 clock-names = "xo";
145 };
146 };
147 };
148 };
149
150 reserved-memory {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 ranges;
154
155 mpss_region: mpss@8000000 {
156 reg = <0x08000000 0x5100000>;
157 no-map;
158 };
159
160 mba_region: mba@d100000 {
161 reg = <0x0d100000 0x100000>;
162 no-map;
163 };
164
165 wcnss_region: wcnss@d200000 {
166 reg = <0x0d200000 0xa00000>;
167 no-map;
168 };
169
170 adsp_region: adsp@dc00000 {
171 reg = <0x0dc00000 0x1900000>;
172 no-map;
173 };
174
175 venus_region: memory@f500000 {
176 reg = <0x0f500000 0x500000>;
177 no-map;
178 };
179
180 smem_region: smem@fa00000 {
181 reg = <0xfa00000 0x200000>;
182 no-map;
183 };
184
185 tz_region: memory@fc00000 {
186 reg = <0x0fc00000 0x160000>;
187 no-map;
188 };
189
190 rfsa_mem: memory@fd60000 {
191 reg = <0x0fd60000 0x20000>;
192 no-map;
193 };
194
195 rmtfs@fd80000 {
196 compatible = "qcom,rmtfs-mem";
197 reg = <0x0fd80000 0x180000>;
198 no-map;
199
200 qcom,client-id = <1>;
201 };
202 };
203
204 smem {
205 compatible = "qcom,smem";
206
207 memory-region = <&smem_region>;
208 qcom,rpm-msg-ram = <&rpm_msg_ram>;
209
210 hwlocks = <&tcsr_mutex 3>;
211 };
212
213 smp2p-adsp {
214 compatible = "qcom,smp2p";
215 qcom,smem = <443>, <429>;
216
217 interrupt-parent = <&intc>;
218 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
219
220 qcom,ipc = <&apcs 8 10>;
221
222 qcom,local-pid = <0>;
223 qcom,remote-pid = <2>;
224
225 adsp_smp2p_out: master-kernel {
226 qcom,entry-name = "master-kernel";
227 #qcom,smem-state-cells = <1>;
228 };
229
230 adsp_smp2p_in: slave-kernel {
231 qcom,entry-name = "slave-kernel";
232
233 interrupt-controller;
234 #interrupt-cells = <2>;
235 };
236 };
237
238 smp2p-modem {
239 compatible = "qcom,smp2p";
240 qcom,smem = <435>, <428>;
241
242 interrupt-parent = <&intc>;
243 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
244
245 qcom,ipc = <&apcs 8 14>;
246
247 qcom,local-pid = <0>;
248 qcom,remote-pid = <1>;
249
250 modem_smp2p_out: master-kernel {
251 qcom,entry-name = "master-kernel";
252 #qcom,smem-state-cells = <1>;
253 };
254
255 modem_smp2p_in: slave-kernel {
256 qcom,entry-name = "slave-kernel";
257
258 interrupt-controller;
259 #interrupt-cells = <2>;
260 };
261 };
262
263 smp2p-wcnss {
264 compatible = "qcom,smp2p";
265 qcom,smem = <451>, <431>;
266
267 interrupt-parent = <&intc>;
268 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
269
270 qcom,ipc = <&apcs 8 18>;
271
272 qcom,local-pid = <0>;
273 qcom,remote-pid = <4>;
274
275 wcnss_smp2p_out: master-kernel {
276 qcom,entry-name = "master-kernel";
277
278 #qcom,smem-state-cells = <1>;
279 };
280
281 wcnss_smp2p_in: slave-kernel {
282 qcom,entry-name = "slave-kernel";
283
284 interrupt-controller;
285 #interrupt-cells = <2>;
286 };
287 };
288
289 smsm {
290 compatible = "qcom,smsm";
291
292 #address-cells = <1>;
293 #size-cells = <0>;
294
295 qcom,ipc-1 = <&apcs 8 13>;
296 qcom,ipc-2 = <&apcs 8 9>;
297 qcom,ipc-3 = <&apcs 8 19>;
298
299 apps_smsm: apps@0 {
300 reg = <0>;
301
302 #qcom,smem-state-cells = <1>;
303 };
304
305 modem_smsm: modem@1 {
306 reg = <1>;
307 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
308
309 interrupt-controller;
310 #interrupt-cells = <2>;
311 };
312
313 adsp_smsm: adsp@2 {
314 reg = <2>;
315 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
316
317 interrupt-controller;
318 #interrupt-cells = <2>;
319 };
320
321 wcnss_smsm: wcnss@7 {
322 reg = <7>;
323 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
324
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 };
328 };
329
330 soc: soc {
331 #address-cells = <1>;
332 #size-cells = <1>;
333 ranges;
334 compatible = "simple-bus";
335
336 intc: interrupt-controller@f9000000 {
337 compatible = "qcom,msm-qgic2";
338 interrupt-controller;
339 #interrupt-cells = <3>;
340 reg = <0xf9000000 0x1000>,
341 <0xf9002000 0x1000>;
342 };
343
344 apcs: syscon@f9011000 {
345 compatible = "syscon";
346 reg = <0xf9011000 0x1000>;
347 };
348
349 saw_l2: power-manager@f9012000 {
350 compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2";
351 reg = <0xf9012000 0x1000>;
352 };
353
354 watchdog@f9017000 {
355 compatible = "qcom,apss-wdt-msm8974", "qcom,kpss-wdt";
356 reg = <0xf9017000 0x1000>;
357 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
358 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
359 clocks = <&sleep_clk>;
360 };
361
362 timer@f9020000 {
363 #address-cells = <1>;
364 #size-cells = <1>;
365 ranges;
366 compatible = "arm,armv7-timer-mem";
367 reg = <0xf9020000 0x1000>;
368 clock-frequency = <19200000>;
369
370 frame@f9021000 {
371 frame-number = <0>;
372 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
374 reg = <0xf9021000 0x1000>,
375 <0xf9022000 0x1000>;
376 };
377
378 frame@f9023000 {
379 frame-number = <1>;
380 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
381 reg = <0xf9023000 0x1000>;
382 status = "disabled";
383 };
384
385 frame@f9024000 {
386 frame-number = <2>;
387 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
388 reg = <0xf9024000 0x1000>;
389 status = "disabled";
390 };
391
392 frame@f9025000 {
393 frame-number = <3>;
394 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
395 reg = <0xf9025000 0x1000>;
396 status = "disabled";
397 };
398
399 frame@f9026000 {
400 frame-number = <4>;
401 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
402 reg = <0xf9026000 0x1000>;
403 status = "disabled";
404 };
405
406 frame@f9027000 {
407 frame-number = <5>;
408 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
409 reg = <0xf9027000 0x1000>;
410 status = "disabled";
411 };
412
413 frame@f9028000 {
414 frame-number = <6>;
415 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
416 reg = <0xf9028000 0x1000>;
417 status = "disabled";
418 };
419 };
420
421 acc0: power-manager@f9088000 {
422 compatible = "qcom,kpss-acc-v2";
423 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
424 };
425
426 saw0: power-manager@f9089000 {
427 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
428 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
429 };
430
431 acc1: power-manager@f9098000 {
432 compatible = "qcom,kpss-acc-v2";
433 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
434 };
435
436 saw1: power-manager@f9099000 {
437 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
438 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
439 };
440
441 acc2: power-manager@f90a8000 {
442 compatible = "qcom,kpss-acc-v2";
443 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
444 };
445
446 saw2: power-manager@f90a9000 {
447 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
448 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
449 };
450
451 acc3: power-manager@f90b8000 {
452 compatible = "qcom,kpss-acc-v2";
453 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
454 };
455
456 saw3: power-manager@f90b9000 {
457 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
458 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
459 };
460
461 sdhc_1: mmc@f9824900 {
462 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
463 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
464 reg-names = "hc", "core";
465 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
467 interrupt-names = "hc_irq", "pwr_irq";
468 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
469 <&gcc GCC_SDCC1_APPS_CLK>,
470 <&xo_board>;
471 clock-names = "iface", "core", "xo";
472 bus-width = <8>;
473 non-removable;
474
475 status = "disabled";
476 };
477
478 sdhc_3: mmc@f9864900 {
479 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
480 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
481 reg-names = "hc", "core";
482 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
484 interrupt-names = "hc_irq", "pwr_irq";
485 clocks = <&gcc GCC_SDCC3_AHB_CLK>,
486 <&gcc GCC_SDCC3_APPS_CLK>,
487 <&xo_board>;
488 clock-names = "iface", "core", "xo";
489 bus-width = <4>;
490
491 #address-cells = <1>;
492 #size-cells = <0>;
493
494 status = "disabled";
495 };
496
497 sdhc_2: mmc@f98a4900 {
498 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
499 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
500 reg-names = "hc", "core";
501 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
503 interrupt-names = "hc_irq", "pwr_irq";
504 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
505 <&gcc GCC_SDCC2_APPS_CLK>,
506 <&xo_board>;
507 clock-names = "iface", "core", "xo";
508 bus-width = <4>;
509
510 #address-cells = <1>;
511 #size-cells = <0>;
512
513 status = "disabled";
514 };
515
516 blsp1_uart1: serial@f991d000 {
517 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
518 reg = <0xf991d000 0x1000>;
519 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
521 clock-names = "core", "iface";
522 status = "disabled";
523 };
524
525 blsp1_uart2: serial@f991e000 {
526 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
527 reg = <0xf991e000 0x1000>;
528 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
530 clock-names = "core", "iface";
531 pinctrl-names = "default";
532 pinctrl-0 = <&blsp1_uart2_default>;
533 status = "disabled";
534 };
535
536 blsp1_i2c1: i2c@f9923000 {
537 status = "disabled";
538 compatible = "qcom,i2c-qup-v2.1.1";
539 reg = <0xf9923000 0x1000>;
540 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
542 clock-names = "core", "iface";
543 pinctrl-names = "default", "sleep";
544 pinctrl-0 = <&blsp1_i2c1_default>;
545 pinctrl-1 = <&blsp1_i2c1_sleep>;
546 #address-cells = <1>;
547 #size-cells = <0>;
548 };
549
550 blsp1_i2c2: i2c@f9924000 {
551 status = "disabled";
552 compatible = "qcom,i2c-qup-v2.1.1";
553 reg = <0xf9924000 0x1000>;
554 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
556 clock-names = "core", "iface";
557 pinctrl-names = "default", "sleep";
558 pinctrl-0 = <&blsp1_i2c2_default>;
559 pinctrl-1 = <&blsp1_i2c2_sleep>;
560 #address-cells = <1>;
561 #size-cells = <0>;
562 };
563
564 blsp1_i2c3: i2c@f9925000 {
565 status = "disabled";
566 compatible = "qcom,i2c-qup-v2.1.1";
567 reg = <0xf9925000 0x1000>;
568 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
570 clock-names = "core", "iface";
571 pinctrl-names = "default", "sleep";
572 pinctrl-0 = <&blsp1_i2c3_default>;
573 pinctrl-1 = <&blsp1_i2c3_sleep>;
574 #address-cells = <1>;
575 #size-cells = <0>;
576 };
577
578 blsp1_i2c6: i2c@f9928000 {
579 status = "disabled";
580 compatible = "qcom,i2c-qup-v2.1.1";
581 reg = <0xf9928000 0x1000>;
582 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
584 clock-names = "core", "iface";
585 pinctrl-names = "default", "sleep";
586 pinctrl-0 = <&blsp1_i2c6_default>;
587 pinctrl-1 = <&blsp1_i2c6_sleep>;
588 #address-cells = <1>;
589 #size-cells = <0>;
590 };
591
592 blsp2_dma: dma-controller@f9944000 {
593 compatible = "qcom,bam-v1.4.0";
594 reg = <0xf9944000 0x19000>;
595 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
597 clock-names = "bam_clk";
598 #dma-cells = <1>;
599 qcom,ee = <0>;
600 };
601
602 blsp2_uart1: serial@f995d000 {
603 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
604 reg = <0xf995d000 0x1000>;
605 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
607 clock-names = "core", "iface";
608 pinctrl-names = "default", "sleep";
609 pinctrl-0 = <&blsp2_uart1_default>;
610 pinctrl-1 = <&blsp2_uart1_sleep>;
611 status = "disabled";
612 };
613
614 blsp2_uart2: serial@f995e000 {
615 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
616 reg = <0xf995e000 0x1000>;
617 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
619 clock-names = "core", "iface";
620 status = "disabled";
621 };
622
623 blsp2_uart4: serial@f9960000 {
624 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
625 reg = <0xf9960000 0x1000>;
626 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
628 clock-names = "core", "iface";
629 pinctrl-names = "default";
630 pinctrl-0 = <&blsp2_uart4_default>;
631 status = "disabled";
632 };
633
634 blsp2_i2c2: i2c@f9964000 {
635 status = "disabled";
636 compatible = "qcom,i2c-qup-v2.1.1";
637 reg = <0xf9964000 0x1000>;
638 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
640 clock-names = "core", "iface";
641 pinctrl-names = "default", "sleep";
642 pinctrl-0 = <&blsp2_i2c2_default>;
643 pinctrl-1 = <&blsp2_i2c2_sleep>;
644 #address-cells = <1>;
645 #size-cells = <0>;
646 };
647
648 blsp2_i2c5: i2c@f9967000 {
649 status = "disabled";
650 compatible = "qcom,i2c-qup-v2.1.1";
651 reg = <0xf9967000 0x1000>;
652 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
654 clock-names = "core", "iface";
655 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
656 dma-names = "tx", "rx";
657 pinctrl-names = "default", "sleep";
658 pinctrl-0 = <&blsp2_i2c5_default>;
659 pinctrl-1 = <&blsp2_i2c5_sleep>;
660 #address-cells = <1>;
661 #size-cells = <0>;
662 };
663
664 blsp2_i2c6: i2c@f9968000 {
665 status = "disabled";
666 compatible = "qcom,i2c-qup-v2.1.1";
667 reg = <0xf9968000 0x1000>;
668 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
670 clock-names = "core", "iface";
671 pinctrl-names = "default", "sleep";
672 pinctrl-0 = <&blsp2_i2c6_default>;
673 pinctrl-1 = <&blsp2_i2c6_sleep>;
674 #address-cells = <1>;
675 #size-cells = <0>;
676 };
677
678 usb: usb@f9a55000 {
679 compatible = "qcom,ci-hdrc";
680 reg = <0xf9a55000 0x200>,
681 <0xf9a55200 0x200>;
682 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
684 <&gcc GCC_USB_HS_SYSTEM_CLK>;
685 clock-names = "iface", "core";
686 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
687 assigned-clock-rates = <75000000>;
688 resets = <&gcc GCC_USB_HS_BCR>;
689 reset-names = "core";
690 phy_type = "ulpi";
691 dr_mode = "otg";
692 ahb-burst-config = <0>;
693 phy-names = "usb-phy";
694 status = "disabled";
695 #reset-cells = <1>;
696
697 ulpi {
698 usb_hs1_phy: phy-0 {
699 compatible = "qcom,usb-hs-phy-msm8974",
700 "qcom,usb-hs-phy";
701 #phy-cells = <0>;
702 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
703 clock-names = "ref", "sleep";
704 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
705 reset-names = "phy", "por";
706 status = "disabled";
707 };
708
709 usb_hs2_phy: phy-1 {
710 compatible = "qcom,usb-hs-phy-msm8974",
711 "qcom,usb-hs-phy";
712 #phy-cells = <0>;
713 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
714 clock-names = "ref", "sleep";
715 resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>;
716 reset-names = "phy", "por";
717 status = "disabled";
718 };
719 };
720 };
721
722 rng@f9bff000 {
723 compatible = "qcom,prng";
724 reg = <0xf9bff000 0x200>;
725 clocks = <&gcc GCC_PRNG_AHB_CLK>;
726 clock-names = "core";
727 };
728
729 pronto: remoteproc@fb204000 {
730 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
731 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
732 reg-names = "ccu", "dxe", "pmu";
733
734 memory-region = <&wcnss_region>;
735
736 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
737 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
738 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
739 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
740 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
741 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
742
743 qcom,smem-states = <&wcnss_smp2p_out 0>;
744 qcom,smem-state-names = "stop";
745
746 status = "disabled";
747
748 iris {
749 compatible = "qcom,wcn3680";
750
751 clocks = <&rpmcc RPM_SMD_CXO_A2>;
752 clock-names = "xo";
753 };
754
755 smd-edge {
756 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
757
758 qcom,ipc = <&apcs 8 17>;
759 qcom,smd-edge = <6>;
760
761 wcnss {
762 compatible = "qcom,wcnss";
763 qcom,smd-channels = "WCNSS_CTRL";
764 status = "disabled";
765
766 qcom,mmio = <&pronto>;
767
768 bluetooth {
769 compatible = "qcom,wcnss-bt";
770 };
771
772 wifi {
773 compatible = "qcom,wcnss-wlan";
774
775 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
776 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
777 interrupt-names = "tx", "rx";
778
779 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
780 qcom,smem-state-names = "tx-enable",
781 "tx-rings-empty";
782 };
783 };
784 };
785 };
786
787 sram@fc190000 {
788 compatible = "qcom,msm8974-rpm-stats";
789 reg = <0xfc190000 0x10000>;
790 };
791
792 etf@fc307000 {
793 compatible = "arm,coresight-tmc", "arm,primecell";
794 reg = <0xfc307000 0x1000>;
795
796 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
797 clock-names = "apb_pclk", "atclk";
798
799 out-ports {
800 port {
801 etf_out: endpoint {
802 remote-endpoint = <&replicator_in>;
803 };
804 };
805 };
806
807 in-ports {
808 port {
809 etf_in: endpoint {
810 remote-endpoint = <&merger_out>;
811 };
812 };
813 };
814 };
815
816 tpiu@fc318000 {
817 compatible = "arm,coresight-tpiu", "arm,primecell";
818 reg = <0xfc318000 0x1000>;
819
820 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
821 clock-names = "apb_pclk", "atclk";
822
823 in-ports {
824 port {
825 tpiu_in: endpoint {
826 remote-endpoint = <&replicator_out1>;
827 };
828 };
829 };
830 };
831
832 funnel@fc31a000 {
833 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
834 reg = <0xfc31a000 0x1000>;
835
836 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
837 clock-names = "apb_pclk", "atclk";
838
839 in-ports {
840 #address-cells = <1>;
841 #size-cells = <0>;
842
843 /*
844 * Not described input ports:
845 * 0 - not-connected
846 * 1 - connected trought funnel to Multimedia CPU
847 * 2 - connected to Wireless CPU
848 * 3 - not-connected
849 * 4 - not-connected
850 * 6 - not-connected
851 * 7 - connected to STM
852 */
853 port@5 {
854 reg = <5>;
855 funnel1_in5: endpoint {
856 remote-endpoint = <&kpss_out>;
857 };
858 };
859 };
860
861 out-ports {
862 port {
863 funnel1_out: endpoint {
864 remote-endpoint = <&merger_in1>;
865 };
866 };
867 };
868 };
869
870 funnel@fc31b000 {
871 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
872 reg = <0xfc31b000 0x1000>;
873
874 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
875 clock-names = "apb_pclk", "atclk";
876
877 in-ports {
878 #address-cells = <1>;
879 #size-cells = <0>;
880
881 /*
882 * Not described input ports:
883 * 0 - connected trought funnel to Audio, Modem and
884 * Resource and Power Manager CPU's
885 * 2...7 - not-connected
886 */
887 port@1 {
888 reg = <1>;
889 merger_in1: endpoint {
890 remote-endpoint = <&funnel1_out>;
891 };
892 };
893 };
894
895 out-ports {
896 port {
897 merger_out: endpoint {
898 remote-endpoint = <&etf_in>;
899 };
900 };
901 };
902 };
903
904 replicator@fc31c000 {
905 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
906 reg = <0xfc31c000 0x1000>;
907
908 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
909 clock-names = "apb_pclk", "atclk";
910
911 out-ports {
912 #address-cells = <1>;
913 #size-cells = <0>;
914
915 port@0 {
916 reg = <0>;
917 replicator_out0: endpoint {
918 remote-endpoint = <&etr_in>;
919 };
920 };
921 port@1 {
922 reg = <1>;
923 replicator_out1: endpoint {
924 remote-endpoint = <&tpiu_in>;
925 };
926 };
927 };
928
929 in-ports {
930 port {
931 replicator_in: endpoint {
932 remote-endpoint = <&etf_out>;
933 };
934 };
935 };
936 };
937
938 etr@fc322000 {
939 compatible = "arm,coresight-tmc", "arm,primecell";
940 reg = <0xfc322000 0x1000>;
941
942 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
943 clock-names = "apb_pclk", "atclk";
944
945 in-ports {
946 port {
947 etr_in: endpoint {
948 remote-endpoint = <&replicator_out0>;
949 };
950 };
951 };
952 };
953
954 etm@fc33c000 {
955 compatible = "arm,coresight-etm4x", "arm,primecell";
956 reg = <0xfc33c000 0x1000>;
957
958 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
959 clock-names = "apb_pclk", "atclk";
960
961 cpu = <&CPU0>;
962
963 out-ports {
964 port {
965 etm0_out: endpoint {
966 remote-endpoint = <&kpss_in0>;
967 };
968 };
969 };
970 };
971
972 etm@fc33d000 {
973 compatible = "arm,coresight-etm4x", "arm,primecell";
974 reg = <0xfc33d000 0x1000>;
975
976 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
977 clock-names = "apb_pclk", "atclk";
978
979 cpu = <&CPU1>;
980
981 out-ports {
982 port {
983 etm1_out: endpoint {
984 remote-endpoint = <&kpss_in1>;
985 };
986 };
987 };
988 };
989
990 etm@fc33e000 {
991 compatible = "arm,coresight-etm4x", "arm,primecell";
992 reg = <0xfc33e000 0x1000>;
993
994 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
995 clock-names = "apb_pclk", "atclk";
996
997 cpu = <&CPU2>;
998
999 out-ports {
1000 port {
1001 etm2_out: endpoint {
1002 remote-endpoint = <&kpss_in2>;
1003 };
1004 };
1005 };
1006 };
1007
1008 etm@fc33f000 {
1009 compatible = "arm,coresight-etm4x", "arm,primecell";
1010 reg = <0xfc33f000 0x1000>;
1011
1012 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1013 clock-names = "apb_pclk", "atclk";
1014
1015 cpu = <&CPU3>;
1016
1017 out-ports {
1018 port {
1019 etm3_out: endpoint {
1020 remote-endpoint = <&kpss_in3>;
1021 };
1022 };
1023 };
1024 };
1025
1026 /* KPSS funnel, only 4 inputs are used */
1027 funnel@fc345000 {
1028 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1029 reg = <0xfc345000 0x1000>;
1030
1031 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1032 clock-names = "apb_pclk", "atclk";
1033
1034 in-ports {
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1037
1038 port@0 {
1039 reg = <0>;
1040 kpss_in0: endpoint {
1041 remote-endpoint = <&etm0_out>;
1042 };
1043 };
1044 port@1 {
1045 reg = <1>;
1046 kpss_in1: endpoint {
1047 remote-endpoint = <&etm1_out>;
1048 };
1049 };
1050 port@2 {
1051 reg = <2>;
1052 kpss_in2: endpoint {
1053 remote-endpoint = <&etm2_out>;
1054 };
1055 };
1056 port@3 {
1057 reg = <3>;
1058 kpss_in3: endpoint {
1059 remote-endpoint = <&etm3_out>;
1060 };
1061 };
1062 };
1063
1064 out-ports {
1065 port {
1066 kpss_out: endpoint {
1067 remote-endpoint = <&funnel1_in5>;
1068 };
1069 };
1070 };
1071 };
1072
1073 bimc: interconnect@fc380000 {
1074 reg = <0xfc380000 0x6a000>;
1075 compatible = "qcom,msm8974-bimc";
1076 #interconnect-cells = <1>;
1077 clock-names = "bus", "bus_a";
1078 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
1079 <&rpmcc RPM_SMD_BIMC_A_CLK>;
1080 };
1081
1082 gcc: clock-controller@fc400000 {
1083 compatible = "qcom,gcc-msm8974";
1084 #clock-cells = <1>;
1085 #reset-cells = <1>;
1086 #power-domain-cells = <1>;
1087 reg = <0xfc400000 0x4000>;
1088
1089 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1090 <&sleep_clk>;
1091 clock-names = "xo",
1092 "sleep_clk";
1093 };
1094
1095 rpm_msg_ram: sram@fc428000 {
1096 compatible = "qcom,rpm-msg-ram";
1097 reg = <0xfc428000 0x4000>;
1098
1099 #address-cells = <1>;
1100 #size-cells = <1>;
1101 ranges = <0 0xfc428000 0x4000>;
1102
1103 apss_master_stats: sram@150 {
1104 reg = <0x150 0x14>;
1105 };
1106
1107 mpss_master_stats: sram@b50 {
1108 reg = <0xb50 0x14>;
1109 };
1110
1111 lpss_master_stats: sram@1550 {
1112 reg = <0x1550 0x14>;
1113 };
1114
1115 pronto_master_stats: sram@1f50 {
1116 reg = <0x1f50 0x14>;
1117 };
1118 };
1119
1120 snoc: interconnect@fc460000 {
1121 reg = <0xfc460000 0x4000>;
1122 compatible = "qcom,msm8974-snoc";
1123 #interconnect-cells = <1>;
1124 clock-names = "bus", "bus_a";
1125 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
1126 <&rpmcc RPM_SMD_SNOC_A_CLK>;
1127 };
1128
1129 pnoc: interconnect@fc468000 {
1130 reg = <0xfc468000 0x4000>;
1131 compatible = "qcom,msm8974-pnoc";
1132 #interconnect-cells = <1>;
1133 clock-names = "bus", "bus_a";
1134 clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
1135 <&rpmcc RPM_SMD_PNOC_A_CLK>;
1136 };
1137
1138 ocmemnoc: interconnect@fc470000 {
1139 reg = <0xfc470000 0x4000>;
1140 compatible = "qcom,msm8974-ocmemnoc";
1141 #interconnect-cells = <1>;
1142 clock-names = "bus", "bus_a";
1143 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1144 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
1145 };
1146
1147 mmssnoc: interconnect@fc478000 {
1148 reg = <0xfc478000 0x4000>;
1149 compatible = "qcom,msm8974-mmssnoc";
1150 #interconnect-cells = <1>;
1151 clock-names = "bus", "bus_a";
1152 clocks = <&mmcc MMSS_S0_AXI_CLK>,
1153 <&mmcc MMSS_S0_AXI_CLK>;
1154 };
1155
1156 cnoc: interconnect@fc480000 {
1157 reg = <0xfc480000 0x4000>;
1158 compatible = "qcom,msm8974-cnoc";
1159 #interconnect-cells = <1>;
1160 clock-names = "bus", "bus_a";
1161 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
1162 <&rpmcc RPM_SMD_CNOC_A_CLK>;
1163 };
1164
1165 tsens: thermal-sensor@fc4a9000 {
1166 compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
1167 reg = <0xfc4a9000 0x1000>, /* TM */
1168 <0xfc4a8000 0x1000>; /* SROT */
1169 nvmem-cells = <&tsens_mode>,
1170 <&tsens_base1>, <&tsens_base2>,
1171 <&tsens_use_backup>,
1172 <&tsens_mode_backup>,
1173 <&tsens_base1_backup>, <&tsens_base2_backup>,
1174 <&tsens_s0_p1>, <&tsens_s0_p2>,
1175 <&tsens_s1_p1>, <&tsens_s1_p2>,
1176 <&tsens_s2_p1>, <&tsens_s2_p2>,
1177 <&tsens_s3_p1>, <&tsens_s3_p2>,
1178 <&tsens_s4_p1>, <&tsens_s4_p2>,
1179 <&tsens_s5_p1>, <&tsens_s5_p2>,
1180 <&tsens_s6_p1>, <&tsens_s6_p2>,
1181 <&tsens_s7_p1>, <&tsens_s7_p2>,
1182 <&tsens_s8_p1>, <&tsens_s8_p2>,
1183 <&tsens_s9_p1>, <&tsens_s9_p2>,
1184 <&tsens_s10_p1>, <&tsens_s10_p2>,
1185 <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>,
1186 <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>,
1187 <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>,
1188 <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>,
1189 <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>,
1190 <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>,
1191 <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>,
1192 <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>,
1193 <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>,
1194 <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>,
1195 <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>;
1196 nvmem-cell-names = "mode",
1197 "base1", "base2",
1198 "use_backup",
1199 "mode_backup",
1200 "base1_backup", "base2_backup",
1201 "s0_p1", "s0_p2",
1202 "s1_p1", "s1_p2",
1203 "s2_p1", "s2_p2",
1204 "s3_p1", "s3_p2",
1205 "s4_p1", "s4_p2",
1206 "s5_p1", "s5_p2",
1207 "s6_p1", "s6_p2",
1208 "s7_p1", "s7_p2",
1209 "s8_p1", "s8_p2",
1210 "s9_p1", "s9_p2",
1211 "s10_p1", "s10_p2",
1212 "s0_p1_backup", "s0_p2_backup",
1213 "s1_p1_backup", "s1_p2_backup",
1214 "s2_p1_backup", "s2_p2_backup",
1215 "s3_p1_backup", "s3_p2_backup",
1216 "s4_p1_backup", "s4_p2_backup",
1217 "s5_p1_backup", "s5_p2_backup",
1218 "s6_p1_backup", "s6_p2_backup",
1219 "s7_p1_backup", "s7_p2_backup",
1220 "s8_p1_backup", "s8_p2_backup",
1221 "s9_p1_backup", "s9_p2_backup",
1222 "s10_p1_backup", "s10_p2_backup";
1223 #qcom,sensors = <11>;
1224 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1225 interrupt-names = "uplow";
1226 #thermal-sensor-cells = <1>;
1227 };
1228
1229 restart@fc4ab000 {
1230 compatible = "qcom,pshold";
1231 reg = <0xfc4ab000 0x4>;
1232 };
1233
1234 qfprom: qfprom@fc4bc000 {
1235 compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
1236 reg = <0xfc4bc000 0x2100>;
1237 #address-cells = <1>;
1238 #size-cells = <1>;
1239
1240 tsens_base1: base1@d0 {
1241 reg = <0xd0 0x1>;
1242 bits = <0 8>;
1243 };
1244
1245 tsens_s0_p1: s0-p1@d1 {
1246 reg = <0xd1 0x1>;
1247 bits = <0 6>;
1248 };
1249
1250 tsens_s1_p1: s1-p1@d2 {
1251 reg = <0xd1 0x2>;
1252 bits = <6 6>;
1253 };
1254
1255 tsens_s2_p1: s2-p1@d2 {
1256 reg = <0xd2 0x2>;
1257 bits = <4 6>;
1258 };
1259
1260 tsens_s3_p1: s3-p1@d3 {
1261 reg = <0xd3 0x1>;
1262 bits = <2 6>;
1263 };
1264
1265 tsens_s4_p1: s4-p1@d4 {
1266 reg = <0xd4 0x1>;
1267 bits = <0 6>;
1268 };
1269
1270 tsens_s5_p1: s5-p1@d4 {
1271 reg = <0xd4 0x2>;
1272 bits = <6 6>;
1273 };
1274
1275 tsens_s6_p1: s6-p1@d5 {
1276 reg = <0xd5 0x2>;
1277 bits = <4 6>;
1278 };
1279
1280 tsens_s7_p1: s7-p1@d6 {
1281 reg = <0xd6 0x1>;
1282 bits = <2 6>;
1283 };
1284
1285 tsens_s8_p1: s8-p1@d7 {
1286 reg = <0xd7 0x1>;
1287 bits = <0 6>;
1288 };
1289
1290 tsens_mode: mode@d7 {
1291 reg = <0xd7 0x1>;
1292 bits = <6 2>;
1293 };
1294
1295 tsens_s9_p1: s9-p1@d8 {
1296 reg = <0xd8 0x1>;
1297 bits = <0 6>;
1298 };
1299
1300 tsens_s10_p1: s10_p1@d8 {
1301 reg = <0xd8 0x2>;
1302 bits = <6 6>;
1303 };
1304
1305 tsens_base2: base2@d9 {
1306 reg = <0xd9 0x2>;
1307 bits = <4 8>;
1308 };
1309
1310 tsens_s0_p2: s0-p2@da {
1311 reg = <0xda 0x2>;
1312 bits = <4 6>;
1313 };
1314
1315 tsens_s1_p2: s1-p2@db {
1316 reg = <0xdb 0x1>;
1317 bits = <2 6>;
1318 };
1319
1320 tsens_s2_p2: s2-p2@dc {
1321 reg = <0xdc 0x1>;
1322 bits = <0 6>;
1323 };
1324
1325 tsens_s3_p2: s3-p2@dc {
1326 reg = <0xdc 0x2>;
1327 bits = <6 6>;
1328 };
1329
1330 tsens_s4_p2: s4-p2@dd {
1331 reg = <0xdd 0x2>;
1332 bits = <4 6>;
1333 };
1334
1335 tsens_s5_p2: s5-p2@de {
1336 reg = <0xde 0x2>;
1337 bits = <2 6>;
1338 };
1339
1340 tsens_s6_p2: s6-p2@df {
1341 reg = <0xdf 0x1>;
1342 bits = <0 6>;
1343 };
1344
1345 tsens_s7_p2: s7-p2@e0 {
1346 reg = <0xe0 0x1>;
1347 bits = <0 6>;
1348 };
1349
1350 tsens_s8_p2: s8-p2@e0 {
1351 reg = <0xe0 0x2>;
1352 bits = <6 6>;
1353 };
1354
1355 tsens_s9_p2: s9-p2@e1 {
1356 reg = <0xe1 0x2>;
1357 bits = <4 6>;
1358 };
1359
1360 tsens_s10_p2: s10_p2@e2 {
1361 reg = <0xe2 0x2>;
1362 bits = <2 6>;
1363 };
1364
1365 tsens_s5_p2_backup: s5-p2_backup@e3 {
1366 reg = <0xe3 0x2>;
1367 bits = <0 6>;
1368 };
1369
1370 tsens_mode_backup: mode_backup@e3 {
1371 reg = <0xe3 0x1>;
1372 bits = <6 2>;
1373 };
1374
1375 tsens_s6_p2_backup: s6-p2_backup@e4 {
1376 reg = <0xe4 0x1>;
1377 bits = <0 6>;
1378 };
1379
1380 tsens_s7_p2_backup: s7-p2_backup@e4 {
1381 reg = <0xe4 0x2>;
1382 bits = <6 6>;
1383 };
1384
1385 tsens_s8_p2_backup: s8-p2_backup@e5 {
1386 reg = <0xe5 0x2>;
1387 bits = <4 6>;
1388 };
1389
1390 tsens_s9_p2_backup: s9-p2_backup@e6 {
1391 reg = <0xe6 0x2>;
1392 bits = <2 6>;
1393 };
1394
1395 tsens_s10_p2_backup: s10_p2_backup@e7 {
1396 reg = <0xe7 0x1>;
1397 bits = <0 6>;
1398 };
1399
1400 tsens_base1_backup: base1_backup@440 {
1401 reg = <0x440 0x1>;
1402 bits = <0 8>;
1403 };
1404
1405 tsens_s0_p1_backup: s0-p1_backup@441 {
1406 reg = <0x441 0x1>;
1407 bits = <0 6>;
1408 };
1409
1410 tsens_s1_p1_backup: s1-p1_backup@442 {
1411 reg = <0x441 0x2>;
1412 bits = <6 6>;
1413 };
1414
1415 tsens_s2_p1_backup: s2-p1_backup@442 {
1416 reg = <0x442 0x2>;
1417 bits = <4 6>;
1418 };
1419
1420 tsens_s3_p1_backup: s3-p1_backup@443 {
1421 reg = <0x443 0x1>;
1422 bits = <2 6>;
1423 };
1424
1425 tsens_s4_p1_backup: s4-p1_backup@444 {
1426 reg = <0x444 0x1>;
1427 bits = <0 6>;
1428 };
1429
1430 tsens_s5_p1_backup: s5-p1_backup@444 {
1431 reg = <0x444 0x2>;
1432 bits = <6 6>;
1433 };
1434
1435 tsens_s6_p1_backup: s6-p1_backup@445 {
1436 reg = <0x445 0x2>;
1437 bits = <4 6>;
1438 };
1439
1440 tsens_s7_p1_backup: s7-p1_backup@446 {
1441 reg = <0x446 0x1>;
1442 bits = <2 6>;
1443 };
1444
1445 tsens_use_backup: use_backup@447 {
1446 reg = <0x447 0x1>;
1447 bits = <5 3>;
1448 };
1449
1450 tsens_s8_p1_backup: s8-p1_backup@448 {
1451 reg = <0x448 0x1>;
1452 bits = <0 6>;
1453 };
1454
1455 tsens_s9_p1_backup: s9-p1_backup@448 {
1456 reg = <0x448 0x2>;
1457 bits = <6 6>;
1458 };
1459
1460 tsens_s10_p1_backup: s10_p1_backup@449 {
1461 reg = <0x449 0x2>;
1462 bits = <4 6>;
1463 };
1464
1465 tsens_base2_backup: base2_backup@44a {
1466 reg = <0x44a 0x2>;
1467 bits = <2 8>;
1468 };
1469
1470 tsens_s0_p2_backup: s0-p2_backup@44b {
1471 reg = <0x44b 0x3>;
1472 bits = <2 6>;
1473 };
1474
1475 tsens_s1_p2_backup: s1-p2_backup@44c {
1476 reg = <0x44c 0x1>;
1477 bits = <0 6>;
1478 };
1479
1480 tsens_s2_p2_backup: s2-p2_backup@44c {
1481 reg = <0x44c 0x2>;
1482 bits = <6 6>;
1483 };
1484
1485 tsens_s3_p2_backup: s3-p2_backup@44d {
1486 reg = <0x44d 0x2>;
1487 bits = <4 6>;
1488 };
1489
1490 tsens_s4_p2_backup: s4-p2_backup@44e {
1491 reg = <0x44e 0x1>;
1492 bits = <2 6>;
1493 };
1494 };
1495
1496 spmi_bus: spmi@fc4cf000 {
1497 compatible = "qcom,spmi-pmic-arb";
1498 reg-names = "core", "intr", "cnfg";
1499 reg = <0xfc4cf000 0x1000>,
1500 <0xfc4cb000 0x1000>,
1501 <0xfc4ca000 0x1000>;
1502 interrupt-names = "periph_irq";
1503 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1504 qcom,ee = <0>;
1505 qcom,channel = <0>;
1506 #address-cells = <2>;
1507 #size-cells = <0>;
1508 interrupt-controller;
1509 #interrupt-cells = <4>;
1510 };
1511
1512 bam_dmux_dma: dma-controller@fc834000 {
1513 compatible = "qcom,bam-v1.4.0";
1514 reg = <0xfc834000 0x7000>;
1515 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1516 #dma-cells = <1>;
1517 qcom,ee = <0>;
1518
1519 num-channels = <6>;
1520 qcom,num-ees = <1>;
1521 qcom,powered-remotely;
1522 };
1523
1524 remoteproc_mss: remoteproc@fc880000 {
1525 compatible = "qcom,msm8974-mss-pil";
1526 reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
1527 reg-names = "qdsp6", "rmb";
1528
1529 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1530 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1531 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1532 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1533 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1534 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1535
1536 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1537 <&gcc GCC_MSS_CFG_AHB_CLK>,
1538 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1539 <&xo_board>;
1540 clock-names = "iface", "bus", "mem", "xo";
1541
1542 resets = <&gcc GCC_MSS_RESTART>;
1543 reset-names = "mss_restart";
1544
1545 qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>;
1546
1547 qcom,smem-states = <&modem_smp2p_out 0>;
1548 qcom,smem-state-names = "stop";
1549
1550 status = "disabled";
1551
1552 mba {
1553 memory-region = <&mba_region>;
1554 };
1555
1556 mpss {
1557 memory-region = <&mpss_region>;
1558 };
1559
1560 bam_dmux: bam-dmux {
1561 compatible = "qcom,bam-dmux";
1562
1563 interrupt-parent = <&modem_smsm>;
1564 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1565 interrupt-names = "pc", "pc-ack";
1566
1567 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1568 qcom,smem-state-names = "pc", "pc-ack";
1569
1570 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1571 dma-names = "tx", "rx";
1572 };
1573
1574 smd-edge {
1575 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1576
1577 qcom,ipc = <&apcs 8 12>;
1578 qcom,smd-edge = <0>;
1579
1580 label = "modem";
1581 };
1582 };
1583
1584 tcsr_mutex: hwlock@fd484000 {
1585 compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon";
1586 reg = <0xfd484000 0x2000>;
1587 #hwlock-cells = <1>;
1588 };
1589
1590 tcsr: syscon@fd4a0000 {
1591 compatible = "qcom,tcsr-msm8974", "syscon";
1592 reg = <0xfd4a0000 0x10000>;
1593 };
1594
1595 tlmm: pinctrl@fd510000 {
1596 compatible = "qcom,msm8974-pinctrl";
1597 reg = <0xfd510000 0x4000>;
1598 gpio-controller;
1599 gpio-ranges = <&tlmm 0 0 146>;
1600 #gpio-cells = <2>;
1601 interrupt-controller;
1602 #interrupt-cells = <2>;
1603 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1604
1605 sdc1_off: sdc1-off-state {
1606 clk-pins {
1607 pins = "sdc1_clk";
1608 bias-disable;
1609 drive-strength = <2>;
1610 };
1611
1612 cmd-pins {
1613 pins = "sdc1_cmd";
1614 bias-pull-up;
1615 drive-strength = <2>;
1616 };
1617
1618 data-pins {
1619 pins = "sdc1_data";
1620 bias-pull-up;
1621 drive-strength = <2>;
1622 };
1623 };
1624
1625 sdc2_off: sdc2-off-state {
1626 clk-pins {
1627 pins = "sdc2_clk";
1628 bias-disable;
1629 drive-strength = <2>;
1630 };
1631
1632 cmd-pins {
1633 pins = "sdc2_cmd";
1634 bias-pull-up;
1635 drive-strength = <2>;
1636 };
1637
1638 data-pins {
1639 pins = "sdc2_data";
1640 bias-pull-up;
1641 drive-strength = <2>;
1642 };
1643 };
1644
1645 blsp1_uart2_default: blsp1-uart2-default-state {
1646 rx-pins {
1647 pins = "gpio5";
1648 function = "blsp_uart2";
1649 drive-strength = <2>;
1650 bias-pull-up;
1651 };
1652
1653 tx-pins {
1654 pins = "gpio4";
1655 function = "blsp_uart2";
1656 drive-strength = <4>;
1657 bias-disable;
1658 };
1659 };
1660
1661 blsp2_uart1_default: blsp2-uart1-default-state {
1662 tx-rts-pins {
1663 pins = "gpio41", "gpio44";
1664 function = "blsp_uart7";
1665 drive-strength = <2>;
1666 bias-disable;
1667 };
1668
1669 rx-cts-pins {
1670 pins = "gpio42", "gpio43";
1671 function = "blsp_uart7";
1672 drive-strength = <2>;
1673 bias-pull-up;
1674 };
1675 };
1676
1677 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
1678 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1679 function = "gpio";
1680 drive-strength = <2>;
1681 bias-pull-down;
1682 };
1683
1684 blsp2_uart4_default: blsp2-uart4-default-state {
1685 tx-rts-pins {
1686 pins = "gpio53", "gpio56";
1687 function = "blsp_uart10";
1688 drive-strength = <2>;
1689 bias-disable;
1690 };
1691
1692 rx-cts-pins {
1693 pins = "gpio54", "gpio55";
1694 function = "blsp_uart10";
1695 drive-strength = <2>;
1696 bias-pull-up;
1697 };
1698 };
1699
1700 blsp1_i2c1_default: blsp1-i2c1-default-state {
1701 pins = "gpio2", "gpio3";
1702 function = "blsp_i2c1";
1703 drive-strength = <2>;
1704 bias-disable;
1705 };
1706
1707 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state {
1708 pins = "gpio2", "gpio3";
1709 function = "blsp_i2c1";
1710 drive-strength = <2>;
1711 bias-pull-up;
1712 };
1713
1714 blsp1_i2c2_default: blsp1-i2c2-default-state {
1715 pins = "gpio6", "gpio7";
1716 function = "blsp_i2c2";
1717 drive-strength = <2>;
1718 bias-disable;
1719 };
1720
1721 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
1722 pins = "gpio6", "gpio7";
1723 function = "blsp_i2c2";
1724 drive-strength = <2>;
1725 bias-pull-up;
1726 };
1727
1728 blsp1_i2c3_default: blsp1-i2c3-default-state {
1729 pins = "gpio10", "gpio11";
1730 function = "blsp_i2c3";
1731 drive-strength = <2>;
1732 bias-disable;
1733 };
1734
1735 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1736 pins = "gpio10", "gpio11";
1737 function = "blsp_i2c3";
1738 drive-strength = <2>;
1739 bias-pull-up;
1740 };
1741
1742 /* BLSP1_I2C4 info is missing */
1743
1744 /* BLSP1_I2C5 info is missing */
1745
1746 blsp1_i2c6_default: blsp1-i2c6-default-state {
1747 pins = "gpio29", "gpio30";
1748 function = "blsp_i2c6";
1749 drive-strength = <2>;
1750 bias-disable;
1751 };
1752
1753 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1754 pins = "gpio29", "gpio30";
1755 function = "blsp_i2c6";
1756 drive-strength = <2>;
1757 bias-pull-up;
1758 };
1759 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1760
1761 /* BLSP2_I2C1 info is missing */
1762
1763 blsp2_i2c2_default: blsp2-i2c2-default-state {
1764 pins = "gpio47", "gpio48";
1765 function = "blsp_i2c8";
1766 drive-strength = <2>;
1767 bias-disable;
1768 };
1769
1770 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1771 pins = "gpio47", "gpio48";
1772 function = "blsp_i2c8";
1773 drive-strength = <2>;
1774 bias-pull-up;
1775 };
1776
1777 /* BLSP2_I2C3 info is missing */
1778
1779 /* BLSP2_I2C4 info is missing */
1780
1781 blsp2_i2c5_default: blsp2-i2c5-default-state {
1782 pins = "gpio83", "gpio84";
1783 function = "blsp_i2c11";
1784 drive-strength = <2>;
1785 bias-disable;
1786 };
1787
1788 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1789 pins = "gpio83", "gpio84";
1790 function = "blsp_i2c11";
1791 drive-strength = <2>;
1792 bias-pull-up;
1793 };
1794
1795 blsp2_i2c6_default: blsp2-i2c6-default-state {
1796 pins = "gpio87", "gpio88";
1797 function = "blsp_i2c12";
1798 drive-strength = <2>;
1799 bias-disable;
1800 };
1801
1802 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1803 pins = "gpio87", "gpio88";
1804 function = "blsp_i2c12";
1805 drive-strength = <2>;
1806 bias-pull-up;
1807 };
1808
1809 cci_default: cci-default-state {
1810 cci_i2c0_default: cci-i2c0-default-pins {
1811 pins = "gpio19", "gpio20";
1812 function = "cci_i2c0";
1813 drive-strength = <2>;
1814 bias-disable;
1815 };
1816
1817 cci_i2c1_default: cci-i2c1-default-pins {
1818 pins = "gpio21", "gpio22";
1819 function = "cci_i2c1";
1820 drive-strength = <2>;
1821 bias-disable;
1822 };
1823 };
1824
1825 cci_sleep: cci-sleep-state {
1826 cci_i2c0_sleep: cci-i2c0-sleep-pins {
1827 pins = "gpio19", "gpio20";
1828 function = "gpio";
1829 drive-strength = <2>;
1830 bias-disable;
1831 };
1832
1833 cci_i2c1_sleep: cci-i2c1-sleep-pins {
1834 pins = "gpio21", "gpio22";
1835 function = "gpio";
1836 drive-strength = <2>;
1837 bias-disable;
1838 };
1839 };
1840
1841 spi8_default: spi8_default-state {
1842 mosi-pins {
1843 pins = "gpio45";
1844 function = "blsp_spi8";
1845 };
1846 miso-pins {
1847 pins = "gpio46";
1848 function = "blsp_spi8";
1849 };
1850 cs-pins {
1851 pins = "gpio47";
1852 function = "blsp_spi8";
1853 };
1854 clk-pins {
1855 pins = "gpio48";
1856 function = "blsp_spi8";
1857 };
1858 };
1859 };
1860
1861 mmcc: clock-controller@fd8c0000 {
1862 compatible = "qcom,mmcc-msm8974";
1863 #clock-cells = <1>;
1864 #reset-cells = <1>;
1865 #power-domain-cells = <1>;
1866 reg = <0xfd8c0000 0x6000>;
1867 clocks = <&xo_board>,
1868 <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
1869 <&gcc GPLL0_VOTE>,
1870 <&gcc GPLL1_VOTE>,
1871 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1872 <&mdss_dsi0_phy 1>,
1873 <&mdss_dsi0_phy 0>,
1874 <&mdss_dsi1_phy 1>,
1875 <&mdss_dsi1_phy 0>,
1876 <0>,
1877 <0>,
1878 <0>;
1879 clock-names = "xo",
1880 "mmss_gpll0_vote",
1881 "gpll0_vote",
1882 "gpll1_vote",
1883 "gfx3d_clk_src",
1884 "dsi0pll",
1885 "dsi0pllbyte",
1886 "dsi1pll",
1887 "dsi1pllbyte",
1888 "hdmipll",
1889 "edp_link_clk",
1890 "edp_vco_div";
1891 };
1892
1893 mdss: display-subsystem@fd900000 {
1894 compatible = "qcom,mdss";
1895 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1896 reg-names = "mdss_phys", "vbif_phys";
1897
1898 power-domains = <&mmcc MDSS_GDSC>;
1899
1900 clocks = <&mmcc MDSS_AHB_CLK>,
1901 <&mmcc MDSS_AXI_CLK>,
1902 <&mmcc MDSS_VSYNC_CLK>;
1903 clock-names = "iface", "bus", "vsync";
1904
1905 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1906
1907 interrupt-controller;
1908 #interrupt-cells = <1>;
1909
1910 status = "disabled";
1911
1912 #address-cells = <1>;
1913 #size-cells = <1>;
1914 ranges;
1915
1916 mdp: display-controller@fd900000 {
1917 compatible = "qcom,msm8974-mdp5", "qcom,mdp5";
1918 reg = <0xfd900100 0x22000>;
1919 reg-names = "mdp_phys";
1920
1921 interrupt-parent = <&mdss>;
1922 interrupts = <0>;
1923
1924 clocks = <&mmcc MDSS_AHB_CLK>,
1925 <&mmcc MDSS_AXI_CLK>,
1926 <&mmcc MDSS_MDP_CLK>,
1927 <&mmcc MDSS_VSYNC_CLK>;
1928 clock-names = "iface", "bus", "core", "vsync";
1929
1930 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
1931 interconnect-names = "mdp0-mem";
1932
1933 ports {
1934 #address-cells = <1>;
1935 #size-cells = <0>;
1936
1937 port@0 {
1938 reg = <0>;
1939 mdp5_intf1_out: endpoint {
1940 remote-endpoint = <&mdss_dsi0_in>;
1941 };
1942 };
1943
1944 port@1 {
1945 reg = <1>;
1946 mdp5_intf2_out: endpoint {
1947 remote-endpoint = <&mdss_dsi1_in>;
1948 };
1949 };
1950 };
1951 };
1952
1953 mdss_dsi0: dsi@fd922800 {
1954 compatible = "qcom,msm8974-dsi-ctrl",
1955 "qcom,mdss-dsi-ctrl";
1956 reg = <0xfd922800 0x1f8>;
1957 reg-names = "dsi_ctrl";
1958
1959 interrupt-parent = <&mdss>;
1960 interrupts = <4>;
1961
1962 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1963 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1964
1965 clocks = <&mmcc MDSS_MDP_CLK>,
1966 <&mmcc MDSS_AHB_CLK>,
1967 <&mmcc MDSS_AXI_CLK>,
1968 <&mmcc MDSS_BYTE0_CLK>,
1969 <&mmcc MDSS_PCLK0_CLK>,
1970 <&mmcc MDSS_ESC0_CLK>,
1971 <&mmcc MMSS_MISC_AHB_CLK>;
1972 clock-names = "mdp_core",
1973 "iface",
1974 "bus",
1975 "byte",
1976 "pixel",
1977 "core",
1978 "core_mmss";
1979
1980 phys = <&mdss_dsi0_phy>;
1981
1982 status = "disabled";
1983
1984 #address-cells = <1>;
1985 #size-cells = <0>;
1986
1987 ports {
1988 #address-cells = <1>;
1989 #size-cells = <0>;
1990
1991 port@0 {
1992 reg = <0>;
1993 mdss_dsi0_in: endpoint {
1994 remote-endpoint = <&mdp5_intf1_out>;
1995 };
1996 };
1997
1998 port@1 {
1999 reg = <1>;
2000 mdss_dsi0_out: endpoint {
2001 };
2002 };
2003 };
2004 };
2005
2006 mdss_dsi0_phy: phy@fd922a00 {
2007 compatible = "qcom,dsi-phy-28nm-hpm";
2008 reg = <0xfd922a00 0xd4>,
2009 <0xfd922b00 0x280>,
2010 <0xfd922d80 0x30>;
2011 reg-names = "dsi_pll",
2012 "dsi_phy",
2013 "dsi_phy_regulator";
2014
2015 #clock-cells = <1>;
2016 #phy-cells = <0>;
2017
2018 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
2019 clock-names = "iface", "ref";
2020
2021 status = "disabled";
2022 };
2023
2024 mdss_dsi1: dsi@fd922e00 {
2025 compatible = "qcom,msm8974-dsi-ctrl",
2026 "qcom,mdss-dsi-ctrl";
2027 reg = <0xfd922e00 0x1f8>;
2028 reg-names = "dsi_ctrl";
2029
2030 interrupt-parent = <&mdss>;
2031 interrupts = <4>;
2032
2033 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
2034 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
2035
2036 clocks = <&mmcc MDSS_MDP_CLK>,
2037 <&mmcc MDSS_AHB_CLK>,
2038 <&mmcc MDSS_AXI_CLK>,
2039 <&mmcc MDSS_BYTE1_CLK>,
2040 <&mmcc MDSS_PCLK1_CLK>,
2041 <&mmcc MDSS_ESC1_CLK>,
2042 <&mmcc MMSS_MISC_AHB_CLK>;
2043 clock-names = "mdp_core",
2044 "iface",
2045 "bus",
2046 "byte",
2047 "pixel",
2048 "core",
2049 "core_mmss";
2050
2051 phys = <&mdss_dsi1_phy>;
2052
2053 status = "disabled";
2054
2055 #address-cells = <1>;
2056 #size-cells = <0>;
2057
2058 ports {
2059 #address-cells = <1>;
2060 #size-cells = <0>;
2061
2062 port@0 {
2063 reg = <0>;
2064 mdss_dsi1_in: endpoint {
2065 remote-endpoint = <&mdp5_intf2_out>;
2066 };
2067 };
2068
2069 port@1 {
2070 reg = <1>;
2071 mdss_dsi1_out: endpoint {
2072 };
2073 };
2074 };
2075 };
2076
2077 mdss_dsi1_phy: phy@fd923000 {
2078 compatible = "qcom,dsi-phy-28nm-hpm";
2079 reg = <0xfd923000 0xd4>,
2080 <0xfd923100 0x280>,
2081 <0xfd923380 0x30>;
2082 reg-names = "dsi_pll",
2083 "dsi_phy",
2084 "dsi_phy_regulator";
2085
2086 #clock-cells = <1>;
2087 #phy-cells = <0>;
2088
2089 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
2090 clock-names = "iface", "ref";
2091
2092 status = "disabled";
2093 };
2094 };
2095
2096 cci: cci@fda0c000 {
2097 compatible = "qcom,msm8974-cci";
2098 #address-cells = <1>;
2099 #size-cells = <0>;
2100 reg = <0xfda0c000 0x1000>;
2101 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
2102 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2103 <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
2104 <&mmcc CAMSS_CCI_CCI_CLK>;
2105 clock-names = "camss_top_ahb",
2106 "cci_ahb",
2107 "cci";
2108
2109 pinctrl-names = "default", "sleep";
2110 pinctrl-0 = <&cci_default>;
2111 pinctrl-1 = <&cci_sleep>;
2112
2113 status = "disabled";
2114
2115 cci_i2c0: i2c-bus@0 {
2116 reg = <0>;
2117 clock-frequency = <100000>;
2118 #address-cells = <1>;
2119 #size-cells = <0>;
2120 };
2121
2122 cci_i2c1: i2c-bus@1 {
2123 reg = <1>;
2124 clock-frequency = <100000>;
2125 #address-cells = <1>;
2126 #size-cells = <0>;
2127 };
2128 };
2129
2130 gpu: adreno@fdb00000 {
2131 compatible = "qcom,adreno-330.1", "qcom,adreno";
2132 reg = <0xfdb00000 0x10000>;
2133 reg-names = "kgsl_3d0_reg_memory";
2134
2135 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2136 interrupt-names = "kgsl_3d0_irq";
2137
2138 clocks = <&mmcc OXILI_GFX3D_CLK>,
2139 <&mmcc OXILICX_AHB_CLK>,
2140 <&mmcc OXILICX_AXI_CLK>;
2141 clock-names = "core", "iface", "mem_iface";
2142
2143 sram = <&gmu_sram>;
2144 power-domains = <&mmcc OXILICX_GDSC>;
2145 operating-points-v2 = <&gpu_opp_table>;
2146
2147 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
2148 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
2149 interconnect-names = "gfx-mem", "ocmem";
2150
2151 // iommus = <&gpu_iommu 0>;
2152
2153 status = "disabled";
2154
2155 gpu_opp_table: opp-table {
2156 compatible = "operating-points-v2";
2157
2158 opp-320000000 {
2159 opp-hz = /bits/ 64 <320000000>;
2160 };
2161
2162 opp-200000000 {
2163 opp-hz = /bits/ 64 <200000000>;
2164 };
2165
2166 opp-27000000 {
2167 opp-hz = /bits/ 64 <27000000>;
2168 };
2169 };
2170 };
2171
2172 sram@fdd00000 {
2173 compatible = "qcom,msm8974-ocmem";
2174 reg = <0xfdd00000 0x2000>,
2175 <0xfec00000 0x180000>;
2176 reg-names = "ctrl", "mem";
2177 ranges = <0 0xfec00000 0x180000>;
2178 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
2179 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
2180 clock-names = "core", "iface";
2181
2182 #address-cells = <1>;
2183 #size-cells = <1>;
2184
2185 gmu_sram: gmu-sram@0 {
2186 reg = <0x0 0x100000>;
2187 };
2188 };
2189
2190 remoteproc_adsp: remoteproc@fe200000 {
2191 compatible = "qcom,msm8974-adsp-pil";
2192 reg = <0xfe200000 0x100>;
2193
2194 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2195 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2196 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2197 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2198 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2199 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
2200
2201 clocks = <&xo_board>;
2202 clock-names = "xo";
2203
2204 memory-region = <&adsp_region>;
2205
2206 qcom,smem-states = <&adsp_smp2p_out 0>;
2207 qcom,smem-state-names = "stop";
2208
2209 status = "disabled";
2210
2211 smd-edge {
2212 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2213
2214 qcom,ipc = <&apcs 8 8>;
2215 qcom,smd-edge = <1>;
2216 label = "lpass";
2217 };
2218 };
2219
2220 imem: sram@fe805000 {
2221 compatible = "qcom,msm8974-imem", "syscon", "simple-mfd";
2222 reg = <0xfe805000 0x1000>;
2223
2224 reboot-mode {
2225 compatible = "syscon-reboot-mode";
2226 offset = <0x65c>;
2227 };
2228 };
2229 };
2230
2231 thermal-zones {
2232 cpu0-thermal {
2233 polling-delay-passive = <250>;
2234 polling-delay = <1000>;
2235
2236 thermal-sensors = <&tsens 5>;
2237
2238 trips {
2239 cpu_alert0: trip0 {
2240 temperature = <75000>;
2241 hysteresis = <2000>;
2242 type = "passive";
2243 };
2244 cpu_crit0: trip1 {
2245 temperature = <110000>;
2246 hysteresis = <2000>;
2247 type = "critical";
2248 };
2249 };
2250 };
2251
2252 cpu1-thermal {
2253 polling-delay-passive = <250>;
2254 polling-delay = <1000>;
2255
2256 thermal-sensors = <&tsens 6>;
2257
2258 trips {
2259 cpu_alert1: trip0 {
2260 temperature = <75000>;
2261 hysteresis = <2000>;
2262 type = "passive";
2263 };
2264 cpu_crit1: trip1 {
2265 temperature = <110000>;
2266 hysteresis = <2000>;
2267 type = "critical";
2268 };
2269 };
2270 };
2271
2272 cpu2-thermal {
2273 polling-delay-passive = <250>;
2274 polling-delay = <1000>;
2275
2276 thermal-sensors = <&tsens 7>;
2277
2278 trips {
2279 cpu_alert2: trip0 {
2280 temperature = <75000>;
2281 hysteresis = <2000>;
2282 type = "passive";
2283 };
2284 cpu_crit2: trip1 {
2285 temperature = <110000>;
2286 hysteresis = <2000>;
2287 type = "critical";
2288 };
2289 };
2290 };
2291
2292 cpu3-thermal {
2293 polling-delay-passive = <250>;
2294 polling-delay = <1000>;
2295
2296 thermal-sensors = <&tsens 8>;
2297
2298 trips {
2299 cpu_alert3: trip0 {
2300 temperature = <75000>;
2301 hysteresis = <2000>;
2302 type = "passive";
2303 };
2304 cpu_crit3: trip1 {
2305 temperature = <110000>;
2306 hysteresis = <2000>;
2307 type = "critical";
2308 };
2309 };
2310 };
2311
2312 q6-dsp-thermal {
2313 polling-delay-passive = <250>;
2314 polling-delay = <1000>;
2315
2316 thermal-sensors = <&tsens 1>;
2317
2318 trips {
2319 q6_dsp_alert0: trip-point0 {
2320 temperature = <90000>;
2321 hysteresis = <2000>;
2322 type = "hot";
2323 };
2324 };
2325 };
2326
2327 modemtx-thermal {
2328 polling-delay-passive = <250>;
2329 polling-delay = <1000>;
2330
2331 thermal-sensors = <&tsens 2>;
2332
2333 trips {
2334 modemtx_alert0: trip-point0 {
2335 temperature = <90000>;
2336 hysteresis = <2000>;
2337 type = "hot";
2338 };
2339 };
2340 };
2341
2342 video-thermal {
2343 polling-delay-passive = <250>;
2344 polling-delay = <1000>;
2345
2346 thermal-sensors = <&tsens 3>;
2347
2348 trips {
2349 video_alert0: trip-point0 {
2350 temperature = <95000>;
2351 hysteresis = <2000>;
2352 type = "hot";
2353 };
2354 };
2355 };
2356
2357 wlan-thermal {
2358 polling-delay-passive = <250>;
2359 polling-delay = <1000>;
2360
2361 thermal-sensors = <&tsens 4>;
2362
2363 trips {
2364 wlan_alert0: trip-point0 {
2365 temperature = <105000>;
2366 hysteresis = <2000>;
2367 type = "hot";
2368 };
2369 };
2370 };
2371
2372 gpu-top-thermal {
2373 polling-delay-passive = <250>;
2374 polling-delay = <1000>;
2375
2376 thermal-sensors = <&tsens 9>;
2377
2378 trips {
2379 gpu1_alert0: trip-point0 {
2380 temperature = <90000>;
2381 hysteresis = <2000>;
2382 type = "hot";
2383 };
2384 };
2385 };
2386
2387 gpu-bottom-thermal {
2388 polling-delay-passive = <250>;
2389 polling-delay = <1000>;
2390
2391 thermal-sensors = <&tsens 10>;
2392
2393 trips {
2394 gpu2_alert0: trip-point0 {
2395 temperature = <90000>;
2396 hysteresis = <2000>;
2397 type = "hot";
2398 };
2399 };
2400 };
2401 };
2402
2403 timer {
2404 compatible = "arm,armv7-timer";
2405 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2406 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2407 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2408 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2409 clock-frequency = <19200000>;
2410 };
2411};