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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8660.h>
7#include <dt-bindings/soc/qcom,gsbi.h>
8
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12 model = "Qualcomm MSM8660";
13 compatible = "qcom,msm8660";
14 interrupt-parent = <&intc>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 compatible = "qcom,scorpion";
22 enable-method = "qcom,gcc-msm8660";
23 device_type = "cpu";
24 reg = <0>;
25 next-level-cache = <&L2>;
26 };
27
28 cpu@1 {
29 compatible = "qcom,scorpion";
30 enable-method = "qcom,gcc-msm8660";
31 device_type = "cpu";
32 reg = <1>;
33 next-level-cache = <&L2>;
34 };
35
36 L2: l2-cache {
37 compatible = "cache";
38 cache-level = <2>;
39 cache-unified;
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 reg = <0x0 0x0>;
46 };
47
48 cpu-pmu {
49 compatible = "qcom,scorpion-mp-pmu";
50 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
51 };
52
53 clocks {
54 cxo_board: cxo-board-clk {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <19200000>;
58 clock-output-names = "cxo_board";
59 };
60
61 pxo_board: pxo-board-clk {
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <27000000>;
65 clock-output-names = "pxo_board";
66 };
67
68 sleep-clk {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <32768>;
72 clock-output-names = "sleep_clk";
73 };
74 };
75
76 soc: soc {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80 compatible = "simple-bus";
81
82 intc: interrupt-controller@2080000 {
83 compatible = "qcom,msm-8660-qgic";
84 interrupt-controller;
85 #interrupt-cells = <3>;
86 reg = < 0x02080000 0x1000 >,
87 < 0x02081000 0x1000 >;
88 };
89
90 timer@2000000 {
91 compatible = "qcom,scss-timer", "qcom,msm-timer";
92 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
93 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
94 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
95 reg = <0x02000000 0x100>;
96 clock-frequency = <27000000>;
97 cpu-offset = <0x40000>;
98 };
99
100 tlmm: pinctrl@800000 {
101 compatible = "qcom,msm8660-pinctrl";
102 reg = <0x800000 0x4000>;
103
104 gpio-controller;
105 gpio-ranges = <&tlmm 0 0 173>;
106 #gpio-cells = <2>;
107 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
108 interrupt-controller;
109 #interrupt-cells = <2>;
110
111 };
112
113 gcc: clock-controller@900000 {
114 compatible = "qcom,gcc-msm8660";
115 #clock-cells = <1>;
116 #power-domain-cells = <1>;
117 #reset-cells = <1>;
118 reg = <0x900000 0x4000>;
119 clocks = <&pxo_board>, <&cxo_board>;
120 clock-names = "pxo", "cxo";
121 };
122
123 gsbi1: gsbi@16000000 {
124 compatible = "qcom,gsbi-v1.0.0";
125 cell-index = <12>;
126 reg = <0x16000000 0x100>;
127 clocks = <&gcc GSBI1_H_CLK>;
128 clock-names = "iface";
129 #address-cells = <1>;
130 #size-cells = <1>;
131 ranges;
132
133 syscon-tcsr = <&tcsr>;
134
135 status = "disabled";
136
137 gsbi1_spi: spi@16080000 {
138 compatible = "qcom,spi-qup-v1.1.1";
139 reg = <0x16080000 0x1000>;
140 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
142 clock-names = "core", "iface";
143 #address-cells = <1>;
144 #size-cells = <0>;
145 status = "disabled";
146 };
147 };
148
149 gsbi3: gsbi@16200000 {
150 compatible = "qcom,gsbi-v1.0.0";
151 cell-index = <12>;
152 reg = <0x16200000 0x100>;
153 clocks = <&gcc GSBI3_H_CLK>;
154 clock-names = "iface";
155 #address-cells = <1>;
156 #size-cells = <1>;
157 ranges;
158
159 syscon-tcsr = <&tcsr>;
160 status = "disabled";
161
162 gsbi3_i2c: i2c@16280000 {
163 compatible = "qcom,i2c-qup-v1.1.1";
164 reg = <0x16280000 0x1000>;
165 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
167 clock-names = "core", "iface";
168 #address-cells = <1>;
169 #size-cells = <0>;
170 status = "disabled";
171 };
172 };
173
174 gsbi6: gsbi@16500000 {
175 compatible = "qcom,gsbi-v1.0.0";
176 cell-index = <12>;
177 reg = <0x16500000 0x100>;
178 clocks = <&gcc GSBI6_H_CLK>;
179 clock-names = "iface";
180 #address-cells = <1>;
181 #size-cells = <1>;
182 ranges;
183 status = "disabled";
184
185 syscon-tcsr = <&tcsr>;
186
187 gsbi6_serial: serial@16540000 {
188 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
189 reg = <0x16540000 0x1000>,
190 <0x16500000 0x1000>;
191 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
193 clock-names = "core", "iface";
194 status = "disabled";
195 };
196
197 gsbi6_i2c: i2c@16580000 {
198 compatible = "qcom,i2c-qup-v1.1.1";
199 reg = <0x16580000 0x1000>;
200 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
202 clock-names = "core", "iface";
203 #address-cells = <1>;
204 #size-cells = <0>;
205 status = "disabled";
206 };
207 };
208
209 gsbi7: gsbi@16600000 {
210 compatible = "qcom,gsbi-v1.0.0";
211 cell-index = <12>;
212 reg = <0x16600000 0x100>;
213 clocks = <&gcc GSBI7_H_CLK>;
214 clock-names = "iface";
215 #address-cells = <1>;
216 #size-cells = <1>;
217 ranges;
218 status = "disabled";
219
220 syscon-tcsr = <&tcsr>;
221
222 gsbi7_serial: serial@16640000 {
223 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
224 reg = <0x16640000 0x1000>,
225 <0x16600000 0x1000>;
226 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
228 clock-names = "core", "iface";
229 status = "disabled";
230 };
231
232 gsbi7_i2c: i2c@16680000 {
233 compatible = "qcom,i2c-qup-v1.1.1";
234 reg = <0x16680000 0x1000>;
235 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
237 clock-names = "core", "iface";
238 #address-cells = <1>;
239 #size-cells = <0>;
240 status = "disabled";
241 };
242 };
243
244 gsbi8: gsbi@19800000 {
245 compatible = "qcom,gsbi-v1.0.0";
246 cell-index = <12>;
247 reg = <0x19800000 0x100>;
248 clocks = <&gcc GSBI8_H_CLK>;
249 clock-names = "iface";
250 #address-cells = <1>;
251 #size-cells = <1>;
252 ranges;
253
254 syscon-tcsr = <&tcsr>;
255 status = "disabled";
256
257 gsbi8_i2c: i2c@19880000 {
258 compatible = "qcom,i2c-qup-v1.1.1";
259 reg = <0x19880000 0x1000>;
260 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
262 clock-names = "core", "iface";
263 #address-cells = <1>;
264 #size-cells = <0>;
265 status = "disabled";
266 };
267 };
268
269 gsbi12: gsbi@19c00000 {
270 compatible = "qcom,gsbi-v1.0.0";
271 cell-index = <12>;
272 reg = <0x19c00000 0x100>;
273 clocks = <&gcc GSBI12_H_CLK>;
274 clock-names = "iface";
275 #address-cells = <1>;
276 #size-cells = <1>;
277 ranges;
278
279 syscon-tcsr = <&tcsr>;
280
281 gsbi12_serial: serial@19c40000 {
282 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
283 reg = <0x19c40000 0x1000>,
284 <0x19c00000 0x1000>;
285 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
287 clock-names = "core", "iface";
288 status = "disabled";
289 };
290
291 gsbi12_i2c: i2c@19c80000 {
292 compatible = "qcom,i2c-qup-v1.1.1";
293 reg = <0x19c80000 0x1000>;
294 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
296 clock-names = "core", "iface";
297 #address-cells = <1>;
298 #size-cells = <0>;
299 status = "disabled";
300 };
301 };
302
303 ebi2: external-bus@1a100000 {
304 compatible = "qcom,msm8660-ebi2";
305 #address-cells = <2>;
306 #size-cells = <1>;
307 ranges = <0 0x0 0x1a800000 0x00800000>,
308 <1 0x0 0x1b000000 0x00800000>,
309 <2 0x0 0x1b800000 0x00800000>,
310 <3 0x0 0x1d000000 0x08000000>,
311 <4 0x0 0x1c800000 0x00800000>,
312 <5 0x0 0x1c000000 0x00800000>;
313 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
314 reg-names = "ebi2", "xmem";
315 clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
316 clock-names = "ebi2x", "ebi2";
317 status = "disabled";
318 };
319
320 ssbi: ssbi@500000 {
321 compatible = "qcom,ssbi";
322 reg = <0x500000 0x1000>;
323 qcom,controller-type = "pmic-arbiter";
324 };
325
326 l2cc: clock-controller@2082000 {
327 compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon";
328 reg = <0x02082000 0x1000>;
329 };
330
331 rpm: rpm@104000 {
332 compatible = "qcom,rpm-msm8660";
333 reg = <0x00104000 0x1000>;
334 qcom,ipc = <&l2cc 0x8 2>;
335
336 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
337 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
338 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
339 interrupt-names = "ack", "err", "wakeup";
340 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
341 clock-names = "ram";
342
343 rpmcc: clock-controller {
344 compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
345 #clock-cells = <1>;
346 clocks = <&pxo_board>;
347 clock-names = "pxo";
348 };
349 };
350
351 amba {
352 compatible = "simple-bus";
353 #address-cells = <1>;
354 #size-cells = <1>;
355 ranges;
356 sdcc1: mmc@12400000 {
357 status = "disabled";
358 compatible = "arm,pl18x", "arm,primecell";
359 arm,primecell-periphid = <0x00051180>;
360 reg = <0x12400000 0x8000>;
361 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
363 clock-names = "mclk", "apb_pclk";
364 bus-width = <8>;
365 max-frequency = <48000000>;
366 non-removable;
367 cap-sd-highspeed;
368 cap-mmc-highspeed;
369 };
370
371 sdcc2: mmc@12140000 {
372 status = "disabled";
373 compatible = "arm,pl18x", "arm,primecell";
374 arm,primecell-periphid = <0x00051180>;
375 reg = <0x12140000 0x8000>;
376 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
378 clock-names = "mclk", "apb_pclk";
379 bus-width = <8>;
380 max-frequency = <48000000>;
381 cap-sd-highspeed;
382 cap-mmc-highspeed;
383 };
384
385 sdcc3: mmc@12180000 {
386 compatible = "arm,pl18x", "arm,primecell";
387 arm,primecell-periphid = <0x00051180>;
388 status = "disabled";
389 reg = <0x12180000 0x8000>;
390 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
392 clock-names = "mclk", "apb_pclk";
393 bus-width = <4>;
394 cap-sd-highspeed;
395 cap-mmc-highspeed;
396 max-frequency = <48000000>;
397 no-1-8-v;
398 };
399
400 sdcc4: mmc@121c0000 {
401 compatible = "arm,pl18x", "arm,primecell";
402 arm,primecell-periphid = <0x00051180>;
403 status = "disabled";
404 reg = <0x121c0000 0x8000>;
405 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
407 clock-names = "mclk", "apb_pclk";
408 bus-width = <4>;
409 max-frequency = <48000000>;
410 cap-sd-highspeed;
411 cap-mmc-highspeed;
412 };
413
414 sdcc5: mmc@12200000 {
415 compatible = "arm,pl18x", "arm,primecell";
416 arm,primecell-periphid = <0x00051180>;
417 status = "disabled";
418 reg = <0x12200000 0x8000>;
419 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
421 clock-names = "mclk", "apb_pclk";
422 bus-width = <4>;
423 cap-sd-highspeed;
424 cap-mmc-highspeed;
425 max-frequency = <48000000>;
426 };
427 };
428
429 tcsr: syscon@1a400000 {
430 compatible = "qcom,tcsr-msm8660", "syscon";
431 reg = <0x1a400000 0x100>;
432 };
433 };
434
435};