1/* SPDX-License-Identifier: GPL-2.0-or-later */
 2/*
 3 * Copyright (C) 2013  Horms Solutions Ltd.
 4 *
 5 * Contact: Simon Horman <horms@verge.net.au>
 6 */
 7
 8#ifndef __DT_BINDINGS_CLOCK_R8A7779_H__
 9#define __DT_BINDINGS_CLOCK_R8A7779_H__
10
11/* CPG */
12#define R8A7779_CLK_PLLA	0
13#define R8A7779_CLK_Z		1
14#define R8A7779_CLK_ZS		2
15#define R8A7779_CLK_S		3
16#define R8A7779_CLK_S1		4
17#define R8A7779_CLK_P		5
18#define R8A7779_CLK_B		6
19#define R8A7779_CLK_OUT		7
20
21/* MSTP 0 */
 
22#define R8A7779_CLK_HSPI	7
23#define R8A7779_CLK_TMU2	14
24#define R8A7779_CLK_TMU1	15
25#define R8A7779_CLK_TMU0	16
26#define R8A7779_CLK_HSCIF1	18
27#define R8A7779_CLK_HSCIF0	19
28#define R8A7779_CLK_SCIF5	21
29#define R8A7779_CLK_SCIF4	22
30#define R8A7779_CLK_SCIF3	23
31#define R8A7779_CLK_SCIF2	24
32#define R8A7779_CLK_SCIF1	25
33#define R8A7779_CLK_SCIF0	26
34#define R8A7779_CLK_I2C3	27
35#define R8A7779_CLK_I2C2	28
36#define R8A7779_CLK_I2C1	29
37#define R8A7779_CLK_I2C0	30
38
39/* MSTP 1 */
40#define R8A7779_CLK_USB01	0
41#define R8A7779_CLK_USB2	1
42#define R8A7779_CLK_DU		3
43#define R8A7779_CLK_VIN2	8
44#define R8A7779_CLK_VIN1	9
45#define R8A7779_CLK_VIN0	10
46#define R8A7779_CLK_ETHER	14
47#define R8A7779_CLK_SATA	15
48#define R8A7779_CLK_PCIE	16
49#define R8A7779_CLK_VIN3	20
50
51/* MSTP 3 */
52#define R8A7779_CLK_SDHI3	20
53#define R8A7779_CLK_SDHI2	21
54#define R8A7779_CLK_SDHI1	22
55#define R8A7779_CLK_SDHI0	23
56#define R8A7779_CLK_MMC1	30
57#define R8A7779_CLK_MMC0	31
58
59
60#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */

 1/* SPDX-License-Identifier: GPL-2.0-or-later */
 2/*
 3 * Copyright (C) 2013  Horms Solutions Ltd.
 4 *
 5 * Contact: Simon Horman <horms@verge.net.au>
 6 */
 7
 8#ifndef __DT_BINDINGS_CLOCK_R8A7779_H__
 9#define __DT_BINDINGS_CLOCK_R8A7779_H__
10
11/* CPG */
12#define R8A7779_CLK_PLLA	0
13#define R8A7779_CLK_Z		1
14#define R8A7779_CLK_ZS		2
15#define R8A7779_CLK_S		3
16#define R8A7779_CLK_S1		4
17#define R8A7779_CLK_P		5
18#define R8A7779_CLK_B		6
19#define R8A7779_CLK_OUT		7
20
21/* MSTP 0 */
22#define R8A7779_CLK_PWM		5
23#define R8A7779_CLK_HSPI	7
24#define R8A7779_CLK_TMU2	14
25#define R8A7779_CLK_TMU1	15
26#define R8A7779_CLK_TMU0	16
27#define R8A7779_CLK_HSCIF1	18
28#define R8A7779_CLK_HSCIF0	19
29#define R8A7779_CLK_SCIF5	21
30#define R8A7779_CLK_SCIF4	22
31#define R8A7779_CLK_SCIF3	23
32#define R8A7779_CLK_SCIF2	24
33#define R8A7779_CLK_SCIF1	25
34#define R8A7779_CLK_SCIF0	26
35#define R8A7779_CLK_I2C3	27
36#define R8A7779_CLK_I2C2	28
37#define R8A7779_CLK_I2C1	29
38#define R8A7779_CLK_I2C0	30
39
40/* MSTP 1 */
41#define R8A7779_CLK_USB01	0
42#define R8A7779_CLK_USB2	1
43#define R8A7779_CLK_DU		3
44#define R8A7779_CLK_VIN2	8
45#define R8A7779_CLK_VIN1	9
46#define R8A7779_CLK_VIN0	10
47#define R8A7779_CLK_ETHER	14
48#define R8A7779_CLK_SATA	15
49#define R8A7779_CLK_PCIE	16
50#define R8A7779_CLK_VIN3	20
51
52/* MSTP 3 */
53#define R8A7779_CLK_SDHI3	20
54#define R8A7779_CLK_SDHI2	21
55#define R8A7779_CLK_SDHI1	22
56#define R8A7779_CLK_SDHI0	23
57#define R8A7779_CLK_MMC1	30
58#define R8A7779_CLK_MMC0	31
59
60
61#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */