1/*
   2 * AXP20x regulators driver.
   3 *
   4 * Copyright (C) 2013 Carlo Caione <carlo@caione.org>
   5 *
   6 * This file is subject to the terms and conditions of the GNU General
   7 * Public License. See the file "COPYING" in the main directory of this
   8 * archive for more details.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 * GNU General Public License for more details.
  14 */
  15
  16#include <linux/bitops.h>
  17#include <linux/delay.h>
  18#include <linux/err.h>
  19#include <linux/init.h>
  20#include <linux/mfd/axp20x.h>
  21#include <linux/module.h>
  22#include <linux/of.h>
  23#include <linux/of_device.h>
  24#include <linux/platform_device.h>
  25#include <linux/regmap.h>
  26#include <linux/regulator/driver.h>
  27#include <linux/regulator/machine.h>
  28#include <linux/regulator/of_regulator.h>
  29
  30#define AXP20X_GPIO0_FUNC_MASK		GENMASK(3, 0)
  31#define AXP20X_GPIO1_FUNC_MASK		GENMASK(3, 0)
  32
  33#define AXP20X_IO_ENABLED		0x03
  34#define AXP20X_IO_DISABLED		0x07
  35
  36#define AXP20X_WORKMODE_DCDC2_MASK	BIT_MASK(2)
  37#define AXP20X_WORKMODE_DCDC3_MASK	BIT_MASK(1)
  38
  39#define AXP20X_FREQ_DCDC_MASK		GENMASK(3, 0)
  40
  41#define AXP20X_VBUS_IPSOUT_MGMT_MASK	BIT_MASK(2)
  42
  43#define AXP20X_DCDC2_V_OUT_MASK		GENMASK(5, 0)
  44#define AXP20X_DCDC3_V_OUT_MASK		GENMASK(7, 0)
  45#define AXP20X_LDO2_V_OUT_MASK		GENMASK(7, 4)
  46#define AXP20X_LDO3_V_OUT_MASK		GENMASK(6, 0)
  47#define AXP20X_LDO4_V_OUT_MASK		GENMASK(3, 0)
  48#define AXP20X_LDO5_V_OUT_MASK		GENMASK(7, 4)
  49
  50#define AXP20X_PWR_OUT_EXTEN_MASK	BIT_MASK(0)
  51#define AXP20X_PWR_OUT_DCDC3_MASK	BIT_MASK(1)
  52#define AXP20X_PWR_OUT_LDO2_MASK	BIT_MASK(2)
  53#define AXP20X_PWR_OUT_LDO4_MASK	BIT_MASK(3)
  54#define AXP20X_PWR_OUT_DCDC2_MASK	BIT_MASK(4)
  55#define AXP20X_PWR_OUT_LDO3_MASK	BIT_MASK(6)
  56
  57#define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK	BIT_MASK(0)
  58#define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \
  59	((x) << 0)
  60#define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK		BIT_MASK(1)
  61#define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \
  62	((x) << 1)
  63#define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK		BIT_MASK(2)
  64#define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN		BIT(2)
  65#define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK		BIT_MASK(3)
  66#define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN		BIT(3)
  67
  68#define AXP20X_LDO4_V_OUT_1250mV_START	0x0
  69#define AXP20X_LDO4_V_OUT_1250mV_STEPS	0
  70#define AXP20X_LDO4_V_OUT_1250mV_END	\
  71	(AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS)
  72#define AXP20X_LDO4_V_OUT_1300mV_START	0x1
  73#define AXP20X_LDO4_V_OUT_1300mV_STEPS	7
  74#define AXP20X_LDO4_V_OUT_1300mV_END	\
  75	(AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS)
  76#define AXP20X_LDO4_V_OUT_2500mV_START	0x9
  77#define AXP20X_LDO4_V_OUT_2500mV_STEPS	0
  78#define AXP20X_LDO4_V_OUT_2500mV_END	\
  79	(AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS)
  80#define AXP20X_LDO4_V_OUT_2700mV_START	0xa
  81#define AXP20X_LDO4_V_OUT_2700mV_STEPS	1
  82#define AXP20X_LDO4_V_OUT_2700mV_END	\
  83	(AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS)
  84#define AXP20X_LDO4_V_OUT_3000mV_START	0xc
  85#define AXP20X_LDO4_V_OUT_3000mV_STEPS	3
  86#define AXP20X_LDO4_V_OUT_3000mV_END	\
  87	(AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS)
  88#define AXP20X_LDO4_V_OUT_NUM_VOLTAGES	16
  89
  90#define AXP22X_IO_ENABLED		0x03
  91#define AXP22X_IO_DISABLED		0x04
  92
  93#define AXP22X_WORKMODE_DCDCX_MASK(x)	BIT_MASK(x)
  94
  95#define AXP22X_MISC_N_VBUSEN_FUNC	BIT(4)
  96
  97#define AXP22X_DCDC1_V_OUT_MASK		GENMASK(4, 0)
  98#define AXP22X_DCDC2_V_OUT_MASK		GENMASK(5, 0)
  99#define AXP22X_DCDC3_V_OUT_MASK		GENMASK(5, 0)
 100#define AXP22X_DCDC4_V_OUT_MASK		GENMASK(5, 0)
 101#define AXP22X_DCDC5_V_OUT_MASK		GENMASK(4, 0)
 102#define AXP22X_DC5LDO_V_OUT_MASK	GENMASK(2, 0)
 103#define AXP22X_ALDO1_V_OUT_MASK		GENMASK(4, 0)
 104#define AXP22X_ALDO2_V_OUT_MASK		GENMASK(4, 0)
 105#define AXP22X_ALDO3_V_OUT_MASK		GENMASK(4, 0)
 106#define AXP22X_DLDO1_V_OUT_MASK		GENMASK(4, 0)
 107#define AXP22X_DLDO2_V_OUT_MASK		GENMASK(4, 0)
 108#define AXP22X_DLDO3_V_OUT_MASK		GENMASK(4, 0)
 109#define AXP22X_DLDO4_V_OUT_MASK		GENMASK(4, 0)
 110#define AXP22X_ELDO1_V_OUT_MASK		GENMASK(4, 0)
 111#define AXP22X_ELDO2_V_OUT_MASK		GENMASK(4, 0)
 112#define AXP22X_ELDO3_V_OUT_MASK		GENMASK(4, 0)
 113#define AXP22X_LDO_IO0_V_OUT_MASK	GENMASK(4, 0)
 114#define AXP22X_LDO_IO1_V_OUT_MASK	GENMASK(4, 0)
 115
 116#define AXP22X_PWR_OUT_DC5LDO_MASK	BIT_MASK(0)
 117#define AXP22X_PWR_OUT_DCDC1_MASK	BIT_MASK(1)
 118#define AXP22X_PWR_OUT_DCDC2_MASK	BIT_MASK(2)
 119#define AXP22X_PWR_OUT_DCDC3_MASK	BIT_MASK(3)
 120#define AXP22X_PWR_OUT_DCDC4_MASK	BIT_MASK(4)
 121#define AXP22X_PWR_OUT_DCDC5_MASK	BIT_MASK(5)
 122#define AXP22X_PWR_OUT_ALDO1_MASK	BIT_MASK(6)
 123#define AXP22X_PWR_OUT_ALDO2_MASK	BIT_MASK(7)
 124
 125#define AXP22X_PWR_OUT_SW_MASK		BIT_MASK(6)
 126#define AXP22X_PWR_OUT_DC1SW_MASK	BIT_MASK(7)
 127
 128#define AXP22X_PWR_OUT_ELDO1_MASK	BIT_MASK(0)
 129#define AXP22X_PWR_OUT_ELDO2_MASK	BIT_MASK(1)
 130#define AXP22X_PWR_OUT_ELDO3_MASK	BIT_MASK(2)
 131#define AXP22X_PWR_OUT_DLDO1_MASK	BIT_MASK(3)
 132#define AXP22X_PWR_OUT_DLDO2_MASK	BIT_MASK(4)
 133#define AXP22X_PWR_OUT_DLDO3_MASK	BIT_MASK(5)
 134#define AXP22X_PWR_OUT_DLDO4_MASK	BIT_MASK(6)
 135#define AXP22X_PWR_OUT_ALDO3_MASK	BIT_MASK(7)
 136
 
 
 
 
 
 137#define AXP803_PWR_OUT_DCDC1_MASK	BIT_MASK(0)
 138#define AXP803_PWR_OUT_DCDC2_MASK	BIT_MASK(1)
 139#define AXP803_PWR_OUT_DCDC3_MASK	BIT_MASK(2)
 140#define AXP803_PWR_OUT_DCDC4_MASK	BIT_MASK(3)
 141#define AXP803_PWR_OUT_DCDC5_MASK	BIT_MASK(4)
 142#define AXP803_PWR_OUT_DCDC6_MASK	BIT_MASK(5)
 143
 144#define AXP803_PWR_OUT_FLDO1_MASK	BIT_MASK(2)
 145#define AXP803_PWR_OUT_FLDO2_MASK	BIT_MASK(3)
 146
 147#define AXP803_DCDC1_V_OUT_MASK		GENMASK(4, 0)
 148#define AXP803_DCDC2_V_OUT_MASK		GENMASK(6, 0)
 149#define AXP803_DCDC3_V_OUT_MASK		GENMASK(6, 0)
 150#define AXP803_DCDC4_V_OUT_MASK		GENMASK(6, 0)
 151#define AXP803_DCDC5_V_OUT_MASK		GENMASK(6, 0)
 152#define AXP803_DCDC6_V_OUT_MASK		GENMASK(6, 0)
 153
 154#define AXP803_FLDO1_V_OUT_MASK		GENMASK(3, 0)
 155#define AXP803_FLDO2_V_OUT_MASK		GENMASK(3, 0)
 156
 157#define AXP803_DCDC23_POLYPHASE_DUAL	BIT(6)
 158#define AXP803_DCDC56_POLYPHASE_DUAL	BIT(5)
 159
 160#define AXP803_DCDC234_500mV_START	0x00
 161#define AXP803_DCDC234_500mV_STEPS	70
 162#define AXP803_DCDC234_500mV_END	\
 163	(AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS)
 164#define AXP803_DCDC234_1220mV_START	0x47
 165#define AXP803_DCDC234_1220mV_STEPS	4
 166#define AXP803_DCDC234_1220mV_END	\
 167	(AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS)
 168#define AXP803_DCDC234_NUM_VOLTAGES	76
 169
 170#define AXP803_DCDC5_800mV_START	0x00
 171#define AXP803_DCDC5_800mV_STEPS	32
 172#define AXP803_DCDC5_800mV_END		\
 173	(AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS)
 174#define AXP803_DCDC5_1140mV_START	0x21
 175#define AXP803_DCDC5_1140mV_STEPS	35
 176#define AXP803_DCDC5_1140mV_END		\
 177	(AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS)
 178#define AXP803_DCDC5_NUM_VOLTAGES	69
 179
 180#define AXP803_DCDC6_600mV_START	0x00
 181#define AXP803_DCDC6_600mV_STEPS	50
 182#define AXP803_DCDC6_600mV_END		\
 183	(AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS)
 184#define AXP803_DCDC6_1120mV_START	0x33
 185#define AXP803_DCDC6_1120mV_STEPS	20
 186#define AXP803_DCDC6_1120mV_END		\
 187	(AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS)
 188#define AXP803_DCDC6_NUM_VOLTAGES	72
 189
 190#define AXP803_DLDO2_700mV_START	0x00
 191#define AXP803_DLDO2_700mV_STEPS	26
 192#define AXP803_DLDO2_700mV_END		\
 193	(AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS)
 194#define AXP803_DLDO2_3400mV_START	0x1b
 195#define AXP803_DLDO2_3400mV_STEPS	4
 196#define AXP803_DLDO2_3400mV_END		\
 197	(AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS)
 198#define AXP803_DLDO2_NUM_VOLTAGES	32
 199
 200#define AXP806_DCDCA_V_CTRL_MASK	GENMASK(6, 0)
 201#define AXP806_DCDCB_V_CTRL_MASK	GENMASK(4, 0)
 202#define AXP806_DCDCC_V_CTRL_MASK	GENMASK(6, 0)
 203#define AXP806_DCDCD_V_CTRL_MASK	GENMASK(5, 0)
 204#define AXP806_DCDCE_V_CTRL_MASK	GENMASK(4, 0)
 205#define AXP806_ALDO1_V_CTRL_MASK	GENMASK(4, 0)
 206#define AXP806_ALDO2_V_CTRL_MASK	GENMASK(4, 0)
 207#define AXP806_ALDO3_V_CTRL_MASK	GENMASK(4, 0)
 208#define AXP806_BLDO1_V_CTRL_MASK	GENMASK(3, 0)
 209#define AXP806_BLDO2_V_CTRL_MASK	GENMASK(3, 0)
 210#define AXP806_BLDO3_V_CTRL_MASK	GENMASK(3, 0)
 211#define AXP806_BLDO4_V_CTRL_MASK	GENMASK(3, 0)
 212#define AXP806_CLDO1_V_CTRL_MASK	GENMASK(4, 0)
 213#define AXP806_CLDO2_V_CTRL_MASK	GENMASK(4, 0)
 214#define AXP806_CLDO3_V_CTRL_MASK	GENMASK(4, 0)
 215
 216#define AXP806_PWR_OUT_DCDCA_MASK	BIT_MASK(0)
 217#define AXP806_PWR_OUT_DCDCB_MASK	BIT_MASK(1)
 218#define AXP806_PWR_OUT_DCDCC_MASK	BIT_MASK(2)
 219#define AXP806_PWR_OUT_DCDCD_MASK	BIT_MASK(3)
 220#define AXP806_PWR_OUT_DCDCE_MASK	BIT_MASK(4)
 221#define AXP806_PWR_OUT_ALDO1_MASK	BIT_MASK(5)
 222#define AXP806_PWR_OUT_ALDO2_MASK	BIT_MASK(6)
 223#define AXP806_PWR_OUT_ALDO3_MASK	BIT_MASK(7)
 224#define AXP806_PWR_OUT_BLDO1_MASK	BIT_MASK(0)
 225#define AXP806_PWR_OUT_BLDO2_MASK	BIT_MASK(1)
 226#define AXP806_PWR_OUT_BLDO3_MASK	BIT_MASK(2)
 227#define AXP806_PWR_OUT_BLDO4_MASK	BIT_MASK(3)
 228#define AXP806_PWR_OUT_CLDO1_MASK	BIT_MASK(4)
 229#define AXP806_PWR_OUT_CLDO2_MASK	BIT_MASK(5)
 230#define AXP806_PWR_OUT_CLDO3_MASK	BIT_MASK(6)
 231#define AXP806_PWR_OUT_SW_MASK		BIT_MASK(7)
 232
 233#define AXP806_DCDCAB_POLYPHASE_DUAL	0x40
 234#define AXP806_DCDCABC_POLYPHASE_TRI	0x80
 235#define AXP806_DCDCABC_POLYPHASE_MASK	GENMASK(7, 6)
 236
 237#define AXP806_DCDCDE_POLYPHASE_DUAL	BIT(5)
 238
 239#define AXP806_DCDCA_600mV_START	0x00
 240#define AXP806_DCDCA_600mV_STEPS	50
 241#define AXP806_DCDCA_600mV_END		\
 242	(AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS)
 243#define AXP806_DCDCA_1120mV_START	0x33
 244#define AXP806_DCDCA_1120mV_STEPS	20
 245#define AXP806_DCDCA_1120mV_END		\
 246	(AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS)
 247#define AXP806_DCDCA_NUM_VOLTAGES	72
 248
 249#define AXP806_DCDCD_600mV_START	0x00
 250#define AXP806_DCDCD_600mV_STEPS	45
 251#define AXP806_DCDCD_600mV_END		\
 252	(AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS)
 253#define AXP806_DCDCD_1600mV_START	0x2e
 254#define AXP806_DCDCD_1600mV_STEPS	17
 255#define AXP806_DCDCD_1600mV_END		\
 256	(AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS)
 257#define AXP806_DCDCD_NUM_VOLTAGES	64
 258
 259#define AXP809_DCDC4_600mV_START	0x00
 260#define AXP809_DCDC4_600mV_STEPS	47
 261#define AXP809_DCDC4_600mV_END		\
 262	(AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS)
 263#define AXP809_DCDC4_1800mV_START	0x30
 264#define AXP809_DCDC4_1800mV_STEPS	8
 265#define AXP809_DCDC4_1800mV_END		\
 266	(AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS)
 267#define AXP809_DCDC4_NUM_VOLTAGES	57
 268
 269#define AXP813_DCDC7_V_OUT_MASK		GENMASK(6, 0)
 270
 271#define AXP813_PWR_OUT_DCDC7_MASK	BIT_MASK(6)
 272
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 273#define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg,	\
 274		    _vmask, _ereg, _emask, _enable_val, _disable_val)		\
 275	[_family##_##_id] = {							\
 276		.name		= (_match),					\
 277		.supply_name	= (_supply),					\
 278		.of_match	= of_match_ptr(_match),				\
 279		.regulators_node = of_match_ptr("regulators"),			\
 280		.type		= REGULATOR_VOLTAGE,				\
 281		.id		= _family##_##_id,				\
 282		.n_voltages	= (((_max) - (_min)) / (_step) + 1),		\
 283		.owner		= THIS_MODULE,					\
 284		.min_uV		= (_min) * 1000,				\
 285		.uV_step	= (_step) * 1000,				\
 286		.vsel_reg	= (_vreg),					\
 287		.vsel_mask	= (_vmask),					\
 288		.enable_reg	= (_ereg),					\
 289		.enable_mask	= (_emask),					\
 290		.enable_val	= (_enable_val),				\
 291		.disable_val	= (_disable_val),				\
 292		.ops		= &axp20x_ops,					\
 293	}
 294
 295#define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg,	\
 296		 _vmask, _ereg, _emask) 					\
 297	[_family##_##_id] = {							\
 298		.name		= (_match),					\
 299		.supply_name	= (_supply),					\
 300		.of_match	= of_match_ptr(_match),				\
 301		.regulators_node = of_match_ptr("regulators"),			\
 302		.type		= REGULATOR_VOLTAGE,				\
 303		.id		= _family##_##_id,				\
 304		.n_voltages	= (((_max) - (_min)) / (_step) + 1),		\
 305		.owner		= THIS_MODULE,					\
 306		.min_uV		= (_min) * 1000,				\
 307		.uV_step	= (_step) * 1000,				\
 308		.vsel_reg	= (_vreg),					\
 309		.vsel_mask	= (_vmask),					\
 310		.enable_reg	= (_ereg),					\
 311		.enable_mask	= (_emask),					\
 312		.ops		= &axp20x_ops,					\
 313	}
 314
 315#define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask)		\
 316	[_family##_##_id] = {							\
 317		.name		= (_match),					\
 318		.supply_name	= (_supply),					\
 319		.of_match	= of_match_ptr(_match),				\
 320		.regulators_node = of_match_ptr("regulators"),			\
 321		.type		= REGULATOR_VOLTAGE,				\
 322		.id		= _family##_##_id,				\
 323		.owner		= THIS_MODULE,					\
 324		.enable_reg	= (_ereg),					\
 325		.enable_mask	= (_emask),					\
 326		.ops		= &axp20x_ops_sw,				\
 327	}
 328
 329#define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt)			\
 330	[_family##_##_id] = {							\
 331		.name		= (_match),					\
 332		.supply_name	= (_supply),					\
 333		.of_match	= of_match_ptr(_match),				\
 334		.regulators_node = of_match_ptr("regulators"),			\
 335		.type		= REGULATOR_VOLTAGE,				\
 336		.id		= _family##_##_id,				\
 337		.n_voltages	= 1,						\
 338		.owner		= THIS_MODULE,					\
 339		.min_uV		= (_volt) * 1000,				\
 340		.ops		= &axp20x_ops_fixed				\
 341	}
 342
 343#define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages,	\
 344			_vreg, _vmask, _ereg, _emask)				\
 345	[_family##_##_id] = {							\
 346		.name		= (_match),					\
 347		.supply_name	= (_supply),					\
 348		.of_match	= of_match_ptr(_match),				\
 349		.regulators_node = of_match_ptr("regulators"),			\
 350		.type		= REGULATOR_VOLTAGE,				\
 351		.id		= _family##_##_id,				\
 352		.n_voltages	= (_n_voltages),				\
 353		.owner		= THIS_MODULE,					\
 354		.vsel_reg	= (_vreg),					\
 355		.vsel_mask	= (_vmask),					\
 356		.enable_reg	= (_ereg),					\
 357		.enable_mask	= (_emask),					\
 358		.linear_ranges	= (_ranges),					\
 359		.n_linear_ranges = ARRAY_SIZE(_ranges),				\
 360		.ops		= &axp20x_ops_range,				\
 361	}
 362
 363static const int axp209_dcdc2_ldo3_slew_rates[] = {
 364	1600,
 365	 800,
 366};
 367
 368static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp)
 369{
 370	struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
 371	int id = rdev_get_id(rdev);
 372	u8 reg, mask, enable, cfg = 0xff;
 373	const int *slew_rates;
 374	int rate_count = 0;
 375
 376	switch (axp20x->variant) {
 377	case AXP209_ID:
 378		if (id == AXP20X_DCDC2) {
 379			slew_rates = axp209_dcdc2_ldo3_slew_rates;
 380			rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
 381			reg = AXP20X_DCDC2_LDO3_V_RAMP;
 382			mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK |
 383			       AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK;
 384			enable = (ramp > 0) ?
 385				 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN : 0;
 386			break;
 387		}
 388
 389		if (id == AXP20X_LDO3) {
 390			slew_rates = axp209_dcdc2_ldo3_slew_rates;
 391			rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
 392			reg = AXP20X_DCDC2_LDO3_V_RAMP;
 393			mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK |
 394			       AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK;
 395			enable = (ramp > 0) ?
 396				 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN : 0;
 397			break;
 398		}
 399
 400		if (rate_count > 0)
 401			break;
 402
 403		fallthrough;
 404	default:
 405		/* Not supported for this regulator */
 406		return -ENOTSUPP;
 407	}
 408
 409	if (ramp == 0) {
 410		cfg = enable;
 411	} else {
 412		int i;
 413
 414		for (i = 0; i < rate_count; i++) {
 415			if (ramp > slew_rates[i])
 416				break;
 417
 418			if (id == AXP20X_DCDC2)
 419				cfg = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(i);
 420			else
 421				cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i);
 422		}
 423
 424		if (cfg == 0xff) {
 425			dev_err(axp20x->dev, "unsupported ramp value %d", ramp);
 426			return -EINVAL;
 427		}
 428
 429		cfg |= enable;
 430	}
 431
 432	return regmap_update_bits(axp20x->regmap, reg, mask, cfg);
 433}
 434
 435static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev)
 436{
 437	struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
 438	int id = rdev_get_id(rdev);
 439
 440	switch (axp20x->variant) {
 441	case AXP209_ID:
 442		if ((id == AXP20X_LDO3) &&
 443		    rdev->constraints && rdev->constraints->soft_start) {
 444			int v_out;
 445			int ret;
 446
 447			/*
 448			 * On some boards, the LDO3 can be overloaded when
 449			 * turning on, causing the entire PMIC to shutdown
 450			 * without warning. Turning it on at the minimal voltage
 451			 * and then setting the voltage to the requested value
 452			 * works reliably.
 453			 */
 454			if (regulator_is_enabled_regmap(rdev))
 455				break;
 456
 457			v_out = regulator_get_voltage_sel_regmap(rdev);
 458			if (v_out < 0)
 459				return v_out;
 460
 461			if (v_out == 0)
 462				break;
 463
 464			ret = regulator_set_voltage_sel_regmap(rdev, 0x00);
 465			/*
 466			 * A small pause is needed between
 467			 * setting the voltage and enabling the LDO to give the
 468			 * internal state machine time to process the request.
 469			 */
 470			usleep_range(1000, 5000);
 471			ret |= regulator_enable_regmap(rdev);
 472			ret |= regulator_set_voltage_sel_regmap(rdev, v_out);
 473
 474			return ret;
 475		}
 476		break;
 477	default:
 478		/* No quirks */
 479		break;
 480	}
 481
 482	return regulator_enable_regmap(rdev);
 483};
 484
 485static const struct regulator_ops axp20x_ops_fixed = {
 486	.list_voltage		= regulator_list_voltage_linear,
 487};
 488
 489static const struct regulator_ops axp20x_ops_range = {
 490	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
 491	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
 492	.list_voltage		= regulator_list_voltage_linear_range,
 493	.enable			= regulator_enable_regmap,
 494	.disable		= regulator_disable_regmap,
 495	.is_enabled		= regulator_is_enabled_regmap,
 496};
 497
 498static const struct regulator_ops axp20x_ops = {
 499	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
 500	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
 501	.list_voltage		= regulator_list_voltage_linear,
 502	.enable			= axp20x_regulator_enable_regmap,
 503	.disable		= regulator_disable_regmap,
 504	.is_enabled		= regulator_is_enabled_regmap,
 505	.set_ramp_delay		= axp20x_set_ramp_delay,
 506};
 507
 508static const struct regulator_ops axp20x_ops_sw = {
 509	.enable			= regulator_enable_regmap,
 510	.disable		= regulator_disable_regmap,
 511	.is_enabled		= regulator_is_enabled_regmap,
 512};
 513
 514static const struct linear_range axp20x_ldo4_ranges[] = {
 515	REGULATOR_LINEAR_RANGE(1250000,
 516			       AXP20X_LDO4_V_OUT_1250mV_START,
 517			       AXP20X_LDO4_V_OUT_1250mV_END,
 518			       0),
 519	REGULATOR_LINEAR_RANGE(1300000,
 520			       AXP20X_LDO4_V_OUT_1300mV_START,
 521			       AXP20X_LDO4_V_OUT_1300mV_END,
 522			       100000),
 523	REGULATOR_LINEAR_RANGE(2500000,
 524			       AXP20X_LDO4_V_OUT_2500mV_START,
 525			       AXP20X_LDO4_V_OUT_2500mV_END,
 526			       0),
 527	REGULATOR_LINEAR_RANGE(2700000,
 528			       AXP20X_LDO4_V_OUT_2700mV_START,
 529			       AXP20X_LDO4_V_OUT_2700mV_END,
 530			       100000),
 531	REGULATOR_LINEAR_RANGE(3000000,
 532			       AXP20X_LDO4_V_OUT_3000mV_START,
 533			       AXP20X_LDO4_V_OUT_3000mV_END,
 534			       100000),
 535};
 536
 537static const struct regulator_desc axp20x_regulators[] = {
 538	AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25,
 539		 AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK,
 540		 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK),
 541	AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25,
 542		 AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK,
 543		 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK),
 544	AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300),
 545	AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100,
 546		 AXP20X_LDO24_V_OUT, AXP20X_LDO2_V_OUT_MASK,
 547		 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK),
 548	AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25,
 549		 AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK,
 550		 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK),
 551	AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in",
 552			axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES,
 553			AXP20X_LDO24_V_OUT, AXP20X_LDO4_V_OUT_MASK,
 554			AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK),
 555	AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100,
 556		    AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK,
 557		    AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 558		    AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),
 559};
 560
 561static const struct regulator_desc axp22x_regulators[] = {
 562	AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
 563		 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
 564		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
 565	AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
 566		 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
 567		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
 568	AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
 569		 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
 570		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
 571	AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20,
 572		 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
 573		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
 574	AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
 575		 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
 576		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
 577	/* secondary switchable output of DCDC1 */
 578	AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL,
 579		    AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
 580	/* LDO regulator internally chained to DCDC5 */
 581	AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
 582		 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
 583		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
 584	AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 585		 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
 586		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
 587	AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
 588		 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
 589		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
 590	AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 591		 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
 592		 AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK),
 593	AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
 594		 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
 595		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
 596	AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
 597		 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
 598		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
 599	AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
 600		 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
 601		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
 602	AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
 603		 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
 604		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
 605	AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
 606		 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
 607		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
 608	AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
 609		 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
 610		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
 611	AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
 612		 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
 613		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
 614	/* Note the datasheet only guarantees reliable operation up to
 615	 * 3.3V, this needs to be enforced via dts provided constraints */
 616	AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
 617		    AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
 618		    AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 619		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 620	/* Note the datasheet only guarantees reliable operation up to
 621	 * 3.3V, this needs to be enforced via dts provided constraints */
 622	AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
 623		    AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
 624		    AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
 625		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 626	AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000),
 627};
 628
 629static const struct regulator_desc axp22x_drivevbus_regulator = {
 630	.name		= "drivevbus",
 631	.supply_name	= "drivevbus",
 632	.of_match	= of_match_ptr("drivevbus"),
 633	.regulators_node = of_match_ptr("regulators"),
 634	.type		= REGULATOR_VOLTAGE,
 635	.owner		= THIS_MODULE,
 636	.enable_reg	= AXP20X_VBUS_IPSOUT_MGMT,
 637	.enable_mask	= AXP20X_VBUS_IPSOUT_MGMT_MASK,
 638	.ops		= &axp20x_ops_sw,
 639};
 640
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 641/* DCDC ranges shared with AXP813 */
 642static const struct linear_range axp803_dcdc234_ranges[] = {
 643	REGULATOR_LINEAR_RANGE(500000,
 644			       AXP803_DCDC234_500mV_START,
 645			       AXP803_DCDC234_500mV_END,
 646			       10000),
 647	REGULATOR_LINEAR_RANGE(1220000,
 648			       AXP803_DCDC234_1220mV_START,
 649			       AXP803_DCDC234_1220mV_END,
 650			       20000),
 651};
 652
 653static const struct linear_range axp803_dcdc5_ranges[] = {
 654	REGULATOR_LINEAR_RANGE(800000,
 655			       AXP803_DCDC5_800mV_START,
 656			       AXP803_DCDC5_800mV_END,
 657			       10000),
 658	REGULATOR_LINEAR_RANGE(1140000,
 659			       AXP803_DCDC5_1140mV_START,
 660			       AXP803_DCDC5_1140mV_END,
 661			       20000),
 662};
 663
 664static const struct linear_range axp803_dcdc6_ranges[] = {
 665	REGULATOR_LINEAR_RANGE(600000,
 666			       AXP803_DCDC6_600mV_START,
 667			       AXP803_DCDC6_600mV_END,
 668			       10000),
 669	REGULATOR_LINEAR_RANGE(1120000,
 670			       AXP803_DCDC6_1120mV_START,
 671			       AXP803_DCDC6_1120mV_END,
 672			       20000),
 673};
 674
 675/* AXP806's CLDO2 and AXP809's DLDO1 share the same range */
 676static const struct linear_range axp803_dldo2_ranges[] = {
 677	REGULATOR_LINEAR_RANGE(700000,
 678			       AXP803_DLDO2_700mV_START,
 679			       AXP803_DLDO2_700mV_END,
 680			       100000),
 681	REGULATOR_LINEAR_RANGE(3400000,
 682			       AXP803_DLDO2_3400mV_START,
 683			       AXP803_DLDO2_3400mV_END,
 684			       200000),
 685};
 686
 687static const struct regulator_desc axp803_regulators[] = {
 688	AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
 689		 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
 690		 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
 691	AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2",
 692			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 693			AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
 694			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
 695	AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3",
 696			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 697			AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
 698			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
 699	AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4",
 700			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 701			AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
 702			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
 703	AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5",
 704			axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
 705			AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
 706			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
 707	AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6",
 708			axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
 709			AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
 710			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
 711	/* secondary switchable output of DCDC1 */
 712	AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL,
 713		    AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
 714	AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 715		 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
 716		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
 717	AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
 718		 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
 719		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
 720	AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 721		 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
 722		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
 723	AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
 724		 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
 725		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
 726	AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin",
 727			axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
 728			AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
 729			AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
 730	AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
 731		 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
 732		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
 733	AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
 734		 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
 735		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
 736	AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
 737		 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
 738		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
 739	AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
 740		 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
 741		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
 742	AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
 743		 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
 744		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
 745	AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
 746		 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
 747		 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
 748	AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
 749		 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
 750		 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
 751	AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
 752		    AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
 753		    AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 754		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 755	AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
 756		    AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
 757		    AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
 758		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 759	AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000),
 760};
 761
 762static const struct linear_range axp806_dcdca_ranges[] = {
 763	REGULATOR_LINEAR_RANGE(600000,
 764			       AXP806_DCDCA_600mV_START,
 765			       AXP806_DCDCA_600mV_END,
 766			       10000),
 767	REGULATOR_LINEAR_RANGE(1120000,
 768			       AXP806_DCDCA_1120mV_START,
 769			       AXP806_DCDCA_1120mV_END,
 770			       20000),
 771};
 772
 773static const struct linear_range axp806_dcdcd_ranges[] = {
 774	REGULATOR_LINEAR_RANGE(600000,
 775			       AXP806_DCDCD_600mV_START,
 776			       AXP806_DCDCD_600mV_END,
 777			       20000),
 778	REGULATOR_LINEAR_RANGE(1600000,
 779			       AXP806_DCDCD_1600mV_START,
 780			       AXP806_DCDCD_1600mV_END,
 781			       100000),
 782};
 783
 784static const struct regulator_desc axp806_regulators[] = {
 785	AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina",
 786			axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
 787			AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK,
 788			AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK),
 789	AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50,
 790		 AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK,
 791		 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK),
 792	AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc",
 793			axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
 794			AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK,
 795			AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK),
 796	AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind",
 797			axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES,
 798			AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK,
 799			AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK),
 800	AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100,
 801		 AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK,
 802		 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK),
 803	AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 804		 AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK,
 805		 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK),
 806	AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100,
 807		 AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK,
 808		 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK),
 809	AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 810		 AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK,
 811		 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK),
 812	AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100,
 813		 AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK,
 814		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK),
 815	AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100,
 816		 AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK,
 817		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK),
 818	AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100,
 819		 AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK,
 820		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK),
 821	AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100,
 822		 AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK,
 823		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK),
 824	AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100,
 825		 AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK,
 826		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK),
 827	AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin",
 828			axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
 829			AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK,
 830			AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK),
 831	AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100,
 832		 AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK,
 833		 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK),
 834	AXP_DESC_SW(AXP806, SW, "sw", "swin",
 835		    AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK),
 836};
 837
 838static const struct linear_range axp809_dcdc4_ranges[] = {
 839	REGULATOR_LINEAR_RANGE(600000,
 840			       AXP809_DCDC4_600mV_START,
 841			       AXP809_DCDC4_600mV_END,
 842			       20000),
 843	REGULATOR_LINEAR_RANGE(1800000,
 844			       AXP809_DCDC4_1800mV_START,
 845			       AXP809_DCDC4_1800mV_END,
 846			       100000),
 847};
 848
 849static const struct regulator_desc axp809_regulators[] = {
 850	AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
 851		 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
 852		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
 853	AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
 854		 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
 855		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
 856	AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
 857		 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
 858		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
 859	AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4",
 860			axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES,
 861			AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
 862			AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
 863	AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
 864		 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
 865		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
 866	/* secondary switchable output of DCDC1 */
 867	AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL,
 868		    AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
 869	/* LDO regulator internally chained to DCDC5 */
 870	AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
 871		 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
 872		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
 873	AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 874		 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
 875		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
 876	AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
 877		 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
 878		 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
 879	AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 880		 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
 881		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK),
 882	AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin",
 883			axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
 884			AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
 885			AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
 886	AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
 887		 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
 888		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
 889	AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
 890		 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
 891		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
 892	AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
 893		 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
 894		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
 895	AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
 896		 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
 897		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
 898	/*
 899	 * Note the datasheet only guarantees reliable operation up to
 900	 * 3.3V, this needs to be enforced via dts provided constraints
 901	 */
 902	AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
 903		    AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
 904		    AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 905		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 906	/*
 907	 * Note the datasheet only guarantees reliable operation up to
 908	 * 3.3V, this needs to be enforced via dts provided constraints
 909	 */
 910	AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
 911		    AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
 912		    AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
 913		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 914	AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800),
 915	AXP_DESC_SW(AXP809, SW, "sw", "swin",
 916		    AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK),
 917};
 918
 919static const struct regulator_desc axp813_regulators[] = {
 920	AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
 921		 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
 922		 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
 923	AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2",
 924			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 925			AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
 926			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
 927	AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3",
 928			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 929			AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
 930			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
 931	AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4",
 932			axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
 933			AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
 934			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
 935	AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5",
 936			axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
 937			AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
 938			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
 939	AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6",
 940			axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
 941			AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
 942			AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
 943	AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7",
 944			axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
 945			AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK,
 946			AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK),
 947	AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
 948		 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
 949		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
 950	AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
 951		 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
 952		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
 953	AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
 954		 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
 955		 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
 956	AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
 957		 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
 958		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
 959	AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin",
 960			axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
 961			AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
 962			AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
 963	AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
 964		 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
 965		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
 966	AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
 967		 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
 968		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
 969	AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
 970		 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
 971		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
 972	AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
 973		 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
 974		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
 975	AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
 976		 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
 977		 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
 978	/* to do / check ... */
 979	AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
 980		 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
 981		 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
 982	AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
 983		 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
 984		 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
 985	/*
 986	 * TODO: FLDO3 = {DCDC5, FLDOIN} / 2
 987	 *
 988	 * This means FLDO3 effectively switches supplies at runtime,
 989	 * something the regulator subsystem does not support.
 990	 */
 991	AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800),
 992	AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
 993		    AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
 994		    AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
 995		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
 996	AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
 997		    AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
 998		    AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
 999		    AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
1000	AXP_DESC_SW(AXP813, SW, "sw", "swin",
1001		    AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
1002};
1003
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1004static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
1005{
1006	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
1007	unsigned int reg = AXP20X_DCDC_FREQ;
1008	u32 min, max, def, step;
1009
1010	switch (axp20x->variant) {
1011	case AXP202_ID:
1012	case AXP209_ID:
1013		min = 750;
1014		max = 1875;
1015		def = 1500;
1016		step = 75;
1017		break;
1018	case AXP803_ID:
1019	case AXP813_ID:
1020		/*
1021		 * AXP803/AXP813 DCDC work frequency setting has the same
1022		 * range and step as AXP22X, but at a different register.
1023		 * (See include/linux/mfd/axp20x.h)
1024		 */
1025		reg = AXP803_DCDC_FREQ_CTRL;
1026		fallthrough;	/* to the check below */
1027	case AXP806_ID:
1028		/*
1029		 * AXP806 also have DCDC work frequency setting register at a
1030		 * different position.
1031		 */
1032		if (axp20x->variant == AXP806_ID)
1033			reg = AXP806_DCDC_FREQ_CTRL;
1034		fallthrough;
1035	case AXP221_ID:
1036	case AXP223_ID:
1037	case AXP809_ID:
1038		min = 1800;
1039		max = 4050;
1040		def = 3000;
1041		step = 150;
1042		break;
 
 
 
 
 
 
 
 
 
 
1043	default:
1044		dev_err(&pdev->dev,
1045			"Setting DCDC frequency for unsupported AXP variant\n");
1046		return -EINVAL;
1047	}
1048
1049	if (dcdcfreq == 0)
1050		dcdcfreq = def;
1051
1052	if (dcdcfreq < min) {
1053		dcdcfreq = min;
1054		dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n",
1055			 min);
1056	}
1057
1058	if (dcdcfreq > max) {
1059		dcdcfreq = max;
1060		dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n",
1061			 max);
1062	}
1063
1064	dcdcfreq = (dcdcfreq - min) / step;
1065
1066	return regmap_update_bits(axp20x->regmap, reg,
1067				  AXP20X_FREQ_DCDC_MASK, dcdcfreq);
1068}
1069
1070static int axp20x_regulator_parse_dt(struct platform_device *pdev)
1071{
1072	struct device_node *np, *regulators;
1073	int ret = 0;
1074	u32 dcdcfreq = 0;
1075
1076	np = of_node_get(pdev->dev.parent->of_node);
1077	if (!np)
1078		return 0;
1079
1080	regulators = of_get_child_by_name(np, "regulators");
1081	if (!regulators) {
1082		dev_warn(&pdev->dev, "regulators node not found\n");
1083	} else {
1084		of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);
1085		ret = axp20x_set_dcdc_freq(pdev, dcdcfreq);
1086		if (ret < 0) {
1087			dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret);
1088		}
1089		of_node_put(regulators);
1090	}
1091
1092	of_node_put(np);
1093	return ret;
1094}
1095
1096static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode)
1097{
1098	struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
1099	unsigned int reg = AXP20X_DCDC_MODE;
1100	unsigned int mask;
1101
1102	switch (axp20x->variant) {
1103	case AXP202_ID:
1104	case AXP209_ID:
1105		if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))
1106			return -EINVAL;
1107
1108		mask = AXP20X_WORKMODE_DCDC2_MASK;
1109		if (id == AXP20X_DCDC3)
1110			mask = AXP20X_WORKMODE_DCDC3_MASK;
1111
1112		workmode <<= ffs(mask) - 1;
1113		break;
1114
1115	case AXP806_ID:
1116		/*
1117		 * AXP806 DCDC regulator IDs have the same range as AXP22X.
1118		 * (See include/linux/mfd/axp20x.h)
1119		 */
1120		reg = AXP806_DCDC_MODE_CTRL2;
1121		fallthrough;	/* to the check below */
1122	case AXP221_ID:
1123	case AXP223_ID:
1124	case AXP809_ID:
1125		if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
1126			return -EINVAL;
1127
1128		mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1);
1129		workmode <<= id - AXP22X_DCDC1;
1130		break;
1131
1132	case AXP803_ID:
1133		if (id < AXP803_DCDC1 || id > AXP803_DCDC6)
1134			return -EINVAL;
1135
1136		mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1);
1137		workmode <<= id - AXP803_DCDC1;
1138		break;
1139
1140	case AXP813_ID:
1141		if (id < AXP813_DCDC1 || id > AXP813_DCDC7)
1142			return -EINVAL;
1143
1144		mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1);
1145		workmode <<= id - AXP813_DCDC1;
1146		break;
1147
 
 
 
 
 
 
 
 
 
1148	default:
1149		/* should not happen */
1150		WARN_ON(1);
1151		return -EINVAL;
1152	}
1153
1154	return regmap_update_bits(rdev->regmap, reg, mask, workmode);
1155}
1156
1157/*
1158 * This function checks whether a regulator is part of a poly-phase
1159 * output setup based on the registers settings. Returns true if it is.
1160 */
1161static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id)
1162{
1163	u32 reg = 0;
1164
1165	/*
1166	 * Currently in our supported AXP variants, only AXP803, AXP806,
1167	 * and AXP813 have polyphase regulators.
1168	 */
1169	switch (axp20x->variant) {
1170	case AXP803_ID:
1171	case AXP813_ID:
1172		regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, &reg);
1173
1174		switch (id) {
1175		case AXP803_DCDC3:
1176			return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL);
1177		case AXP803_DCDC6:
1178			return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL);
1179		}
1180		break;
1181
1182	case AXP806_ID:
1183		regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, &reg);
1184
1185		switch (id) {
1186		case AXP806_DCDCB:
1187			return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1188				AXP806_DCDCAB_POLYPHASE_DUAL) ||
1189				((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1190				AXP806_DCDCABC_POLYPHASE_TRI));
1191		case AXP806_DCDCC:
1192			return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
1193				AXP806_DCDCABC_POLYPHASE_TRI);
1194		case AXP806_DCDCE:
1195			return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL);
1196		}
1197		break;
1198
 
 
 
 
 
 
 
 
 
 
 
1199	default:
1200		return false;
1201	}
1202
1203	return false;
1204}
1205
1206static int axp20x_regulator_probe(struct platform_device *pdev)
1207{
1208	struct regulator_dev *rdev;
1209	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
1210	const struct regulator_desc *regulators;
1211	struct regulator_config config = {
1212		.dev = pdev->dev.parent,
1213		.regmap = axp20x->regmap,
1214		.driver_data = axp20x,
1215	};
1216	int ret, i, nregulators;
1217	u32 workmode;
1218	const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name;
1219	const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name;
 
1220	bool drivevbus = false;
1221
1222	switch (axp20x->variant) {
1223	case AXP202_ID:
1224	case AXP209_ID:
1225		regulators = axp20x_regulators;
1226		nregulators = AXP20X_REG_ID_MAX;
1227		break;
1228	case AXP221_ID:
1229	case AXP223_ID:
1230		regulators = axp22x_regulators;
1231		nregulators = AXP22X_REG_ID_MAX;
1232		drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1233						  "x-powers,drive-vbus-en");
1234		break;
 
 
 
 
1235	case AXP803_ID:
1236		regulators = axp803_regulators;
1237		nregulators = AXP803_REG_ID_MAX;
1238		drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1239						  "x-powers,drive-vbus-en");
1240		break;
1241	case AXP806_ID:
1242		regulators = axp806_regulators;
1243		nregulators = AXP806_REG_ID_MAX;
1244		break;
1245	case AXP809_ID:
1246		regulators = axp809_regulators;
1247		nregulators = AXP809_REG_ID_MAX;
1248		break;
1249	case AXP813_ID:
1250		regulators = axp813_regulators;
1251		nregulators = AXP813_REG_ID_MAX;
1252		drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
1253						  "x-powers,drive-vbus-en");
1254		break;
 
 
 
 
1255	default:
1256		dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
1257			axp20x->variant);
1258		return -EINVAL;
1259	}
1260
1261	/* This only sets the dcdc freq. Ignore any errors */
1262	axp20x_regulator_parse_dt(pdev);
1263
1264	for (i = 0; i < nregulators; i++) {
1265		const struct regulator_desc *desc = &regulators[i];
1266		struct regulator_desc *new_desc;
1267
1268		/*
1269		 * If this regulator is a slave in a poly-phase setup,
1270		 * skip it, as its controls are bound to the master
1271		 * regulator and won't work.
1272		 */
1273		if (axp20x_is_polyphase_slave(axp20x, i))
1274			continue;
1275
1276		/* Support for AXP813's FLDO3 is not implemented */
1277		if (axp20x->variant == AXP813_ID && i == AXP813_FLDO3)
1278			continue;
1279
1280		/*
1281		 * Regulators DC1SW and DC5LDO are connected internally,
1282		 * so we have to handle their supply names separately.
 
1283		 *
1284		 * We always register the regulators in proper sequence,
1285		 * so the supply names are correctly read. See the last
1286		 * part of this loop to see where we save the DT defined
1287		 * name.
1288		 */
1289		if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) ||
1290		    (regulators == axp803_regulators && i == AXP803_DC1SW) ||
1291		    (regulators == axp809_regulators && i == AXP809_DC1SW)) {
 
1292			new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1293						GFP_KERNEL);
1294			if (!new_desc)
1295				return -ENOMEM;
1296
1297			*new_desc = regulators[i];
1298			new_desc->supply_name = dcdc1_name;
1299			desc = new_desc;
1300		}
1301
1302		if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) ||
1303		    (regulators == axp809_regulators && i == AXP809_DC5LDO)) {
 
1304			new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
1305						GFP_KERNEL);
1306			if (!new_desc)
1307				return -ENOMEM;
1308
1309			*new_desc = regulators[i];
1310			new_desc->supply_name = dcdc5_name;
1311			desc = new_desc;
1312		}
1313
 
 
 
 
 
 
 
 
 
 
 
 
1314		rdev = devm_regulator_register(&pdev->dev, desc, &config);
1315		if (IS_ERR(rdev)) {
1316			dev_err(&pdev->dev, "Failed to register %s\n",
1317				regulators[i].name);
1318
1319			return PTR_ERR(rdev);
1320		}
1321
1322		ret = of_property_read_u32(rdev->dev.of_node,
1323					   "x-powers,dcdc-workmode",
1324					   &workmode);
1325		if (!ret) {
1326			if (axp20x_set_dcdc_workmode(rdev, i, workmode))
1327				dev_err(&pdev->dev, "Failed to set workmode on %s\n",
1328					rdev->desc->name);
1329		}
1330
1331		/*
1332		 * Save AXP22X DCDC1 / DCDC5 regulator names for later.
1333		 */
1334		if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) ||
1335		    (regulators == axp809_regulators && i == AXP809_DCDC1))
 
1336			of_property_read_string(rdev->dev.of_node,
1337						"regulator-name",
1338						&dcdc1_name);
1339
1340		if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) ||
1341		    (regulators == axp809_regulators && i == AXP809_DCDC5))
 
1342			of_property_read_string(rdev->dev.of_node,
1343						"regulator-name",
1344						&dcdc5_name);
 
 
 
 
 
1345	}
1346
1347	if (drivevbus) {
1348		/* Change N_VBUSEN sense pin to DRIVEVBUS output pin */
1349		regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
1350				   AXP22X_MISC_N_VBUSEN_FUNC, 0);
1351		rdev = devm_regulator_register(&pdev->dev,
1352					       &axp22x_drivevbus_regulator,
1353					       &config);
1354		if (IS_ERR(rdev)) {
1355			dev_err(&pdev->dev, "Failed to register drivevbus\n");
1356			return PTR_ERR(rdev);
1357		}
1358	}
1359
1360	return 0;
1361}
1362
1363static struct platform_driver axp20x_regulator_driver = {
1364	.probe	= axp20x_regulator_probe,
1365	.driver	= {
1366		.name		= "axp20x-regulator",
 
1367	},
1368};
1369
1370module_platform_driver(axp20x_regulator_driver);
1371
1372MODULE_LICENSE("GPL v2");
1373MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
1374MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC");
1375MODULE_ALIAS("platform:axp20x-regulator");