1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Microchip Image Sensor Controller (ISC) common driver base
   4 *
   5 * Copyright (C) 2016-2019 Microchip Technology, Inc.
   6 *
   7 * Author: Songjun Wu
   8 * Author: Eugen Hristev <eugen.hristev@microchip.com>
   9 *
  10 */
  11#include <linux/delay.h>
  12#include <linux/interrupt.h>
  13#include <linux/math64.h>
  14#include <linux/module.h>
  15#include <linux/of.h>
  16#include <linux/of_graph.h>
  17#include <linux/platform_device.h>
  18#include <linux/pm_runtime.h>
  19#include <linux/regmap.h>
  20#include <linux/videodev2.h>
  21#include <linux/atmel-isc-media.h>
  22
  23#include <media/v4l2-ctrls.h>
  24#include <media/v4l2-device.h>
  25#include <media/v4l2-event.h>
  26#include <media/v4l2-image-sizes.h>
  27#include <media/v4l2-ioctl.h>
  28#include <media/v4l2-fwnode.h>
  29#include <media/v4l2-subdev.h>
  30#include <media/videobuf2-dma-contig.h>
  31
  32#include "microchip-isc-regs.h"
  33#include "microchip-isc.h"
  34
  35static unsigned int debug;
  36module_param(debug, int, 0644);
  37MODULE_PARM_DESC(debug, "debug level (0-2)");
  38
  39#define ISC_IS_FORMAT_RAW(mbus_code) \
  40	(((mbus_code) & 0xf000) == 0x3000)
  41
  42#define ISC_IS_FORMAT_GREY(mbus_code) \
  43	(((mbus_code) == MEDIA_BUS_FMT_Y10_1X10) | \
  44	(((mbus_code) == MEDIA_BUS_FMT_Y8_1X8)))
  45
  46static inline void isc_update_v4l2_ctrls(struct isc_device *isc)
  47{
  48	struct isc_ctrls *ctrls = &isc->ctrls;
  49
  50	/* In here we set the v4l2 controls w.r.t. our pipeline config */
  51	v4l2_ctrl_s_ctrl(isc->r_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_R]);
  52	v4l2_ctrl_s_ctrl(isc->b_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_B]);
  53	v4l2_ctrl_s_ctrl(isc->gr_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GR]);
  54	v4l2_ctrl_s_ctrl(isc->gb_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GB]);
  55
  56	v4l2_ctrl_s_ctrl(isc->r_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_R]);
  57	v4l2_ctrl_s_ctrl(isc->b_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_B]);
  58	v4l2_ctrl_s_ctrl(isc->gr_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GR]);
  59	v4l2_ctrl_s_ctrl(isc->gb_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GB]);
  60}
  61
  62static inline void isc_update_awb_ctrls(struct isc_device *isc)
  63{
  64	struct isc_ctrls *ctrls = &isc->ctrls;
  65
  66	/* In here we set our actual hw pipeline config */
  67
  68	regmap_write(isc->regmap, ISC_WB_O_RGR,
  69		     ((ctrls->offset[ISC_HIS_CFG_MODE_R])) |
  70		     ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16));
  71	regmap_write(isc->regmap, ISC_WB_O_BGB,
  72		     ((ctrls->offset[ISC_HIS_CFG_MODE_B])) |
  73		     ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16));
  74	regmap_write(isc->regmap, ISC_WB_G_RGR,
  75		     ctrls->gain[ISC_HIS_CFG_MODE_R] |
  76		     (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16));
  77	regmap_write(isc->regmap, ISC_WB_G_BGB,
  78		     ctrls->gain[ISC_HIS_CFG_MODE_B] |
  79		     (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16));
  80}
  81
  82static inline void isc_reset_awb_ctrls(struct isc_device *isc)
  83{
  84	unsigned int c;
  85
  86	for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
  87		/* gains have a fixed point at 9 decimals */
  88		isc->ctrls.gain[c] = 1 << 9;
  89		/* offsets are in 2's complements */
  90		isc->ctrls.offset[c] = 0;
  91	}
  92}
  93
  94static int isc_queue_setup(struct vb2_queue *vq,
  95			   unsigned int *nbuffers, unsigned int *nplanes,
  96			   unsigned int sizes[], struct device *alloc_devs[])
  97{
  98	struct isc_device *isc = vb2_get_drv_priv(vq);
  99	unsigned int size = isc->fmt.fmt.pix.sizeimage;
 100
 101	if (*nplanes)
 102		return sizes[0] < size ? -EINVAL : 0;
 103
 104	*nplanes = 1;
 105	sizes[0] = size;
 106
 107	return 0;
 108}
 109
 110static int isc_buffer_prepare(struct vb2_buffer *vb)
 111{
 112	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 113	struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
 114	unsigned long size = isc->fmt.fmt.pix.sizeimage;
 115
 116	if (vb2_plane_size(vb, 0) < size) {
 117		v4l2_err(&isc->v4l2_dev, "buffer too small (%lu < %lu)\n",
 118			 vb2_plane_size(vb, 0), size);
 119		return -EINVAL;
 120	}
 121
 122	vb2_set_plane_payload(vb, 0, size);
 123
 124	vbuf->field = isc->fmt.fmt.pix.field;
 125
 126	return 0;
 127}
 128
 129static void isc_crop_pfe(struct isc_device *isc)
 130{
 131	struct regmap *regmap = isc->regmap;
 132	u32 h, w;
 133
 134	h = isc->fmt.fmt.pix.height;
 135	w = isc->fmt.fmt.pix.width;
 136
 137	/*
 138	 * In case the sensor is not RAW, it will output a pixel (12-16 bits)
 139	 * with two samples on the ISC Data bus (which is 8-12)
 140	 * ISC will count each sample, so, we need to multiply these values
 141	 * by two, to get the real number of samples for the required pixels.
 142	 */
 143	if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) {
 144		h <<= 1;
 145		w <<= 1;
 146	}
 147
 148	/*
 149	 * We limit the column/row count that the ISC will output according
 150	 * to the configured resolution that we want.
 151	 * This will avoid the situation where the sensor is misconfigured,
 152	 * sending more data, and the ISC will just take it and DMA to memory,
 153	 * causing corruption.
 154	 */
 155	regmap_write(regmap, ISC_PFE_CFG1,
 156		     (ISC_PFE_CFG1_COLMIN(0) & ISC_PFE_CFG1_COLMIN_MASK) |
 157		     (ISC_PFE_CFG1_COLMAX(w - 1) & ISC_PFE_CFG1_COLMAX_MASK));
 158
 159	regmap_write(regmap, ISC_PFE_CFG2,
 160		     (ISC_PFE_CFG2_ROWMIN(0) & ISC_PFE_CFG2_ROWMIN_MASK) |
 161		     (ISC_PFE_CFG2_ROWMAX(h - 1) & ISC_PFE_CFG2_ROWMAX_MASK));
 162
 163	regmap_update_bits(regmap, ISC_PFE_CFG0,
 164			   ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN,
 165			   ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN);
 166}
 167
 168static void isc_start_dma(struct isc_device *isc)
 169{
 170	struct regmap *regmap = isc->regmap;
 171	u32 sizeimage = isc->fmt.fmt.pix.sizeimage;
 172	u32 dctrl_dview;
 173	dma_addr_t addr0;
 174
 175	addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);
 176	regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0);
 177
 178	switch (isc->config.fourcc) {
 179	case V4L2_PIX_FMT_YUV420:
 180		regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
 181			     addr0 + (sizeimage * 2) / 3);
 182		regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
 183			     addr0 + (sizeimage * 5) / 6);
 184		break;
 185	case V4L2_PIX_FMT_YUV422P:
 186		regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
 187			     addr0 + sizeimage / 2);
 188		regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
 189			     addr0 + (sizeimage * 3) / 4);
 190		break;
 191	default:
 192		break;
 193	}
 194
 195	dctrl_dview = isc->config.dctrl_dview;
 196
 197	regmap_write(regmap, ISC_DCTRL + isc->offsets.dma,
 198		     dctrl_dview | ISC_DCTRL_IE_IS);
 199	spin_lock(&isc->awb_lock);
 200	regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);
 201	spin_unlock(&isc->awb_lock);
 202}
 203
 204static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
 205{
 206	struct regmap *regmap = isc->regmap;
 207	struct isc_ctrls *ctrls = &isc->ctrls;
 208	u32 val, bay_cfg;
 209	const u32 *gamma;
 210	unsigned int i;
 211
 212	/* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
 213	for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
 214		val = pipeline & BIT(i) ? 1 : 0;
 215		regmap_field_write(isc->pipeline[i], val);
 216	}
 217
 218	if (!pipeline)
 219		return;
 220
 221	bay_cfg = isc->config.sd_format->cfa_baycfg;
 222
 223	regmap_write(regmap, ISC_WB_CFG, bay_cfg);
 224	isc_update_awb_ctrls(isc);
 225	isc_update_v4l2_ctrls(isc);
 226
 227	regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL);
 228
 229	gamma = &isc->gamma_table[ctrls->gamma_index][0];
 230	regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES);
 231	regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
 232	regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
 233
 234	isc->config_dpc(isc);
 235	isc->config_csc(isc);
 236	isc->config_cbc(isc);
 237	isc->config_cc(isc);
 238	isc->config_gam(isc);
 239}
 240
 241static int isc_update_profile(struct isc_device *isc)
 242{
 243	struct regmap *regmap = isc->regmap;
 244	u32 sr;
 245	int counter = 100;
 246
 247	regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_UPPRO);
 248
 249	regmap_read(regmap, ISC_CTRLSR, &sr);
 250	while ((sr & ISC_CTRL_UPPRO) && counter--) {
 251		usleep_range(1000, 2000);
 252		regmap_read(regmap, ISC_CTRLSR, &sr);
 253	}
 254
 255	if (counter < 0) {
 256		v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n");
 257		return -ETIMEDOUT;
 258	}
 259
 260	return 0;
 261}
 262
 263static void isc_set_histogram(struct isc_device *isc, bool enable)
 264{
 265	struct regmap *regmap = isc->regmap;
 266	struct isc_ctrls *ctrls = &isc->ctrls;
 267
 268	if (enable) {
 269		regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
 270			     ISC_HIS_CFG_MODE_GR |
 271			     (isc->config.sd_format->cfa_baycfg
 272					<< ISC_HIS_CFG_BAYSEL_SHIFT) |
 273					ISC_HIS_CFG_RAR);
 274		regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
 275			     ISC_HIS_CTRL_EN);
 276		regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);
 277		ctrls->hist_id = ISC_HIS_CFG_MODE_GR;
 278		isc_update_profile(isc);
 279		regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
 280
 281		ctrls->hist_stat = HIST_ENABLED;
 282	} else {
 283		regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE);
 284		regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
 285			     ISC_HIS_CTRL_DIS);
 286
 287		ctrls->hist_stat = HIST_DISABLED;
 288	}
 289}
 290
 291static int isc_configure(struct isc_device *isc)
 292{
 293	struct regmap *regmap = isc->regmap;
 294	u32 pfe_cfg0, dcfg, mask, pipeline;
 295	struct isc_subdev_entity *subdev = isc->current_subdev;
 296
 297	pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps;
 298	pipeline = isc->config.bits_pipeline;
 299
 300	dcfg = isc->config.dcfg_imode | isc->dcfg;
 301
 302	pfe_cfg0  |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
 303	mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
 304	       ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
 305	       ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |
 306	       ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI;
 307
 308	regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
 309
 310	isc->config_rlp(isc);
 311
 312	regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg);
 313
 314	/* Set the pipeline */
 315	isc_set_pipeline(isc, pipeline);
 316
 317	/*
 318	 * The current implemented histogram is available for RAW R, B, GB, GR
 319	 * channels. We need to check if sensor is outputting RAW BAYER
 320	 */
 321	if (isc->ctrls.awb &&
 322	    ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
 323		isc_set_histogram(isc, true);
 324	else
 325		isc_set_histogram(isc, false);
 326
 327	/* Update profile */
 328	return isc_update_profile(isc);
 329}
 330
 331static int isc_prepare_streaming(struct vb2_queue *vq)
 332{
 333	struct isc_device *isc = vb2_get_drv_priv(vq);
 334
 335	return media_pipeline_start(isc->video_dev.entity.pads, &isc->mpipe);
 336}
 337
 338static int isc_start_streaming(struct vb2_queue *vq, unsigned int count)
 339{
 340	struct isc_device *isc = vb2_get_drv_priv(vq);
 341	struct regmap *regmap = isc->regmap;
 342	struct isc_buffer *buf;
 343	unsigned long flags;
 344	int ret;
 345
 346	/* Enable stream on the sub device */
 347	ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1);
 348	if (ret && ret != -ENOIOCTLCMD) {
 349		v4l2_err(&isc->v4l2_dev, "stream on failed in subdev %d\n",
 350			 ret);
 351		goto err_start_stream;
 352	}
 353
 354	ret = pm_runtime_resume_and_get(isc->dev);
 355	if (ret < 0) {
 356		v4l2_err(&isc->v4l2_dev, "RPM resume failed in subdev %d\n",
 357			 ret);
 358		goto err_pm_get;
 359	}
 360
 361	ret = isc_configure(isc);
 362	if (unlikely(ret))
 363		goto err_configure;
 364
 365	/* Enable DMA interrupt */
 366	regmap_write(regmap, ISC_INTEN, ISC_INT_DDONE);
 367
 368	spin_lock_irqsave(&isc->dma_queue_lock, flags);
 369
 370	isc->sequence = 0;
 371	isc->stop = false;
 372	reinit_completion(&isc->comp);
 373
 374	isc->cur_frm = list_first_entry(&isc->dma_queue,
 375					struct isc_buffer, list);
 376	list_del(&isc->cur_frm->list);
 377
 378	isc_crop_pfe(isc);
 379	isc_start_dma(isc);
 380
 381	spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 382
 383	/* if we streaming from RAW, we can do one-shot white balance adj */
 384	if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
 385		v4l2_ctrl_activate(isc->do_wb_ctrl, true);
 386
 387	return 0;
 388
 389err_configure:
 390	pm_runtime_put_sync(isc->dev);
 391err_pm_get:
 392	v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
 393
 394err_start_stream:
 395	spin_lock_irqsave(&isc->dma_queue_lock, flags);
 396	list_for_each_entry(buf, &isc->dma_queue, list)
 397		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
 398	INIT_LIST_HEAD(&isc->dma_queue);
 399	spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 400
 401	return ret;
 402}
 403
 404static void isc_unprepare_streaming(struct vb2_queue *vq)
 405{
 406	struct isc_device *isc = vb2_get_drv_priv(vq);
 407
 408	/* Stop media pipeline */
 409	media_pipeline_stop(isc->video_dev.entity.pads);
 410}
 411
 412static void isc_stop_streaming(struct vb2_queue *vq)
 413{
 414	struct isc_device *isc = vb2_get_drv_priv(vq);
 415	unsigned long flags;
 416	struct isc_buffer *buf;
 417	int ret;
 418
 419	mutex_lock(&isc->awb_mutex);
 420	v4l2_ctrl_activate(isc->do_wb_ctrl, false);
 421
 422	isc->stop = true;
 423
 424	/* Wait until the end of the current frame */
 425	if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ))
 426		v4l2_err(&isc->v4l2_dev,
 427			 "Timeout waiting for end of the capture\n");
 428
 429	mutex_unlock(&isc->awb_mutex);
 430
 431	/* Disable DMA interrupt */
 432	regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE);
 433
 434	pm_runtime_put_sync(isc->dev);
 435
 436	/* Disable stream on the sub device */
 437	ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
 438	if (ret && ret != -ENOIOCTLCMD)
 439		v4l2_err(&isc->v4l2_dev, "stream off failed in subdev\n");
 440
 441	/* Release all active buffers */
 442	spin_lock_irqsave(&isc->dma_queue_lock, flags);
 443	if (unlikely(isc->cur_frm)) {
 444		vb2_buffer_done(&isc->cur_frm->vb.vb2_buf,
 445				VB2_BUF_STATE_ERROR);
 446		isc->cur_frm = NULL;
 447	}
 448	list_for_each_entry(buf, &isc->dma_queue, list)
 449		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
 450	INIT_LIST_HEAD(&isc->dma_queue);
 451	spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 452}
 453
 454static void isc_buffer_queue(struct vb2_buffer *vb)
 455{
 456	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 457	struct isc_buffer *buf = container_of(vbuf, struct isc_buffer, vb);
 458	struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
 459	unsigned long flags;
 460
 461	spin_lock_irqsave(&isc->dma_queue_lock, flags);
 462	if (!isc->cur_frm && list_empty(&isc->dma_queue) &&
 463	    vb2_start_streaming_called(vb->vb2_queue)) {
 464		isc->cur_frm = buf;
 465		isc_start_dma(isc);
 466	} else {
 467		list_add_tail(&buf->list, &isc->dma_queue);
 468	}
 469	spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
 470}
 471
 472static const struct vb2_ops isc_vb2_ops = {
 473	.queue_setup		= isc_queue_setup,
 474	.wait_prepare		= vb2_ops_wait_prepare,
 475	.wait_finish		= vb2_ops_wait_finish,
 476	.buf_prepare		= isc_buffer_prepare,
 477	.start_streaming	= isc_start_streaming,
 478	.stop_streaming		= isc_stop_streaming,
 479	.buf_queue		= isc_buffer_queue,
 480	.prepare_streaming	= isc_prepare_streaming,
 481	.unprepare_streaming	= isc_unprepare_streaming,
 482};
 483
 484static int isc_querycap(struct file *file, void *priv,
 485			struct v4l2_capability *cap)
 486{
 487	struct isc_device *isc = video_drvdata(file);
 488
 489	strscpy(cap->driver, "microchip-isc", sizeof(cap->driver));
 490	strscpy(cap->card, "Microchip Image Sensor Controller", sizeof(cap->card));
 491	snprintf(cap->bus_info, sizeof(cap->bus_info),
 492		 "platform:%s", isc->v4l2_dev.name);
 493
 494	return 0;
 495}
 496
 497static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
 498				struct v4l2_fmtdesc *f)
 499{
 500	struct isc_device *isc = video_drvdata(file);
 501	u32 index = f->index;
 502	u32 i, supported_index = 0;
 503	struct isc_format *fmt;
 504
 505	/*
 506	 * If we are not asked a specific mbus_code, we have to report all
 507	 * the formats that we can output.
 508	 */
 509	if (!f->mbus_code) {
 510		if (index >= isc->controller_formats_size)
 511			return -EINVAL;
 512
 513		f->pixelformat = isc->controller_formats[index].fourcc;
 514
 515		return 0;
 516	}
 517
 518	/*
 519	 * If a specific mbus_code is requested, check if we support
 520	 * this mbus_code as input for the ISC.
 521	 * If it's supported, then we report the corresponding pixelformat
 522	 * as first possible option for the ISC.
 523	 * E.g. mbus MEDIA_BUS_FMT_YUYV8_2X8 and report
 524	 * 'YUYV' (YUYV 4:2:2)
 525	 */
 526	fmt = isc_find_format_by_code(isc, f->mbus_code, &i);
 527	if (!fmt)
 528		return -EINVAL;
 529
 530	if (!index) {
 531		f->pixelformat = fmt->fourcc;
 532
 533		return 0;
 534	}
 535
 536	supported_index++;
 537
 538	/* If the index is not raw, we don't have anymore formats to report */
 539	if (!ISC_IS_FORMAT_RAW(f->mbus_code))
 540		return -EINVAL;
 541
 542	/*
 543	 * We are asked for a specific mbus code, which is raw.
 544	 * We have to search through the formats we can convert to.
 545	 * We have to skip the raw formats, we cannot convert to raw.
 546	 * E.g. 'AR12' (16-bit ARGB 4-4-4-4), 'AR15' (16-bit ARGB 1-5-5-5), etc.
 547	 */
 548	for (i = 0; i < isc->controller_formats_size; i++) {
 549		if (isc->controller_formats[i].raw)
 550			continue;
 551		if (index == supported_index) {
 552			f->pixelformat = isc->controller_formats[i].fourcc;
 553			return 0;
 554		}
 555		supported_index++;
 556	}
 557
 558	return -EINVAL;
 559}
 560
 561static int isc_g_fmt_vid_cap(struct file *file, void *priv,
 562			     struct v4l2_format *fmt)
 563{
 564	struct isc_device *isc = video_drvdata(file);
 565
 566	*fmt = isc->fmt;
 567
 568	return 0;
 569}
 570
 571/*
 572 * Checks the current configured format, if ISC can output it,
 573 * considering which type of format the ISC receives from the sensor
 574 */
 575static int isc_try_validate_formats(struct isc_device *isc)
 576{
 577	int ret;
 578	bool bayer = false, yuv = false, rgb = false, grey = false;
 579
 580	/* all formats supported by the RLP module are OK */
 581	switch (isc->try_config.fourcc) {
 582	case V4L2_PIX_FMT_SBGGR8:
 583	case V4L2_PIX_FMT_SGBRG8:
 584	case V4L2_PIX_FMT_SGRBG8:
 585	case V4L2_PIX_FMT_SRGGB8:
 586	case V4L2_PIX_FMT_SBGGR10:
 587	case V4L2_PIX_FMT_SGBRG10:
 588	case V4L2_PIX_FMT_SGRBG10:
 589	case V4L2_PIX_FMT_SRGGB10:
 590	case V4L2_PIX_FMT_SBGGR12:
 591	case V4L2_PIX_FMT_SGBRG12:
 592	case V4L2_PIX_FMT_SGRBG12:
 593	case V4L2_PIX_FMT_SRGGB12:
 594		ret = 0;
 595		bayer = true;
 596		break;
 597
 598	case V4L2_PIX_FMT_YUV420:
 599	case V4L2_PIX_FMT_YUV422P:
 600	case V4L2_PIX_FMT_YUYV:
 601	case V4L2_PIX_FMT_UYVY:
 602	case V4L2_PIX_FMT_VYUY:
 603		ret = 0;
 604		yuv = true;
 605		break;
 606
 607	case V4L2_PIX_FMT_RGB565:
 608	case V4L2_PIX_FMT_ABGR32:
 609	case V4L2_PIX_FMT_XBGR32:
 610	case V4L2_PIX_FMT_ARGB444:
 611	case V4L2_PIX_FMT_ARGB555:
 612		ret = 0;
 613		rgb = true;
 614		break;
 615	case V4L2_PIX_FMT_GREY:
 616	case V4L2_PIX_FMT_Y10:
 617	case V4L2_PIX_FMT_Y16:
 618		ret = 0;
 619		grey = true;
 620		break;
 621	default:
 622	/* any other different formats are not supported */
 623		v4l2_err(&isc->v4l2_dev, "Requested unsupported format.\n");
 624		ret = -EINVAL;
 625	}
 626	v4l2_dbg(1, debug, &isc->v4l2_dev,
 627		 "Format validation, requested rgb=%u, yuv=%u, grey=%u, bayer=%u\n",
 628		 rgb, yuv, grey, bayer);
 629
 630	if (bayer &&
 631	    !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 632		v4l2_err(&isc->v4l2_dev, "Cannot output RAW if we do not receive RAW.\n");
 633		return -EINVAL;
 634	}
 635
 636	if (grey && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code) &&
 637	    !ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code)) {
 638		v4l2_err(&isc->v4l2_dev, "Cannot output GREY if we do not receive RAW/GREY.\n");
 639		return -EINVAL;
 640	}
 641
 642	if ((rgb || bayer || yuv) &&
 643	    ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code)) {
 644		v4l2_err(&isc->v4l2_dev, "Cannot convert GREY to another format.\n");
 645		return -EINVAL;
 646	}
 647
 648	return ret;
 649}
 650
 651/*
 652 * Configures the RLP and DMA modules, depending on the output format
 653 * configured for the ISC.
 654 * If direct_dump == true, just dump raw data 8/16 bits depending on format.
 655 */
 656static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
 657{
 658	isc->try_config.rlp_cfg_mode = 0;
 659
 660	switch (isc->try_config.fourcc) {
 661	case V4L2_PIX_FMT_SBGGR8:
 662	case V4L2_PIX_FMT_SGBRG8:
 663	case V4L2_PIX_FMT_SGRBG8:
 664	case V4L2_PIX_FMT_SRGGB8:
 665		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
 666		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
 667		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 668		isc->try_config.bpp = 8;
 669		isc->try_config.bpp_v4l2 = 8;
 670		break;
 671	case V4L2_PIX_FMT_SBGGR10:
 672	case V4L2_PIX_FMT_SGBRG10:
 673	case V4L2_PIX_FMT_SGRBG10:
 674	case V4L2_PIX_FMT_SRGGB10:
 675		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10;
 676		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
 677		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 678		isc->try_config.bpp = 16;
 679		isc->try_config.bpp_v4l2 = 16;
 680		break;
 681	case V4L2_PIX_FMT_SBGGR12:
 682	case V4L2_PIX_FMT_SGBRG12:
 683	case V4L2_PIX_FMT_SGRBG12:
 684	case V4L2_PIX_FMT_SRGGB12:
 685		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12;
 686		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
 687		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 688		isc->try_config.bpp = 16;
 689		isc->try_config.bpp_v4l2 = 16;
 690		break;
 691	case V4L2_PIX_FMT_RGB565:
 692		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565;
 693		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
 694		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 695		isc->try_config.bpp = 16;
 696		isc->try_config.bpp_v4l2 = 16;
 697		break;
 698	case V4L2_PIX_FMT_ARGB444:
 699		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444;
 700		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
 701		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 702		isc->try_config.bpp = 16;
 703		isc->try_config.bpp_v4l2 = 16;
 704		break;
 705	case V4L2_PIX_FMT_ARGB555:
 706		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555;
 707		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
 708		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 709		isc->try_config.bpp = 16;
 710		isc->try_config.bpp_v4l2 = 16;
 711		break;
 712	case V4L2_PIX_FMT_ABGR32:
 713	case V4L2_PIX_FMT_XBGR32:
 714		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32;
 715		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
 716		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 717		isc->try_config.bpp = 32;
 718		isc->try_config.bpp_v4l2 = 32;
 719		break;
 720	case V4L2_PIX_FMT_YUV420:
 721		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
 722		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P;
 723		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
 724		isc->try_config.bpp = 12;
 725		isc->try_config.bpp_v4l2 = 8; /* only first plane */
 726		break;
 727	case V4L2_PIX_FMT_YUV422P:
 728		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
 729		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P;
 730		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
 731		isc->try_config.bpp = 16;
 732		isc->try_config.bpp_v4l2 = 8; /* only first plane */
 733		break;
 734	case V4L2_PIX_FMT_YUYV:
 735		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV;
 736		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
 737		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 738		isc->try_config.bpp = 16;
 739		isc->try_config.bpp_v4l2 = 16;
 740		break;
 741	case V4L2_PIX_FMT_UYVY:
 742		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY;
 743		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
 744		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 745		isc->try_config.bpp = 16;
 746		isc->try_config.bpp_v4l2 = 16;
 747		break;
 748	case V4L2_PIX_FMT_VYUY:
 749		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY;
 750		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
 751		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 752		isc->try_config.bpp = 16;
 753		isc->try_config.bpp_v4l2 = 16;
 754		break;
 755	case V4L2_PIX_FMT_GREY:
 756		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8;
 757		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
 758		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 759		isc->try_config.bpp = 8;
 760		isc->try_config.bpp_v4l2 = 8;
 761		break;
 762	case V4L2_PIX_FMT_Y16:
 763		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH;
 764		fallthrough;
 765	case V4L2_PIX_FMT_Y10:
 766		isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10;
 767		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
 768		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 769		isc->try_config.bpp = 16;
 770		isc->try_config.bpp_v4l2 = 16;
 771		break;
 772	default:
 773		return -EINVAL;
 774	}
 775
 776	if (direct_dump) {
 777		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
 778		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
 779		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 780		return 0;
 781	}
 782
 783	return 0;
 784}
 785
 786/*
 787 * Configuring pipeline modules, depending on which format the ISC outputs
 788 * and considering which format it has as input from the sensor.
 789 */
 790static int isc_try_configure_pipeline(struct isc_device *isc)
 791{
 792	switch (isc->try_config.fourcc) {
 793	case V4L2_PIX_FMT_RGB565:
 794	case V4L2_PIX_FMT_ARGB555:
 795	case V4L2_PIX_FMT_ARGB444:
 796	case V4L2_PIX_FMT_ABGR32:
 797	case V4L2_PIX_FMT_XBGR32:
 798		/* if sensor format is RAW, we convert inside ISC */
 799		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 800			isc->try_config.bits_pipeline = CFA_ENABLE |
 801				WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE |
 802				CC_ENABLE;
 803		} else {
 804			isc->try_config.bits_pipeline = 0x0;
 805		}
 806		break;
 807	case V4L2_PIX_FMT_YUV420:
 808		/* if sensor format is RAW, we convert inside ISC */
 809		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 810			isc->try_config.bits_pipeline = CFA_ENABLE |
 811				CSC_ENABLE | GAM_ENABLES | WB_ENABLE |
 812				SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE |
 813				DPC_BLCENABLE;
 814		} else {
 815			isc->try_config.bits_pipeline = 0x0;
 816		}
 817		break;
 818	case V4L2_PIX_FMT_YUV422P:
 819		/* if sensor format is RAW, we convert inside ISC */
 820		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 821			isc->try_config.bits_pipeline = CFA_ENABLE |
 822				CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
 823				SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;
 824		} else {
 825			isc->try_config.bits_pipeline = 0x0;
 826		}
 827		break;
 828	case V4L2_PIX_FMT_YUYV:
 829	case V4L2_PIX_FMT_UYVY:
 830	case V4L2_PIX_FMT_VYUY:
 831		/* if sensor format is RAW, we convert inside ISC */
 832		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 833			isc->try_config.bits_pipeline = CFA_ENABLE |
 834				CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
 835				SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;
 836		} else {
 837			isc->try_config.bits_pipeline = 0x0;
 838		}
 839		break;
 840	case V4L2_PIX_FMT_GREY:
 841	case V4L2_PIX_FMT_Y16:
 842		/* if sensor format is RAW, we convert inside ISC */
 843		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 844			isc->try_config.bits_pipeline = CFA_ENABLE |
 845				CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
 846				CBC_ENABLE | DPC_BLCENABLE;
 847		} else {
 848			isc->try_config.bits_pipeline = 0x0;
 849		}
 850		break;
 851	default:
 852		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
 853			isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE;
 854		else
 855			isc->try_config.bits_pipeline = 0x0;
 856	}
 857
 858	/* Tune the pipeline to product specific */
 859	isc->adapt_pipeline(isc);
 860
 861	return 0;
 862}
 863
 864static void isc_try_fse(struct isc_device *isc,
 865			struct v4l2_subdev_state *sd_state)
 866{
 867	int ret;
 868	struct v4l2_subdev_frame_size_enum fse = {};
 869
 870	/*
 871	 * If we do not know yet which format the subdev is using, we cannot
 872	 * do anything.
 873	 */
 874	if (!isc->config.sd_format)
 875		return;
 876
 877	fse.code = isc->try_config.sd_format->mbus_code;
 878	fse.which = V4L2_SUBDEV_FORMAT_TRY;
 879
 880	ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
 881			       sd_state, &fse);
 882	/*
 883	 * Attempt to obtain format size from subdev. If not available,
 884	 * just use the maximum ISC can receive.
 885	 */
 886	if (ret) {
 887		sd_state->pads->try_crop.width = isc->max_width;
 888		sd_state->pads->try_crop.height = isc->max_height;
 889	} else {
 890		sd_state->pads->try_crop.width = fse.max_width;
 891		sd_state->pads->try_crop.height = fse.max_height;
 892	}
 893}
 894
 895static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f)
 896{
 897	struct v4l2_pix_format *pixfmt = &f->fmt.pix;
 898	unsigned int i;
 899
 900	if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
 901		return -EINVAL;
 902
 903	isc->try_config.fourcc = isc->controller_formats[0].fourcc;
 904
 905	/* find if the format requested is supported */
 906	for (i = 0; i < isc->controller_formats_size; i++)
 907		if (isc->controller_formats[i].fourcc == pixfmt->pixelformat) {
 908			isc->try_config.fourcc = pixfmt->pixelformat;
 909			break;
 910		}
 911
 912	isc_try_configure_rlp_dma(isc, false);
 913
 914	/* Limit to Microchip ISC hardware capabilities */
 915	v4l_bound_align_image(&pixfmt->width, 16, isc->max_width, 0,
 916			      &pixfmt->height, 16, isc->max_height, 0, 0);
 917	/* If we did not find the requested format, we will fallback here */
 918	pixfmt->pixelformat = isc->try_config.fourcc;
 919	pixfmt->colorspace = V4L2_COLORSPACE_SRGB;
 920	pixfmt->field = V4L2_FIELD_NONE;
 921
 922	pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp_v4l2) >> 3;
 923	pixfmt->sizeimage = ((pixfmt->width * isc->try_config.bpp) >> 3) *
 924			     pixfmt->height;
 925
 926	isc->try_fmt = *f;
 927
 928	return 0;
 929}
 930
 931static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f)
 932{
 933	isc_try_fmt(isc, f);
 934
 935	/* make the try configuration active */
 936	isc->config = isc->try_config;
 937	isc->fmt = isc->try_fmt;
 938
 939	v4l2_dbg(1, debug, &isc->v4l2_dev, "ISC set_fmt to %.4s @%dx%d\n",
 940		 (char *)&f->fmt.pix.pixelformat,
 941		 f->fmt.pix.width, f->fmt.pix.height);
 942
 943	return 0;
 944}
 945
 946static int isc_validate(struct isc_device *isc)
 947{
 948	int ret;
 949	int i;
 950	struct isc_format *sd_fmt = NULL;
 951	struct v4l2_pix_format *pixfmt = &isc->fmt.fmt.pix;
 952	struct v4l2_subdev_format format = {
 953		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
 954		.pad = isc->remote_pad,
 955	};
 956	struct v4l2_subdev_pad_config pad_cfg = {};
 957	struct v4l2_subdev_state pad_state = {
 958		.pads = &pad_cfg,
 959	};
 960
 961	/* Get current format from subdev */
 962	ret = v4l2_subdev_call(isc->current_subdev->sd, pad, get_fmt, NULL,
 963			       &format);
 964	if (ret)
 965		return ret;
 966
 967	/* Identify the subdev's format configuration */
 968	for (i = 0; i < isc->formats_list_size; i++)
 969		if (isc->formats_list[i].mbus_code == format.format.code) {
 970			sd_fmt = &isc->formats_list[i];
 971			break;
 972		}
 973
 974	/* Check if the format is not supported */
 975	if (!sd_fmt) {
 976		v4l2_err(&isc->v4l2_dev,
 977			 "Current subdevice is streaming a media bus code that is not supported 0x%x\n",
 978			 format.format.code);
 979		return -EPIPE;
 980	}
 981
 982	/* At this moment we know which format the subdev will use */
 983	isc->try_config.sd_format = sd_fmt;
 984
 985	/* If the sensor is not RAW, we can only do a direct dump */
 986	if (!ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
 987		isc_try_configure_rlp_dma(isc, true);
 988
 989	/* Limit to Microchip ISC hardware capabilities */
 990	v4l_bound_align_image(&format.format.width, 16, isc->max_width, 0,
 991			      &format.format.height, 16, isc->max_height, 0, 0);
 992
 993	/* Check if the frame size is the same. Otherwise we may overflow */
 994	if (pixfmt->height != format.format.height ||
 995	    pixfmt->width != format.format.width) {
 996		v4l2_err(&isc->v4l2_dev,
 997			 "ISC not configured with the proper frame size: %dx%d\n",
 998			 format.format.width, format.format.height);
 999		return -EPIPE;
1000	}
1001
1002	v4l2_dbg(1, debug, &isc->v4l2_dev,
1003		 "Identified subdev using format %.4s with %dx%d %d bpp\n",
1004		 (char *)&sd_fmt->fourcc, pixfmt->width, pixfmt->height,
1005		 isc->try_config.bpp);
1006
1007	/* Reset and restart AWB if the subdevice changed the format */
1008	if (isc->try_config.sd_format && isc->config.sd_format &&
1009	    isc->try_config.sd_format != isc->config.sd_format) {
1010		isc->ctrls.hist_stat = HIST_INIT;
1011		isc_reset_awb_ctrls(isc);
1012		isc_update_v4l2_ctrls(isc);
1013	}
1014
1015	/* Validate formats */
1016	ret = isc_try_validate_formats(isc);
1017	if (ret)
1018		return ret;
1019
1020	/* Obtain frame sizes if possible to have crop requirements ready */
1021	isc_try_fse(isc, &pad_state);
1022
1023	/* Configure ISC pipeline for the config */
1024	ret = isc_try_configure_pipeline(isc);
1025	if (ret)
1026		return ret;
1027
1028	isc->config = isc->try_config;
1029
1030	v4l2_dbg(1, debug, &isc->v4l2_dev, "New ISC configuration in place\n");
1031
1032	return 0;
1033}
1034
1035static int isc_s_fmt_vid_cap(struct file *file, void *priv,
1036			     struct v4l2_format *f)
1037{
1038	struct isc_device *isc = video_drvdata(file);
1039
1040	if (vb2_is_busy(&isc->vb2_vidq))
1041		return -EBUSY;
1042
1043	return isc_set_fmt(isc, f);
1044}
1045
1046static int isc_try_fmt_vid_cap(struct file *file, void *priv,
1047			       struct v4l2_format *f)
1048{
1049	struct isc_device *isc = video_drvdata(file);
1050
1051	return isc_try_fmt(isc, f);
1052}
1053
1054static int isc_enum_input(struct file *file, void *priv,
1055			  struct v4l2_input *inp)
1056{
1057	if (inp->index != 0)
1058		return -EINVAL;
1059
1060	inp->type = V4L2_INPUT_TYPE_CAMERA;
1061	inp->std = 0;
1062	strscpy(inp->name, "Camera", sizeof(inp->name));
1063
1064	return 0;
1065}
1066
1067static int isc_g_input(struct file *file, void *priv, unsigned int *i)
1068{
1069	*i = 0;
1070
1071	return 0;
1072}
1073
1074static int isc_s_input(struct file *file, void *priv, unsigned int i)
1075{
1076	if (i > 0)
1077		return -EINVAL;
1078
1079	return 0;
1080}
1081
1082static int isc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1083{
1084	struct isc_device *isc = video_drvdata(file);
1085
1086	return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1087}
1088
1089static int isc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1090{
1091	struct isc_device *isc = video_drvdata(file);
1092
1093	return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1094}
1095
1096static int isc_enum_framesizes(struct file *file, void *fh,
1097			       struct v4l2_frmsizeenum *fsize)
1098{
1099	struct isc_device *isc = video_drvdata(file);
1100	int ret = -EINVAL;
1101	int i;
1102
1103	if (fsize->index)
1104		return -EINVAL;
1105
1106	for (i = 0; i < isc->controller_formats_size; i++)
1107		if (isc->controller_formats[i].fourcc == fsize->pixel_format)
1108			ret = 0;
1109
1110	if (ret)
1111		return ret;
1112
1113	fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
1114
1115	fsize->stepwise.min_width = 16;
1116	fsize->stepwise.max_width = isc->max_width;
1117	fsize->stepwise.min_height = 16;
1118	fsize->stepwise.max_height = isc->max_height;
1119	fsize->stepwise.step_width = 1;
1120	fsize->stepwise.step_height = 1;
1121
1122	return 0;
1123}
1124
1125static const struct v4l2_ioctl_ops isc_ioctl_ops = {
1126	.vidioc_querycap		= isc_querycap,
1127	.vidioc_enum_fmt_vid_cap	= isc_enum_fmt_vid_cap,
1128	.vidioc_g_fmt_vid_cap		= isc_g_fmt_vid_cap,
1129	.vidioc_s_fmt_vid_cap		= isc_s_fmt_vid_cap,
1130	.vidioc_try_fmt_vid_cap		= isc_try_fmt_vid_cap,
1131
1132	.vidioc_enum_input		= isc_enum_input,
1133	.vidioc_g_input			= isc_g_input,
1134	.vidioc_s_input			= isc_s_input,
1135
1136	.vidioc_reqbufs			= vb2_ioctl_reqbufs,
1137	.vidioc_querybuf		= vb2_ioctl_querybuf,
1138	.vidioc_qbuf			= vb2_ioctl_qbuf,
1139	.vidioc_expbuf			= vb2_ioctl_expbuf,
1140	.vidioc_dqbuf			= vb2_ioctl_dqbuf,
1141	.vidioc_create_bufs		= vb2_ioctl_create_bufs,
1142	.vidioc_prepare_buf		= vb2_ioctl_prepare_buf,
1143	.vidioc_streamon		= vb2_ioctl_streamon,
1144	.vidioc_streamoff		= vb2_ioctl_streamoff,
1145
1146	.vidioc_g_parm			= isc_g_parm,
1147	.vidioc_s_parm			= isc_s_parm,
1148	.vidioc_enum_framesizes		= isc_enum_framesizes,
1149
1150	.vidioc_log_status		= v4l2_ctrl_log_status,
1151	.vidioc_subscribe_event		= v4l2_ctrl_subscribe_event,
1152	.vidioc_unsubscribe_event	= v4l2_event_unsubscribe,
1153};
1154
1155static int isc_open(struct file *file)
1156{
1157	struct isc_device *isc = video_drvdata(file);
1158	struct v4l2_subdev *sd = isc->current_subdev->sd;
1159	int ret;
1160
1161	if (mutex_lock_interruptible(&isc->lock))
1162		return -ERESTARTSYS;
1163
1164	ret = v4l2_fh_open(file);
1165	if (ret < 0)
1166		goto unlock;
1167
1168	if (!v4l2_fh_is_singular_file(file))
1169		goto unlock;
1170
1171	ret = v4l2_subdev_call(sd, core, s_power, 1);
1172	if (ret < 0 && ret != -ENOIOCTLCMD) {
1173		v4l2_fh_release(file);
1174		goto unlock;
1175	}
1176
1177	ret = isc_set_fmt(isc, &isc->fmt);
1178	if (ret) {
1179		v4l2_subdev_call(sd, core, s_power, 0);
1180		v4l2_fh_release(file);
1181	}
1182
1183unlock:
1184	mutex_unlock(&isc->lock);
1185	return ret;
1186}
1187
1188static int isc_release(struct file *file)
1189{
1190	struct isc_device *isc = video_drvdata(file);
1191	struct v4l2_subdev *sd = isc->current_subdev->sd;
1192	bool fh_singular;
1193	int ret;
1194
1195	mutex_lock(&isc->lock);
1196
1197	fh_singular = v4l2_fh_is_singular_file(file);
1198
1199	ret = _vb2_fop_release(file, NULL);
1200
1201	if (fh_singular)
1202		v4l2_subdev_call(sd, core, s_power, 0);
1203
1204	mutex_unlock(&isc->lock);
1205
1206	return ret;
1207}
1208
1209static const struct v4l2_file_operations isc_fops = {
1210	.owner		= THIS_MODULE,
1211	.open		= isc_open,
1212	.release	= isc_release,
1213	.unlocked_ioctl	= video_ioctl2,
1214	.read		= vb2_fop_read,
1215	.mmap		= vb2_fop_mmap,
1216	.poll		= vb2_fop_poll,
1217};
1218
1219irqreturn_t microchip_isc_interrupt(int irq, void *dev_id)
1220{
1221	struct isc_device *isc = (struct isc_device *)dev_id;
1222	struct regmap *regmap = isc->regmap;
1223	u32 isc_intsr, isc_intmask, pending;
1224	irqreturn_t ret = IRQ_NONE;
1225
1226	regmap_read(regmap, ISC_INTSR, &isc_intsr);
1227	regmap_read(regmap, ISC_INTMASK, &isc_intmask);
1228
1229	pending = isc_intsr & isc_intmask;
1230
1231	if (likely(pending & ISC_INT_DDONE)) {
1232		spin_lock(&isc->dma_queue_lock);
1233		if (isc->cur_frm) {
1234			struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb;
1235			struct vb2_buffer *vb = &vbuf->vb2_buf;
1236
1237			vb->timestamp = ktime_get_ns();
1238			vbuf->sequence = isc->sequence++;
1239			vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1240			isc->cur_frm = NULL;
1241		}
1242
1243		if (!list_empty(&isc->dma_queue) && !isc->stop) {
1244			isc->cur_frm = list_first_entry(&isc->dma_queue,
1245							struct isc_buffer, list);
1246			list_del(&isc->cur_frm->list);
1247
1248			isc_start_dma(isc);
1249		}
1250
1251		if (isc->stop)
1252			complete(&isc->comp);
1253
1254		ret = IRQ_HANDLED;
1255		spin_unlock(&isc->dma_queue_lock);
1256	}
1257
1258	if (pending & ISC_INT_HISDONE) {
1259		schedule_work(&isc->awb_work);
1260		ret = IRQ_HANDLED;
1261	}
1262
1263	return ret;
1264}
1265EXPORT_SYMBOL_GPL(microchip_isc_interrupt);
1266
1267static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max)
1268{
1269	struct regmap *regmap = isc->regmap;
1270	struct isc_ctrls *ctrls = &isc->ctrls;
1271	u32 *hist_count = &ctrls->hist_count[ctrls->hist_id];
1272	u32 *hist_entry = &ctrls->hist_entry[0];
1273	u32 i;
1274
1275	*min = 0;
1276	*max = HIST_ENTRIES;
1277
1278	regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry,
1279			 hist_entry, HIST_ENTRIES);
1280
1281	*hist_count = 0;
1282	/*
1283	 * we deliberately ignore the end of the histogram,
1284	 * the most white pixels
1285	 */
1286	for (i = 1; i < HIST_ENTRIES; i++) {
1287		if (*hist_entry && !*min)
1288			*min = i;
1289		if (*hist_entry)
1290			*max = i;
1291		*hist_count += i * (*hist_entry++);
1292	}
1293
1294	if (!*min)
1295		*min = 1;
1296
1297	v4l2_dbg(1, debug, &isc->v4l2_dev,
1298		 "isc wb: hist_id %u, hist_count %u",
1299		 ctrls->hist_id, *hist_count);
1300}
1301
1302static void isc_wb_update(struct isc_ctrls *ctrls)
1303{
1304	struct isc_device *isc = container_of(ctrls, struct isc_device, ctrls);
1305	u32 *hist_count = &ctrls->hist_count[0];
1306	u32 c, offset[4];
1307	u64 avg = 0;
1308	/* We compute two gains, stretch gain and grey world gain */
1309	u32 s_gain[4], gw_gain[4];
1310
1311	/*
1312	 * According to Grey World, we need to set gains for R/B to normalize
1313	 * them towards the green channel.
1314	 * Thus we want to keep Green as fixed and adjust only Red/Blue
1315	 * Compute the average of the both green channels first
1316	 */
1317	avg = (u64)hist_count[ISC_HIS_CFG_MODE_GR] +
1318		(u64)hist_count[ISC_HIS_CFG_MODE_GB];
1319	avg >>= 1;
1320
1321	v4l2_dbg(1, debug, &isc->v4l2_dev,
1322		 "isc wb: green components average %llu\n", avg);
1323
1324	/* Green histogram is null, nothing to do */
1325	if (!avg)
1326		return;
1327
1328	for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
1329		/*
1330		 * the color offset is the minimum value of the histogram.
1331		 * we stretch this color to the full range by substracting
1332		 * this value from the color component.
1333		 */
1334		offset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX];
1335		/*
1336		 * The offset is always at least 1. If the offset is 1, we do
1337		 * not need to adjust it, so our result must be zero.
1338		 * the offset is computed in a histogram on 9 bits (0..512)
1339		 * but the offset in register is based on
1340		 * 12 bits pipeline (0..4096).
1341		 * we need to shift with the 3 bits that the histogram is
1342		 * ignoring
1343		 */
1344		ctrls->offset[c] = (offset[c] - 1) << 3;
1345
1346		/*
1347		 * the offset is then taken and converted to 2's complements,
1348		 * and must be negative, as we subtract this value from the
1349		 * color components
1350		 */
1351		ctrls->offset[c] = -ctrls->offset[c];
1352
1353		/*
1354		 * the stretch gain is the total number of histogram bins
1355		 * divided by the actual range of color component (Max - Min)
1356		 * If we compute gain like this, the actual color component
1357		 * will be stretched to the full histogram.
1358		 * We need to shift 9 bits for precision, we have 9 bits for
1359		 * decimals
1360		 */
1361		s_gain[c] = (HIST_ENTRIES << 9) /
1362			(ctrls->hist_minmax[c][HIST_MAX_INDEX] -
1363			ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1);
1364
1365		/*
1366		 * Now we have to compute the gain w.r.t. the average.
1367		 * Add/lose gain to the component towards the average.
1368		 * If it happens that the component is zero, use the
1369		 * fixed point value : 1.0 gain.
1370		 */
1371		if (hist_count[c])
1372			gw_gain[c] = div_u64(avg << 9, hist_count[c]);
1373		else
1374			gw_gain[c] = 1 << 9;
1375
1376		v4l2_dbg(1, debug, &isc->v4l2_dev,
1377			 "isc wb: component %d, s_gain %u, gw_gain %u\n",
1378			 c, s_gain[c], gw_gain[c]);
1379		/* multiply both gains and adjust for decimals */
1380		ctrls->gain[c] = s_gain[c] * gw_gain[c];
1381		ctrls->gain[c] >>= 9;
1382
1383		/* make sure we are not out of range */
1384		ctrls->gain[c] = clamp_val(ctrls->gain[c], 0, GENMASK(12, 0));
1385
1386		v4l2_dbg(1, debug, &isc->v4l2_dev,
1387			 "isc wb: component %d, final gain %u\n",
1388			 c, ctrls->gain[c]);
1389	}
1390}
1391
1392static void isc_awb_work(struct work_struct *w)
1393{
1394	struct isc_device *isc =
1395		container_of(w, struct isc_device, awb_work);
1396	struct regmap *regmap = isc->regmap;
1397	struct isc_ctrls *ctrls = &isc->ctrls;
1398	u32 hist_id = ctrls->hist_id;
1399	u32 baysel;
1400	unsigned long flags;
1401	u32 min, max;
1402	int ret;
1403
1404	if (ctrls->hist_stat != HIST_ENABLED)
1405		return;
1406
1407	isc_hist_count(isc, &min, &max);
1408
1409	v4l2_dbg(1, debug, &isc->v4l2_dev,
1410		 "isc wb mode %d: hist min %u , max %u\n", hist_id, min, max);
1411
1412	ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min;
1413	ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max;
1414
1415	if (hist_id != ISC_HIS_CFG_MODE_B) {
1416		hist_id++;
1417	} else {
1418		isc_wb_update(ctrls);
1419		hist_id = ISC_HIS_CFG_MODE_GR;
1420	}
1421
1422	ctrls->hist_id = hist_id;
1423	baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;
1424
1425	ret = pm_runtime_resume_and_get(isc->dev);
1426	if (ret < 0)
1427		return;
1428
1429	/*
1430	 * only update if we have all the required histograms and controls
1431	 * if awb has been disabled, we need to reset registers as well.
1432	 */
1433	if (hist_id == ISC_HIS_CFG_MODE_GR || ctrls->awb == ISC_WB_NONE) {
1434		/*
1435		 * It may happen that DMA Done IRQ will trigger while we are
1436		 * updating white balance registers here.
1437		 * In that case, only parts of the controls have been updated.
1438		 * We can avoid that by locking the section.
1439		 */
1440		spin_lock_irqsave(&isc->awb_lock, flags);
1441		isc_update_awb_ctrls(isc);
1442		spin_unlock_irqrestore(&isc->awb_lock, flags);
1443
1444		/*
1445		 * if we are doing just the one time white balance adjustment,
1446		 * we are basically done.
1447		 */
1448		if (ctrls->awb == ISC_WB_ONETIME) {
1449			v4l2_info(&isc->v4l2_dev,
1450				  "Completed one time white-balance adjustment.\n");
1451			/* update the v4l2 controls values */
1452			isc_update_v4l2_ctrls(isc);
1453			ctrls->awb = ISC_WB_NONE;
1454		}
1455	}
1456	regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
1457		     hist_id | baysel | ISC_HIS_CFG_RAR);
1458
1459	/*
1460	 * We have to make sure the streaming has not stopped meanwhile.
1461	 * ISC requires a frame to clock the internal profile update.
1462	 * To avoid issues, lock the sequence with a mutex
1463	 */
1464	mutex_lock(&isc->awb_mutex);
1465
1466	/* streaming is not active anymore */
1467	if (isc->stop) {
1468		mutex_unlock(&isc->awb_mutex);
1469		return;
1470	}
1471
1472	isc_update_profile(isc);
1473
1474	mutex_unlock(&isc->awb_mutex);
1475
1476	/* if awb has been disabled, we don't need to start another histogram */
1477	if (ctrls->awb)
1478		regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
1479
1480	pm_runtime_put_sync(isc->dev);
1481}
1482
1483static int isc_s_ctrl(struct v4l2_ctrl *ctrl)
1484{
1485	struct isc_device *isc = container_of(ctrl->handler,
1486					     struct isc_device, ctrls.handler);
1487	struct isc_ctrls *ctrls = &isc->ctrls;
1488
1489	if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1490		return 0;
1491
1492	switch (ctrl->id) {
1493	case V4L2_CID_BRIGHTNESS:
1494		ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK;
1495		break;
1496	case V4L2_CID_CONTRAST:
1497		ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK;
1498		break;
1499	case V4L2_CID_GAMMA:
1500		ctrls->gamma_index = ctrl->val;
1501		break;
1502	default:
1503		return -EINVAL;
1504	}
1505
1506	return 0;
1507}
1508
1509static const struct v4l2_ctrl_ops isc_ctrl_ops = {
1510	.s_ctrl	= isc_s_ctrl,
1511};
1512
1513static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl)
1514{
1515	struct isc_device *isc = container_of(ctrl->handler,
1516					     struct isc_device, ctrls.handler);
1517	struct isc_ctrls *ctrls = &isc->ctrls;
1518
1519	if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1520		return 0;
1521
1522	switch (ctrl->id) {
1523	case V4L2_CID_AUTO_WHITE_BALANCE:
1524		if (ctrl->val == 1)
1525			ctrls->awb = ISC_WB_AUTO;
1526		else
1527			ctrls->awb = ISC_WB_NONE;
1528
1529		/* configure the controls with new values from v4l2 */
1530		if (ctrl->cluster[ISC_CTRL_R_GAIN]->is_new)
1531			ctrls->gain[ISC_HIS_CFG_MODE_R] = isc->r_gain_ctrl->val;
1532		if (ctrl->cluster[ISC_CTRL_B_GAIN]->is_new)
1533			ctrls->gain[ISC_HIS_CFG_MODE_B] = isc->b_gain_ctrl->val;
1534		if (ctrl->cluster[ISC_CTRL_GR_GAIN]->is_new)
1535			ctrls->gain[ISC_HIS_CFG_MODE_GR] = isc->gr_gain_ctrl->val;
1536		if (ctrl->cluster[ISC_CTRL_GB_GAIN]->is_new)
1537			ctrls->gain[ISC_HIS_CFG_MODE_GB] = isc->gb_gain_ctrl->val;
1538
1539		if (ctrl->cluster[ISC_CTRL_R_OFF]->is_new)
1540			ctrls->offset[ISC_HIS_CFG_MODE_R] = isc->r_off_ctrl->val;
1541		if (ctrl->cluster[ISC_CTRL_B_OFF]->is_new)
1542			ctrls->offset[ISC_HIS_CFG_MODE_B] = isc->b_off_ctrl->val;
1543		if (ctrl->cluster[ISC_CTRL_GR_OFF]->is_new)
1544			ctrls->offset[ISC_HIS_CFG_MODE_GR] = isc->gr_off_ctrl->val;
1545		if (ctrl->cluster[ISC_CTRL_GB_OFF]->is_new)
1546			ctrls->offset[ISC_HIS_CFG_MODE_GB] = isc->gb_off_ctrl->val;
1547
1548		isc_update_awb_ctrls(isc);
1549
1550		mutex_lock(&isc->awb_mutex);
1551		if (vb2_is_streaming(&isc->vb2_vidq)) {
1552			/*
1553			 * If we are streaming, we can update profile to
1554			 * have the new settings in place.
1555			 */
1556			isc_update_profile(isc);
1557		} else {
1558			/*
1559			 * The auto cluster will activate automatically this
1560			 * control. This has to be deactivated when not
1561			 * streaming.
1562			 */
1563			v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1564		}
1565		mutex_unlock(&isc->awb_mutex);
1566
1567		/* if we have autowhitebalance on, start histogram procedure */
1568		if (ctrls->awb == ISC_WB_AUTO &&
1569		    vb2_is_streaming(&isc->vb2_vidq) &&
1570		    ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
1571			isc_set_histogram(isc, true);
1572
1573		/*
1574		 * for one time whitebalance adjustment, check the button,
1575		 * if it's pressed, perform the one time operation.
1576		 */
1577		if (ctrls->awb == ISC_WB_NONE &&
1578		    ctrl->cluster[ISC_CTRL_DO_WB]->is_new &&
1579		    !(ctrl->cluster[ISC_CTRL_DO_WB]->flags &
1580		    V4L2_CTRL_FLAG_INACTIVE)) {
1581			ctrls->awb = ISC_WB_ONETIME;
1582			isc_set_histogram(isc, true);
1583			v4l2_dbg(1, debug, &isc->v4l2_dev,
1584				 "One time white-balance started.\n");
1585		}
1586		return 0;
1587	}
1588	return 0;
1589}
1590
1591static int isc_g_volatile_awb_ctrl(struct v4l2_ctrl *ctrl)
1592{
1593	struct isc_device *isc = container_of(ctrl->handler,
1594					     struct isc_device, ctrls.handler);
1595	struct isc_ctrls *ctrls = &isc->ctrls;
1596
1597	switch (ctrl->id) {
1598	/* being a cluster, this id will be called for every control */
1599	case V4L2_CID_AUTO_WHITE_BALANCE:
1600		ctrl->cluster[ISC_CTRL_R_GAIN]->val =
1601					ctrls->gain[ISC_HIS_CFG_MODE_R];
1602		ctrl->cluster[ISC_CTRL_B_GAIN]->val =
1603					ctrls->gain[ISC_HIS_CFG_MODE_B];
1604		ctrl->cluster[ISC_CTRL_GR_GAIN]->val =
1605					ctrls->gain[ISC_HIS_CFG_MODE_GR];
1606		ctrl->cluster[ISC_CTRL_GB_GAIN]->val =
1607					ctrls->gain[ISC_HIS_CFG_MODE_GB];
1608
1609		ctrl->cluster[ISC_CTRL_R_OFF]->val =
1610			ctrls->offset[ISC_HIS_CFG_MODE_R];
1611		ctrl->cluster[ISC_CTRL_B_OFF]->val =
1612			ctrls->offset[ISC_HIS_CFG_MODE_B];
1613		ctrl->cluster[ISC_CTRL_GR_OFF]->val =
1614			ctrls->offset[ISC_HIS_CFG_MODE_GR];
1615		ctrl->cluster[ISC_CTRL_GB_OFF]->val =
1616			ctrls->offset[ISC_HIS_CFG_MODE_GB];
1617		break;
1618	}
1619	return 0;
1620}
1621
1622static const struct v4l2_ctrl_ops isc_awb_ops = {
1623	.s_ctrl = isc_s_awb_ctrl,
1624	.g_volatile_ctrl = isc_g_volatile_awb_ctrl,
1625};
1626
1627#define ISC_CTRL_OFF(_name, _id, _name_str) \
1628	static const struct v4l2_ctrl_config _name = { \
1629		.ops = &isc_awb_ops, \
1630		.id = _id, \
1631		.name = _name_str, \
1632		.type = V4L2_CTRL_TYPE_INTEGER, \
1633		.flags = V4L2_CTRL_FLAG_SLIDER, \
1634		.min = -4095, \
1635		.max = 4095, \
1636		.step = 1, \
1637		.def = 0, \
1638	}
1639
1640ISC_CTRL_OFF(isc_r_off_ctrl, ISC_CID_R_OFFSET, "Red Component Offset");
1641ISC_CTRL_OFF(isc_b_off_ctrl, ISC_CID_B_OFFSET, "Blue Component Offset");
1642ISC_CTRL_OFF(isc_gr_off_ctrl, ISC_CID_GR_OFFSET, "Green Red Component Offset");
1643ISC_CTRL_OFF(isc_gb_off_ctrl, ISC_CID_GB_OFFSET, "Green Blue Component Offset");
1644
1645#define ISC_CTRL_GAIN(_name, _id, _name_str) \
1646	static const struct v4l2_ctrl_config _name = { \
1647		.ops = &isc_awb_ops, \
1648		.id = _id, \
1649		.name = _name_str, \
1650		.type = V4L2_CTRL_TYPE_INTEGER, \
1651		.flags = V4L2_CTRL_FLAG_SLIDER, \
1652		.min = 0, \
1653		.max = 8191, \
1654		.step = 1, \
1655		.def = 512, \
1656	}
1657
1658ISC_CTRL_GAIN(isc_r_gain_ctrl, ISC_CID_R_GAIN, "Red Component Gain");
1659ISC_CTRL_GAIN(isc_b_gain_ctrl, ISC_CID_B_GAIN, "Blue Component Gain");
1660ISC_CTRL_GAIN(isc_gr_gain_ctrl, ISC_CID_GR_GAIN, "Green Red Component Gain");
1661ISC_CTRL_GAIN(isc_gb_gain_ctrl, ISC_CID_GB_GAIN, "Green Blue Component Gain");
1662
1663static int isc_ctrl_init(struct isc_device *isc)
1664{
1665	const struct v4l2_ctrl_ops *ops = &isc_ctrl_ops;
1666	struct isc_ctrls *ctrls = &isc->ctrls;
1667	struct v4l2_ctrl_handler *hdl = &ctrls->handler;
1668	int ret;
1669
1670	ctrls->hist_stat = HIST_INIT;
1671	isc_reset_awb_ctrls(isc);
1672
1673	ret = v4l2_ctrl_handler_init(hdl, 13);
1674	if (ret < 0)
1675		return ret;
1676
1677	/* Initialize product specific controls. For example, contrast */
1678	isc->config_ctrls(isc, ops);
1679
1680	ctrls->brightness = 0;
1681
1682	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);
1683	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1,
1684			  isc->gamma_max);
1685	isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
1686					  V4L2_CID_AUTO_WHITE_BALANCE,
1687					  0, 1, 1, 1);
1688
1689	/* do_white_balance is a button, so min,max,step,default are ignored */
1690	isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
1691					    V4L2_CID_DO_WHITE_BALANCE,
1692					    0, 0, 0, 0);
1693
1694	if (!isc->do_wb_ctrl) {
1695		ret = hdl->error;
1696		v4l2_ctrl_handler_free(hdl);
1697		return ret;
1698	}
1699
1700	v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1701
1702	isc->r_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL);
1703	isc->b_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL);
1704	isc->gr_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_gain_ctrl, NULL);
1705	isc->gb_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_gain_ctrl, NULL);
1706	isc->r_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_off_ctrl, NULL);
1707	isc->b_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_off_ctrl, NULL);
1708	isc->gr_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_off_ctrl, NULL);
1709	isc->gb_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_off_ctrl, NULL);
1710
1711	/*
1712	 * The cluster is in auto mode with autowhitebalance enabled
1713	 * and manual mode otherwise.
1714	 */
1715	v4l2_ctrl_auto_cluster(10, &isc->awb_ctrl, 0, true);
1716
1717	v4l2_ctrl_handler_setup(hdl);
1718
1719	return 0;
1720}
1721
1722static int isc_async_bound(struct v4l2_async_notifier *notifier,
1723			   struct v4l2_subdev *subdev,
1724			   struct v4l2_async_subdev *asd)
1725{
1726	struct isc_device *isc = container_of(notifier->v4l2_dev,
1727					      struct isc_device, v4l2_dev);
1728	struct isc_subdev_entity *subdev_entity =
1729		container_of(notifier, struct isc_subdev_entity, notifier);
1730	int pad;
1731
1732	if (video_is_registered(&isc->video_dev)) {
1733		v4l2_err(&isc->v4l2_dev, "only supports one sub-device.\n");
1734		return -EBUSY;
1735	}
1736
1737	subdev_entity->sd = subdev;
1738
1739	pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode,
1740					  MEDIA_PAD_FL_SOURCE);
1741	if (pad < 0) {
1742		v4l2_err(&isc->v4l2_dev, "failed to find pad for %s\n",
1743			 subdev->name);
1744		return pad;
1745	}
1746
1747	isc->remote_pad = pad;
1748
1749	return 0;
1750}
1751
1752static void isc_async_unbind(struct v4l2_async_notifier *notifier,
1753			     struct v4l2_subdev *subdev,
1754			     struct v4l2_async_subdev *asd)
1755{
1756	struct isc_device *isc = container_of(notifier->v4l2_dev,
1757					      struct isc_device, v4l2_dev);
1758	mutex_destroy(&isc->awb_mutex);
1759	cancel_work_sync(&isc->awb_work);
1760	video_unregister_device(&isc->video_dev);
1761	v4l2_ctrl_handler_free(&isc->ctrls.handler);
1762}
1763
1764struct isc_format *isc_find_format_by_code(struct isc_device *isc,
1765					   unsigned int code, int *index)
1766{
1767	struct isc_format *fmt = &isc->formats_list[0];
1768	unsigned int i;
1769
1770	for (i = 0; i < isc->formats_list_size; i++) {
1771		if (fmt->mbus_code == code) {
1772			*index = i;
1773			return fmt;
1774		}
1775
1776		fmt++;
1777	}
1778
1779	return NULL;
1780}
1781EXPORT_SYMBOL_GPL(isc_find_format_by_code);
1782
1783static int isc_set_default_fmt(struct isc_device *isc)
1784{
1785	struct v4l2_format f = {
1786		.type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
1787		.fmt.pix = {
1788			.width		= VGA_WIDTH,
1789			.height		= VGA_HEIGHT,
1790			.field		= V4L2_FIELD_NONE,
1791			.pixelformat	= isc->controller_formats[0].fourcc,
1792		},
1793	};
1794	int ret;
1795
1796	ret = isc_try_fmt(isc, &f);
1797	if (ret)
1798		return ret;
1799
1800	isc->fmt = f;
1801	return 0;
1802}
1803
1804static int isc_async_complete(struct v4l2_async_notifier *notifier)
1805{
1806	struct isc_device *isc = container_of(notifier->v4l2_dev,
1807					      struct isc_device, v4l2_dev);
1808	struct video_device *vdev = &isc->video_dev;
1809	struct vb2_queue *q = &isc->vb2_vidq;
1810	int ret = 0;
1811
1812	INIT_WORK(&isc->awb_work, isc_awb_work);
1813
1814	ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev);
1815	if (ret < 0) {
1816		v4l2_err(&isc->v4l2_dev, "Failed to register subdev nodes\n");
1817		return ret;
1818	}
1819
1820	isc->current_subdev = container_of(notifier,
1821					   struct isc_subdev_entity, notifier);
1822	mutex_init(&isc->lock);
1823	mutex_init(&isc->awb_mutex);
1824
1825	init_completion(&isc->comp);
1826
1827	/* Initialize videobuf2 queue */
1828	q->type			= V4L2_BUF_TYPE_VIDEO_CAPTURE;
1829	q->io_modes		= VB2_MMAP | VB2_DMABUF | VB2_READ;
1830	q->drv_priv		= isc;
1831	q->buf_struct_size	= sizeof(struct isc_buffer);
1832	q->ops			= &isc_vb2_ops;
1833	q->mem_ops		= &vb2_dma_contig_memops;
1834	q->timestamp_flags	= V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1835	q->lock			= &isc->lock;
1836	q->min_buffers_needed	= 1;
1837	q->dev			= isc->dev;
1838
1839	ret = vb2_queue_init(q);
1840	if (ret < 0) {
1841		v4l2_err(&isc->v4l2_dev,
1842			 "vb2_queue_init() failed: %d\n", ret);
1843		goto isc_async_complete_err;
1844	}
1845
1846	/* Init video dma queues */
1847	INIT_LIST_HEAD(&isc->dma_queue);
1848	spin_lock_init(&isc->dma_queue_lock);
1849	spin_lock_init(&isc->awb_lock);
1850
1851	ret = isc_set_default_fmt(isc);
1852	if (ret) {
1853		v4l2_err(&isc->v4l2_dev, "Could not set default format\n");
1854		goto isc_async_complete_err;
1855	}
1856
1857	ret = isc_ctrl_init(isc);
1858	if (ret) {
1859		v4l2_err(&isc->v4l2_dev, "Init isc ctrols failed: %d\n", ret);
1860		goto isc_async_complete_err;
1861	}
1862
1863	/* Register video device */
1864	strscpy(vdev->name, KBUILD_MODNAME, sizeof(vdev->name));
1865	vdev->release		= video_device_release_empty;
1866	vdev->fops		= &isc_fops;
1867	vdev->ioctl_ops		= &isc_ioctl_ops;
1868	vdev->v4l2_dev		= &isc->v4l2_dev;
1869	vdev->vfl_dir		= VFL_DIR_RX;
1870	vdev->queue		= q;
1871	vdev->lock		= &isc->lock;
1872	vdev->ctrl_handler	= &isc->ctrls.handler;
1873	vdev->device_caps	= V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE |
1874				  V4L2_CAP_IO_MC;
1875	video_set_drvdata(vdev, isc);
1876
1877	ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
1878	if (ret < 0) {
1879		v4l2_err(&isc->v4l2_dev,
1880			 "video_register_device failed: %d\n", ret);
1881		goto isc_async_complete_err;
1882	}
1883
1884	ret = isc_scaler_link(isc);
1885	if (ret < 0)
1886		goto isc_async_complete_unregister_device;
1887
1888	ret = media_device_register(&isc->mdev);
1889	if (ret < 0)
1890		goto isc_async_complete_unregister_device;
1891
1892	return 0;
1893
1894isc_async_complete_unregister_device:
1895	video_unregister_device(vdev);
1896
1897isc_async_complete_err:
1898	mutex_destroy(&isc->awb_mutex);
1899	mutex_destroy(&isc->lock);
1900	return ret;
1901}
1902
1903const struct v4l2_async_notifier_operations microchip_isc_async_ops = {
1904	.bound = isc_async_bound,
1905	.unbind = isc_async_unbind,
1906	.complete = isc_async_complete,
1907};
1908EXPORT_SYMBOL_GPL(microchip_isc_async_ops);
1909
1910void microchip_isc_subdev_cleanup(struct isc_device *isc)
1911{
1912	struct isc_subdev_entity *subdev_entity;
1913
1914	list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
1915		v4l2_async_nf_unregister(&subdev_entity->notifier);
1916		v4l2_async_nf_cleanup(&subdev_entity->notifier);
1917	}
1918
1919	INIT_LIST_HEAD(&isc->subdev_entities);
1920}
1921EXPORT_SYMBOL_GPL(microchip_isc_subdev_cleanup);
1922
1923int microchip_isc_pipeline_init(struct isc_device *isc)
1924{
1925	struct device *dev = isc->dev;
1926	struct regmap *regmap = isc->regmap;
1927	struct regmap_field *regs;
1928	unsigned int i;
1929
1930	/*
1931	 * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC-->
1932	 * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420
1933	 */
1934	const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {
1935		REG_FIELD(ISC_DPC_CTRL, 0, 0),
1936		REG_FIELD(ISC_DPC_CTRL, 1, 1),
1937		REG_FIELD(ISC_DPC_CTRL, 2, 2),
1938		REG_FIELD(ISC_WB_CTRL, 0, 0),
1939		REG_FIELD(ISC_CFA_CTRL, 0, 0),
1940		REG_FIELD(ISC_CC_CTRL, 0, 0),
1941		REG_FIELD(ISC_GAM_CTRL, 0, 0),
1942		REG_FIELD(ISC_GAM_CTRL, 1, 1),
1943		REG_FIELD(ISC_GAM_CTRL, 2, 2),
1944		REG_FIELD(ISC_GAM_CTRL, 3, 3),
1945		REG_FIELD(ISC_VHXS_CTRL, 0, 0),
1946		REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
1947		REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
1948		REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),
1949		REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0),
1950	};
1951
1952	for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
1953		regs = devm_regmap_field_alloc(dev, regmap, regfields[i]);
1954		if (IS_ERR(regs))
1955			return PTR_ERR(regs);
1956
1957		isc->pipeline[i] =  regs;
1958	}
1959
1960	return 0;
1961}
1962EXPORT_SYMBOL_GPL(microchip_isc_pipeline_init);
1963
1964static int isc_link_validate(struct media_link *link)
1965{
1966	struct video_device *vdev =
1967		media_entity_to_video_device(link->sink->entity);
1968	struct isc_device *isc = video_get_drvdata(vdev);
1969	int ret;
1970
1971	ret = v4l2_subdev_link_validate(link);
1972	if (ret)
1973		return ret;
1974
1975	return isc_validate(isc);
1976}
1977
1978static const struct media_entity_operations isc_entity_operations = {
1979	.link_validate = isc_link_validate,
1980};
1981
1982int isc_mc_init(struct isc_device *isc, u32 ver)
1983{
1984	const struct of_device_id *match;
1985	int ret;
1986
1987	isc->video_dev.entity.function = MEDIA_ENT_F_IO_V4L;
1988	isc->video_dev.entity.flags = MEDIA_ENT_FL_DEFAULT;
1989	isc->video_dev.entity.ops = &isc_entity_operations;
1990
1991	isc->pads[ISC_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1992
1993	ret = media_entity_pads_init(&isc->video_dev.entity, ISC_PADS_NUM,
1994				     isc->pads);
1995	if (ret < 0) {
1996		dev_err(isc->dev, "media entity init failed\n");
1997		return ret;
1998	}
1999
2000	isc->mdev.dev = isc->dev;
2001
2002	match = of_match_node(isc->dev->driver->of_match_table,
2003			      isc->dev->of_node);
2004
2005	strscpy(isc->mdev.driver_name, KBUILD_MODNAME,
2006		sizeof(isc->mdev.driver_name));
2007	strscpy(isc->mdev.model, match->compatible, sizeof(isc->mdev.model));
2008	snprintf(isc->mdev.bus_info, sizeof(isc->mdev.bus_info), "platform:%s",
2009		 isc->v4l2_dev.name);
2010	isc->mdev.hw_revision = ver;
2011
2012	media_device_init(&isc->mdev);
2013
2014	isc->v4l2_dev.mdev = &isc->mdev;
2015
2016	return isc_scaler_init(isc);
2017}
2018EXPORT_SYMBOL_GPL(isc_mc_init);
2019
2020void isc_mc_cleanup(struct isc_device *isc)
2021{
2022	media_entity_cleanup(&isc->video_dev.entity);
2023	media_device_cleanup(&isc->mdev);
2024}
2025EXPORT_SYMBOL_GPL(isc_mc_cleanup);
2026
2027/* regmap configuration */
2028#define MICROCHIP_ISC_REG_MAX    0xd5c
2029const struct regmap_config microchip_isc_regmap_config = {
2030	.reg_bits       = 32,
2031	.reg_stride     = 4,
2032	.val_bits       = 32,
2033	.max_register	= MICROCHIP_ISC_REG_MAX,
2034};
2035EXPORT_SYMBOL_GPL(microchip_isc_regmap_config);
2036
2037MODULE_AUTHOR("Songjun Wu");
2038MODULE_AUTHOR("Eugen Hristev");
2039MODULE_DESCRIPTION("Microchip ISC common code base");
2040MODULE_LICENSE("GPL v2");