1// SPDX-License-Identifier: GPL-2.0-only OR MIT
  2/*
  3 * Apple mailbox driver
  4 *
  5 * Copyright (C) 2021 The Asahi Linux Contributors
  6 *
  7 * This driver adds support for two mailbox variants (called ASC and M3 by
  8 * Apple) found in Apple SoCs such as the M1. It consists of two FIFOs used to
  9 * exchange 64+32 bit messages between the main CPU and a co-processor.
 10 * Various coprocessors implement different IPC protocols based on these simple
 11 * messages and shared memory buffers.
 12 *
 13 * Both the main CPU and the co-processor see the same set of registers but
 14 * the first FIFO (A2I) is always used to transfer messages from the application
 15 * processor (us) to the I/O processor and the second one (I2A) for the
 16 * other direction.
 17 */
 18
 19#include <linux/apple-mailbox.h>
 20#include <linux/delay.h>
 21#include <linux/device.h>
 22#include <linux/gfp.h>
 23#include <linux/interrupt.h>
 24#include <linux/io.h>
 25#include <linux/mailbox_controller.h>
 26#include <linux/module.h>
 27#include <linux/of.h>
 28#include <linux/platform_device.h>
 29#include <linux/spinlock.h>
 30#include <linux/types.h>
 31
 32#define APPLE_ASC_MBOX_CONTROL_FULL  BIT(16)
 33#define APPLE_ASC_MBOX_CONTROL_EMPTY BIT(17)
 34
 35#define APPLE_ASC_MBOX_A2I_CONTROL 0x110
 36#define APPLE_ASC_MBOX_A2I_SEND0   0x800
 37#define APPLE_ASC_MBOX_A2I_SEND1   0x808
 38#define APPLE_ASC_MBOX_A2I_RECV0   0x810
 39#define APPLE_ASC_MBOX_A2I_RECV1   0x818
 40
 41#define APPLE_ASC_MBOX_I2A_CONTROL 0x114
 42#define APPLE_ASC_MBOX_I2A_SEND0   0x820
 43#define APPLE_ASC_MBOX_I2A_SEND1   0x828
 44#define APPLE_ASC_MBOX_I2A_RECV0   0x830
 45#define APPLE_ASC_MBOX_I2A_RECV1   0x838
 46
 47#define APPLE_M3_MBOX_CONTROL_FULL  BIT(16)
 48#define APPLE_M3_MBOX_CONTROL_EMPTY BIT(17)
 49
 50#define APPLE_M3_MBOX_A2I_CONTROL 0x50
 51#define APPLE_M3_MBOX_A2I_SEND0	  0x60
 52#define APPLE_M3_MBOX_A2I_SEND1	  0x68
 53#define APPLE_M3_MBOX_A2I_RECV0	  0x70
 54#define APPLE_M3_MBOX_A2I_RECV1	  0x78
 55
 56#define APPLE_M3_MBOX_I2A_CONTROL 0x80
 57#define APPLE_M3_MBOX_I2A_SEND0	  0x90
 58#define APPLE_M3_MBOX_I2A_SEND1	  0x98
 59#define APPLE_M3_MBOX_I2A_RECV0	  0xa0
 60#define APPLE_M3_MBOX_I2A_RECV1	  0xa8
 61
 62#define APPLE_M3_MBOX_IRQ_ENABLE	0x48
 63#define APPLE_M3_MBOX_IRQ_ACK		0x4c
 64#define APPLE_M3_MBOX_IRQ_A2I_EMPTY	BIT(0)
 65#define APPLE_M3_MBOX_IRQ_A2I_NOT_EMPTY BIT(1)
 66#define APPLE_M3_MBOX_IRQ_I2A_EMPTY	BIT(2)
 67#define APPLE_M3_MBOX_IRQ_I2A_NOT_EMPTY BIT(3)
 68
 69#define APPLE_MBOX_MSG1_OUTCNT GENMASK(56, 52)
 70#define APPLE_MBOX_MSG1_INCNT  GENMASK(51, 48)
 71#define APPLE_MBOX_MSG1_OUTPTR GENMASK(47, 44)
 72#define APPLE_MBOX_MSG1_INPTR  GENMASK(43, 40)
 73#define APPLE_MBOX_MSG1_MSG    GENMASK(31, 0)
 74
 75struct apple_mbox_hw {
 76	unsigned int control_full;
 77	unsigned int control_empty;
 78
 79	unsigned int a2i_control;
 80	unsigned int a2i_send0;
 81	unsigned int a2i_send1;
 82
 83	unsigned int i2a_control;
 84	unsigned int i2a_recv0;
 85	unsigned int i2a_recv1;
 86
 87	bool has_irq_controls;
 88	unsigned int irq_enable;
 89	unsigned int irq_ack;
 90	unsigned int irq_bit_recv_not_empty;
 91	unsigned int irq_bit_send_empty;
 92};
 93
 94struct apple_mbox {
 95	void __iomem *regs;
 96	const struct apple_mbox_hw *hw;
 97
 98	int irq_recv_not_empty;
 99	int irq_send_empty;
100
101	struct mbox_chan chan;
102
103	struct device *dev;
104	struct mbox_controller controller;
105	spinlock_t rx_lock;
106};
107
108static const struct of_device_id apple_mbox_of_match[];
109
110static bool apple_mbox_hw_can_send(struct apple_mbox *apple_mbox)
111{
112	u32 mbox_ctrl =
113		readl_relaxed(apple_mbox->regs + apple_mbox->hw->a2i_control);
114
115	return !(mbox_ctrl & apple_mbox->hw->control_full);
116}
117
118static bool apple_mbox_hw_send_empty(struct apple_mbox *apple_mbox)
119{
120	u32 mbox_ctrl =
121		readl_relaxed(apple_mbox->regs + apple_mbox->hw->a2i_control);
122
123	return mbox_ctrl & apple_mbox->hw->control_empty;
124}
125
126static int apple_mbox_hw_send(struct apple_mbox *apple_mbox,
127			      struct apple_mbox_msg *msg)
128{
129	if (!apple_mbox_hw_can_send(apple_mbox))
130		return -EBUSY;
131
132	dev_dbg(apple_mbox->dev, "> TX %016llx %08x\n", msg->msg0, msg->msg1);
133
134	writeq_relaxed(msg->msg0, apple_mbox->regs + apple_mbox->hw->a2i_send0);
135	writeq_relaxed(FIELD_PREP(APPLE_MBOX_MSG1_MSG, msg->msg1),
136		       apple_mbox->regs + apple_mbox->hw->a2i_send1);
137
138	return 0;
139}
140
141static bool apple_mbox_hw_can_recv(struct apple_mbox *apple_mbox)
142{
143	u32 mbox_ctrl =
144		readl_relaxed(apple_mbox->regs + apple_mbox->hw->i2a_control);
145
146	return !(mbox_ctrl & apple_mbox->hw->control_empty);
147}
148
149static int apple_mbox_hw_recv(struct apple_mbox *apple_mbox,
150			      struct apple_mbox_msg *msg)
151{
152	if (!apple_mbox_hw_can_recv(apple_mbox))
153		return -ENOMSG;
154
155	msg->msg0 = readq_relaxed(apple_mbox->regs + apple_mbox->hw->i2a_recv0);
156	msg->msg1 = FIELD_GET(
157		APPLE_MBOX_MSG1_MSG,
158		readq_relaxed(apple_mbox->regs + apple_mbox->hw->i2a_recv1));
159
160	dev_dbg(apple_mbox->dev, "< RX %016llx %08x\n", msg->msg0, msg->msg1);
161
162	return 0;
163}
164
165static int apple_mbox_chan_send_data(struct mbox_chan *chan, void *data)
166{
167	struct apple_mbox *apple_mbox = chan->con_priv;
168	struct apple_mbox_msg *msg = data;
169	int ret;
170
171	ret = apple_mbox_hw_send(apple_mbox, msg);
172	if (ret)
173		return ret;
174
175	/*
176	 * The interrupt is level triggered and will keep firing as long as the
177	 * FIFO is empty. It will also keep firing if the FIFO was empty
178	 * at any point in the past until it has been acknowledged at the
179	 * mailbox level. By acknowledging it here we can ensure that we will
180	 * only get the interrupt once the FIFO has been cleared again.
181	 * If the FIFO is already empty before the ack it will fire again
182	 * immediately after the ack.
183	 */
184	if (apple_mbox->hw->has_irq_controls) {
185		writel_relaxed(apple_mbox->hw->irq_bit_send_empty,
186			       apple_mbox->regs + apple_mbox->hw->irq_ack);
187	}
188	enable_irq(apple_mbox->irq_send_empty);
189
190	return 0;
191}
192
193static irqreturn_t apple_mbox_send_empty_irq(int irq, void *data)
194{
195	struct apple_mbox *apple_mbox = data;
196
197	/*
198	 * We don't need to acknowledge the interrupt at the mailbox level
199	 * here even if supported by the hardware. It will keep firing but that
200	 * doesn't matter since it's disabled at the main interrupt controller.
201	 * apple_mbox_chan_send_data will acknowledge it before enabling
202	 * it at the main controller again.
203	 */
204	disable_irq_nosync(apple_mbox->irq_send_empty);
205	mbox_chan_txdone(&apple_mbox->chan, 0);
206	return IRQ_HANDLED;
207}
208
209static int apple_mbox_poll(struct apple_mbox *apple_mbox)
210{
211	struct apple_mbox_msg msg;
212	int ret = 0;
213
214	while (apple_mbox_hw_recv(apple_mbox, &msg) == 0) {
215		mbox_chan_received_data(&apple_mbox->chan, (void *)&msg);
216		ret++;
217	}
218
219	/*
220	 * The interrupt will keep firing even if there are no more messages
221	 * unless we also acknowledge it at the mailbox level here.
222	 * There's no race if a message comes in between the check in the while
223	 * loop above and the ack below: If a new messages arrives inbetween
224	 * those two the interrupt will just fire again immediately after the
225	 * ack since it's level triggered.
226	 */
227	if (apple_mbox->hw->has_irq_controls) {
228		writel_relaxed(apple_mbox->hw->irq_bit_recv_not_empty,
229			       apple_mbox->regs + apple_mbox->hw->irq_ack);
230	}
231
232	return ret;
233}
234
235static irqreturn_t apple_mbox_recv_irq(int irq, void *data)
236{
237	struct apple_mbox *apple_mbox = data;
238
239	spin_lock(&apple_mbox->rx_lock);
240	apple_mbox_poll(apple_mbox);
241	spin_unlock(&apple_mbox->rx_lock);
242
243	return IRQ_HANDLED;
244}
245
246static bool apple_mbox_chan_peek_data(struct mbox_chan *chan)
247{
248	struct apple_mbox *apple_mbox = chan->con_priv;
249	unsigned long flags;
250	int ret;
251
252	spin_lock_irqsave(&apple_mbox->rx_lock, flags);
253	ret = apple_mbox_poll(apple_mbox);
254	spin_unlock_irqrestore(&apple_mbox->rx_lock, flags);
255
256	return ret > 0;
257}
258
259static int apple_mbox_chan_flush(struct mbox_chan *chan, unsigned long timeout)
260{
261	struct apple_mbox *apple_mbox = chan->con_priv;
262	unsigned long deadline = jiffies + msecs_to_jiffies(timeout);
263
264	while (time_before(jiffies, deadline)) {
265		if (apple_mbox_hw_send_empty(apple_mbox)) {
266			mbox_chan_txdone(&apple_mbox->chan, 0);
267			return 0;
268		}
269
270		udelay(1);
271	}
272
273	return -ETIME;
274}
275
276static int apple_mbox_chan_startup(struct mbox_chan *chan)
277{
278	struct apple_mbox *apple_mbox = chan->con_priv;
279
280	/*
281	 * Only some variants of this mailbox HW provide interrupt control
282	 * at the mailbox level. We therefore need to handle enabling/disabling
283	 * interrupts at the main interrupt controller anyway for hardware that
284	 * doesn't. Just always keep the interrupts we care about enabled at
285	 * the mailbox level so that both hardware revisions behave almost
286	 * the same.
287	 */
288	if (apple_mbox->hw->has_irq_controls) {
289		writel_relaxed(apple_mbox->hw->irq_bit_recv_not_empty |
290				       apple_mbox->hw->irq_bit_send_empty,
291			       apple_mbox->regs + apple_mbox->hw->irq_enable);
292	}
293
294	enable_irq(apple_mbox->irq_recv_not_empty);
295	return 0;
296}
297
298static void apple_mbox_chan_shutdown(struct mbox_chan *chan)
299{
300	struct apple_mbox *apple_mbox = chan->con_priv;
301
302	disable_irq(apple_mbox->irq_recv_not_empty);
303}
304
305static const struct mbox_chan_ops apple_mbox_ops = {
306	.send_data = apple_mbox_chan_send_data,
307	.peek_data = apple_mbox_chan_peek_data,
308	.flush = apple_mbox_chan_flush,
309	.startup = apple_mbox_chan_startup,
310	.shutdown = apple_mbox_chan_shutdown,
311};
312
313static struct mbox_chan *apple_mbox_of_xlate(struct mbox_controller *mbox,
314					     const struct of_phandle_args *args)
315{
316	if (args->args_count != 0)
317		return ERR_PTR(-EINVAL);
318
319	return &mbox->chans[0];
320}
321
322static int apple_mbox_probe(struct platform_device *pdev)
323{
324	int ret;
325	const struct of_device_id *match;
326	char *irqname;
327	struct apple_mbox *mbox;
328	struct device *dev = &pdev->dev;
329
330	match = of_match_node(apple_mbox_of_match, pdev->dev.of_node);
331	if (!match)
332		return -EINVAL;
333	if (!match->data)
334		return -EINVAL;
335
336	mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
337	if (!mbox)
338		return -ENOMEM;
339	platform_set_drvdata(pdev, mbox);
340
341	mbox->dev = dev;
342	mbox->regs = devm_platform_ioremap_resource(pdev, 0);
343	if (IS_ERR(mbox->regs))
344		return PTR_ERR(mbox->regs);
345
346	mbox->hw = match->data;
347	mbox->irq_recv_not_empty =
348		platform_get_irq_byname(pdev, "recv-not-empty");
349	if (mbox->irq_recv_not_empty < 0)
350		return -ENODEV;
351
352	mbox->irq_send_empty = platform_get_irq_byname(pdev, "send-empty");
353	if (mbox->irq_send_empty < 0)
354		return -ENODEV;
355
356	mbox->controller.dev = mbox->dev;
357	mbox->controller.num_chans = 1;
358	mbox->controller.chans = &mbox->chan;
359	mbox->controller.ops = &apple_mbox_ops;
360	mbox->controller.txdone_irq = true;
361	mbox->controller.of_xlate = apple_mbox_of_xlate;
362	mbox->chan.con_priv = mbox;
363	spin_lock_init(&mbox->rx_lock);
364
365	irqname = devm_kasprintf(dev, GFP_KERNEL, "%s-recv", dev_name(dev));
366	if (!irqname)
367		return -ENOMEM;
368
369	ret = devm_request_threaded_irq(dev, mbox->irq_recv_not_empty, NULL,
370					apple_mbox_recv_irq,
371					IRQF_NO_AUTOEN | IRQF_ONESHOT, irqname,
372					mbox);
373	if (ret)
374		return ret;
375
376	irqname = devm_kasprintf(dev, GFP_KERNEL, "%s-send", dev_name(dev));
377	if (!irqname)
378		return -ENOMEM;
379
380	ret = devm_request_irq(dev, mbox->irq_send_empty,
381			       apple_mbox_send_empty_irq, IRQF_NO_AUTOEN,
382			       irqname, mbox);
383	if (ret)
384		return ret;
385
386	return devm_mbox_controller_register(dev, &mbox->controller);
387}
388
389static const struct apple_mbox_hw apple_mbox_asc_hw = {
390	.control_full = APPLE_ASC_MBOX_CONTROL_FULL,
391	.control_empty = APPLE_ASC_MBOX_CONTROL_EMPTY,
392
393	.a2i_control = APPLE_ASC_MBOX_A2I_CONTROL,
394	.a2i_send0 = APPLE_ASC_MBOX_A2I_SEND0,
395	.a2i_send1 = APPLE_ASC_MBOX_A2I_SEND1,
396
397	.i2a_control = APPLE_ASC_MBOX_I2A_CONTROL,
398	.i2a_recv0 = APPLE_ASC_MBOX_I2A_RECV0,
399	.i2a_recv1 = APPLE_ASC_MBOX_I2A_RECV1,
400
401	.has_irq_controls = false,
402};
403
404static const struct apple_mbox_hw apple_mbox_m3_hw = {
405	.control_full = APPLE_M3_MBOX_CONTROL_FULL,
406	.control_empty = APPLE_M3_MBOX_CONTROL_EMPTY,
407
408	.a2i_control = APPLE_M3_MBOX_A2I_CONTROL,
409	.a2i_send0 = APPLE_M3_MBOX_A2I_SEND0,
410	.a2i_send1 = APPLE_M3_MBOX_A2I_SEND1,
411
412	.i2a_control = APPLE_M3_MBOX_I2A_CONTROL,
413	.i2a_recv0 = APPLE_M3_MBOX_I2A_RECV0,
414	.i2a_recv1 = APPLE_M3_MBOX_I2A_RECV1,
415
416	.has_irq_controls = true,
417	.irq_enable = APPLE_M3_MBOX_IRQ_ENABLE,
418	.irq_ack = APPLE_M3_MBOX_IRQ_ACK,
419	.irq_bit_recv_not_empty = APPLE_M3_MBOX_IRQ_I2A_NOT_EMPTY,
420	.irq_bit_send_empty = APPLE_M3_MBOX_IRQ_A2I_EMPTY,
421};
422
423static const struct of_device_id apple_mbox_of_match[] = {
424	{ .compatible = "apple,asc-mailbox-v4", .data = &apple_mbox_asc_hw },
425	{ .compatible = "apple,m3-mailbox-v2", .data = &apple_mbox_m3_hw },
426	{}
427};
428MODULE_DEVICE_TABLE(of, apple_mbox_of_match);
429
430static struct platform_driver apple_mbox_driver = {
431	.driver = {
432		.name = "apple-mailbox",
433		.of_match_table = apple_mbox_of_match,
434	},
435	.probe = apple_mbox_probe,
436};
437module_platform_driver(apple_mbox_driver);
438
439MODULE_LICENSE("Dual MIT/GPL");
440MODULE_AUTHOR("Sven Peter <sven@svenpeter.dev>");
441MODULE_DESCRIPTION("Apple Mailbox driver");