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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Intel(R) Trace Hub Memory Storage Unit (MSU) data structures
4 *
5 * Copyright (C) 2014-2015 Intel Corporation.
6 */
7
8#ifndef __INTEL_TH_MSU_H__
9#define __INTEL_TH_MSU_H__
10
11enum {
12 REG_MSU_MSUPARAMS = 0x0000,
13 REG_MSU_MSUSTS = 0x0008,
14 REG_MSU_MINTCTL = 0x0004, /* MSU-global interrupt control */
15 REG_MSU_MSC0CTL = 0x0100, /* MSC0 control */
16 REG_MSU_MSC0STS = 0x0104, /* MSC0 status */
17 REG_MSU_MSC0BAR = 0x0108, /* MSC0 output base address */
18 REG_MSU_MSC0SIZE = 0x010c, /* MSC0 output size */
19 REG_MSU_MSC0MWP = 0x0110, /* MSC0 write pointer */
20 REG_MSU_MSC0NWSA = 0x011c, /* MSC0 next window start address */
21
22 REG_MSU_MSC1CTL = 0x0200, /* MSC1 control */
23 REG_MSU_MSC1STS = 0x0204, /* MSC1 status */
24 REG_MSU_MSC1BAR = 0x0208, /* MSC1 output base address */
25 REG_MSU_MSC1SIZE = 0x020c, /* MSC1 output size */
26 REG_MSU_MSC1MWP = 0x0210, /* MSC1 write pointer */
27 REG_MSU_MSC1NWSA = 0x021c, /* MSC1 next window start address */
28};
29
30/* MSUSTS bits */
31#define MSUSTS_MSU_INT BIT(0)
32#define MSUSTS_MSC0BLAST BIT(16)
33#define MSUSTS_MSC1BLAST BIT(24)
34
35/* MSCnCTL bits */
36#define MSC_EN BIT(0)
37#define MSC_WRAPEN BIT(1)
38#define MSC_RD_HDR_OVRD BIT(2)
39#define MSC_MODE (BIT(4) | BIT(5))
40#define MSC_LEN (BIT(8) | BIT(9) | BIT(10))
41
42/* MINTCTL bits */
43#define MICDE BIT(0)
44#define M0BLIE BIT(16)
45#define M1BLIE BIT(24)
46
47/* MSCnSTS bits */
48#define MSCSTS_WRAPSTAT BIT(1) /* Wrap occurred */
49#define MSCSTS_PLE BIT(2) /* Pipeline Empty */
50
51/*
52 * Multiblock/multiwindow block descriptor
53 */
54struct msc_block_desc {
55 u32 sw_tag;
56 u32 block_sz;
57 u32 next_blk;
58 u32 next_win;
59 u32 res0[4];
60 u32 hw_tag;
61 u32 valid_dw;
62 u32 ts_low;
63 u32 ts_high;
64 u32 res1[4];
65} __packed;
66
67#define MSC_BDESC sizeof(struct msc_block_desc)
68#define DATA_IN_PAGE (PAGE_SIZE - MSC_BDESC)
69
70/* MSC multiblock sw tag bits */
71#define MSC_SW_TAG_LASTBLK BIT(0)
72#define MSC_SW_TAG_LASTWIN BIT(1)
73
74/* MSC multiblock hw tag bits */
75#define MSC_HW_TAG_TRIGGER BIT(0)
76#define MSC_HW_TAG_BLOCKWRAP BIT(1)
77#define MSC_HW_TAG_WINWRAP BIT(2)
78#define MSC_HW_TAG_ENDBIT BIT(3)
79
80static inline unsigned long msc_data_sz(struct msc_block_desc *bdesc)
81{
82 if (!bdesc->valid_dw)
83 return 0;
84
85 return bdesc->valid_dw * 4 - MSC_BDESC;
86}
87
88static inline unsigned long msc_total_sz(struct msc_block_desc *bdesc)
89{
90 return bdesc->valid_dw * 4;
91}
92
93static inline unsigned long msc_block_sz(struct msc_block_desc *bdesc)
94{
95 return bdesc->block_sz * 64 - MSC_BDESC;
96}
97
98static inline bool msc_block_wrapped(struct msc_block_desc *bdesc)
99{
100 if (bdesc->hw_tag & (MSC_HW_TAG_BLOCKWRAP | MSC_HW_TAG_WINWRAP))
101 return true;
102
103 return false;
104}
105
106static inline bool msc_block_last_written(struct msc_block_desc *bdesc)
107{
108 if ((bdesc->hw_tag & MSC_HW_TAG_ENDBIT) ||
109 (msc_data_sz(bdesc) != msc_block_sz(bdesc)))
110 return true;
111
112 return false;
113}
114
115/* waiting for Pipeline Empty bit(s) to assert for MSC */
116#define MSC_PLE_WAITLOOP_DEPTH 10000
117
118#endif /* __INTEL_TH_MSU_H__ */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Intel(R) Trace Hub Memory Storage Unit (MSU) data structures
4 *
5 * Copyright (C) 2014-2015 Intel Corporation.
6 */
7
8#ifndef __INTEL_TH_MSU_H__
9#define __INTEL_TH_MSU_H__
10
11enum {
12 REG_MSU_MSUPARAMS = 0x0000,
13 REG_MSU_MSUSTS = 0x0008,
14 REG_MSU_MINTCTL = 0x0004, /* MSU-global interrupt control */
15 REG_MSU_MSC0CTL = 0x0100, /* MSC0 control */
16 REG_MSU_MSC0STS = 0x0104, /* MSC0 status */
17 REG_MSU_MSC0BAR = 0x0108, /* MSC0 output base address */
18 REG_MSU_MSC0SIZE = 0x010c, /* MSC0 output size */
19 REG_MSU_MSC0MWP = 0x0110, /* MSC0 write pointer */
20 REG_MSU_MSC0NWSA = 0x011c, /* MSC0 next window start address */
21
22 REG_MSU_MSC1CTL = 0x0200, /* MSC1 control */
23 REG_MSU_MSC1STS = 0x0204, /* MSC1 status */
24 REG_MSU_MSC1BAR = 0x0208, /* MSC1 output base address */
25 REG_MSU_MSC1SIZE = 0x020c, /* MSC1 output size */
26 REG_MSU_MSC1MWP = 0x0210, /* MSC1 write pointer */
27 REG_MSU_MSC1NWSA = 0x021c, /* MSC1 next window start address */
28};
29
30/* MSUSTS bits */
31#define MSUSTS_MSU_INT BIT(0)
32#define MSUSTS_MSC0BLAST BIT(16)
33#define MSUSTS_MSC1BLAST BIT(24)
34
35/* MSCnCTL bits */
36#define MSC_EN BIT(0)
37#define MSC_WRAPEN BIT(1)
38#define MSC_RD_HDR_OVRD BIT(2)
39#define MSC_MODE (BIT(4) | BIT(5))
40#define MSC_LEN (BIT(8) | BIT(9) | BIT(10))
41
42/* MINTCTL bits */
43#define MICDE BIT(0)
44#define M0BLIE BIT(16)
45#define M1BLIE BIT(24)
46
47/* MSCnSTS bits */
48#define MSCSTS_WRAPSTAT BIT(1) /* Wrap occurred */
49#define MSCSTS_PLE BIT(2) /* Pipeline Empty */
50
51/*
52 * Multiblock/multiwindow block descriptor
53 */
54struct msc_block_desc {
55 u32 sw_tag;
56 u32 block_sz;
57 u32 next_blk;
58 u32 next_win;
59 u32 res0[4];
60 u32 hw_tag;
61 u32 valid_dw;
62 u32 ts_low;
63 u32 ts_high;
64 u32 res1[4];
65} __packed;
66
67#define MSC_BDESC sizeof(struct msc_block_desc)
68#define DATA_IN_PAGE (PAGE_SIZE - MSC_BDESC)
69
70/* MSC multiblock sw tag bits */
71#define MSC_SW_TAG_LASTBLK BIT(0)
72#define MSC_SW_TAG_LASTWIN BIT(1)
73
74/* MSC multiblock hw tag bits */
75#define MSC_HW_TAG_TRIGGER BIT(0)
76#define MSC_HW_TAG_BLOCKWRAP BIT(1)
77#define MSC_HW_TAG_WINWRAP BIT(2)
78#define MSC_HW_TAG_ENDBIT BIT(3)
79
80static inline unsigned long msc_data_sz(struct msc_block_desc *bdesc)
81{
82 if (!bdesc->valid_dw)
83 return 0;
84
85 return bdesc->valid_dw * 4 - MSC_BDESC;
86}
87
88static inline unsigned long msc_total_sz(struct msc_block_desc *bdesc)
89{
90 return bdesc->valid_dw * 4;
91}
92
93static inline unsigned long msc_block_sz(struct msc_block_desc *bdesc)
94{
95 return bdesc->block_sz * 64 - MSC_BDESC;
96}
97
98static inline bool msc_block_wrapped(struct msc_block_desc *bdesc)
99{
100 if (bdesc->hw_tag & (MSC_HW_TAG_BLOCKWRAP | MSC_HW_TAG_WINWRAP))
101 return true;
102
103 return false;
104}
105
106static inline bool msc_block_last_written(struct msc_block_desc *bdesc)
107{
108 if ((bdesc->hw_tag & MSC_HW_TAG_ENDBIT) ||
109 (msc_data_sz(bdesc) != msc_block_sz(bdesc)))
110 return true;
111
112 return false;
113}
114
115/* waiting for Pipeline Empty bit(s) to assert for MSC */
116#define MSC_PLE_WAITLOOP_DEPTH 10000
117
118#endif /* __INTEL_TH_MSU_H__ */