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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * DMA driver for Xilinx Video DMA Engine
4 *
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
6 *
7 * Based on the Freescale DMA driver.
8 *
9 * Description:
10 * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP
11 * core that provides high-bandwidth direct memory access between memory
12 * and AXI4-Stream type video target peripherals. The core provides efficient
13 * two dimensional DMA operations with independent asynchronous read (S2MM)
14 * and write (MM2S) channel operation. It can be configured to have either
15 * one channel or two channels. If configured as two channels, one is to
16 * transmit to the video device (MM2S) and another is to receive from the
17 * video device (S2MM). Initialization, status, interrupt and management
18 * registers are accessed through an AXI4-Lite slave interface.
19 *
20 * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that
21 * provides high-bandwidth one dimensional direct memory access between memory
22 * and AXI4-Stream target peripherals. It supports one receive and one
23 * transmit channel, both of them optional at synthesis time.
24 *
25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
26 * Access (DMA) between a memory-mapped source address and a memory-mapped
27 * destination address.
28 *
29 * The AXI Multichannel Direct Memory Access (AXI MCDMA) core is a soft
30 * Xilinx IP that provides high-bandwidth direct memory access between
31 * memory and AXI4-Stream target peripherals. It provides scatter gather
32 * (SG) interface with multiple channels independent configuration support.
33 *
34 */
35
36#include <linux/bitops.h>
37#include <linux/dmapool.h>
38#include <linux/dma/xilinx_dma.h>
39#include <linux/init.h>
40#include <linux/interrupt.h>
41#include <linux/io.h>
42#include <linux/iopoll.h>
43#include <linux/module.h>
44#include <linux/of_address.h>
45#include <linux/of_dma.h>
46#include <linux/of_platform.h>
47#include <linux/of_irq.h>
48#include <linux/slab.h>
49#include <linux/clk.h>
50#include <linux/io-64-nonatomic-lo-hi.h>
51
52#include "../dmaengine.h"
53
54/* Register/Descriptor Offsets */
55#define XILINX_DMA_MM2S_CTRL_OFFSET 0x0000
56#define XILINX_DMA_S2MM_CTRL_OFFSET 0x0030
57#define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050
58#define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0
59
60/* Control Registers */
61#define XILINX_DMA_REG_DMACR 0x0000
62#define XILINX_DMA_DMACR_DELAY_MAX 0xff
63#define XILINX_DMA_DMACR_DELAY_SHIFT 24
64#define XILINX_DMA_DMACR_FRAME_COUNT_MAX 0xff
65#define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT 16
66#define XILINX_DMA_DMACR_ERR_IRQ BIT(14)
67#define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13)
68#define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12)
69#define XILINX_DMA_DMACR_MASTER_SHIFT 8
70#define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5
71#define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4)
72#define XILINX_DMA_DMACR_GENLOCK_EN BIT(3)
73#define XILINX_DMA_DMACR_RESET BIT(2)
74#define XILINX_DMA_DMACR_CIRC_EN BIT(1)
75#define XILINX_DMA_DMACR_RUNSTOP BIT(0)
76#define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5)
77#define XILINX_DMA_DMACR_DELAY_MASK GENMASK(31, 24)
78#define XILINX_DMA_DMACR_FRAME_COUNT_MASK GENMASK(23, 16)
79#define XILINX_DMA_DMACR_MASTER_MASK GENMASK(11, 8)
80
81#define XILINX_DMA_REG_DMASR 0x0004
82#define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15)
83#define XILINX_DMA_DMASR_ERR_IRQ BIT(14)
84#define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13)
85#define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12)
86#define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11)
87#define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10)
88#define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9)
89#define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8)
90#define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7)
91#define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6)
92#define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5)
93#define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4)
94#define XILINX_DMA_DMASR_SG_MASK BIT(3)
95#define XILINX_DMA_DMASR_IDLE BIT(1)
96#define XILINX_DMA_DMASR_HALTED BIT(0)
97#define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24)
98#define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16)
99
100#define XILINX_DMA_REG_CURDESC 0x0008
101#define XILINX_DMA_REG_TAILDESC 0x0010
102#define XILINX_DMA_REG_REG_INDEX 0x0014
103#define XILINX_DMA_REG_FRMSTORE 0x0018
104#define XILINX_DMA_REG_THRESHOLD 0x001c
105#define XILINX_DMA_REG_FRMPTR_STS 0x0024
106#define XILINX_DMA_REG_PARK_PTR 0x0028
107#define XILINX_DMA_PARK_PTR_WR_REF_SHIFT 8
108#define XILINX_DMA_PARK_PTR_WR_REF_MASK GENMASK(12, 8)
109#define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0
110#define XILINX_DMA_PARK_PTR_RD_REF_MASK GENMASK(4, 0)
111#define XILINX_DMA_REG_VDMA_VERSION 0x002c
112
113/* Register Direct Mode Registers */
114#define XILINX_DMA_REG_VSIZE 0x0000
115#define XILINX_DMA_REG_HSIZE 0x0004
116
117#define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008
118#define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24
119#define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT 0
120
121#define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n))
122#define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n))
123
124#define XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP 0x00ec
125#define XILINX_VDMA_ENABLE_VERTICAL_FLIP BIT(0)
126
127/* HW specific definitions */
128#define XILINX_MCDMA_MAX_CHANS_PER_DEVICE 0x20
129#define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x2
130#define XILINX_CDMA_MAX_CHANS_PER_DEVICE 0x1
131
132#define XILINX_DMA_DMAXR_ALL_IRQ_MASK \
133 (XILINX_DMA_DMASR_FRM_CNT_IRQ | \
134 XILINX_DMA_DMASR_DLY_CNT_IRQ | \
135 XILINX_DMA_DMASR_ERR_IRQ)
136
137#define XILINX_DMA_DMASR_ALL_ERR_MASK \
138 (XILINX_DMA_DMASR_EOL_LATE_ERR | \
139 XILINX_DMA_DMASR_SOF_LATE_ERR | \
140 XILINX_DMA_DMASR_SG_DEC_ERR | \
141 XILINX_DMA_DMASR_SG_SLV_ERR | \
142 XILINX_DMA_DMASR_EOF_EARLY_ERR | \
143 XILINX_DMA_DMASR_SOF_EARLY_ERR | \
144 XILINX_DMA_DMASR_DMA_DEC_ERR | \
145 XILINX_DMA_DMASR_DMA_SLAVE_ERR | \
146 XILINX_DMA_DMASR_DMA_INT_ERR)
147
148/*
149 * Recoverable errors are DMA Internal error, SOF Early, EOF Early
150 * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC
151 * is enabled in the h/w system.
152 */
153#define XILINX_DMA_DMASR_ERR_RECOVER_MASK \
154 (XILINX_DMA_DMASR_SOF_LATE_ERR | \
155 XILINX_DMA_DMASR_EOF_EARLY_ERR | \
156 XILINX_DMA_DMASR_SOF_EARLY_ERR | \
157 XILINX_DMA_DMASR_DMA_INT_ERR)
158
159/* Axi VDMA Flush on Fsync bits */
160#define XILINX_DMA_FLUSH_S2MM 3
161#define XILINX_DMA_FLUSH_MM2S 2
162#define XILINX_DMA_FLUSH_BOTH 1
163
164/* Delay loop counter to prevent hardware failure */
165#define XILINX_DMA_LOOP_COUNT 1000000
166
167/* AXI DMA Specific Registers/Offsets */
168#define XILINX_DMA_REG_SRCDSTADDR 0x18
169#define XILINX_DMA_REG_BTT 0x28
170
171/* AXI DMA Specific Masks/Bit fields */
172#define XILINX_DMA_MAX_TRANS_LEN_MIN 8
173#define XILINX_DMA_MAX_TRANS_LEN_MAX 23
174#define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26
175#define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16)
176#define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4)
177#define XILINX_DMA_CR_COALESCE_SHIFT 16
178#define XILINX_DMA_BD_SOP BIT(27)
179#define XILINX_DMA_BD_EOP BIT(26)
180#define XILINX_DMA_COALESCE_MAX 255
181#define XILINX_DMA_NUM_DESCS 255
182#define XILINX_DMA_NUM_APP_WORDS 5
183
184/* AXI CDMA Specific Registers/Offsets */
185#define XILINX_CDMA_REG_SRCADDR 0x18
186#define XILINX_CDMA_REG_DSTADDR 0x20
187
188/* AXI CDMA Specific Masks */
189#define XILINX_CDMA_CR_SGMODE BIT(3)
190
191#define xilinx_prep_dma_addr_t(addr) \
192 ((dma_addr_t)((u64)addr##_##msb << 32 | (addr)))
193
194/* AXI MCDMA Specific Registers/Offsets */
195#define XILINX_MCDMA_MM2S_CTRL_OFFSET 0x0000
196#define XILINX_MCDMA_S2MM_CTRL_OFFSET 0x0500
197#define XILINX_MCDMA_CHEN_OFFSET 0x0008
198#define XILINX_MCDMA_CH_ERR_OFFSET 0x0010
199#define XILINX_MCDMA_RXINT_SER_OFFSET 0x0020
200#define XILINX_MCDMA_TXINT_SER_OFFSET 0x0028
201#define XILINX_MCDMA_CHAN_CR_OFFSET(x) (0x40 + (x) * 0x40)
202#define XILINX_MCDMA_CHAN_SR_OFFSET(x) (0x44 + (x) * 0x40)
203#define XILINX_MCDMA_CHAN_CDESC_OFFSET(x) (0x48 + (x) * 0x40)
204#define XILINX_MCDMA_CHAN_TDESC_OFFSET(x) (0x50 + (x) * 0x40)
205
206/* AXI MCDMA Specific Masks/Shifts */
207#define XILINX_MCDMA_COALESCE_SHIFT 16
208#define XILINX_MCDMA_COALESCE_MAX 24
209#define XILINX_MCDMA_IRQ_ALL_MASK GENMASK(7, 5)
210#define XILINX_MCDMA_COALESCE_MASK GENMASK(23, 16)
211#define XILINX_MCDMA_CR_RUNSTOP_MASK BIT(0)
212#define XILINX_MCDMA_IRQ_IOC_MASK BIT(5)
213#define XILINX_MCDMA_IRQ_DELAY_MASK BIT(6)
214#define XILINX_MCDMA_IRQ_ERR_MASK BIT(7)
215#define XILINX_MCDMA_BD_EOP BIT(30)
216#define XILINX_MCDMA_BD_SOP BIT(31)
217
218/**
219 * struct xilinx_vdma_desc_hw - Hardware Descriptor
220 * @next_desc: Next Descriptor Pointer @0x00
221 * @pad1: Reserved @0x04
222 * @buf_addr: Buffer address @0x08
223 * @buf_addr_msb: MSB of Buffer address @0x0C
224 * @vsize: Vertical Size @0x10
225 * @hsize: Horizontal Size @0x14
226 * @stride: Number of bytes between the first
227 * pixels of each horizontal line @0x18
228 */
229struct xilinx_vdma_desc_hw {
230 u32 next_desc;
231 u32 pad1;
232 u32 buf_addr;
233 u32 buf_addr_msb;
234 u32 vsize;
235 u32 hsize;
236 u32 stride;
237} __aligned(64);
238
239/**
240 * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA
241 * @next_desc: Next Descriptor Pointer @0x00
242 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04
243 * @buf_addr: Buffer address @0x08
244 * @buf_addr_msb: MSB of Buffer address @0x0C
245 * @reserved1: Reserved @0x10
246 * @reserved2: Reserved @0x14
247 * @control: Control field @0x18
248 * @status: Status field @0x1C
249 * @app: APP Fields @0x20 - 0x30
250 */
251struct xilinx_axidma_desc_hw {
252 u32 next_desc;
253 u32 next_desc_msb;
254 u32 buf_addr;
255 u32 buf_addr_msb;
256 u32 reserved1;
257 u32 reserved2;
258 u32 control;
259 u32 status;
260 u32 app[XILINX_DMA_NUM_APP_WORDS];
261} __aligned(64);
262
263/**
264 * struct xilinx_aximcdma_desc_hw - Hardware Descriptor for AXI MCDMA
265 * @next_desc: Next Descriptor Pointer @0x00
266 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04
267 * @buf_addr: Buffer address @0x08
268 * @buf_addr_msb: MSB of Buffer address @0x0C
269 * @rsvd: Reserved field @0x10
270 * @control: Control Information field @0x14
271 * @status: Status field @0x18
272 * @sideband_status: Status of sideband signals @0x1C
273 * @app: APP Fields @0x20 - 0x30
274 */
275struct xilinx_aximcdma_desc_hw {
276 u32 next_desc;
277 u32 next_desc_msb;
278 u32 buf_addr;
279 u32 buf_addr_msb;
280 u32 rsvd;
281 u32 control;
282 u32 status;
283 u32 sideband_status;
284 u32 app[XILINX_DMA_NUM_APP_WORDS];
285} __aligned(64);
286
287/**
288 * struct xilinx_cdma_desc_hw - Hardware Descriptor
289 * @next_desc: Next Descriptor Pointer @0x00
290 * @next_desc_msb: Next Descriptor Pointer MSB @0x04
291 * @src_addr: Source address @0x08
292 * @src_addr_msb: Source address MSB @0x0C
293 * @dest_addr: Destination address @0x10
294 * @dest_addr_msb: Destination address MSB @0x14
295 * @control: Control field @0x18
296 * @status: Status field @0x1C
297 */
298struct xilinx_cdma_desc_hw {
299 u32 next_desc;
300 u32 next_desc_msb;
301 u32 src_addr;
302 u32 src_addr_msb;
303 u32 dest_addr;
304 u32 dest_addr_msb;
305 u32 control;
306 u32 status;
307} __aligned(64);
308
309/**
310 * struct xilinx_vdma_tx_segment - Descriptor segment
311 * @hw: Hardware descriptor
312 * @node: Node in the descriptor segments list
313 * @phys: Physical address of segment
314 */
315struct xilinx_vdma_tx_segment {
316 struct xilinx_vdma_desc_hw hw;
317 struct list_head node;
318 dma_addr_t phys;
319} __aligned(64);
320
321/**
322 * struct xilinx_axidma_tx_segment - Descriptor segment
323 * @hw: Hardware descriptor
324 * @node: Node in the descriptor segments list
325 * @phys: Physical address of segment
326 */
327struct xilinx_axidma_tx_segment {
328 struct xilinx_axidma_desc_hw hw;
329 struct list_head node;
330 dma_addr_t phys;
331} __aligned(64);
332
333/**
334 * struct xilinx_aximcdma_tx_segment - Descriptor segment
335 * @hw: Hardware descriptor
336 * @node: Node in the descriptor segments list
337 * @phys: Physical address of segment
338 */
339struct xilinx_aximcdma_tx_segment {
340 struct xilinx_aximcdma_desc_hw hw;
341 struct list_head node;
342 dma_addr_t phys;
343} __aligned(64);
344
345/**
346 * struct xilinx_cdma_tx_segment - Descriptor segment
347 * @hw: Hardware descriptor
348 * @node: Node in the descriptor segments list
349 * @phys: Physical address of segment
350 */
351struct xilinx_cdma_tx_segment {
352 struct xilinx_cdma_desc_hw hw;
353 struct list_head node;
354 dma_addr_t phys;
355} __aligned(64);
356
357/**
358 * struct xilinx_dma_tx_descriptor - Per Transaction structure
359 * @async_tx: Async transaction descriptor
360 * @segments: TX segments list
361 * @node: Node in the channel descriptors list
362 * @cyclic: Check for cyclic transfers.
363 * @err: Whether the descriptor has an error.
364 * @residue: Residue of the completed descriptor
365 */
366struct xilinx_dma_tx_descriptor {
367 struct dma_async_tx_descriptor async_tx;
368 struct list_head segments;
369 struct list_head node;
370 bool cyclic;
371 bool err;
372 u32 residue;
373};
374
375/**
376 * struct xilinx_dma_chan - Driver specific DMA channel structure
377 * @xdev: Driver specific device structure
378 * @ctrl_offset: Control registers offset
379 * @desc_offset: TX descriptor registers offset
380 * @lock: Descriptor operation lock
381 * @pending_list: Descriptors waiting
382 * @active_list: Descriptors ready to submit
383 * @done_list: Complete descriptors
384 * @free_seg_list: Free descriptors
385 * @common: DMA common channel
386 * @desc_pool: Descriptors pool
387 * @dev: The dma device
388 * @irq: Channel IRQ
389 * @id: Channel ID
390 * @direction: Transfer direction
391 * @num_frms: Number of frames
392 * @has_sg: Support scatter transfers
393 * @cyclic: Check for cyclic transfers.
394 * @genlock: Support genlock mode
395 * @err: Channel has errors
396 * @idle: Check for channel idle
397 * @terminating: Check for channel being synchronized by user
398 * @tasklet: Cleanup work after irq
399 * @config: Device configuration info
400 * @flush_on_fsync: Flush on Frame sync
401 * @desc_pendingcount: Descriptor pending count
402 * @ext_addr: Indicates 64 bit addressing is supported by dma channel
403 * @desc_submitcount: Descriptor h/w submitted count
404 * @seg_v: Statically allocated segments base
405 * @seg_mv: Statically allocated segments base for MCDMA
406 * @seg_p: Physical allocated segments base
407 * @cyclic_seg_v: Statically allocated segment base for cyclic transfers
408 * @cyclic_seg_p: Physical allocated segments base for cyclic dma
409 * @start_transfer: Differentiate b/w DMA IP's transfer
410 * @stop_transfer: Differentiate b/w DMA IP's quiesce
411 * @tdest: TDEST value for mcdma
412 * @has_vflip: S2MM vertical flip
413 */
414struct xilinx_dma_chan {
415 struct xilinx_dma_device *xdev;
416 u32 ctrl_offset;
417 u32 desc_offset;
418 spinlock_t lock;
419 struct list_head pending_list;
420 struct list_head active_list;
421 struct list_head done_list;
422 struct list_head free_seg_list;
423 struct dma_chan common;
424 struct dma_pool *desc_pool;
425 struct device *dev;
426 int irq;
427 int id;
428 enum dma_transfer_direction direction;
429 int num_frms;
430 bool has_sg;
431 bool cyclic;
432 bool genlock;
433 bool err;
434 bool idle;
435 bool terminating;
436 struct tasklet_struct tasklet;
437 struct xilinx_vdma_config config;
438 bool flush_on_fsync;
439 u32 desc_pendingcount;
440 bool ext_addr;
441 u32 desc_submitcount;
442 struct xilinx_axidma_tx_segment *seg_v;
443 struct xilinx_aximcdma_tx_segment *seg_mv;
444 dma_addr_t seg_p;
445 struct xilinx_axidma_tx_segment *cyclic_seg_v;
446 dma_addr_t cyclic_seg_p;
447 void (*start_transfer)(struct xilinx_dma_chan *chan);
448 int (*stop_transfer)(struct xilinx_dma_chan *chan);
449 u16 tdest;
450 bool has_vflip;
451};
452
453/**
454 * enum xdma_ip_type - DMA IP type.
455 *
456 * @XDMA_TYPE_AXIDMA: Axi dma ip.
457 * @XDMA_TYPE_CDMA: Axi cdma ip.
458 * @XDMA_TYPE_VDMA: Axi vdma ip.
459 * @XDMA_TYPE_AXIMCDMA: Axi MCDMA ip.
460 *
461 */
462enum xdma_ip_type {
463 XDMA_TYPE_AXIDMA = 0,
464 XDMA_TYPE_CDMA,
465 XDMA_TYPE_VDMA,
466 XDMA_TYPE_AXIMCDMA
467};
468
469struct xilinx_dma_config {
470 enum xdma_ip_type dmatype;
471 int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk,
472 struct clk **tx_clk, struct clk **txs_clk,
473 struct clk **rx_clk, struct clk **rxs_clk);
474 irqreturn_t (*irq_handler)(int irq, void *data);
475 const int max_channels;
476};
477
478/**
479 * struct xilinx_dma_device - DMA device structure
480 * @regs: I/O mapped base address
481 * @dev: Device Structure
482 * @common: DMA device structure
483 * @chan: Driver specific DMA channel
484 * @flush_on_fsync: Flush on frame sync
485 * @ext_addr: Indicates 64 bit addressing is supported by dma device
486 * @pdev: Platform device structure pointer
487 * @dma_config: DMA config structure
488 * @axi_clk: DMA Axi4-lite interace clock
489 * @tx_clk: DMA mm2s clock
490 * @txs_clk: DMA mm2s stream clock
491 * @rx_clk: DMA s2mm clock
492 * @rxs_clk: DMA s2mm stream clock
493 * @s2mm_chan_id: DMA s2mm channel identifier
494 * @mm2s_chan_id: DMA mm2s channel identifier
495 * @max_buffer_len: Max buffer length
496 */
497struct xilinx_dma_device {
498 void __iomem *regs;
499 struct device *dev;
500 struct dma_device common;
501 struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE];
502 u32 flush_on_fsync;
503 bool ext_addr;
504 struct platform_device *pdev;
505 const struct xilinx_dma_config *dma_config;
506 struct clk *axi_clk;
507 struct clk *tx_clk;
508 struct clk *txs_clk;
509 struct clk *rx_clk;
510 struct clk *rxs_clk;
511 u32 s2mm_chan_id;
512 u32 mm2s_chan_id;
513 u32 max_buffer_len;
514};
515
516/* Macros */
517#define to_xilinx_chan(chan) \
518 container_of(chan, struct xilinx_dma_chan, common)
519#define to_dma_tx_descriptor(tx) \
520 container_of(tx, struct xilinx_dma_tx_descriptor, async_tx)
521#define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \
522 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
523 val, cond, delay_us, timeout_us)
524
525/* IO accessors */
526static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg)
527{
528 return ioread32(chan->xdev->regs + reg);
529}
530
531static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value)
532{
533 iowrite32(value, chan->xdev->regs + reg);
534}
535
536static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg,
537 u32 value)
538{
539 dma_write(chan, chan->desc_offset + reg, value);
540}
541
542static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg)
543{
544 return dma_read(chan, chan->ctrl_offset + reg);
545}
546
547static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,
548 u32 value)
549{
550 dma_write(chan, chan->ctrl_offset + reg, value);
551}
552
553static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg,
554 u32 clr)
555{
556 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);
557}
558
559static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg,
560 u32 set)
561{
562 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);
563}
564
565/**
566 * vdma_desc_write_64 - 64-bit descriptor write
567 * @chan: Driver specific VDMA channel
568 * @reg: Register to write
569 * @value_lsb: lower address of the descriptor.
570 * @value_msb: upper address of the descriptor.
571 *
572 * Since vdma driver is trying to write to a register offset which is not a
573 * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits
574 * instead of a single 64 bit register write.
575 */
576static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg,
577 u32 value_lsb, u32 value_msb)
578{
579 /* Write the lsb 32 bits*/
580 writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg);
581
582 /* Write the msb 32 bits */
583 writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4);
584}
585
586static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value)
587{
588 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg);
589}
590
591static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg,
592 dma_addr_t addr)
593{
594 if (chan->ext_addr)
595 dma_writeq(chan, reg, addr);
596 else
597 dma_ctrl_write(chan, reg, addr);
598}
599
600static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan,
601 struct xilinx_axidma_desc_hw *hw,
602 dma_addr_t buf_addr, size_t sg_used,
603 size_t period_len)
604{
605 if (chan->ext_addr) {
606 hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len);
607 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used +
608 period_len);
609 } else {
610 hw->buf_addr = buf_addr + sg_used + period_len;
611 }
612}
613
614static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan,
615 struct xilinx_aximcdma_desc_hw *hw,
616 dma_addr_t buf_addr, size_t sg_used)
617{
618 if (chan->ext_addr) {
619 hw->buf_addr = lower_32_bits(buf_addr + sg_used);
620 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used);
621 } else {
622 hw->buf_addr = buf_addr + sg_used;
623 }
624}
625
626/* -----------------------------------------------------------------------------
627 * Descriptors and segments alloc and free
628 */
629
630/**
631 * xilinx_vdma_alloc_tx_segment - Allocate transaction segment
632 * @chan: Driver specific DMA channel
633 *
634 * Return: The allocated segment on success and NULL on failure.
635 */
636static struct xilinx_vdma_tx_segment *
637xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
638{
639 struct xilinx_vdma_tx_segment *segment;
640 dma_addr_t phys;
641
642 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
643 if (!segment)
644 return NULL;
645
646 segment->phys = phys;
647
648 return segment;
649}
650
651/**
652 * xilinx_cdma_alloc_tx_segment - Allocate transaction segment
653 * @chan: Driver specific DMA channel
654 *
655 * Return: The allocated segment on success and NULL on failure.
656 */
657static struct xilinx_cdma_tx_segment *
658xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
659{
660 struct xilinx_cdma_tx_segment *segment;
661 dma_addr_t phys;
662
663 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
664 if (!segment)
665 return NULL;
666
667 segment->phys = phys;
668
669 return segment;
670}
671
672/**
673 * xilinx_axidma_alloc_tx_segment - Allocate transaction segment
674 * @chan: Driver specific DMA channel
675 *
676 * Return: The allocated segment on success and NULL on failure.
677 */
678static struct xilinx_axidma_tx_segment *
679xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan)
680{
681 struct xilinx_axidma_tx_segment *segment = NULL;
682 unsigned long flags;
683
684 spin_lock_irqsave(&chan->lock, flags);
685 if (!list_empty(&chan->free_seg_list)) {
686 segment = list_first_entry(&chan->free_seg_list,
687 struct xilinx_axidma_tx_segment,
688 node);
689 list_del(&segment->node);
690 }
691 spin_unlock_irqrestore(&chan->lock, flags);
692
693 if (!segment)
694 dev_dbg(chan->dev, "Could not find free tx segment\n");
695
696 return segment;
697}
698
699/**
700 * xilinx_aximcdma_alloc_tx_segment - Allocate transaction segment
701 * @chan: Driver specific DMA channel
702 *
703 * Return: The allocated segment on success and NULL on failure.
704 */
705static struct xilinx_aximcdma_tx_segment *
706xilinx_aximcdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
707{
708 struct xilinx_aximcdma_tx_segment *segment = NULL;
709 unsigned long flags;
710
711 spin_lock_irqsave(&chan->lock, flags);
712 if (!list_empty(&chan->free_seg_list)) {
713 segment = list_first_entry(&chan->free_seg_list,
714 struct xilinx_aximcdma_tx_segment,
715 node);
716 list_del(&segment->node);
717 }
718 spin_unlock_irqrestore(&chan->lock, flags);
719
720 return segment;
721}
722
723static void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw)
724{
725 u32 next_desc = hw->next_desc;
726 u32 next_desc_msb = hw->next_desc_msb;
727
728 memset(hw, 0, sizeof(struct xilinx_axidma_desc_hw));
729
730 hw->next_desc = next_desc;
731 hw->next_desc_msb = next_desc_msb;
732}
733
734static void xilinx_mcdma_clean_hw_desc(struct xilinx_aximcdma_desc_hw *hw)
735{
736 u32 next_desc = hw->next_desc;
737 u32 next_desc_msb = hw->next_desc_msb;
738
739 memset(hw, 0, sizeof(struct xilinx_aximcdma_desc_hw));
740
741 hw->next_desc = next_desc;
742 hw->next_desc_msb = next_desc_msb;
743}
744
745/**
746 * xilinx_dma_free_tx_segment - Free transaction segment
747 * @chan: Driver specific DMA channel
748 * @segment: DMA transaction segment
749 */
750static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan,
751 struct xilinx_axidma_tx_segment *segment)
752{
753 xilinx_dma_clean_hw_desc(&segment->hw);
754
755 list_add_tail(&segment->node, &chan->free_seg_list);
756}
757
758/**
759 * xilinx_mcdma_free_tx_segment - Free transaction segment
760 * @chan: Driver specific DMA channel
761 * @segment: DMA transaction segment
762 */
763static void xilinx_mcdma_free_tx_segment(struct xilinx_dma_chan *chan,
764 struct xilinx_aximcdma_tx_segment *
765 segment)
766{
767 xilinx_mcdma_clean_hw_desc(&segment->hw);
768
769 list_add_tail(&segment->node, &chan->free_seg_list);
770}
771
772/**
773 * xilinx_cdma_free_tx_segment - Free transaction segment
774 * @chan: Driver specific DMA channel
775 * @segment: DMA transaction segment
776 */
777static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan,
778 struct xilinx_cdma_tx_segment *segment)
779{
780 dma_pool_free(chan->desc_pool, segment, segment->phys);
781}
782
783/**
784 * xilinx_vdma_free_tx_segment - Free transaction segment
785 * @chan: Driver specific DMA channel
786 * @segment: DMA transaction segment
787 */
788static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan,
789 struct xilinx_vdma_tx_segment *segment)
790{
791 dma_pool_free(chan->desc_pool, segment, segment->phys);
792}
793
794/**
795 * xilinx_dma_alloc_tx_descriptor - Allocate transaction descriptor
796 * @chan: Driver specific DMA channel
797 *
798 * Return: The allocated descriptor on success and NULL on failure.
799 */
800static struct xilinx_dma_tx_descriptor *
801xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan)
802{
803 struct xilinx_dma_tx_descriptor *desc;
804
805 desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
806 if (!desc)
807 return NULL;
808
809 INIT_LIST_HEAD(&desc->segments);
810
811 return desc;
812}
813
814/**
815 * xilinx_dma_free_tx_descriptor - Free transaction descriptor
816 * @chan: Driver specific DMA channel
817 * @desc: DMA transaction descriptor
818 */
819static void
820xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan,
821 struct xilinx_dma_tx_descriptor *desc)
822{
823 struct xilinx_vdma_tx_segment *segment, *next;
824 struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next;
825 struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next;
826 struct xilinx_aximcdma_tx_segment *aximcdma_segment, *aximcdma_next;
827
828 if (!desc)
829 return;
830
831 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
832 list_for_each_entry_safe(segment, next, &desc->segments, node) {
833 list_del(&segment->node);
834 xilinx_vdma_free_tx_segment(chan, segment);
835 }
836 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
837 list_for_each_entry_safe(cdma_segment, cdma_next,
838 &desc->segments, node) {
839 list_del(&cdma_segment->node);
840 xilinx_cdma_free_tx_segment(chan, cdma_segment);
841 }
842 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
843 list_for_each_entry_safe(axidma_segment, axidma_next,
844 &desc->segments, node) {
845 list_del(&axidma_segment->node);
846 xilinx_dma_free_tx_segment(chan, axidma_segment);
847 }
848 } else {
849 list_for_each_entry_safe(aximcdma_segment, aximcdma_next,
850 &desc->segments, node) {
851 list_del(&aximcdma_segment->node);
852 xilinx_mcdma_free_tx_segment(chan, aximcdma_segment);
853 }
854 }
855
856 kfree(desc);
857}
858
859/* Required functions */
860
861/**
862 * xilinx_dma_free_desc_list - Free descriptors list
863 * @chan: Driver specific DMA channel
864 * @list: List to parse and delete the descriptor
865 */
866static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan,
867 struct list_head *list)
868{
869 struct xilinx_dma_tx_descriptor *desc, *next;
870
871 list_for_each_entry_safe(desc, next, list, node) {
872 list_del(&desc->node);
873 xilinx_dma_free_tx_descriptor(chan, desc);
874 }
875}
876
877/**
878 * xilinx_dma_free_descriptors - Free channel descriptors
879 * @chan: Driver specific DMA channel
880 */
881static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan)
882{
883 unsigned long flags;
884
885 spin_lock_irqsave(&chan->lock, flags);
886
887 xilinx_dma_free_desc_list(chan, &chan->pending_list);
888 xilinx_dma_free_desc_list(chan, &chan->done_list);
889 xilinx_dma_free_desc_list(chan, &chan->active_list);
890
891 spin_unlock_irqrestore(&chan->lock, flags);
892}
893
894/**
895 * xilinx_dma_free_chan_resources - Free channel resources
896 * @dchan: DMA channel
897 */
898static void xilinx_dma_free_chan_resources(struct dma_chan *dchan)
899{
900 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
901 unsigned long flags;
902
903 dev_dbg(chan->dev, "Free all channel resources.\n");
904
905 xilinx_dma_free_descriptors(chan);
906
907 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
908 spin_lock_irqsave(&chan->lock, flags);
909 INIT_LIST_HEAD(&chan->free_seg_list);
910 spin_unlock_irqrestore(&chan->lock, flags);
911
912 /* Free memory that is allocated for BD */
913 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
914 XILINX_DMA_NUM_DESCS, chan->seg_v,
915 chan->seg_p);
916
917 /* Free Memory that is allocated for cyclic DMA Mode */
918 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v),
919 chan->cyclic_seg_v, chan->cyclic_seg_p);
920 }
921
922 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
923 spin_lock_irqsave(&chan->lock, flags);
924 INIT_LIST_HEAD(&chan->free_seg_list);
925 spin_unlock_irqrestore(&chan->lock, flags);
926
927 /* Free memory that is allocated for BD */
928 dma_free_coherent(chan->dev, sizeof(*chan->seg_mv) *
929 XILINX_DMA_NUM_DESCS, chan->seg_mv,
930 chan->seg_p);
931 }
932
933 if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA &&
934 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) {
935 dma_pool_destroy(chan->desc_pool);
936 chan->desc_pool = NULL;
937 }
938
939}
940
941/**
942 * xilinx_dma_get_residue - Compute residue for a given descriptor
943 * @chan: Driver specific dma channel
944 * @desc: dma transaction descriptor
945 *
946 * Return: The number of residue bytes for the descriptor.
947 */
948static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan,
949 struct xilinx_dma_tx_descriptor *desc)
950{
951 struct xilinx_cdma_tx_segment *cdma_seg;
952 struct xilinx_axidma_tx_segment *axidma_seg;
953 struct xilinx_aximcdma_tx_segment *aximcdma_seg;
954 struct xilinx_cdma_desc_hw *cdma_hw;
955 struct xilinx_axidma_desc_hw *axidma_hw;
956 struct xilinx_aximcdma_desc_hw *aximcdma_hw;
957 struct list_head *entry;
958 u32 residue = 0;
959
960 list_for_each(entry, &desc->segments) {
961 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
962 cdma_seg = list_entry(entry,
963 struct xilinx_cdma_tx_segment,
964 node);
965 cdma_hw = &cdma_seg->hw;
966 residue += (cdma_hw->control - cdma_hw->status) &
967 chan->xdev->max_buffer_len;
968 } else if (chan->xdev->dma_config->dmatype ==
969 XDMA_TYPE_AXIDMA) {
970 axidma_seg = list_entry(entry,
971 struct xilinx_axidma_tx_segment,
972 node);
973 axidma_hw = &axidma_seg->hw;
974 residue += (axidma_hw->control - axidma_hw->status) &
975 chan->xdev->max_buffer_len;
976 } else {
977 aximcdma_seg =
978 list_entry(entry,
979 struct xilinx_aximcdma_tx_segment,
980 node);
981 aximcdma_hw = &aximcdma_seg->hw;
982 residue +=
983 (aximcdma_hw->control - aximcdma_hw->status) &
984 chan->xdev->max_buffer_len;
985 }
986 }
987
988 return residue;
989}
990
991/**
992 * xilinx_dma_chan_handle_cyclic - Cyclic dma callback
993 * @chan: Driver specific dma channel
994 * @desc: dma transaction descriptor
995 * @flags: flags for spin lock
996 */
997static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan,
998 struct xilinx_dma_tx_descriptor *desc,
999 unsigned long *flags)
1000{
1001 struct dmaengine_desc_callback cb;
1002
1003 dmaengine_desc_get_callback(&desc->async_tx, &cb);
1004 if (dmaengine_desc_callback_valid(&cb)) {
1005 spin_unlock_irqrestore(&chan->lock, *flags);
1006 dmaengine_desc_callback_invoke(&cb, NULL);
1007 spin_lock_irqsave(&chan->lock, *flags);
1008 }
1009}
1010
1011/**
1012 * xilinx_dma_chan_desc_cleanup - Clean channel descriptors
1013 * @chan: Driver specific DMA channel
1014 */
1015static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan)
1016{
1017 struct xilinx_dma_tx_descriptor *desc, *next;
1018 unsigned long flags;
1019
1020 spin_lock_irqsave(&chan->lock, flags);
1021
1022 list_for_each_entry_safe(desc, next, &chan->done_list, node) {
1023 struct dmaengine_result result;
1024
1025 if (desc->cyclic) {
1026 xilinx_dma_chan_handle_cyclic(chan, desc, &flags);
1027 break;
1028 }
1029
1030 /* Remove from the list of running transactions */
1031 list_del(&desc->node);
1032
1033 if (unlikely(desc->err)) {
1034 if (chan->direction == DMA_DEV_TO_MEM)
1035 result.result = DMA_TRANS_READ_FAILED;
1036 else
1037 result.result = DMA_TRANS_WRITE_FAILED;
1038 } else {
1039 result.result = DMA_TRANS_NOERROR;
1040 }
1041
1042 result.residue = desc->residue;
1043
1044 /* Run the link descriptor callback function */
1045 spin_unlock_irqrestore(&chan->lock, flags);
1046 dmaengine_desc_get_callback_invoke(&desc->async_tx, &result);
1047 spin_lock_irqsave(&chan->lock, flags);
1048
1049 /* Run any dependencies, then free the descriptor */
1050 dma_run_dependencies(&desc->async_tx);
1051 xilinx_dma_free_tx_descriptor(chan, desc);
1052
1053 /*
1054 * While we ran a callback the user called a terminate function,
1055 * which takes care of cleaning up any remaining descriptors
1056 */
1057 if (chan->terminating)
1058 break;
1059 }
1060
1061 spin_unlock_irqrestore(&chan->lock, flags);
1062}
1063
1064/**
1065 * xilinx_dma_do_tasklet - Schedule completion tasklet
1066 * @t: Pointer to the Xilinx DMA channel structure
1067 */
1068static void xilinx_dma_do_tasklet(struct tasklet_struct *t)
1069{
1070 struct xilinx_dma_chan *chan = from_tasklet(chan, t, tasklet);
1071
1072 xilinx_dma_chan_desc_cleanup(chan);
1073}
1074
1075/**
1076 * xilinx_dma_alloc_chan_resources - Allocate channel resources
1077 * @dchan: DMA channel
1078 *
1079 * Return: '0' on success and failure value on error
1080 */
1081static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
1082{
1083 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1084 int i;
1085
1086 /* Has this channel already been allocated? */
1087 if (chan->desc_pool)
1088 return 0;
1089
1090 /*
1091 * We need the descriptor to be aligned to 64bytes
1092 * for meeting Xilinx VDMA specification requirement.
1093 */
1094 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1095 /* Allocate the buffer descriptors. */
1096 chan->seg_v = dma_alloc_coherent(chan->dev,
1097 sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS,
1098 &chan->seg_p, GFP_KERNEL);
1099 if (!chan->seg_v) {
1100 dev_err(chan->dev,
1101 "unable to allocate channel %d descriptors\n",
1102 chan->id);
1103 return -ENOMEM;
1104 }
1105 /*
1106 * For cyclic DMA mode we need to program the tail Descriptor
1107 * register with a value which is not a part of the BD chain
1108 * so allocating a desc segment during channel allocation for
1109 * programming tail descriptor.
1110 */
1111 chan->cyclic_seg_v = dma_alloc_coherent(chan->dev,
1112 sizeof(*chan->cyclic_seg_v),
1113 &chan->cyclic_seg_p,
1114 GFP_KERNEL);
1115 if (!chan->cyclic_seg_v) {
1116 dev_err(chan->dev,
1117 "unable to allocate desc segment for cyclic DMA\n");
1118 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
1119 XILINX_DMA_NUM_DESCS, chan->seg_v,
1120 chan->seg_p);
1121 return -ENOMEM;
1122 }
1123 chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
1124
1125 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
1126 chan->seg_v[i].hw.next_desc =
1127 lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
1128 ((i + 1) % XILINX_DMA_NUM_DESCS));
1129 chan->seg_v[i].hw.next_desc_msb =
1130 upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
1131 ((i + 1) % XILINX_DMA_NUM_DESCS));
1132 chan->seg_v[i].phys = chan->seg_p +
1133 sizeof(*chan->seg_v) * i;
1134 list_add_tail(&chan->seg_v[i].node,
1135 &chan->free_seg_list);
1136 }
1137 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
1138 /* Allocate the buffer descriptors. */
1139 chan->seg_mv = dma_alloc_coherent(chan->dev,
1140 sizeof(*chan->seg_mv) *
1141 XILINX_DMA_NUM_DESCS,
1142 &chan->seg_p, GFP_KERNEL);
1143 if (!chan->seg_mv) {
1144 dev_err(chan->dev,
1145 "unable to allocate channel %d descriptors\n",
1146 chan->id);
1147 return -ENOMEM;
1148 }
1149 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
1150 chan->seg_mv[i].hw.next_desc =
1151 lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) *
1152 ((i + 1) % XILINX_DMA_NUM_DESCS));
1153 chan->seg_mv[i].hw.next_desc_msb =
1154 upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) *
1155 ((i + 1) % XILINX_DMA_NUM_DESCS));
1156 chan->seg_mv[i].phys = chan->seg_p +
1157 sizeof(*chan->seg_mv) * i;
1158 list_add_tail(&chan->seg_mv[i].node,
1159 &chan->free_seg_list);
1160 }
1161 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
1162 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool",
1163 chan->dev,
1164 sizeof(struct xilinx_cdma_tx_segment),
1165 __alignof__(struct xilinx_cdma_tx_segment),
1166 0);
1167 } else {
1168 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool",
1169 chan->dev,
1170 sizeof(struct xilinx_vdma_tx_segment),
1171 __alignof__(struct xilinx_vdma_tx_segment),
1172 0);
1173 }
1174
1175 if (!chan->desc_pool &&
1176 ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) &&
1177 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) {
1178 dev_err(chan->dev,
1179 "unable to allocate channel %d descriptor pool\n",
1180 chan->id);
1181 return -ENOMEM;
1182 }
1183
1184 dma_cookie_init(dchan);
1185
1186 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1187 /* For AXI DMA resetting once channel will reset the
1188 * other channel as well so enable the interrupts here.
1189 */
1190 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1191 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1192 }
1193
1194 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
1195 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1196 XILINX_CDMA_CR_SGMODE);
1197
1198 return 0;
1199}
1200
1201/**
1202 * xilinx_dma_calc_copysize - Calculate the amount of data to copy
1203 * @chan: Driver specific DMA channel
1204 * @size: Total data that needs to be copied
1205 * @done: Amount of data that has been already copied
1206 *
1207 * Return: Amount of data that has to be copied
1208 */
1209static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan,
1210 int size, int done)
1211{
1212 size_t copy;
1213
1214 copy = min_t(size_t, size - done,
1215 chan->xdev->max_buffer_len);
1216
1217 if ((copy + done < size) &&
1218 chan->xdev->common.copy_align) {
1219 /*
1220 * If this is not the last descriptor, make sure
1221 * the next one will be properly aligned
1222 */
1223 copy = rounddown(copy,
1224 (1 << chan->xdev->common.copy_align));
1225 }
1226 return copy;
1227}
1228
1229/**
1230 * xilinx_dma_tx_status - Get DMA transaction status
1231 * @dchan: DMA channel
1232 * @cookie: Transaction identifier
1233 * @txstate: Transaction state
1234 *
1235 * Return: DMA transaction status
1236 */
1237static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
1238 dma_cookie_t cookie,
1239 struct dma_tx_state *txstate)
1240{
1241 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1242 struct xilinx_dma_tx_descriptor *desc;
1243 enum dma_status ret;
1244 unsigned long flags;
1245 u32 residue = 0;
1246
1247 ret = dma_cookie_status(dchan, cookie, txstate);
1248 if (ret == DMA_COMPLETE || !txstate)
1249 return ret;
1250
1251 spin_lock_irqsave(&chan->lock, flags);
1252 if (!list_empty(&chan->active_list)) {
1253 desc = list_last_entry(&chan->active_list,
1254 struct xilinx_dma_tx_descriptor, node);
1255 /*
1256 * VDMA and simple mode do not support residue reporting, so the
1257 * residue field will always be 0.
1258 */
1259 if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA)
1260 residue = xilinx_dma_get_residue(chan, desc);
1261 }
1262 spin_unlock_irqrestore(&chan->lock, flags);
1263
1264 dma_set_residue(txstate, residue);
1265
1266 return ret;
1267}
1268
1269/**
1270 * xilinx_dma_stop_transfer - Halt DMA channel
1271 * @chan: Driver specific DMA channel
1272 *
1273 * Return: '0' on success and failure value on error
1274 */
1275static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan)
1276{
1277 u32 val;
1278
1279 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
1280
1281 /* Wait for the hardware to halt */
1282 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1283 val & XILINX_DMA_DMASR_HALTED, 0,
1284 XILINX_DMA_LOOP_COUNT);
1285}
1286
1287/**
1288 * xilinx_cdma_stop_transfer - Wait for the current transfer to complete
1289 * @chan: Driver specific DMA channel
1290 *
1291 * Return: '0' on success and failure value on error
1292 */
1293static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan)
1294{
1295 u32 val;
1296
1297 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1298 val & XILINX_DMA_DMASR_IDLE, 0,
1299 XILINX_DMA_LOOP_COUNT);
1300}
1301
1302/**
1303 * xilinx_dma_start - Start DMA channel
1304 * @chan: Driver specific DMA channel
1305 */
1306static void xilinx_dma_start(struct xilinx_dma_chan *chan)
1307{
1308 int err;
1309 u32 val;
1310
1311 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
1312
1313 /* Wait for the hardware to start */
1314 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1315 !(val & XILINX_DMA_DMASR_HALTED), 0,
1316 XILINX_DMA_LOOP_COUNT);
1317
1318 if (err) {
1319 dev_err(chan->dev, "Cannot start channel %p: %x\n",
1320 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1321
1322 chan->err = true;
1323 }
1324}
1325
1326/**
1327 * xilinx_vdma_start_transfer - Starts VDMA transfer
1328 * @chan: Driver specific channel struct pointer
1329 */
1330static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
1331{
1332 struct xilinx_vdma_config *config = &chan->config;
1333 struct xilinx_dma_tx_descriptor *desc;
1334 u32 reg, j;
1335 struct xilinx_vdma_tx_segment *segment, *last = NULL;
1336 int i = 0;
1337
1338 /* This function was invoked with lock held */
1339 if (chan->err)
1340 return;
1341
1342 if (!chan->idle)
1343 return;
1344
1345 if (list_empty(&chan->pending_list))
1346 return;
1347
1348 desc = list_first_entry(&chan->pending_list,
1349 struct xilinx_dma_tx_descriptor, node);
1350
1351 /* Configure the hardware using info in the config structure */
1352 if (chan->has_vflip) {
1353 reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP);
1354 reg &= ~XILINX_VDMA_ENABLE_VERTICAL_FLIP;
1355 reg |= config->vflip_en;
1356 dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP,
1357 reg);
1358 }
1359
1360 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1361
1362 if (config->frm_cnt_en)
1363 reg |= XILINX_DMA_DMACR_FRAMECNT_EN;
1364 else
1365 reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN;
1366
1367 /* If not parking, enable circular mode */
1368 if (config->park)
1369 reg &= ~XILINX_DMA_DMACR_CIRC_EN;
1370 else
1371 reg |= XILINX_DMA_DMACR_CIRC_EN;
1372
1373 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1374
1375 j = chan->desc_submitcount;
1376 reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR);
1377 if (chan->direction == DMA_MEM_TO_DEV) {
1378 reg &= ~XILINX_DMA_PARK_PTR_RD_REF_MASK;
1379 reg |= j << XILINX_DMA_PARK_PTR_RD_REF_SHIFT;
1380 } else {
1381 reg &= ~XILINX_DMA_PARK_PTR_WR_REF_MASK;
1382 reg |= j << XILINX_DMA_PARK_PTR_WR_REF_SHIFT;
1383 }
1384 dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg);
1385
1386 /* Start the hardware */
1387 xilinx_dma_start(chan);
1388
1389 if (chan->err)
1390 return;
1391
1392 /* Start the transfer */
1393 if (chan->desc_submitcount < chan->num_frms)
1394 i = chan->desc_submitcount;
1395
1396 list_for_each_entry(segment, &desc->segments, node) {
1397 if (chan->ext_addr)
1398 vdma_desc_write_64(chan,
1399 XILINX_VDMA_REG_START_ADDRESS_64(i++),
1400 segment->hw.buf_addr,
1401 segment->hw.buf_addr_msb);
1402 else
1403 vdma_desc_write(chan,
1404 XILINX_VDMA_REG_START_ADDRESS(i++),
1405 segment->hw.buf_addr);
1406
1407 last = segment;
1408 }
1409
1410 if (!last)
1411 return;
1412
1413 /* HW expects these parameters to be same for one transaction */
1414 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize);
1415 vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE,
1416 last->hw.stride);
1417 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize);
1418
1419 chan->desc_submitcount++;
1420 chan->desc_pendingcount--;
1421 list_move_tail(&desc->node, &chan->active_list);
1422 if (chan->desc_submitcount == chan->num_frms)
1423 chan->desc_submitcount = 0;
1424
1425 chan->idle = false;
1426}
1427
1428/**
1429 * xilinx_cdma_start_transfer - Starts cdma transfer
1430 * @chan: Driver specific channel struct pointer
1431 */
1432static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
1433{
1434 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1435 struct xilinx_cdma_tx_segment *tail_segment;
1436 u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR);
1437
1438 if (chan->err)
1439 return;
1440
1441 if (!chan->idle)
1442 return;
1443
1444 if (list_empty(&chan->pending_list))
1445 return;
1446
1447 head_desc = list_first_entry(&chan->pending_list,
1448 struct xilinx_dma_tx_descriptor, node);
1449 tail_desc = list_last_entry(&chan->pending_list,
1450 struct xilinx_dma_tx_descriptor, node);
1451 tail_segment = list_last_entry(&tail_desc->segments,
1452 struct xilinx_cdma_tx_segment, node);
1453
1454 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1455 ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1456 ctrl_reg |= chan->desc_pendingcount <<
1457 XILINX_DMA_CR_COALESCE_SHIFT;
1458 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);
1459 }
1460
1461 if (chan->has_sg) {
1462 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
1463 XILINX_CDMA_CR_SGMODE);
1464
1465 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1466 XILINX_CDMA_CR_SGMODE);
1467
1468 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1469 head_desc->async_tx.phys);
1470
1471 /* Update tail ptr register which will start the transfer */
1472 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1473 tail_segment->phys);
1474 } else {
1475 /* In simple mode */
1476 struct xilinx_cdma_tx_segment *segment;
1477 struct xilinx_cdma_desc_hw *hw;
1478
1479 segment = list_first_entry(&head_desc->segments,
1480 struct xilinx_cdma_tx_segment,
1481 node);
1482
1483 hw = &segment->hw;
1484
1485 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
1486 xilinx_prep_dma_addr_t(hw->src_addr));
1487 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR,
1488 xilinx_prep_dma_addr_t(hw->dest_addr));
1489
1490 /* Start the transfer */
1491 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1492 hw->control & chan->xdev->max_buffer_len);
1493 }
1494
1495 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1496 chan->desc_pendingcount = 0;
1497 chan->idle = false;
1498}
1499
1500/**
1501 * xilinx_dma_start_transfer - Starts DMA transfer
1502 * @chan: Driver specific channel struct pointer
1503 */
1504static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
1505{
1506 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1507 struct xilinx_axidma_tx_segment *tail_segment;
1508 u32 reg;
1509
1510 if (chan->err)
1511 return;
1512
1513 if (list_empty(&chan->pending_list))
1514 return;
1515
1516 if (!chan->idle)
1517 return;
1518
1519 head_desc = list_first_entry(&chan->pending_list,
1520 struct xilinx_dma_tx_descriptor, node);
1521 tail_desc = list_last_entry(&chan->pending_list,
1522 struct xilinx_dma_tx_descriptor, node);
1523 tail_segment = list_last_entry(&tail_desc->segments,
1524 struct xilinx_axidma_tx_segment, node);
1525
1526 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1527
1528 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1529 reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1530 reg |= chan->desc_pendingcount <<
1531 XILINX_DMA_CR_COALESCE_SHIFT;
1532 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1533 }
1534
1535 if (chan->has_sg)
1536 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1537 head_desc->async_tx.phys);
1538
1539 xilinx_dma_start(chan);
1540
1541 if (chan->err)
1542 return;
1543
1544 /* Start the transfer */
1545 if (chan->has_sg) {
1546 if (chan->cyclic)
1547 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1548 chan->cyclic_seg_v->phys);
1549 else
1550 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1551 tail_segment->phys);
1552 } else {
1553 struct xilinx_axidma_tx_segment *segment;
1554 struct xilinx_axidma_desc_hw *hw;
1555
1556 segment = list_first_entry(&head_desc->segments,
1557 struct xilinx_axidma_tx_segment,
1558 node);
1559 hw = &segment->hw;
1560
1561 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR,
1562 xilinx_prep_dma_addr_t(hw->buf_addr));
1563
1564 /* Start the transfer */
1565 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1566 hw->control & chan->xdev->max_buffer_len);
1567 }
1568
1569 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1570 chan->desc_pendingcount = 0;
1571 chan->idle = false;
1572}
1573
1574/**
1575 * xilinx_mcdma_start_transfer - Starts MCDMA transfer
1576 * @chan: Driver specific channel struct pointer
1577 */
1578static void xilinx_mcdma_start_transfer(struct xilinx_dma_chan *chan)
1579{
1580 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1581 struct xilinx_aximcdma_tx_segment *tail_segment;
1582 u32 reg;
1583
1584 /*
1585 * lock has been held by calling functions, so we don't need it
1586 * to take it here again.
1587 */
1588
1589 if (chan->err)
1590 return;
1591
1592 if (!chan->idle)
1593 return;
1594
1595 if (list_empty(&chan->pending_list))
1596 return;
1597
1598 head_desc = list_first_entry(&chan->pending_list,
1599 struct xilinx_dma_tx_descriptor, node);
1600 tail_desc = list_last_entry(&chan->pending_list,
1601 struct xilinx_dma_tx_descriptor, node);
1602 tail_segment = list_last_entry(&tail_desc->segments,
1603 struct xilinx_aximcdma_tx_segment, node);
1604
1605 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest));
1606
1607 if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) {
1608 reg &= ~XILINX_MCDMA_COALESCE_MASK;
1609 reg |= chan->desc_pendingcount <<
1610 XILINX_MCDMA_COALESCE_SHIFT;
1611 }
1612
1613 reg |= XILINX_MCDMA_IRQ_ALL_MASK;
1614 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);
1615
1616 /* Program current descriptor */
1617 xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest),
1618 head_desc->async_tx.phys);
1619
1620 /* Program channel enable register */
1621 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET);
1622 reg |= BIT(chan->tdest);
1623 dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg);
1624
1625 /* Start the fetch of BDs for the channel */
1626 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest));
1627 reg |= XILINX_MCDMA_CR_RUNSTOP_MASK;
1628 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);
1629
1630 xilinx_dma_start(chan);
1631
1632 if (chan->err)
1633 return;
1634
1635 /* Start the transfer */
1636 xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest),
1637 tail_segment->phys);
1638
1639 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1640 chan->desc_pendingcount = 0;
1641 chan->idle = false;
1642}
1643
1644/**
1645 * xilinx_dma_issue_pending - Issue pending transactions
1646 * @dchan: DMA channel
1647 */
1648static void xilinx_dma_issue_pending(struct dma_chan *dchan)
1649{
1650 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1651 unsigned long flags;
1652
1653 spin_lock_irqsave(&chan->lock, flags);
1654 chan->start_transfer(chan);
1655 spin_unlock_irqrestore(&chan->lock, flags);
1656}
1657
1658/**
1659 * xilinx_dma_device_config - Configure the DMA channel
1660 * @dchan: DMA channel
1661 * @config: channel configuration
1662 *
1663 * Return: 0 always.
1664 */
1665static int xilinx_dma_device_config(struct dma_chan *dchan,
1666 struct dma_slave_config *config)
1667{
1668 return 0;
1669}
1670
1671/**
1672 * xilinx_dma_complete_descriptor - Mark the active descriptor as complete
1673 * @chan : xilinx DMA channel
1674 *
1675 * CONTEXT: hardirq
1676 */
1677static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
1678{
1679 struct xilinx_dma_tx_descriptor *desc, *next;
1680
1681 /* This function was invoked with lock held */
1682 if (list_empty(&chan->active_list))
1683 return;
1684
1685 list_for_each_entry_safe(desc, next, &chan->active_list, node) {
1686 if (chan->has_sg && chan->xdev->dma_config->dmatype !=
1687 XDMA_TYPE_VDMA)
1688 desc->residue = xilinx_dma_get_residue(chan, desc);
1689 else
1690 desc->residue = 0;
1691 desc->err = chan->err;
1692
1693 list_del(&desc->node);
1694 if (!desc->cyclic)
1695 dma_cookie_complete(&desc->async_tx);
1696 list_add_tail(&desc->node, &chan->done_list);
1697 }
1698}
1699
1700/**
1701 * xilinx_dma_reset - Reset DMA channel
1702 * @chan: Driver specific DMA channel
1703 *
1704 * Return: '0' on success and failure value on error
1705 */
1706static int xilinx_dma_reset(struct xilinx_dma_chan *chan)
1707{
1708 int err;
1709 u32 tmp;
1710
1711 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET);
1712
1713 /* Wait for the hardware to finish reset */
1714 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp,
1715 !(tmp & XILINX_DMA_DMACR_RESET), 0,
1716 XILINX_DMA_LOOP_COUNT);
1717
1718 if (err) {
1719 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n",
1720 dma_ctrl_read(chan, XILINX_DMA_REG_DMACR),
1721 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1722 return -ETIMEDOUT;
1723 }
1724
1725 chan->err = false;
1726 chan->idle = true;
1727 chan->desc_pendingcount = 0;
1728 chan->desc_submitcount = 0;
1729
1730 return err;
1731}
1732
1733/**
1734 * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts
1735 * @chan: Driver specific DMA channel
1736 *
1737 * Return: '0' on success and failure value on error
1738 */
1739static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan)
1740{
1741 int err;
1742
1743 /* Reset VDMA */
1744 err = xilinx_dma_reset(chan);
1745 if (err)
1746 return err;
1747
1748 /* Enable interrupts */
1749 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1750 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1751
1752 return 0;
1753}
1754
1755/**
1756 * xilinx_mcdma_irq_handler - MCDMA Interrupt handler
1757 * @irq: IRQ number
1758 * @data: Pointer to the Xilinx MCDMA channel structure
1759 *
1760 * Return: IRQ_HANDLED/IRQ_NONE
1761 */
1762static irqreturn_t xilinx_mcdma_irq_handler(int irq, void *data)
1763{
1764 struct xilinx_dma_chan *chan = data;
1765 u32 status, ser_offset, chan_sermask, chan_offset = 0, chan_id;
1766
1767 if (chan->direction == DMA_DEV_TO_MEM)
1768 ser_offset = XILINX_MCDMA_RXINT_SER_OFFSET;
1769 else
1770 ser_offset = XILINX_MCDMA_TXINT_SER_OFFSET;
1771
1772 /* Read the channel id raising the interrupt*/
1773 chan_sermask = dma_ctrl_read(chan, ser_offset);
1774 chan_id = ffs(chan_sermask);
1775
1776 if (!chan_id)
1777 return IRQ_NONE;
1778
1779 if (chan->direction == DMA_DEV_TO_MEM)
1780 chan_offset = chan->xdev->dma_config->max_channels / 2;
1781
1782 chan_offset = chan_offset + (chan_id - 1);
1783 chan = chan->xdev->chan[chan_offset];
1784 /* Read the status and ack the interrupts. */
1785 status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest));
1786 if (!(status & XILINX_MCDMA_IRQ_ALL_MASK))
1787 return IRQ_NONE;
1788
1789 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest),
1790 status & XILINX_MCDMA_IRQ_ALL_MASK);
1791
1792 if (status & XILINX_MCDMA_IRQ_ERR_MASK) {
1793 dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n",
1794 chan,
1795 dma_ctrl_read(chan, XILINX_MCDMA_CH_ERR_OFFSET),
1796 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET
1797 (chan->tdest)),
1798 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET
1799 (chan->tdest)));
1800 chan->err = true;
1801 }
1802
1803 if (status & XILINX_MCDMA_IRQ_DELAY_MASK) {
1804 /*
1805 * Device takes too long to do the transfer when user requires
1806 * responsiveness.
1807 */
1808 dev_dbg(chan->dev, "Inter-packet latency too long\n");
1809 }
1810
1811 if (status & XILINX_MCDMA_IRQ_IOC_MASK) {
1812 spin_lock(&chan->lock);
1813 xilinx_dma_complete_descriptor(chan);
1814 chan->idle = true;
1815 chan->start_transfer(chan);
1816 spin_unlock(&chan->lock);
1817 }
1818
1819 tasklet_schedule(&chan->tasklet);
1820 return IRQ_HANDLED;
1821}
1822
1823/**
1824 * xilinx_dma_irq_handler - DMA Interrupt handler
1825 * @irq: IRQ number
1826 * @data: Pointer to the Xilinx DMA channel structure
1827 *
1828 * Return: IRQ_HANDLED/IRQ_NONE
1829 */
1830static irqreturn_t xilinx_dma_irq_handler(int irq, void *data)
1831{
1832 struct xilinx_dma_chan *chan = data;
1833 u32 status;
1834
1835 /* Read the status and ack the interrupts. */
1836 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR);
1837 if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK))
1838 return IRQ_NONE;
1839
1840 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1841 status & XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1842
1843 if (status & XILINX_DMA_DMASR_ERR_IRQ) {
1844 /*
1845 * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the
1846 * error is recoverable, ignore it. Otherwise flag the error.
1847 *
1848 * Only recoverable errors can be cleared in the DMASR register,
1849 * make sure not to write to other error bits to 1.
1850 */
1851 u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK;
1852
1853 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1854 errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK);
1855
1856 if (!chan->flush_on_fsync ||
1857 (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) {
1858 dev_err(chan->dev,
1859 "Channel %p has errors %x, cdr %x tdr %x\n",
1860 chan, errors,
1861 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC),
1862 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC));
1863 chan->err = true;
1864 }
1865 }
1866
1867 if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) {
1868 /*
1869 * Device takes too long to do the transfer when user requires
1870 * responsiveness.
1871 */
1872 dev_dbg(chan->dev, "Inter-packet latency too long\n");
1873 }
1874
1875 if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) {
1876 spin_lock(&chan->lock);
1877 xilinx_dma_complete_descriptor(chan);
1878 chan->idle = true;
1879 chan->start_transfer(chan);
1880 spin_unlock(&chan->lock);
1881 }
1882
1883 tasklet_schedule(&chan->tasklet);
1884 return IRQ_HANDLED;
1885}
1886
1887/**
1888 * append_desc_queue - Queuing descriptor
1889 * @chan: Driver specific dma channel
1890 * @desc: dma transaction descriptor
1891 */
1892static void append_desc_queue(struct xilinx_dma_chan *chan,
1893 struct xilinx_dma_tx_descriptor *desc)
1894{
1895 struct xilinx_vdma_tx_segment *tail_segment;
1896 struct xilinx_dma_tx_descriptor *tail_desc;
1897 struct xilinx_axidma_tx_segment *axidma_tail_segment;
1898 struct xilinx_aximcdma_tx_segment *aximcdma_tail_segment;
1899 struct xilinx_cdma_tx_segment *cdma_tail_segment;
1900
1901 if (list_empty(&chan->pending_list))
1902 goto append;
1903
1904 /*
1905 * Add the hardware descriptor to the chain of hardware descriptors
1906 * that already exists in memory.
1907 */
1908 tail_desc = list_last_entry(&chan->pending_list,
1909 struct xilinx_dma_tx_descriptor, node);
1910 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
1911 tail_segment = list_last_entry(&tail_desc->segments,
1912 struct xilinx_vdma_tx_segment,
1913 node);
1914 tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1915 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
1916 cdma_tail_segment = list_last_entry(&tail_desc->segments,
1917 struct xilinx_cdma_tx_segment,
1918 node);
1919 cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1920 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1921 axidma_tail_segment = list_last_entry(&tail_desc->segments,
1922 struct xilinx_axidma_tx_segment,
1923 node);
1924 axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1925 } else {
1926 aximcdma_tail_segment =
1927 list_last_entry(&tail_desc->segments,
1928 struct xilinx_aximcdma_tx_segment,
1929 node);
1930 aximcdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1931 }
1932
1933 /*
1934 * Add the software descriptor and all children to the list
1935 * of pending transactions
1936 */
1937append:
1938 list_add_tail(&desc->node, &chan->pending_list);
1939 chan->desc_pendingcount++;
1940
1941 if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA)
1942 && unlikely(chan->desc_pendingcount > chan->num_frms)) {
1943 dev_dbg(chan->dev, "desc pendingcount is too high\n");
1944 chan->desc_pendingcount = chan->num_frms;
1945 }
1946}
1947
1948/**
1949 * xilinx_dma_tx_submit - Submit DMA transaction
1950 * @tx: Async transaction descriptor
1951 *
1952 * Return: cookie value on success and failure value on error
1953 */
1954static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
1955{
1956 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
1957 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan);
1958 dma_cookie_t cookie;
1959 unsigned long flags;
1960 int err;
1961
1962 if (chan->cyclic) {
1963 xilinx_dma_free_tx_descriptor(chan, desc);
1964 return -EBUSY;
1965 }
1966
1967 if (chan->err) {
1968 /*
1969 * If reset fails, need to hard reset the system.
1970 * Channel is no longer functional
1971 */
1972 err = xilinx_dma_chan_reset(chan);
1973 if (err < 0)
1974 return err;
1975 }
1976
1977 spin_lock_irqsave(&chan->lock, flags);
1978
1979 cookie = dma_cookie_assign(tx);
1980
1981 /* Put this transaction onto the tail of the pending queue */
1982 append_desc_queue(chan, desc);
1983
1984 if (desc->cyclic)
1985 chan->cyclic = true;
1986
1987 chan->terminating = false;
1988
1989 spin_unlock_irqrestore(&chan->lock, flags);
1990
1991 return cookie;
1992}
1993
1994/**
1995 * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a
1996 * DMA_SLAVE transaction
1997 * @dchan: DMA channel
1998 * @xt: Interleaved template pointer
1999 * @flags: transfer ack flags
2000 *
2001 * Return: Async transaction descriptor on success and NULL on failure
2002 */
2003static struct dma_async_tx_descriptor *
2004xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
2005 struct dma_interleaved_template *xt,
2006 unsigned long flags)
2007{
2008 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2009 struct xilinx_dma_tx_descriptor *desc;
2010 struct xilinx_vdma_tx_segment *segment;
2011 struct xilinx_vdma_desc_hw *hw;
2012
2013 if (!is_slave_direction(xt->dir))
2014 return NULL;
2015
2016 if (!xt->numf || !xt->sgl[0].size)
2017 return NULL;
2018
2019 if (xt->frame_size != 1)
2020 return NULL;
2021
2022 /* Allocate a transaction descriptor. */
2023 desc = xilinx_dma_alloc_tx_descriptor(chan);
2024 if (!desc)
2025 return NULL;
2026
2027 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2028 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2029 async_tx_ack(&desc->async_tx);
2030
2031 /* Allocate the link descriptor from DMA pool */
2032 segment = xilinx_vdma_alloc_tx_segment(chan);
2033 if (!segment)
2034 goto error;
2035
2036 /* Fill in the hardware descriptor */
2037 hw = &segment->hw;
2038 hw->vsize = xt->numf;
2039 hw->hsize = xt->sgl[0].size;
2040 hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) <<
2041 XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT;
2042 hw->stride |= chan->config.frm_dly <<
2043 XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT;
2044
2045 if (xt->dir != DMA_MEM_TO_DEV) {
2046 if (chan->ext_addr) {
2047 hw->buf_addr = lower_32_bits(xt->dst_start);
2048 hw->buf_addr_msb = upper_32_bits(xt->dst_start);
2049 } else {
2050 hw->buf_addr = xt->dst_start;
2051 }
2052 } else {
2053 if (chan->ext_addr) {
2054 hw->buf_addr = lower_32_bits(xt->src_start);
2055 hw->buf_addr_msb = upper_32_bits(xt->src_start);
2056 } else {
2057 hw->buf_addr = xt->src_start;
2058 }
2059 }
2060
2061 /* Insert the segment into the descriptor segments list. */
2062 list_add_tail(&segment->node, &desc->segments);
2063
2064 /* Link the last hardware descriptor with the first. */
2065 segment = list_first_entry(&desc->segments,
2066 struct xilinx_vdma_tx_segment, node);
2067 desc->async_tx.phys = segment->phys;
2068
2069 return &desc->async_tx;
2070
2071error:
2072 xilinx_dma_free_tx_descriptor(chan, desc);
2073 return NULL;
2074}
2075
2076/**
2077 * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction
2078 * @dchan: DMA channel
2079 * @dma_dst: destination address
2080 * @dma_src: source address
2081 * @len: transfer length
2082 * @flags: transfer ack flags
2083 *
2084 * Return: Async transaction descriptor on success and NULL on failure
2085 */
2086static struct dma_async_tx_descriptor *
2087xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst,
2088 dma_addr_t dma_src, size_t len, unsigned long flags)
2089{
2090 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2091 struct xilinx_dma_tx_descriptor *desc;
2092 struct xilinx_cdma_tx_segment *segment;
2093 struct xilinx_cdma_desc_hw *hw;
2094
2095 if (!len || len > chan->xdev->max_buffer_len)
2096 return NULL;
2097
2098 desc = xilinx_dma_alloc_tx_descriptor(chan);
2099 if (!desc)
2100 return NULL;
2101
2102 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2103 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2104
2105 /* Allocate the link descriptor from DMA pool */
2106 segment = xilinx_cdma_alloc_tx_segment(chan);
2107 if (!segment)
2108 goto error;
2109
2110 hw = &segment->hw;
2111 hw->control = len;
2112 hw->src_addr = dma_src;
2113 hw->dest_addr = dma_dst;
2114 if (chan->ext_addr) {
2115 hw->src_addr_msb = upper_32_bits(dma_src);
2116 hw->dest_addr_msb = upper_32_bits(dma_dst);
2117 }
2118
2119 /* Insert the segment into the descriptor segments list. */
2120 list_add_tail(&segment->node, &desc->segments);
2121
2122 desc->async_tx.phys = segment->phys;
2123 hw->next_desc = segment->phys;
2124
2125 return &desc->async_tx;
2126
2127error:
2128 xilinx_dma_free_tx_descriptor(chan, desc);
2129 return NULL;
2130}
2131
2132/**
2133 * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
2134 * @dchan: DMA channel
2135 * @sgl: scatterlist to transfer to/from
2136 * @sg_len: number of entries in @scatterlist
2137 * @direction: DMA direction
2138 * @flags: transfer ack flags
2139 * @context: APP words of the descriptor
2140 *
2141 * Return: Async transaction descriptor on success and NULL on failure
2142 */
2143static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(
2144 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
2145 enum dma_transfer_direction direction, unsigned long flags,
2146 void *context)
2147{
2148 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2149 struct xilinx_dma_tx_descriptor *desc;
2150 struct xilinx_axidma_tx_segment *segment = NULL;
2151 u32 *app_w = (u32 *)context;
2152 struct scatterlist *sg;
2153 size_t copy;
2154 size_t sg_used;
2155 unsigned int i;
2156
2157 if (!is_slave_direction(direction))
2158 return NULL;
2159
2160 /* Allocate a transaction descriptor. */
2161 desc = xilinx_dma_alloc_tx_descriptor(chan);
2162 if (!desc)
2163 return NULL;
2164
2165 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2166 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2167
2168 /* Build transactions using information in the scatter gather list */
2169 for_each_sg(sgl, sg, sg_len, i) {
2170 sg_used = 0;
2171
2172 /* Loop until the entire scatterlist entry is used */
2173 while (sg_used < sg_dma_len(sg)) {
2174 struct xilinx_axidma_desc_hw *hw;
2175
2176 /* Get a free segment */
2177 segment = xilinx_axidma_alloc_tx_segment(chan);
2178 if (!segment)
2179 goto error;
2180
2181 /*
2182 * Calculate the maximum number of bytes to transfer,
2183 * making sure it is less than the hw limit
2184 */
2185 copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg),
2186 sg_used);
2187 hw = &segment->hw;
2188
2189 /* Fill in the descriptor */
2190 xilinx_axidma_buf(chan, hw, sg_dma_address(sg),
2191 sg_used, 0);
2192
2193 hw->control = copy;
2194
2195 if (chan->direction == DMA_MEM_TO_DEV) {
2196 if (app_w)
2197 memcpy(hw->app, app_w, sizeof(u32) *
2198 XILINX_DMA_NUM_APP_WORDS);
2199 }
2200
2201 sg_used += copy;
2202
2203 /*
2204 * Insert the segment into the descriptor segments
2205 * list.
2206 */
2207 list_add_tail(&segment->node, &desc->segments);
2208 }
2209 }
2210
2211 segment = list_first_entry(&desc->segments,
2212 struct xilinx_axidma_tx_segment, node);
2213 desc->async_tx.phys = segment->phys;
2214
2215 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2216 if (chan->direction == DMA_MEM_TO_DEV) {
2217 segment->hw.control |= XILINX_DMA_BD_SOP;
2218 segment = list_last_entry(&desc->segments,
2219 struct xilinx_axidma_tx_segment,
2220 node);
2221 segment->hw.control |= XILINX_DMA_BD_EOP;
2222 }
2223
2224 return &desc->async_tx;
2225
2226error:
2227 xilinx_dma_free_tx_descriptor(chan, desc);
2228 return NULL;
2229}
2230
2231/**
2232 * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction
2233 * @dchan: DMA channel
2234 * @buf_addr: Physical address of the buffer
2235 * @buf_len: Total length of the cyclic buffers
2236 * @period_len: length of individual cyclic buffer
2237 * @direction: DMA direction
2238 * @flags: transfer ack flags
2239 *
2240 * Return: Async transaction descriptor on success and NULL on failure
2241 */
2242static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(
2243 struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len,
2244 size_t period_len, enum dma_transfer_direction direction,
2245 unsigned long flags)
2246{
2247 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2248 struct xilinx_dma_tx_descriptor *desc;
2249 struct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL;
2250 size_t copy, sg_used;
2251 unsigned int num_periods;
2252 int i;
2253 u32 reg;
2254
2255 if (!period_len)
2256 return NULL;
2257
2258 num_periods = buf_len / period_len;
2259
2260 if (!num_periods)
2261 return NULL;
2262
2263 if (!is_slave_direction(direction))
2264 return NULL;
2265
2266 /* Allocate a transaction descriptor. */
2267 desc = xilinx_dma_alloc_tx_descriptor(chan);
2268 if (!desc)
2269 return NULL;
2270
2271 chan->direction = direction;
2272 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2273 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2274
2275 for (i = 0; i < num_periods; ++i) {
2276 sg_used = 0;
2277
2278 while (sg_used < period_len) {
2279 struct xilinx_axidma_desc_hw *hw;
2280
2281 /* Get a free segment */
2282 segment = xilinx_axidma_alloc_tx_segment(chan);
2283 if (!segment)
2284 goto error;
2285
2286 /*
2287 * Calculate the maximum number of bytes to transfer,
2288 * making sure it is less than the hw limit
2289 */
2290 copy = xilinx_dma_calc_copysize(chan, period_len,
2291 sg_used);
2292 hw = &segment->hw;
2293 xilinx_axidma_buf(chan, hw, buf_addr, sg_used,
2294 period_len * i);
2295 hw->control = copy;
2296
2297 if (prev)
2298 prev->hw.next_desc = segment->phys;
2299
2300 prev = segment;
2301 sg_used += copy;
2302
2303 /*
2304 * Insert the segment into the descriptor segments
2305 * list.
2306 */
2307 list_add_tail(&segment->node, &desc->segments);
2308 }
2309 }
2310
2311 head_segment = list_first_entry(&desc->segments,
2312 struct xilinx_axidma_tx_segment, node);
2313 desc->async_tx.phys = head_segment->phys;
2314
2315 desc->cyclic = true;
2316 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2317 reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
2318 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
2319
2320 segment = list_last_entry(&desc->segments,
2321 struct xilinx_axidma_tx_segment,
2322 node);
2323 segment->hw.next_desc = (u32) head_segment->phys;
2324
2325 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2326 if (direction == DMA_MEM_TO_DEV) {
2327 head_segment->hw.control |= XILINX_DMA_BD_SOP;
2328 segment->hw.control |= XILINX_DMA_BD_EOP;
2329 }
2330
2331 return &desc->async_tx;
2332
2333error:
2334 xilinx_dma_free_tx_descriptor(chan, desc);
2335 return NULL;
2336}
2337
2338/**
2339 * xilinx_mcdma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
2340 * @dchan: DMA channel
2341 * @sgl: scatterlist to transfer to/from
2342 * @sg_len: number of entries in @scatterlist
2343 * @direction: DMA direction
2344 * @flags: transfer ack flags
2345 * @context: APP words of the descriptor
2346 *
2347 * Return: Async transaction descriptor on success and NULL on failure
2348 */
2349static struct dma_async_tx_descriptor *
2350xilinx_mcdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
2351 unsigned int sg_len,
2352 enum dma_transfer_direction direction,
2353 unsigned long flags, void *context)
2354{
2355 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2356 struct xilinx_dma_tx_descriptor *desc;
2357 struct xilinx_aximcdma_tx_segment *segment = NULL;
2358 u32 *app_w = (u32 *)context;
2359 struct scatterlist *sg;
2360 size_t copy;
2361 size_t sg_used;
2362 unsigned int i;
2363
2364 if (!is_slave_direction(direction))
2365 return NULL;
2366
2367 /* Allocate a transaction descriptor. */
2368 desc = xilinx_dma_alloc_tx_descriptor(chan);
2369 if (!desc)
2370 return NULL;
2371
2372 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2373 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2374
2375 /* Build transactions using information in the scatter gather list */
2376 for_each_sg(sgl, sg, sg_len, i) {
2377 sg_used = 0;
2378
2379 /* Loop until the entire scatterlist entry is used */
2380 while (sg_used < sg_dma_len(sg)) {
2381 struct xilinx_aximcdma_desc_hw *hw;
2382
2383 /* Get a free segment */
2384 segment = xilinx_aximcdma_alloc_tx_segment(chan);
2385 if (!segment)
2386 goto error;
2387
2388 /*
2389 * Calculate the maximum number of bytes to transfer,
2390 * making sure it is less than the hw limit
2391 */
2392 copy = min_t(size_t, sg_dma_len(sg) - sg_used,
2393 chan->xdev->max_buffer_len);
2394 hw = &segment->hw;
2395
2396 /* Fill in the descriptor */
2397 xilinx_aximcdma_buf(chan, hw, sg_dma_address(sg),
2398 sg_used);
2399 hw->control = copy;
2400
2401 if (chan->direction == DMA_MEM_TO_DEV && app_w) {
2402 memcpy(hw->app, app_w, sizeof(u32) *
2403 XILINX_DMA_NUM_APP_WORDS);
2404 }
2405
2406 sg_used += copy;
2407 /*
2408 * Insert the segment into the descriptor segments
2409 * list.
2410 */
2411 list_add_tail(&segment->node, &desc->segments);
2412 }
2413 }
2414
2415 segment = list_first_entry(&desc->segments,
2416 struct xilinx_aximcdma_tx_segment, node);
2417 desc->async_tx.phys = segment->phys;
2418
2419 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2420 if (chan->direction == DMA_MEM_TO_DEV) {
2421 segment->hw.control |= XILINX_MCDMA_BD_SOP;
2422 segment = list_last_entry(&desc->segments,
2423 struct xilinx_aximcdma_tx_segment,
2424 node);
2425 segment->hw.control |= XILINX_MCDMA_BD_EOP;
2426 }
2427
2428 return &desc->async_tx;
2429
2430error:
2431 xilinx_dma_free_tx_descriptor(chan, desc);
2432
2433 return NULL;
2434}
2435
2436/**
2437 * xilinx_dma_terminate_all - Halt the channel and free descriptors
2438 * @dchan: Driver specific DMA Channel pointer
2439 *
2440 * Return: '0' always.
2441 */
2442static int xilinx_dma_terminate_all(struct dma_chan *dchan)
2443{
2444 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2445 u32 reg;
2446 int err;
2447
2448 if (!chan->cyclic) {
2449 err = chan->stop_transfer(chan);
2450 if (err) {
2451 dev_err(chan->dev, "Cannot stop channel %p: %x\n",
2452 chan, dma_ctrl_read(chan,
2453 XILINX_DMA_REG_DMASR));
2454 chan->err = true;
2455 }
2456 }
2457
2458 xilinx_dma_chan_reset(chan);
2459 /* Remove and free all of the descriptors in the lists */
2460 chan->terminating = true;
2461 xilinx_dma_free_descriptors(chan);
2462 chan->idle = true;
2463
2464 if (chan->cyclic) {
2465 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2466 reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
2467 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
2468 chan->cyclic = false;
2469 }
2470
2471 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
2472 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2473 XILINX_CDMA_CR_SGMODE);
2474
2475 return 0;
2476}
2477
2478static void xilinx_dma_synchronize(struct dma_chan *dchan)
2479{
2480 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2481
2482 tasklet_kill(&chan->tasklet);
2483}
2484
2485/**
2486 * xilinx_vdma_channel_set_config - Configure VDMA channel
2487 * Run-time configuration for Axi VDMA, supports:
2488 * . halt the channel
2489 * . configure interrupt coalescing and inter-packet delay threshold
2490 * . start/stop parking
2491 * . enable genlock
2492 *
2493 * @dchan: DMA channel
2494 * @cfg: VDMA device configuration pointer
2495 *
2496 * Return: '0' on success and failure value on error
2497 */
2498int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
2499 struct xilinx_vdma_config *cfg)
2500{
2501 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2502 u32 dmacr;
2503
2504 if (cfg->reset)
2505 return xilinx_dma_chan_reset(chan);
2506
2507 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2508
2509 chan->config.frm_dly = cfg->frm_dly;
2510 chan->config.park = cfg->park;
2511
2512 /* genlock settings */
2513 chan->config.gen_lock = cfg->gen_lock;
2514 chan->config.master = cfg->master;
2515
2516 dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN;
2517 if (cfg->gen_lock && chan->genlock) {
2518 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN;
2519 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK;
2520 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;
2521 }
2522
2523 chan->config.frm_cnt_en = cfg->frm_cnt_en;
2524 chan->config.vflip_en = cfg->vflip_en;
2525
2526 if (cfg->park)
2527 chan->config.park_frm = cfg->park_frm;
2528 else
2529 chan->config.park_frm = -1;
2530
2531 chan->config.coalesc = cfg->coalesc;
2532 chan->config.delay = cfg->delay;
2533
2534 if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {
2535 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK;
2536 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;
2537 chan->config.coalesc = cfg->coalesc;
2538 }
2539
2540 if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {
2541 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK;
2542 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;
2543 chan->config.delay = cfg->delay;
2544 }
2545
2546 /* FSync Source selection */
2547 dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK;
2548 dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT;
2549
2550 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);
2551
2552 return 0;
2553}
2554EXPORT_SYMBOL(xilinx_vdma_channel_set_config);
2555
2556/* -----------------------------------------------------------------------------
2557 * Probe and remove
2558 */
2559
2560/**
2561 * xilinx_dma_chan_remove - Per Channel remove function
2562 * @chan: Driver specific DMA channel
2563 */
2564static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan)
2565{
2566 /* Disable all interrupts */
2567 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2568 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
2569
2570 if (chan->irq > 0)
2571 free_irq(chan->irq, chan);
2572
2573 tasklet_kill(&chan->tasklet);
2574
2575 list_del(&chan->common.device_node);
2576}
2577
2578static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2579 struct clk **tx_clk, struct clk **rx_clk,
2580 struct clk **sg_clk, struct clk **tmp_clk)
2581{
2582 int err;
2583
2584 *tmp_clk = NULL;
2585
2586 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2587 if (IS_ERR(*axi_clk))
2588 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n");
2589
2590 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2591 if (IS_ERR(*tx_clk))
2592 *tx_clk = NULL;
2593
2594 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2595 if (IS_ERR(*rx_clk))
2596 *rx_clk = NULL;
2597
2598 *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk");
2599 if (IS_ERR(*sg_clk))
2600 *sg_clk = NULL;
2601
2602 err = clk_prepare_enable(*axi_clk);
2603 if (err) {
2604 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2605 return err;
2606 }
2607
2608 err = clk_prepare_enable(*tx_clk);
2609 if (err) {
2610 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2611 goto err_disable_axiclk;
2612 }
2613
2614 err = clk_prepare_enable(*rx_clk);
2615 if (err) {
2616 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2617 goto err_disable_txclk;
2618 }
2619
2620 err = clk_prepare_enable(*sg_clk);
2621 if (err) {
2622 dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n", err);
2623 goto err_disable_rxclk;
2624 }
2625
2626 return 0;
2627
2628err_disable_rxclk:
2629 clk_disable_unprepare(*rx_clk);
2630err_disable_txclk:
2631 clk_disable_unprepare(*tx_clk);
2632err_disable_axiclk:
2633 clk_disable_unprepare(*axi_clk);
2634
2635 return err;
2636}
2637
2638static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2639 struct clk **dev_clk, struct clk **tmp_clk,
2640 struct clk **tmp1_clk, struct clk **tmp2_clk)
2641{
2642 int err;
2643
2644 *tmp_clk = NULL;
2645 *tmp1_clk = NULL;
2646 *tmp2_clk = NULL;
2647
2648 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2649 if (IS_ERR(*axi_clk))
2650 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n");
2651
2652 *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk");
2653 if (IS_ERR(*dev_clk))
2654 return dev_err_probe(&pdev->dev, PTR_ERR(*dev_clk), "failed to get dev_clk\n");
2655
2656 err = clk_prepare_enable(*axi_clk);
2657 if (err) {
2658 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2659 return err;
2660 }
2661
2662 err = clk_prepare_enable(*dev_clk);
2663 if (err) {
2664 dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n", err);
2665 goto err_disable_axiclk;
2666 }
2667
2668 return 0;
2669
2670err_disable_axiclk:
2671 clk_disable_unprepare(*axi_clk);
2672
2673 return err;
2674}
2675
2676static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2677 struct clk **tx_clk, struct clk **txs_clk,
2678 struct clk **rx_clk, struct clk **rxs_clk)
2679{
2680 int err;
2681
2682 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2683 if (IS_ERR(*axi_clk))
2684 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n");
2685
2686 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2687 if (IS_ERR(*tx_clk))
2688 *tx_clk = NULL;
2689
2690 *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk");
2691 if (IS_ERR(*txs_clk))
2692 *txs_clk = NULL;
2693
2694 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2695 if (IS_ERR(*rx_clk))
2696 *rx_clk = NULL;
2697
2698 *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk");
2699 if (IS_ERR(*rxs_clk))
2700 *rxs_clk = NULL;
2701
2702 err = clk_prepare_enable(*axi_clk);
2703 if (err) {
2704 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n",
2705 err);
2706 return err;
2707 }
2708
2709 err = clk_prepare_enable(*tx_clk);
2710 if (err) {
2711 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2712 goto err_disable_axiclk;
2713 }
2714
2715 err = clk_prepare_enable(*txs_clk);
2716 if (err) {
2717 dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n", err);
2718 goto err_disable_txclk;
2719 }
2720
2721 err = clk_prepare_enable(*rx_clk);
2722 if (err) {
2723 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2724 goto err_disable_txsclk;
2725 }
2726
2727 err = clk_prepare_enable(*rxs_clk);
2728 if (err) {
2729 dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n", err);
2730 goto err_disable_rxclk;
2731 }
2732
2733 return 0;
2734
2735err_disable_rxclk:
2736 clk_disable_unprepare(*rx_clk);
2737err_disable_txsclk:
2738 clk_disable_unprepare(*txs_clk);
2739err_disable_txclk:
2740 clk_disable_unprepare(*tx_clk);
2741err_disable_axiclk:
2742 clk_disable_unprepare(*axi_clk);
2743
2744 return err;
2745}
2746
2747static void xdma_disable_allclks(struct xilinx_dma_device *xdev)
2748{
2749 clk_disable_unprepare(xdev->rxs_clk);
2750 clk_disable_unprepare(xdev->rx_clk);
2751 clk_disable_unprepare(xdev->txs_clk);
2752 clk_disable_unprepare(xdev->tx_clk);
2753 clk_disable_unprepare(xdev->axi_clk);
2754}
2755
2756/**
2757 * xilinx_dma_chan_probe - Per Channel Probing
2758 * It get channel features from the device tree entry and
2759 * initialize special channel handling routines
2760 *
2761 * @xdev: Driver specific device structure
2762 * @node: Device node
2763 *
2764 * Return: '0' on success and failure value on error
2765 */
2766static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
2767 struct device_node *node)
2768{
2769 struct xilinx_dma_chan *chan;
2770 bool has_dre = false;
2771 u32 value, width;
2772 int err;
2773
2774 /* Allocate and initialize the channel structure */
2775 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
2776 if (!chan)
2777 return -ENOMEM;
2778
2779 chan->dev = xdev->dev;
2780 chan->xdev = xdev;
2781 chan->desc_pendingcount = 0x0;
2782 chan->ext_addr = xdev->ext_addr;
2783 /* This variable ensures that descriptors are not
2784 * Submitted when dma engine is in progress. This variable is
2785 * Added to avoid polling for a bit in the status register to
2786 * Know dma state in the driver hot path.
2787 */
2788 chan->idle = true;
2789
2790 spin_lock_init(&chan->lock);
2791 INIT_LIST_HEAD(&chan->pending_list);
2792 INIT_LIST_HEAD(&chan->done_list);
2793 INIT_LIST_HEAD(&chan->active_list);
2794 INIT_LIST_HEAD(&chan->free_seg_list);
2795
2796 /* Retrieve the channel properties from the device tree */
2797 has_dre = of_property_read_bool(node, "xlnx,include-dre");
2798
2799 chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode");
2800
2801 err = of_property_read_u32(node, "xlnx,datawidth", &value);
2802 if (err) {
2803 dev_err(xdev->dev, "missing xlnx,datawidth property\n");
2804 return err;
2805 }
2806 width = value >> 3; /* Convert bits to bytes */
2807
2808 /* If data width is greater than 8 bytes, DRE is not in hw */
2809 if (width > 8)
2810 has_dre = false;
2811
2812 if (!has_dre)
2813 xdev->common.copy_align = (enum dmaengine_alignment)fls(width - 1);
2814
2815 if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") ||
2816 of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") ||
2817 of_device_is_compatible(node, "xlnx,axi-cdma-channel")) {
2818 chan->direction = DMA_MEM_TO_DEV;
2819 chan->id = xdev->mm2s_chan_id++;
2820 chan->tdest = chan->id;
2821
2822 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
2823 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2824 chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET;
2825 chan->config.park = 1;
2826
2827 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2828 xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S)
2829 chan->flush_on_fsync = true;
2830 }
2831 } else if (of_device_is_compatible(node,
2832 "xlnx,axi-vdma-s2mm-channel") ||
2833 of_device_is_compatible(node,
2834 "xlnx,axi-dma-s2mm-channel")) {
2835 chan->direction = DMA_DEV_TO_MEM;
2836 chan->id = xdev->s2mm_chan_id++;
2837 chan->tdest = chan->id - xdev->dma_config->max_channels / 2;
2838 chan->has_vflip = of_property_read_bool(node,
2839 "xlnx,enable-vert-flip");
2840 if (chan->has_vflip) {
2841 chan->config.vflip_en = dma_read(chan,
2842 XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP) &
2843 XILINX_VDMA_ENABLE_VERTICAL_FLIP;
2844 }
2845
2846 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA)
2847 chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET;
2848 else
2849 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
2850
2851 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2852 chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET;
2853 chan->config.park = 1;
2854
2855 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2856 xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM)
2857 chan->flush_on_fsync = true;
2858 }
2859 } else {
2860 dev_err(xdev->dev, "Invalid channel compatible node\n");
2861 return -EINVAL;
2862 }
2863
2864 /* Request the interrupt */
2865 chan->irq = of_irq_get(node, chan->tdest);
2866 if (chan->irq < 0)
2867 return dev_err_probe(xdev->dev, chan->irq, "failed to get irq\n");
2868 err = request_irq(chan->irq, xdev->dma_config->irq_handler,
2869 IRQF_SHARED, "xilinx-dma-controller", chan);
2870 if (err) {
2871 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq);
2872 return err;
2873 }
2874
2875 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
2876 chan->start_transfer = xilinx_dma_start_transfer;
2877 chan->stop_transfer = xilinx_dma_stop_transfer;
2878 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
2879 chan->start_transfer = xilinx_mcdma_start_transfer;
2880 chan->stop_transfer = xilinx_dma_stop_transfer;
2881 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
2882 chan->start_transfer = xilinx_cdma_start_transfer;
2883 chan->stop_transfer = xilinx_cdma_stop_transfer;
2884 } else {
2885 chan->start_transfer = xilinx_vdma_start_transfer;
2886 chan->stop_transfer = xilinx_dma_stop_transfer;
2887 }
2888
2889 /* check if SG is enabled (only for AXIDMA, AXIMCDMA, and CDMA) */
2890 if (xdev->dma_config->dmatype != XDMA_TYPE_VDMA) {
2891 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA ||
2892 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) &
2893 XILINX_DMA_DMASR_SG_MASK)
2894 chan->has_sg = true;
2895 dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id,
2896 chan->has_sg ? "enabled" : "disabled");
2897 }
2898
2899 /* Initialize the tasklet */
2900 tasklet_setup(&chan->tasklet, xilinx_dma_do_tasklet);
2901
2902 /*
2903 * Initialize the DMA channel and add it to the DMA engine channels
2904 * list.
2905 */
2906 chan->common.device = &xdev->common;
2907
2908 list_add_tail(&chan->common.device_node, &xdev->common.channels);
2909 xdev->chan[chan->id] = chan;
2910
2911 /* Reset the channel */
2912 err = xilinx_dma_chan_reset(chan);
2913 if (err < 0) {
2914 dev_err(xdev->dev, "Reset channel failed\n");
2915 return err;
2916 }
2917
2918 return 0;
2919}
2920
2921/**
2922 * xilinx_dma_child_probe - Per child node probe
2923 * It get number of dma-channels per child node from
2924 * device-tree and initializes all the channels.
2925 *
2926 * @xdev: Driver specific device structure
2927 * @node: Device node
2928 *
2929 * Return: '0' on success and failure value on error.
2930 */
2931static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev,
2932 struct device_node *node)
2933{
2934 int ret, i;
2935 u32 nr_channels = 1;
2936
2937 ret = of_property_read_u32(node, "dma-channels", &nr_channels);
2938 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA && ret < 0)
2939 dev_warn(xdev->dev, "missing dma-channels property\n");
2940
2941 for (i = 0; i < nr_channels; i++) {
2942 ret = xilinx_dma_chan_probe(xdev, node);
2943 if (ret)
2944 return ret;
2945 }
2946
2947 return 0;
2948}
2949
2950/**
2951 * of_dma_xilinx_xlate - Translation function
2952 * @dma_spec: Pointer to DMA specifier as found in the device tree
2953 * @ofdma: Pointer to DMA controller data
2954 *
2955 * Return: DMA channel pointer on success and NULL on error
2956 */
2957static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
2958 struct of_dma *ofdma)
2959{
2960 struct xilinx_dma_device *xdev = ofdma->of_dma_data;
2961 int chan_id = dma_spec->args[0];
2962
2963 if (chan_id >= xdev->dma_config->max_channels || !xdev->chan[chan_id])
2964 return NULL;
2965
2966 return dma_get_slave_channel(&xdev->chan[chan_id]->common);
2967}
2968
2969static const struct xilinx_dma_config axidma_config = {
2970 .dmatype = XDMA_TYPE_AXIDMA,
2971 .clk_init = axidma_clk_init,
2972 .irq_handler = xilinx_dma_irq_handler,
2973 .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE,
2974};
2975
2976static const struct xilinx_dma_config aximcdma_config = {
2977 .dmatype = XDMA_TYPE_AXIMCDMA,
2978 .clk_init = axidma_clk_init,
2979 .irq_handler = xilinx_mcdma_irq_handler,
2980 .max_channels = XILINX_MCDMA_MAX_CHANS_PER_DEVICE,
2981};
2982static const struct xilinx_dma_config axicdma_config = {
2983 .dmatype = XDMA_TYPE_CDMA,
2984 .clk_init = axicdma_clk_init,
2985 .irq_handler = xilinx_dma_irq_handler,
2986 .max_channels = XILINX_CDMA_MAX_CHANS_PER_DEVICE,
2987};
2988
2989static const struct xilinx_dma_config axivdma_config = {
2990 .dmatype = XDMA_TYPE_VDMA,
2991 .clk_init = axivdma_clk_init,
2992 .irq_handler = xilinx_dma_irq_handler,
2993 .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE,
2994};
2995
2996static const struct of_device_id xilinx_dma_of_ids[] = {
2997 { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config },
2998 { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config },
2999 { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config },
3000 { .compatible = "xlnx,axi-mcdma-1.00.a", .data = &aximcdma_config },
3001 {}
3002};
3003MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids);
3004
3005/**
3006 * xilinx_dma_probe - Driver probe function
3007 * @pdev: Pointer to the platform_device structure
3008 *
3009 * Return: '0' on success and failure value on error
3010 */
3011static int xilinx_dma_probe(struct platform_device *pdev)
3012{
3013 int (*clk_init)(struct platform_device *, struct clk **, struct clk **,
3014 struct clk **, struct clk **, struct clk **)
3015 = axivdma_clk_init;
3016 struct device_node *node = pdev->dev.of_node;
3017 struct xilinx_dma_device *xdev;
3018 struct device_node *child, *np = pdev->dev.of_node;
3019 u32 num_frames, addr_width, len_width;
3020 int i, err;
3021
3022 /* Allocate and initialize the DMA engine structure */
3023 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
3024 if (!xdev)
3025 return -ENOMEM;
3026
3027 xdev->dev = &pdev->dev;
3028 if (np) {
3029 const struct of_device_id *match;
3030
3031 match = of_match_node(xilinx_dma_of_ids, np);
3032 if (match && match->data) {
3033 xdev->dma_config = match->data;
3034 clk_init = xdev->dma_config->clk_init;
3035 }
3036 }
3037
3038 err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk,
3039 &xdev->rx_clk, &xdev->rxs_clk);
3040 if (err)
3041 return err;
3042
3043 /* Request and map I/O memory */
3044 xdev->regs = devm_platform_ioremap_resource(pdev, 0);
3045 if (IS_ERR(xdev->regs)) {
3046 err = PTR_ERR(xdev->regs);
3047 goto disable_clks;
3048 }
3049 /* Retrieve the DMA engine properties from the device tree */
3050 xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0);
3051 xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2;
3052
3053 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA ||
3054 xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
3055 if (!of_property_read_u32(node, "xlnx,sg-length-width",
3056 &len_width)) {
3057 if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN ||
3058 len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) {
3059 dev_warn(xdev->dev,
3060 "invalid xlnx,sg-length-width property value. Using default width\n");
3061 } else {
3062 if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX)
3063 dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n");
3064 xdev->max_buffer_len =
3065 GENMASK(len_width - 1, 0);
3066 }
3067 }
3068 }
3069
3070 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
3071 err = of_property_read_u32(node, "xlnx,num-fstores",
3072 &num_frames);
3073 if (err < 0) {
3074 dev_err(xdev->dev,
3075 "missing xlnx,num-fstores property\n");
3076 goto disable_clks;
3077 }
3078
3079 err = of_property_read_u32(node, "xlnx,flush-fsync",
3080 &xdev->flush_on_fsync);
3081 if (err < 0)
3082 dev_warn(xdev->dev,
3083 "missing xlnx,flush-fsync property\n");
3084 }
3085
3086 err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width);
3087 if (err < 0)
3088 dev_warn(xdev->dev, "missing xlnx,addrwidth property\n");
3089
3090 if (addr_width > 32)
3091 xdev->ext_addr = true;
3092 else
3093 xdev->ext_addr = false;
3094
3095 /* Set the dma mask bits */
3096 err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width));
3097 if (err < 0) {
3098 dev_err(xdev->dev, "DMA mask error %d\n", err);
3099 goto disable_clks;
3100 }
3101
3102 /* Initialize the DMA engine */
3103 xdev->common.dev = &pdev->dev;
3104
3105 INIT_LIST_HEAD(&xdev->common.channels);
3106 if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) {
3107 dma_cap_set(DMA_SLAVE, xdev->common.cap_mask);
3108 dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask);
3109 }
3110
3111 xdev->common.device_alloc_chan_resources =
3112 xilinx_dma_alloc_chan_resources;
3113 xdev->common.device_free_chan_resources =
3114 xilinx_dma_free_chan_resources;
3115 xdev->common.device_terminate_all = xilinx_dma_terminate_all;
3116 xdev->common.device_synchronize = xilinx_dma_synchronize;
3117 xdev->common.device_tx_status = xilinx_dma_tx_status;
3118 xdev->common.device_issue_pending = xilinx_dma_issue_pending;
3119 xdev->common.device_config = xilinx_dma_device_config;
3120 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
3121 dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask);
3122 xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg;
3123 xdev->common.device_prep_dma_cyclic =
3124 xilinx_dma_prep_dma_cyclic;
3125 /* Residue calculation is supported by only AXI DMA and CDMA */
3126 xdev->common.residue_granularity =
3127 DMA_RESIDUE_GRANULARITY_SEGMENT;
3128 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
3129 dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask);
3130 xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy;
3131 /* Residue calculation is supported by only AXI DMA and CDMA */
3132 xdev->common.residue_granularity =
3133 DMA_RESIDUE_GRANULARITY_SEGMENT;
3134 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
3135 xdev->common.device_prep_slave_sg = xilinx_mcdma_prep_slave_sg;
3136 } else {
3137 xdev->common.device_prep_interleaved_dma =
3138 xilinx_vdma_dma_prep_interleaved;
3139 }
3140
3141 platform_set_drvdata(pdev, xdev);
3142
3143 /* Initialize the channels */
3144 for_each_child_of_node(node, child) {
3145 err = xilinx_dma_child_probe(xdev, child);
3146 if (err < 0) {
3147 of_node_put(child);
3148 goto error;
3149 }
3150 }
3151
3152 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
3153 for (i = 0; i < xdev->dma_config->max_channels; i++)
3154 if (xdev->chan[i])
3155 xdev->chan[i]->num_frms = num_frames;
3156 }
3157
3158 /* Register the DMA engine with the core */
3159 err = dma_async_device_register(&xdev->common);
3160 if (err) {
3161 dev_err(xdev->dev, "failed to register the dma device\n");
3162 goto error;
3163 }
3164
3165 err = of_dma_controller_register(node, of_dma_xilinx_xlate,
3166 xdev);
3167 if (err < 0) {
3168 dev_err(&pdev->dev, "Unable to register DMA to DT\n");
3169 dma_async_device_unregister(&xdev->common);
3170 goto error;
3171 }
3172
3173 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
3174 dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n");
3175 else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA)
3176 dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n");
3177 else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA)
3178 dev_info(&pdev->dev, "Xilinx AXI MCDMA Engine Driver Probed!!\n");
3179 else
3180 dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n");
3181
3182 return 0;
3183
3184error:
3185 for (i = 0; i < xdev->dma_config->max_channels; i++)
3186 if (xdev->chan[i])
3187 xilinx_dma_chan_remove(xdev->chan[i]);
3188disable_clks:
3189 xdma_disable_allclks(xdev);
3190
3191 return err;
3192}
3193
3194/**
3195 * xilinx_dma_remove - Driver remove function
3196 * @pdev: Pointer to the platform_device structure
3197 *
3198 * Return: Always '0'
3199 */
3200static int xilinx_dma_remove(struct platform_device *pdev)
3201{
3202 struct xilinx_dma_device *xdev = platform_get_drvdata(pdev);
3203 int i;
3204
3205 of_dma_controller_free(pdev->dev.of_node);
3206
3207 dma_async_device_unregister(&xdev->common);
3208
3209 for (i = 0; i < xdev->dma_config->max_channels; i++)
3210 if (xdev->chan[i])
3211 xilinx_dma_chan_remove(xdev->chan[i]);
3212
3213 xdma_disable_allclks(xdev);
3214
3215 return 0;
3216}
3217
3218static struct platform_driver xilinx_vdma_driver = {
3219 .driver = {
3220 .name = "xilinx-vdma",
3221 .of_match_table = xilinx_dma_of_ids,
3222 },
3223 .probe = xilinx_dma_probe,
3224 .remove = xilinx_dma_remove,
3225};
3226
3227module_platform_driver(xilinx_vdma_driver);
3228
3229MODULE_AUTHOR("Xilinx, Inc.");
3230MODULE_DESCRIPTION("Xilinx VDMA driver");
3231MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * DMA driver for Xilinx Video DMA Engine
4 *
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
6 *
7 * Based on the Freescale DMA driver.
8 *
9 * Description:
10 * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP
11 * core that provides high-bandwidth direct memory access between memory
12 * and AXI4-Stream type video target peripherals. The core provides efficient
13 * two dimensional DMA operations with independent asynchronous read (S2MM)
14 * and write (MM2S) channel operation. It can be configured to have either
15 * one channel or two channels. If configured as two channels, one is to
16 * transmit to the video device (MM2S) and another is to receive from the
17 * video device (S2MM). Initialization, status, interrupt and management
18 * registers are accessed through an AXI4-Lite slave interface.
19 *
20 * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that
21 * provides high-bandwidth one dimensional direct memory access between memory
22 * and AXI4-Stream target peripherals. It supports one receive and one
23 * transmit channel, both of them optional at synthesis time.
24 *
25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
26 * Access (DMA) between a memory-mapped source address and a memory-mapped
27 * destination address.
28 *
29 * The AXI Multichannel Direct Memory Access (AXI MCDMA) core is a soft
30 * Xilinx IP that provides high-bandwidth direct memory access between
31 * memory and AXI4-Stream target peripherals. It provides scatter gather
32 * (SG) interface with multiple channels independent configuration support.
33 *
34 */
35
36#include <linux/bitops.h>
37#include <linux/dmapool.h>
38#include <linux/dma/xilinx_dma.h>
39#include <linux/init.h>
40#include <linux/interrupt.h>
41#include <linux/io.h>
42#include <linux/iopoll.h>
43#include <linux/module.h>
44#include <linux/of.h>
45#include <linux/of_dma.h>
46#include <linux/of_irq.h>
47#include <linux/platform_device.h>
48#include <linux/slab.h>
49#include <linux/clk.h>
50#include <linux/io-64-nonatomic-lo-hi.h>
51
52#include "../dmaengine.h"
53
54/* Register/Descriptor Offsets */
55#define XILINX_DMA_MM2S_CTRL_OFFSET 0x0000
56#define XILINX_DMA_S2MM_CTRL_OFFSET 0x0030
57#define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050
58#define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0
59
60/* Control Registers */
61#define XILINX_DMA_REG_DMACR 0x0000
62#define XILINX_DMA_DMACR_DELAY_MAX 0xff
63#define XILINX_DMA_DMACR_DELAY_SHIFT 24
64#define XILINX_DMA_DMACR_FRAME_COUNT_MAX 0xff
65#define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT 16
66#define XILINX_DMA_DMACR_ERR_IRQ BIT(14)
67#define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13)
68#define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12)
69#define XILINX_DMA_DMACR_MASTER_SHIFT 8
70#define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5
71#define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4)
72#define XILINX_DMA_DMACR_GENLOCK_EN BIT(3)
73#define XILINX_DMA_DMACR_RESET BIT(2)
74#define XILINX_DMA_DMACR_CIRC_EN BIT(1)
75#define XILINX_DMA_DMACR_RUNSTOP BIT(0)
76#define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5)
77#define XILINX_DMA_DMACR_DELAY_MASK GENMASK(31, 24)
78#define XILINX_DMA_DMACR_FRAME_COUNT_MASK GENMASK(23, 16)
79#define XILINX_DMA_DMACR_MASTER_MASK GENMASK(11, 8)
80
81#define XILINX_DMA_REG_DMASR 0x0004
82#define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15)
83#define XILINX_DMA_DMASR_ERR_IRQ BIT(14)
84#define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13)
85#define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12)
86#define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11)
87#define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10)
88#define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9)
89#define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8)
90#define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7)
91#define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6)
92#define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5)
93#define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4)
94#define XILINX_DMA_DMASR_SG_MASK BIT(3)
95#define XILINX_DMA_DMASR_IDLE BIT(1)
96#define XILINX_DMA_DMASR_HALTED BIT(0)
97#define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24)
98#define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16)
99
100#define XILINX_DMA_REG_CURDESC 0x0008
101#define XILINX_DMA_REG_TAILDESC 0x0010
102#define XILINX_DMA_REG_REG_INDEX 0x0014
103#define XILINX_DMA_REG_FRMSTORE 0x0018
104#define XILINX_DMA_REG_THRESHOLD 0x001c
105#define XILINX_DMA_REG_FRMPTR_STS 0x0024
106#define XILINX_DMA_REG_PARK_PTR 0x0028
107#define XILINX_DMA_PARK_PTR_WR_REF_SHIFT 8
108#define XILINX_DMA_PARK_PTR_WR_REF_MASK GENMASK(12, 8)
109#define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0
110#define XILINX_DMA_PARK_PTR_RD_REF_MASK GENMASK(4, 0)
111#define XILINX_DMA_REG_VDMA_VERSION 0x002c
112
113/* Register Direct Mode Registers */
114#define XILINX_DMA_REG_VSIZE 0x0000
115#define XILINX_DMA_REG_HSIZE 0x0004
116
117#define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008
118#define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24
119#define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT 0
120
121#define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n))
122#define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n))
123
124#define XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP 0x00ec
125#define XILINX_VDMA_ENABLE_VERTICAL_FLIP BIT(0)
126
127/* HW specific definitions */
128#define XILINX_MCDMA_MAX_CHANS_PER_DEVICE 0x20
129#define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x2
130#define XILINX_CDMA_MAX_CHANS_PER_DEVICE 0x1
131
132#define XILINX_DMA_DMAXR_ALL_IRQ_MASK \
133 (XILINX_DMA_DMASR_FRM_CNT_IRQ | \
134 XILINX_DMA_DMASR_DLY_CNT_IRQ | \
135 XILINX_DMA_DMASR_ERR_IRQ)
136
137#define XILINX_DMA_DMASR_ALL_ERR_MASK \
138 (XILINX_DMA_DMASR_EOL_LATE_ERR | \
139 XILINX_DMA_DMASR_SOF_LATE_ERR | \
140 XILINX_DMA_DMASR_SG_DEC_ERR | \
141 XILINX_DMA_DMASR_SG_SLV_ERR | \
142 XILINX_DMA_DMASR_EOF_EARLY_ERR | \
143 XILINX_DMA_DMASR_SOF_EARLY_ERR | \
144 XILINX_DMA_DMASR_DMA_DEC_ERR | \
145 XILINX_DMA_DMASR_DMA_SLAVE_ERR | \
146 XILINX_DMA_DMASR_DMA_INT_ERR)
147
148/*
149 * Recoverable errors are DMA Internal error, SOF Early, EOF Early
150 * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC
151 * is enabled in the h/w system.
152 */
153#define XILINX_DMA_DMASR_ERR_RECOVER_MASK \
154 (XILINX_DMA_DMASR_SOF_LATE_ERR | \
155 XILINX_DMA_DMASR_EOF_EARLY_ERR | \
156 XILINX_DMA_DMASR_SOF_EARLY_ERR | \
157 XILINX_DMA_DMASR_DMA_INT_ERR)
158
159/* Axi VDMA Flush on Fsync bits */
160#define XILINX_DMA_FLUSH_S2MM 3
161#define XILINX_DMA_FLUSH_MM2S 2
162#define XILINX_DMA_FLUSH_BOTH 1
163
164/* Delay loop counter to prevent hardware failure */
165#define XILINX_DMA_LOOP_COUNT 1000000
166
167/* AXI DMA Specific Registers/Offsets */
168#define XILINX_DMA_REG_SRCDSTADDR 0x18
169#define XILINX_DMA_REG_BTT 0x28
170
171/* AXI DMA Specific Masks/Bit fields */
172#define XILINX_DMA_MAX_TRANS_LEN_MIN 8
173#define XILINX_DMA_MAX_TRANS_LEN_MAX 23
174#define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26
175#define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16)
176#define XILINX_DMA_CR_DELAY_MAX GENMASK(31, 24)
177#define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4)
178#define XILINX_DMA_CR_COALESCE_SHIFT 16
179#define XILINX_DMA_CR_DELAY_SHIFT 24
180#define XILINX_DMA_BD_SOP BIT(27)
181#define XILINX_DMA_BD_EOP BIT(26)
182#define XILINX_DMA_BD_COMP_MASK BIT(31)
183#define XILINX_DMA_COALESCE_MAX 255
184#define XILINX_DMA_NUM_DESCS 512
185#define XILINX_DMA_NUM_APP_WORDS 5
186
187/* AXI CDMA Specific Registers/Offsets */
188#define XILINX_CDMA_REG_SRCADDR 0x18
189#define XILINX_CDMA_REG_DSTADDR 0x20
190
191/* AXI CDMA Specific Masks */
192#define XILINX_CDMA_CR_SGMODE BIT(3)
193
194#define xilinx_prep_dma_addr_t(addr) \
195 ((dma_addr_t)((u64)addr##_##msb << 32 | (addr)))
196
197/* AXI MCDMA Specific Registers/Offsets */
198#define XILINX_MCDMA_MM2S_CTRL_OFFSET 0x0000
199#define XILINX_MCDMA_S2MM_CTRL_OFFSET 0x0500
200#define XILINX_MCDMA_CHEN_OFFSET 0x0008
201#define XILINX_MCDMA_CH_ERR_OFFSET 0x0010
202#define XILINX_MCDMA_RXINT_SER_OFFSET 0x0020
203#define XILINX_MCDMA_TXINT_SER_OFFSET 0x0028
204#define XILINX_MCDMA_CHAN_CR_OFFSET(x) (0x40 + (x) * 0x40)
205#define XILINX_MCDMA_CHAN_SR_OFFSET(x) (0x44 + (x) * 0x40)
206#define XILINX_MCDMA_CHAN_CDESC_OFFSET(x) (0x48 + (x) * 0x40)
207#define XILINX_MCDMA_CHAN_TDESC_OFFSET(x) (0x50 + (x) * 0x40)
208
209/* AXI MCDMA Specific Masks/Shifts */
210#define XILINX_MCDMA_COALESCE_SHIFT 16
211#define XILINX_MCDMA_COALESCE_MAX 24
212#define XILINX_MCDMA_IRQ_ALL_MASK GENMASK(7, 5)
213#define XILINX_MCDMA_COALESCE_MASK GENMASK(23, 16)
214#define XILINX_MCDMA_CR_RUNSTOP_MASK BIT(0)
215#define XILINX_MCDMA_IRQ_IOC_MASK BIT(5)
216#define XILINX_MCDMA_IRQ_DELAY_MASK BIT(6)
217#define XILINX_MCDMA_IRQ_ERR_MASK BIT(7)
218#define XILINX_MCDMA_BD_EOP BIT(30)
219#define XILINX_MCDMA_BD_SOP BIT(31)
220
221/**
222 * struct xilinx_vdma_desc_hw - Hardware Descriptor
223 * @next_desc: Next Descriptor Pointer @0x00
224 * @pad1: Reserved @0x04
225 * @buf_addr: Buffer address @0x08
226 * @buf_addr_msb: MSB of Buffer address @0x0C
227 * @vsize: Vertical Size @0x10
228 * @hsize: Horizontal Size @0x14
229 * @stride: Number of bytes between the first
230 * pixels of each horizontal line @0x18
231 */
232struct xilinx_vdma_desc_hw {
233 u32 next_desc;
234 u32 pad1;
235 u32 buf_addr;
236 u32 buf_addr_msb;
237 u32 vsize;
238 u32 hsize;
239 u32 stride;
240} __aligned(64);
241
242/**
243 * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA
244 * @next_desc: Next Descriptor Pointer @0x00
245 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04
246 * @buf_addr: Buffer address @0x08
247 * @buf_addr_msb: MSB of Buffer address @0x0C
248 * @reserved1: Reserved @0x10
249 * @reserved2: Reserved @0x14
250 * @control: Control field @0x18
251 * @status: Status field @0x1C
252 * @app: APP Fields @0x20 - 0x30
253 */
254struct xilinx_axidma_desc_hw {
255 u32 next_desc;
256 u32 next_desc_msb;
257 u32 buf_addr;
258 u32 buf_addr_msb;
259 u32 reserved1;
260 u32 reserved2;
261 u32 control;
262 u32 status;
263 u32 app[XILINX_DMA_NUM_APP_WORDS];
264} __aligned(64);
265
266/**
267 * struct xilinx_aximcdma_desc_hw - Hardware Descriptor for AXI MCDMA
268 * @next_desc: Next Descriptor Pointer @0x00
269 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04
270 * @buf_addr: Buffer address @0x08
271 * @buf_addr_msb: MSB of Buffer address @0x0C
272 * @rsvd: Reserved field @0x10
273 * @control: Control Information field @0x14
274 * @status: Status field @0x18
275 * @sideband_status: Status of sideband signals @0x1C
276 * @app: APP Fields @0x20 - 0x30
277 */
278struct xilinx_aximcdma_desc_hw {
279 u32 next_desc;
280 u32 next_desc_msb;
281 u32 buf_addr;
282 u32 buf_addr_msb;
283 u32 rsvd;
284 u32 control;
285 u32 status;
286 u32 sideband_status;
287 u32 app[XILINX_DMA_NUM_APP_WORDS];
288} __aligned(64);
289
290/**
291 * struct xilinx_cdma_desc_hw - Hardware Descriptor
292 * @next_desc: Next Descriptor Pointer @0x00
293 * @next_desc_msb: Next Descriptor Pointer MSB @0x04
294 * @src_addr: Source address @0x08
295 * @src_addr_msb: Source address MSB @0x0C
296 * @dest_addr: Destination address @0x10
297 * @dest_addr_msb: Destination address MSB @0x14
298 * @control: Control field @0x18
299 * @status: Status field @0x1C
300 */
301struct xilinx_cdma_desc_hw {
302 u32 next_desc;
303 u32 next_desc_msb;
304 u32 src_addr;
305 u32 src_addr_msb;
306 u32 dest_addr;
307 u32 dest_addr_msb;
308 u32 control;
309 u32 status;
310} __aligned(64);
311
312/**
313 * struct xilinx_vdma_tx_segment - Descriptor segment
314 * @hw: Hardware descriptor
315 * @node: Node in the descriptor segments list
316 * @phys: Physical address of segment
317 */
318struct xilinx_vdma_tx_segment {
319 struct xilinx_vdma_desc_hw hw;
320 struct list_head node;
321 dma_addr_t phys;
322} __aligned(64);
323
324/**
325 * struct xilinx_axidma_tx_segment - Descriptor segment
326 * @hw: Hardware descriptor
327 * @node: Node in the descriptor segments list
328 * @phys: Physical address of segment
329 */
330struct xilinx_axidma_tx_segment {
331 struct xilinx_axidma_desc_hw hw;
332 struct list_head node;
333 dma_addr_t phys;
334} __aligned(64);
335
336/**
337 * struct xilinx_aximcdma_tx_segment - Descriptor segment
338 * @hw: Hardware descriptor
339 * @node: Node in the descriptor segments list
340 * @phys: Physical address of segment
341 */
342struct xilinx_aximcdma_tx_segment {
343 struct xilinx_aximcdma_desc_hw hw;
344 struct list_head node;
345 dma_addr_t phys;
346} __aligned(64);
347
348/**
349 * struct xilinx_cdma_tx_segment - Descriptor segment
350 * @hw: Hardware descriptor
351 * @node: Node in the descriptor segments list
352 * @phys: Physical address of segment
353 */
354struct xilinx_cdma_tx_segment {
355 struct xilinx_cdma_desc_hw hw;
356 struct list_head node;
357 dma_addr_t phys;
358} __aligned(64);
359
360/**
361 * struct xilinx_dma_tx_descriptor - Per Transaction structure
362 * @async_tx: Async transaction descriptor
363 * @segments: TX segments list
364 * @node: Node in the channel descriptors list
365 * @cyclic: Check for cyclic transfers.
366 * @err: Whether the descriptor has an error.
367 * @residue: Residue of the completed descriptor
368 */
369struct xilinx_dma_tx_descriptor {
370 struct dma_async_tx_descriptor async_tx;
371 struct list_head segments;
372 struct list_head node;
373 bool cyclic;
374 bool err;
375 u32 residue;
376};
377
378/**
379 * struct xilinx_dma_chan - Driver specific DMA channel structure
380 * @xdev: Driver specific device structure
381 * @ctrl_offset: Control registers offset
382 * @desc_offset: TX descriptor registers offset
383 * @lock: Descriptor operation lock
384 * @pending_list: Descriptors waiting
385 * @active_list: Descriptors ready to submit
386 * @done_list: Complete descriptors
387 * @free_seg_list: Free descriptors
388 * @common: DMA common channel
389 * @desc_pool: Descriptors pool
390 * @dev: The dma device
391 * @irq: Channel IRQ
392 * @id: Channel ID
393 * @direction: Transfer direction
394 * @num_frms: Number of frames
395 * @has_sg: Support scatter transfers
396 * @cyclic: Check for cyclic transfers.
397 * @genlock: Support genlock mode
398 * @err: Channel has errors
399 * @idle: Check for channel idle
400 * @terminating: Check for channel being synchronized by user
401 * @tasklet: Cleanup work after irq
402 * @config: Device configuration info
403 * @flush_on_fsync: Flush on Frame sync
404 * @desc_pendingcount: Descriptor pending count
405 * @ext_addr: Indicates 64 bit addressing is supported by dma channel
406 * @desc_submitcount: Descriptor h/w submitted count
407 * @seg_v: Statically allocated segments base
408 * @seg_mv: Statically allocated segments base for MCDMA
409 * @seg_p: Physical allocated segments base
410 * @cyclic_seg_v: Statically allocated segment base for cyclic transfers
411 * @cyclic_seg_p: Physical allocated segments base for cyclic dma
412 * @start_transfer: Differentiate b/w DMA IP's transfer
413 * @stop_transfer: Differentiate b/w DMA IP's quiesce
414 * @tdest: TDEST value for mcdma
415 * @has_vflip: S2MM vertical flip
416 * @irq_delay: Interrupt delay timeout
417 */
418struct xilinx_dma_chan {
419 struct xilinx_dma_device *xdev;
420 u32 ctrl_offset;
421 u32 desc_offset;
422 spinlock_t lock;
423 struct list_head pending_list;
424 struct list_head active_list;
425 struct list_head done_list;
426 struct list_head free_seg_list;
427 struct dma_chan common;
428 struct dma_pool *desc_pool;
429 struct device *dev;
430 int irq;
431 int id;
432 enum dma_transfer_direction direction;
433 int num_frms;
434 bool has_sg;
435 bool cyclic;
436 bool genlock;
437 bool err;
438 bool idle;
439 bool terminating;
440 struct tasklet_struct tasklet;
441 struct xilinx_vdma_config config;
442 bool flush_on_fsync;
443 u32 desc_pendingcount;
444 bool ext_addr;
445 u32 desc_submitcount;
446 struct xilinx_axidma_tx_segment *seg_v;
447 struct xilinx_aximcdma_tx_segment *seg_mv;
448 dma_addr_t seg_p;
449 struct xilinx_axidma_tx_segment *cyclic_seg_v;
450 dma_addr_t cyclic_seg_p;
451 void (*start_transfer)(struct xilinx_dma_chan *chan);
452 int (*stop_transfer)(struct xilinx_dma_chan *chan);
453 u16 tdest;
454 bool has_vflip;
455 u8 irq_delay;
456};
457
458/**
459 * enum xdma_ip_type - DMA IP type.
460 *
461 * @XDMA_TYPE_AXIDMA: Axi dma ip.
462 * @XDMA_TYPE_CDMA: Axi cdma ip.
463 * @XDMA_TYPE_VDMA: Axi vdma ip.
464 * @XDMA_TYPE_AXIMCDMA: Axi MCDMA ip.
465 *
466 */
467enum xdma_ip_type {
468 XDMA_TYPE_AXIDMA = 0,
469 XDMA_TYPE_CDMA,
470 XDMA_TYPE_VDMA,
471 XDMA_TYPE_AXIMCDMA
472};
473
474struct xilinx_dma_config {
475 enum xdma_ip_type dmatype;
476 int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk,
477 struct clk **tx_clk, struct clk **txs_clk,
478 struct clk **rx_clk, struct clk **rxs_clk);
479 irqreturn_t (*irq_handler)(int irq, void *data);
480 const int max_channels;
481};
482
483/**
484 * struct xilinx_dma_device - DMA device structure
485 * @regs: I/O mapped base address
486 * @dev: Device Structure
487 * @common: DMA device structure
488 * @chan: Driver specific DMA channel
489 * @flush_on_fsync: Flush on frame sync
490 * @ext_addr: Indicates 64 bit addressing is supported by dma device
491 * @pdev: Platform device structure pointer
492 * @dma_config: DMA config structure
493 * @axi_clk: DMA Axi4-lite interace clock
494 * @tx_clk: DMA mm2s clock
495 * @txs_clk: DMA mm2s stream clock
496 * @rx_clk: DMA s2mm clock
497 * @rxs_clk: DMA s2mm stream clock
498 * @s2mm_chan_id: DMA s2mm channel identifier
499 * @mm2s_chan_id: DMA mm2s channel identifier
500 * @max_buffer_len: Max buffer length
501 * @has_axistream_connected: AXI DMA connected to AXI Stream IP
502 */
503struct xilinx_dma_device {
504 void __iomem *regs;
505 struct device *dev;
506 struct dma_device common;
507 struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE];
508 u32 flush_on_fsync;
509 bool ext_addr;
510 struct platform_device *pdev;
511 const struct xilinx_dma_config *dma_config;
512 struct clk *axi_clk;
513 struct clk *tx_clk;
514 struct clk *txs_clk;
515 struct clk *rx_clk;
516 struct clk *rxs_clk;
517 u32 s2mm_chan_id;
518 u32 mm2s_chan_id;
519 u32 max_buffer_len;
520 bool has_axistream_connected;
521};
522
523/* Macros */
524#define to_xilinx_chan(chan) \
525 container_of(chan, struct xilinx_dma_chan, common)
526#define to_dma_tx_descriptor(tx) \
527 container_of(tx, struct xilinx_dma_tx_descriptor, async_tx)
528#define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \
529 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
530 val, cond, delay_us, timeout_us)
531
532/* IO accessors */
533static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg)
534{
535 return ioread32(chan->xdev->regs + reg);
536}
537
538static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value)
539{
540 iowrite32(value, chan->xdev->regs + reg);
541}
542
543static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg,
544 u32 value)
545{
546 dma_write(chan, chan->desc_offset + reg, value);
547}
548
549static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg)
550{
551 return dma_read(chan, chan->ctrl_offset + reg);
552}
553
554static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,
555 u32 value)
556{
557 dma_write(chan, chan->ctrl_offset + reg, value);
558}
559
560static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg,
561 u32 clr)
562{
563 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);
564}
565
566static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg,
567 u32 set)
568{
569 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);
570}
571
572/**
573 * vdma_desc_write_64 - 64-bit descriptor write
574 * @chan: Driver specific VDMA channel
575 * @reg: Register to write
576 * @value_lsb: lower address of the descriptor.
577 * @value_msb: upper address of the descriptor.
578 *
579 * Since vdma driver is trying to write to a register offset which is not a
580 * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits
581 * instead of a single 64 bit register write.
582 */
583static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg,
584 u32 value_lsb, u32 value_msb)
585{
586 /* Write the lsb 32 bits*/
587 writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg);
588
589 /* Write the msb 32 bits */
590 writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4);
591}
592
593static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value)
594{
595 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg);
596}
597
598static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg,
599 dma_addr_t addr)
600{
601 if (chan->ext_addr)
602 dma_writeq(chan, reg, addr);
603 else
604 dma_ctrl_write(chan, reg, addr);
605}
606
607static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan,
608 struct xilinx_axidma_desc_hw *hw,
609 dma_addr_t buf_addr, size_t sg_used,
610 size_t period_len)
611{
612 if (chan->ext_addr) {
613 hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len);
614 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used +
615 period_len);
616 } else {
617 hw->buf_addr = buf_addr + sg_used + period_len;
618 }
619}
620
621static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan,
622 struct xilinx_aximcdma_desc_hw *hw,
623 dma_addr_t buf_addr, size_t sg_used)
624{
625 if (chan->ext_addr) {
626 hw->buf_addr = lower_32_bits(buf_addr + sg_used);
627 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used);
628 } else {
629 hw->buf_addr = buf_addr + sg_used;
630 }
631}
632
633/**
634 * xilinx_dma_get_metadata_ptr- Populate metadata pointer and payload length
635 * @tx: async transaction descriptor
636 * @payload_len: metadata payload length
637 * @max_len: metadata max length
638 * Return: The app field pointer.
639 */
640static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx,
641 size_t *payload_len, size_t *max_len)
642{
643 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
644 struct xilinx_axidma_tx_segment *seg;
645
646 *max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS;
647 seg = list_first_entry(&desc->segments,
648 struct xilinx_axidma_tx_segment, node);
649 return seg->hw.app;
650}
651
652static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = {
653 .get_ptr = xilinx_dma_get_metadata_ptr,
654};
655
656/* -----------------------------------------------------------------------------
657 * Descriptors and segments alloc and free
658 */
659
660/**
661 * xilinx_vdma_alloc_tx_segment - Allocate transaction segment
662 * @chan: Driver specific DMA channel
663 *
664 * Return: The allocated segment on success and NULL on failure.
665 */
666static struct xilinx_vdma_tx_segment *
667xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
668{
669 struct xilinx_vdma_tx_segment *segment;
670 dma_addr_t phys;
671
672 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
673 if (!segment)
674 return NULL;
675
676 segment->phys = phys;
677
678 return segment;
679}
680
681/**
682 * xilinx_cdma_alloc_tx_segment - Allocate transaction segment
683 * @chan: Driver specific DMA channel
684 *
685 * Return: The allocated segment on success and NULL on failure.
686 */
687static struct xilinx_cdma_tx_segment *
688xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
689{
690 struct xilinx_cdma_tx_segment *segment;
691 dma_addr_t phys;
692
693 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys);
694 if (!segment)
695 return NULL;
696
697 segment->phys = phys;
698
699 return segment;
700}
701
702/**
703 * xilinx_axidma_alloc_tx_segment - Allocate transaction segment
704 * @chan: Driver specific DMA channel
705 *
706 * Return: The allocated segment on success and NULL on failure.
707 */
708static struct xilinx_axidma_tx_segment *
709xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan)
710{
711 struct xilinx_axidma_tx_segment *segment = NULL;
712 unsigned long flags;
713
714 spin_lock_irqsave(&chan->lock, flags);
715 if (!list_empty(&chan->free_seg_list)) {
716 segment = list_first_entry(&chan->free_seg_list,
717 struct xilinx_axidma_tx_segment,
718 node);
719 list_del(&segment->node);
720 }
721 spin_unlock_irqrestore(&chan->lock, flags);
722
723 if (!segment)
724 dev_dbg(chan->dev, "Could not find free tx segment\n");
725
726 return segment;
727}
728
729/**
730 * xilinx_aximcdma_alloc_tx_segment - Allocate transaction segment
731 * @chan: Driver specific DMA channel
732 *
733 * Return: The allocated segment on success and NULL on failure.
734 */
735static struct xilinx_aximcdma_tx_segment *
736xilinx_aximcdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
737{
738 struct xilinx_aximcdma_tx_segment *segment = NULL;
739 unsigned long flags;
740
741 spin_lock_irqsave(&chan->lock, flags);
742 if (!list_empty(&chan->free_seg_list)) {
743 segment = list_first_entry(&chan->free_seg_list,
744 struct xilinx_aximcdma_tx_segment,
745 node);
746 list_del(&segment->node);
747 }
748 spin_unlock_irqrestore(&chan->lock, flags);
749
750 return segment;
751}
752
753static void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw)
754{
755 u32 next_desc = hw->next_desc;
756 u32 next_desc_msb = hw->next_desc_msb;
757
758 memset(hw, 0, sizeof(struct xilinx_axidma_desc_hw));
759
760 hw->next_desc = next_desc;
761 hw->next_desc_msb = next_desc_msb;
762}
763
764static void xilinx_mcdma_clean_hw_desc(struct xilinx_aximcdma_desc_hw *hw)
765{
766 u32 next_desc = hw->next_desc;
767 u32 next_desc_msb = hw->next_desc_msb;
768
769 memset(hw, 0, sizeof(struct xilinx_aximcdma_desc_hw));
770
771 hw->next_desc = next_desc;
772 hw->next_desc_msb = next_desc_msb;
773}
774
775/**
776 * xilinx_dma_free_tx_segment - Free transaction segment
777 * @chan: Driver specific DMA channel
778 * @segment: DMA transaction segment
779 */
780static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan,
781 struct xilinx_axidma_tx_segment *segment)
782{
783 xilinx_dma_clean_hw_desc(&segment->hw);
784
785 list_add_tail(&segment->node, &chan->free_seg_list);
786}
787
788/**
789 * xilinx_mcdma_free_tx_segment - Free transaction segment
790 * @chan: Driver specific DMA channel
791 * @segment: DMA transaction segment
792 */
793static void xilinx_mcdma_free_tx_segment(struct xilinx_dma_chan *chan,
794 struct xilinx_aximcdma_tx_segment *
795 segment)
796{
797 xilinx_mcdma_clean_hw_desc(&segment->hw);
798
799 list_add_tail(&segment->node, &chan->free_seg_list);
800}
801
802/**
803 * xilinx_cdma_free_tx_segment - Free transaction segment
804 * @chan: Driver specific DMA channel
805 * @segment: DMA transaction segment
806 */
807static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan,
808 struct xilinx_cdma_tx_segment *segment)
809{
810 dma_pool_free(chan->desc_pool, segment, segment->phys);
811}
812
813/**
814 * xilinx_vdma_free_tx_segment - Free transaction segment
815 * @chan: Driver specific DMA channel
816 * @segment: DMA transaction segment
817 */
818static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan,
819 struct xilinx_vdma_tx_segment *segment)
820{
821 dma_pool_free(chan->desc_pool, segment, segment->phys);
822}
823
824/**
825 * xilinx_dma_alloc_tx_descriptor - Allocate transaction descriptor
826 * @chan: Driver specific DMA channel
827 *
828 * Return: The allocated descriptor on success and NULL on failure.
829 */
830static struct xilinx_dma_tx_descriptor *
831xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan)
832{
833 struct xilinx_dma_tx_descriptor *desc;
834
835 desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
836 if (!desc)
837 return NULL;
838
839 INIT_LIST_HEAD(&desc->segments);
840
841 return desc;
842}
843
844/**
845 * xilinx_dma_free_tx_descriptor - Free transaction descriptor
846 * @chan: Driver specific DMA channel
847 * @desc: DMA transaction descriptor
848 */
849static void
850xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan,
851 struct xilinx_dma_tx_descriptor *desc)
852{
853 struct xilinx_vdma_tx_segment *segment, *next;
854 struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next;
855 struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next;
856 struct xilinx_aximcdma_tx_segment *aximcdma_segment, *aximcdma_next;
857
858 if (!desc)
859 return;
860
861 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
862 list_for_each_entry_safe(segment, next, &desc->segments, node) {
863 list_del(&segment->node);
864 xilinx_vdma_free_tx_segment(chan, segment);
865 }
866 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
867 list_for_each_entry_safe(cdma_segment, cdma_next,
868 &desc->segments, node) {
869 list_del(&cdma_segment->node);
870 xilinx_cdma_free_tx_segment(chan, cdma_segment);
871 }
872 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
873 list_for_each_entry_safe(axidma_segment, axidma_next,
874 &desc->segments, node) {
875 list_del(&axidma_segment->node);
876 xilinx_dma_free_tx_segment(chan, axidma_segment);
877 }
878 } else {
879 list_for_each_entry_safe(aximcdma_segment, aximcdma_next,
880 &desc->segments, node) {
881 list_del(&aximcdma_segment->node);
882 xilinx_mcdma_free_tx_segment(chan, aximcdma_segment);
883 }
884 }
885
886 kfree(desc);
887}
888
889/* Required functions */
890
891/**
892 * xilinx_dma_free_desc_list - Free descriptors list
893 * @chan: Driver specific DMA channel
894 * @list: List to parse and delete the descriptor
895 */
896static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan,
897 struct list_head *list)
898{
899 struct xilinx_dma_tx_descriptor *desc, *next;
900
901 list_for_each_entry_safe(desc, next, list, node) {
902 list_del(&desc->node);
903 xilinx_dma_free_tx_descriptor(chan, desc);
904 }
905}
906
907/**
908 * xilinx_dma_free_descriptors - Free channel descriptors
909 * @chan: Driver specific DMA channel
910 */
911static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan)
912{
913 unsigned long flags;
914
915 spin_lock_irqsave(&chan->lock, flags);
916
917 xilinx_dma_free_desc_list(chan, &chan->pending_list);
918 xilinx_dma_free_desc_list(chan, &chan->done_list);
919 xilinx_dma_free_desc_list(chan, &chan->active_list);
920
921 spin_unlock_irqrestore(&chan->lock, flags);
922}
923
924/**
925 * xilinx_dma_free_chan_resources - Free channel resources
926 * @dchan: DMA channel
927 */
928static void xilinx_dma_free_chan_resources(struct dma_chan *dchan)
929{
930 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
931 unsigned long flags;
932
933 dev_dbg(chan->dev, "Free all channel resources.\n");
934
935 xilinx_dma_free_descriptors(chan);
936
937 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
938 spin_lock_irqsave(&chan->lock, flags);
939 INIT_LIST_HEAD(&chan->free_seg_list);
940 spin_unlock_irqrestore(&chan->lock, flags);
941
942 /* Free memory that is allocated for BD */
943 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
944 XILINX_DMA_NUM_DESCS, chan->seg_v,
945 chan->seg_p);
946
947 /* Free Memory that is allocated for cyclic DMA Mode */
948 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v),
949 chan->cyclic_seg_v, chan->cyclic_seg_p);
950 }
951
952 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
953 spin_lock_irqsave(&chan->lock, flags);
954 INIT_LIST_HEAD(&chan->free_seg_list);
955 spin_unlock_irqrestore(&chan->lock, flags);
956
957 /* Free memory that is allocated for BD */
958 dma_free_coherent(chan->dev, sizeof(*chan->seg_mv) *
959 XILINX_DMA_NUM_DESCS, chan->seg_mv,
960 chan->seg_p);
961 }
962
963 if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA &&
964 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) {
965 dma_pool_destroy(chan->desc_pool);
966 chan->desc_pool = NULL;
967 }
968
969}
970
971/**
972 * xilinx_dma_get_residue - Compute residue for a given descriptor
973 * @chan: Driver specific dma channel
974 * @desc: dma transaction descriptor
975 *
976 * Return: The number of residue bytes for the descriptor.
977 */
978static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan,
979 struct xilinx_dma_tx_descriptor *desc)
980{
981 struct xilinx_cdma_tx_segment *cdma_seg;
982 struct xilinx_axidma_tx_segment *axidma_seg;
983 struct xilinx_aximcdma_tx_segment *aximcdma_seg;
984 struct xilinx_cdma_desc_hw *cdma_hw;
985 struct xilinx_axidma_desc_hw *axidma_hw;
986 struct xilinx_aximcdma_desc_hw *aximcdma_hw;
987 struct list_head *entry;
988 u32 residue = 0;
989
990 list_for_each(entry, &desc->segments) {
991 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
992 cdma_seg = list_entry(entry,
993 struct xilinx_cdma_tx_segment,
994 node);
995 cdma_hw = &cdma_seg->hw;
996 residue += (cdma_hw->control - cdma_hw->status) &
997 chan->xdev->max_buffer_len;
998 } else if (chan->xdev->dma_config->dmatype ==
999 XDMA_TYPE_AXIDMA) {
1000 axidma_seg = list_entry(entry,
1001 struct xilinx_axidma_tx_segment,
1002 node);
1003 axidma_hw = &axidma_seg->hw;
1004 residue += (axidma_hw->control - axidma_hw->status) &
1005 chan->xdev->max_buffer_len;
1006 } else {
1007 aximcdma_seg =
1008 list_entry(entry,
1009 struct xilinx_aximcdma_tx_segment,
1010 node);
1011 aximcdma_hw = &aximcdma_seg->hw;
1012 residue +=
1013 (aximcdma_hw->control - aximcdma_hw->status) &
1014 chan->xdev->max_buffer_len;
1015 }
1016 }
1017
1018 return residue;
1019}
1020
1021/**
1022 * xilinx_dma_chan_handle_cyclic - Cyclic dma callback
1023 * @chan: Driver specific dma channel
1024 * @desc: dma transaction descriptor
1025 * @flags: flags for spin lock
1026 */
1027static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan,
1028 struct xilinx_dma_tx_descriptor *desc,
1029 unsigned long *flags)
1030{
1031 struct dmaengine_desc_callback cb;
1032
1033 dmaengine_desc_get_callback(&desc->async_tx, &cb);
1034 if (dmaengine_desc_callback_valid(&cb)) {
1035 spin_unlock_irqrestore(&chan->lock, *flags);
1036 dmaengine_desc_callback_invoke(&cb, NULL);
1037 spin_lock_irqsave(&chan->lock, *flags);
1038 }
1039}
1040
1041/**
1042 * xilinx_dma_chan_desc_cleanup - Clean channel descriptors
1043 * @chan: Driver specific DMA channel
1044 */
1045static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan)
1046{
1047 struct xilinx_dma_tx_descriptor *desc, *next;
1048 unsigned long flags;
1049
1050 spin_lock_irqsave(&chan->lock, flags);
1051
1052 list_for_each_entry_safe(desc, next, &chan->done_list, node) {
1053 struct dmaengine_result result;
1054
1055 if (desc->cyclic) {
1056 xilinx_dma_chan_handle_cyclic(chan, desc, &flags);
1057 break;
1058 }
1059
1060 /* Remove from the list of running transactions */
1061 list_del(&desc->node);
1062
1063 if (unlikely(desc->err)) {
1064 if (chan->direction == DMA_DEV_TO_MEM)
1065 result.result = DMA_TRANS_READ_FAILED;
1066 else
1067 result.result = DMA_TRANS_WRITE_FAILED;
1068 } else {
1069 result.result = DMA_TRANS_NOERROR;
1070 }
1071
1072 result.residue = desc->residue;
1073
1074 /* Run the link descriptor callback function */
1075 spin_unlock_irqrestore(&chan->lock, flags);
1076 dmaengine_desc_get_callback_invoke(&desc->async_tx, &result);
1077 spin_lock_irqsave(&chan->lock, flags);
1078
1079 /* Run any dependencies, then free the descriptor */
1080 dma_run_dependencies(&desc->async_tx);
1081 xilinx_dma_free_tx_descriptor(chan, desc);
1082
1083 /*
1084 * While we ran a callback the user called a terminate function,
1085 * which takes care of cleaning up any remaining descriptors
1086 */
1087 if (chan->terminating)
1088 break;
1089 }
1090
1091 spin_unlock_irqrestore(&chan->lock, flags);
1092}
1093
1094/**
1095 * xilinx_dma_do_tasklet - Schedule completion tasklet
1096 * @t: Pointer to the Xilinx DMA channel structure
1097 */
1098static void xilinx_dma_do_tasklet(struct tasklet_struct *t)
1099{
1100 struct xilinx_dma_chan *chan = from_tasklet(chan, t, tasklet);
1101
1102 xilinx_dma_chan_desc_cleanup(chan);
1103}
1104
1105/**
1106 * xilinx_dma_alloc_chan_resources - Allocate channel resources
1107 * @dchan: DMA channel
1108 *
1109 * Return: '0' on success and failure value on error
1110 */
1111static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
1112{
1113 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1114 int i;
1115
1116 /* Has this channel already been allocated? */
1117 if (chan->desc_pool)
1118 return 0;
1119
1120 /*
1121 * We need the descriptor to be aligned to 64bytes
1122 * for meeting Xilinx VDMA specification requirement.
1123 */
1124 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1125 /* Allocate the buffer descriptors. */
1126 chan->seg_v = dma_alloc_coherent(chan->dev,
1127 sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS,
1128 &chan->seg_p, GFP_KERNEL);
1129 if (!chan->seg_v) {
1130 dev_err(chan->dev,
1131 "unable to allocate channel %d descriptors\n",
1132 chan->id);
1133 return -ENOMEM;
1134 }
1135 /*
1136 * For cyclic DMA mode we need to program the tail Descriptor
1137 * register with a value which is not a part of the BD chain
1138 * so allocating a desc segment during channel allocation for
1139 * programming tail descriptor.
1140 */
1141 chan->cyclic_seg_v = dma_alloc_coherent(chan->dev,
1142 sizeof(*chan->cyclic_seg_v),
1143 &chan->cyclic_seg_p,
1144 GFP_KERNEL);
1145 if (!chan->cyclic_seg_v) {
1146 dev_err(chan->dev,
1147 "unable to allocate desc segment for cyclic DMA\n");
1148 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) *
1149 XILINX_DMA_NUM_DESCS, chan->seg_v,
1150 chan->seg_p);
1151 return -ENOMEM;
1152 }
1153 chan->cyclic_seg_v->phys = chan->cyclic_seg_p;
1154
1155 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
1156 chan->seg_v[i].hw.next_desc =
1157 lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
1158 ((i + 1) % XILINX_DMA_NUM_DESCS));
1159 chan->seg_v[i].hw.next_desc_msb =
1160 upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) *
1161 ((i + 1) % XILINX_DMA_NUM_DESCS));
1162 chan->seg_v[i].phys = chan->seg_p +
1163 sizeof(*chan->seg_v) * i;
1164 list_add_tail(&chan->seg_v[i].node,
1165 &chan->free_seg_list);
1166 }
1167 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
1168 /* Allocate the buffer descriptors. */
1169 chan->seg_mv = dma_alloc_coherent(chan->dev,
1170 sizeof(*chan->seg_mv) *
1171 XILINX_DMA_NUM_DESCS,
1172 &chan->seg_p, GFP_KERNEL);
1173 if (!chan->seg_mv) {
1174 dev_err(chan->dev,
1175 "unable to allocate channel %d descriptors\n",
1176 chan->id);
1177 return -ENOMEM;
1178 }
1179 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) {
1180 chan->seg_mv[i].hw.next_desc =
1181 lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) *
1182 ((i + 1) % XILINX_DMA_NUM_DESCS));
1183 chan->seg_mv[i].hw.next_desc_msb =
1184 upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) *
1185 ((i + 1) % XILINX_DMA_NUM_DESCS));
1186 chan->seg_mv[i].phys = chan->seg_p +
1187 sizeof(*chan->seg_mv) * i;
1188 list_add_tail(&chan->seg_mv[i].node,
1189 &chan->free_seg_list);
1190 }
1191 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
1192 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool",
1193 chan->dev,
1194 sizeof(struct xilinx_cdma_tx_segment),
1195 __alignof__(struct xilinx_cdma_tx_segment),
1196 0);
1197 } else {
1198 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool",
1199 chan->dev,
1200 sizeof(struct xilinx_vdma_tx_segment),
1201 __alignof__(struct xilinx_vdma_tx_segment),
1202 0);
1203 }
1204
1205 if (!chan->desc_pool &&
1206 ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) &&
1207 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) {
1208 dev_err(chan->dev,
1209 "unable to allocate channel %d descriptor pool\n",
1210 chan->id);
1211 return -ENOMEM;
1212 }
1213
1214 dma_cookie_init(dchan);
1215
1216 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1217 /* For AXI DMA resetting once channel will reset the
1218 * other channel as well so enable the interrupts here.
1219 */
1220 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1221 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1222 }
1223
1224 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
1225 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1226 XILINX_CDMA_CR_SGMODE);
1227
1228 return 0;
1229}
1230
1231/**
1232 * xilinx_dma_calc_copysize - Calculate the amount of data to copy
1233 * @chan: Driver specific DMA channel
1234 * @size: Total data that needs to be copied
1235 * @done: Amount of data that has been already copied
1236 *
1237 * Return: Amount of data that has to be copied
1238 */
1239static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan,
1240 int size, int done)
1241{
1242 size_t copy;
1243
1244 copy = min_t(size_t, size - done,
1245 chan->xdev->max_buffer_len);
1246
1247 if ((copy + done < size) &&
1248 chan->xdev->common.copy_align) {
1249 /*
1250 * If this is not the last descriptor, make sure
1251 * the next one will be properly aligned
1252 */
1253 copy = rounddown(copy,
1254 (1 << chan->xdev->common.copy_align));
1255 }
1256 return copy;
1257}
1258
1259/**
1260 * xilinx_dma_tx_status - Get DMA transaction status
1261 * @dchan: DMA channel
1262 * @cookie: Transaction identifier
1263 * @txstate: Transaction state
1264 *
1265 * Return: DMA transaction status
1266 */
1267static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
1268 dma_cookie_t cookie,
1269 struct dma_tx_state *txstate)
1270{
1271 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1272 struct xilinx_dma_tx_descriptor *desc;
1273 enum dma_status ret;
1274 unsigned long flags;
1275 u32 residue = 0;
1276
1277 ret = dma_cookie_status(dchan, cookie, txstate);
1278 if (ret == DMA_COMPLETE || !txstate)
1279 return ret;
1280
1281 spin_lock_irqsave(&chan->lock, flags);
1282 if (!list_empty(&chan->active_list)) {
1283 desc = list_last_entry(&chan->active_list,
1284 struct xilinx_dma_tx_descriptor, node);
1285 /*
1286 * VDMA and simple mode do not support residue reporting, so the
1287 * residue field will always be 0.
1288 */
1289 if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA)
1290 residue = xilinx_dma_get_residue(chan, desc);
1291 }
1292 spin_unlock_irqrestore(&chan->lock, flags);
1293
1294 dma_set_residue(txstate, residue);
1295
1296 return ret;
1297}
1298
1299/**
1300 * xilinx_dma_stop_transfer - Halt DMA channel
1301 * @chan: Driver specific DMA channel
1302 *
1303 * Return: '0' on success and failure value on error
1304 */
1305static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan)
1306{
1307 u32 val;
1308
1309 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
1310
1311 /* Wait for the hardware to halt */
1312 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1313 val & XILINX_DMA_DMASR_HALTED, 0,
1314 XILINX_DMA_LOOP_COUNT);
1315}
1316
1317/**
1318 * xilinx_cdma_stop_transfer - Wait for the current transfer to complete
1319 * @chan: Driver specific DMA channel
1320 *
1321 * Return: '0' on success and failure value on error
1322 */
1323static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan)
1324{
1325 u32 val;
1326
1327 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1328 val & XILINX_DMA_DMASR_IDLE, 0,
1329 XILINX_DMA_LOOP_COUNT);
1330}
1331
1332/**
1333 * xilinx_dma_start - Start DMA channel
1334 * @chan: Driver specific DMA channel
1335 */
1336static void xilinx_dma_start(struct xilinx_dma_chan *chan)
1337{
1338 int err;
1339 u32 val;
1340
1341 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
1342
1343 /* Wait for the hardware to start */
1344 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
1345 !(val & XILINX_DMA_DMASR_HALTED), 0,
1346 XILINX_DMA_LOOP_COUNT);
1347
1348 if (err) {
1349 dev_err(chan->dev, "Cannot start channel %p: %x\n",
1350 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1351
1352 chan->err = true;
1353 }
1354}
1355
1356/**
1357 * xilinx_vdma_start_transfer - Starts VDMA transfer
1358 * @chan: Driver specific channel struct pointer
1359 */
1360static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
1361{
1362 struct xilinx_vdma_config *config = &chan->config;
1363 struct xilinx_dma_tx_descriptor *desc;
1364 u32 reg, j;
1365 struct xilinx_vdma_tx_segment *segment, *last = NULL;
1366 int i = 0;
1367
1368 /* This function was invoked with lock held */
1369 if (chan->err)
1370 return;
1371
1372 if (!chan->idle)
1373 return;
1374
1375 if (list_empty(&chan->pending_list))
1376 return;
1377
1378 desc = list_first_entry(&chan->pending_list,
1379 struct xilinx_dma_tx_descriptor, node);
1380
1381 /* Configure the hardware using info in the config structure */
1382 if (chan->has_vflip) {
1383 reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP);
1384 reg &= ~XILINX_VDMA_ENABLE_VERTICAL_FLIP;
1385 reg |= config->vflip_en;
1386 dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP,
1387 reg);
1388 }
1389
1390 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1391
1392 if (config->frm_cnt_en)
1393 reg |= XILINX_DMA_DMACR_FRAMECNT_EN;
1394 else
1395 reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN;
1396
1397 /* If not parking, enable circular mode */
1398 if (config->park)
1399 reg &= ~XILINX_DMA_DMACR_CIRC_EN;
1400 else
1401 reg |= XILINX_DMA_DMACR_CIRC_EN;
1402
1403 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1404
1405 j = chan->desc_submitcount;
1406 reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR);
1407 if (chan->direction == DMA_MEM_TO_DEV) {
1408 reg &= ~XILINX_DMA_PARK_PTR_RD_REF_MASK;
1409 reg |= j << XILINX_DMA_PARK_PTR_RD_REF_SHIFT;
1410 } else {
1411 reg &= ~XILINX_DMA_PARK_PTR_WR_REF_MASK;
1412 reg |= j << XILINX_DMA_PARK_PTR_WR_REF_SHIFT;
1413 }
1414 dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg);
1415
1416 /* Start the hardware */
1417 xilinx_dma_start(chan);
1418
1419 if (chan->err)
1420 return;
1421
1422 /* Start the transfer */
1423 if (chan->desc_submitcount < chan->num_frms)
1424 i = chan->desc_submitcount;
1425
1426 list_for_each_entry(segment, &desc->segments, node) {
1427 if (chan->ext_addr)
1428 vdma_desc_write_64(chan,
1429 XILINX_VDMA_REG_START_ADDRESS_64(i++),
1430 segment->hw.buf_addr,
1431 segment->hw.buf_addr_msb);
1432 else
1433 vdma_desc_write(chan,
1434 XILINX_VDMA_REG_START_ADDRESS(i++),
1435 segment->hw.buf_addr);
1436
1437 last = segment;
1438 }
1439
1440 if (!last)
1441 return;
1442
1443 /* HW expects these parameters to be same for one transaction */
1444 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize);
1445 vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE,
1446 last->hw.stride);
1447 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize);
1448
1449 chan->desc_submitcount++;
1450 chan->desc_pendingcount--;
1451 list_move_tail(&desc->node, &chan->active_list);
1452 if (chan->desc_submitcount == chan->num_frms)
1453 chan->desc_submitcount = 0;
1454
1455 chan->idle = false;
1456}
1457
1458/**
1459 * xilinx_cdma_start_transfer - Starts cdma transfer
1460 * @chan: Driver specific channel struct pointer
1461 */
1462static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
1463{
1464 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1465 struct xilinx_cdma_tx_segment *tail_segment;
1466 u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR);
1467
1468 if (chan->err)
1469 return;
1470
1471 if (!chan->idle)
1472 return;
1473
1474 if (list_empty(&chan->pending_list))
1475 return;
1476
1477 head_desc = list_first_entry(&chan->pending_list,
1478 struct xilinx_dma_tx_descriptor, node);
1479 tail_desc = list_last_entry(&chan->pending_list,
1480 struct xilinx_dma_tx_descriptor, node);
1481 tail_segment = list_last_entry(&tail_desc->segments,
1482 struct xilinx_cdma_tx_segment, node);
1483
1484 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1485 ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1486 ctrl_reg |= chan->desc_pendingcount <<
1487 XILINX_DMA_CR_COALESCE_SHIFT;
1488 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);
1489 }
1490
1491 if (chan->has_sg) {
1492 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
1493 XILINX_CDMA_CR_SGMODE);
1494
1495 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1496 XILINX_CDMA_CR_SGMODE);
1497
1498 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1499 head_desc->async_tx.phys);
1500
1501 /* Update tail ptr register which will start the transfer */
1502 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1503 tail_segment->phys);
1504 } else {
1505 /* In simple mode */
1506 struct xilinx_cdma_tx_segment *segment;
1507 struct xilinx_cdma_desc_hw *hw;
1508
1509 segment = list_first_entry(&head_desc->segments,
1510 struct xilinx_cdma_tx_segment,
1511 node);
1512
1513 hw = &segment->hw;
1514
1515 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR,
1516 xilinx_prep_dma_addr_t(hw->src_addr));
1517 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR,
1518 xilinx_prep_dma_addr_t(hw->dest_addr));
1519
1520 /* Start the transfer */
1521 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1522 hw->control & chan->xdev->max_buffer_len);
1523 }
1524
1525 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1526 chan->desc_pendingcount = 0;
1527 chan->idle = false;
1528}
1529
1530/**
1531 * xilinx_dma_start_transfer - Starts DMA transfer
1532 * @chan: Driver specific channel struct pointer
1533 */
1534static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
1535{
1536 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1537 struct xilinx_axidma_tx_segment *tail_segment;
1538 u32 reg;
1539
1540 if (chan->err)
1541 return;
1542
1543 if (list_empty(&chan->pending_list))
1544 return;
1545
1546 if (!chan->idle)
1547 return;
1548
1549 head_desc = list_first_entry(&chan->pending_list,
1550 struct xilinx_dma_tx_descriptor, node);
1551 tail_desc = list_last_entry(&chan->pending_list,
1552 struct xilinx_dma_tx_descriptor, node);
1553 tail_segment = list_last_entry(&tail_desc->segments,
1554 struct xilinx_axidma_tx_segment, node);
1555
1556 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
1557
1558 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
1559 reg &= ~XILINX_DMA_CR_COALESCE_MAX;
1560 reg |= chan->desc_pendingcount <<
1561 XILINX_DMA_CR_COALESCE_SHIFT;
1562 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1563 }
1564
1565 if (chan->has_sg)
1566 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
1567 head_desc->async_tx.phys);
1568 reg &= ~XILINX_DMA_CR_DELAY_MAX;
1569 reg |= chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT;
1570 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
1571
1572 xilinx_dma_start(chan);
1573
1574 if (chan->err)
1575 return;
1576
1577 /* Start the transfer */
1578 if (chan->has_sg) {
1579 if (chan->cyclic)
1580 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1581 chan->cyclic_seg_v->phys);
1582 else
1583 xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
1584 tail_segment->phys);
1585 } else {
1586 struct xilinx_axidma_tx_segment *segment;
1587 struct xilinx_axidma_desc_hw *hw;
1588
1589 segment = list_first_entry(&head_desc->segments,
1590 struct xilinx_axidma_tx_segment,
1591 node);
1592 hw = &segment->hw;
1593
1594 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR,
1595 xilinx_prep_dma_addr_t(hw->buf_addr));
1596
1597 /* Start the transfer */
1598 dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
1599 hw->control & chan->xdev->max_buffer_len);
1600 }
1601
1602 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1603 chan->desc_pendingcount = 0;
1604 chan->idle = false;
1605}
1606
1607/**
1608 * xilinx_mcdma_start_transfer - Starts MCDMA transfer
1609 * @chan: Driver specific channel struct pointer
1610 */
1611static void xilinx_mcdma_start_transfer(struct xilinx_dma_chan *chan)
1612{
1613 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc;
1614 struct xilinx_aximcdma_tx_segment *tail_segment;
1615 u32 reg;
1616
1617 /*
1618 * lock has been held by calling functions, so we don't need it
1619 * to take it here again.
1620 */
1621
1622 if (chan->err)
1623 return;
1624
1625 if (!chan->idle)
1626 return;
1627
1628 if (list_empty(&chan->pending_list))
1629 return;
1630
1631 head_desc = list_first_entry(&chan->pending_list,
1632 struct xilinx_dma_tx_descriptor, node);
1633 tail_desc = list_last_entry(&chan->pending_list,
1634 struct xilinx_dma_tx_descriptor, node);
1635 tail_segment = list_last_entry(&tail_desc->segments,
1636 struct xilinx_aximcdma_tx_segment, node);
1637
1638 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest));
1639
1640 if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) {
1641 reg &= ~XILINX_MCDMA_COALESCE_MASK;
1642 reg |= chan->desc_pendingcount <<
1643 XILINX_MCDMA_COALESCE_SHIFT;
1644 }
1645
1646 reg |= XILINX_MCDMA_IRQ_ALL_MASK;
1647 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);
1648
1649 /* Program current descriptor */
1650 xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest),
1651 head_desc->async_tx.phys);
1652
1653 /* Program channel enable register */
1654 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET);
1655 reg |= BIT(chan->tdest);
1656 dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg);
1657
1658 /* Start the fetch of BDs for the channel */
1659 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest));
1660 reg |= XILINX_MCDMA_CR_RUNSTOP_MASK;
1661 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);
1662
1663 xilinx_dma_start(chan);
1664
1665 if (chan->err)
1666 return;
1667
1668 /* Start the transfer */
1669 xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest),
1670 tail_segment->phys);
1671
1672 list_splice_tail_init(&chan->pending_list, &chan->active_list);
1673 chan->desc_pendingcount = 0;
1674 chan->idle = false;
1675}
1676
1677/**
1678 * xilinx_dma_issue_pending - Issue pending transactions
1679 * @dchan: DMA channel
1680 */
1681static void xilinx_dma_issue_pending(struct dma_chan *dchan)
1682{
1683 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
1684 unsigned long flags;
1685
1686 spin_lock_irqsave(&chan->lock, flags);
1687 chan->start_transfer(chan);
1688 spin_unlock_irqrestore(&chan->lock, flags);
1689}
1690
1691/**
1692 * xilinx_dma_device_config - Configure the DMA channel
1693 * @dchan: DMA channel
1694 * @config: channel configuration
1695 *
1696 * Return: 0 always.
1697 */
1698static int xilinx_dma_device_config(struct dma_chan *dchan,
1699 struct dma_slave_config *config)
1700{
1701 return 0;
1702}
1703
1704/**
1705 * xilinx_dma_complete_descriptor - Mark the active descriptor as complete
1706 * @chan : xilinx DMA channel
1707 *
1708 * CONTEXT: hardirq
1709 */
1710static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
1711{
1712 struct xilinx_dma_tx_descriptor *desc, *next;
1713
1714 /* This function was invoked with lock held */
1715 if (list_empty(&chan->active_list))
1716 return;
1717
1718 list_for_each_entry_safe(desc, next, &chan->active_list, node) {
1719 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1720 struct xilinx_axidma_tx_segment *seg;
1721
1722 seg = list_last_entry(&desc->segments,
1723 struct xilinx_axidma_tx_segment, node);
1724 if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg)
1725 break;
1726 }
1727 if (chan->has_sg && chan->xdev->dma_config->dmatype !=
1728 XDMA_TYPE_VDMA)
1729 desc->residue = xilinx_dma_get_residue(chan, desc);
1730 else
1731 desc->residue = 0;
1732 desc->err = chan->err;
1733
1734 list_del(&desc->node);
1735 if (!desc->cyclic)
1736 dma_cookie_complete(&desc->async_tx);
1737 list_add_tail(&desc->node, &chan->done_list);
1738 }
1739}
1740
1741/**
1742 * xilinx_dma_reset - Reset DMA channel
1743 * @chan: Driver specific DMA channel
1744 *
1745 * Return: '0' on success and failure value on error
1746 */
1747static int xilinx_dma_reset(struct xilinx_dma_chan *chan)
1748{
1749 int err;
1750 u32 tmp;
1751
1752 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET);
1753
1754 /* Wait for the hardware to finish reset */
1755 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp,
1756 !(tmp & XILINX_DMA_DMACR_RESET), 0,
1757 XILINX_DMA_LOOP_COUNT);
1758
1759 if (err) {
1760 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n",
1761 dma_ctrl_read(chan, XILINX_DMA_REG_DMACR),
1762 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
1763 return -ETIMEDOUT;
1764 }
1765
1766 chan->err = false;
1767 chan->idle = true;
1768 chan->desc_pendingcount = 0;
1769 chan->desc_submitcount = 0;
1770
1771 return err;
1772}
1773
1774/**
1775 * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts
1776 * @chan: Driver specific DMA channel
1777 *
1778 * Return: '0' on success and failure value on error
1779 */
1780static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan)
1781{
1782 int err;
1783
1784 /* Reset VDMA */
1785 err = xilinx_dma_reset(chan);
1786 if (err)
1787 return err;
1788
1789 /* Enable interrupts */
1790 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
1791 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1792
1793 return 0;
1794}
1795
1796/**
1797 * xilinx_mcdma_irq_handler - MCDMA Interrupt handler
1798 * @irq: IRQ number
1799 * @data: Pointer to the Xilinx MCDMA channel structure
1800 *
1801 * Return: IRQ_HANDLED/IRQ_NONE
1802 */
1803static irqreturn_t xilinx_mcdma_irq_handler(int irq, void *data)
1804{
1805 struct xilinx_dma_chan *chan = data;
1806 u32 status, ser_offset, chan_sermask, chan_offset = 0, chan_id;
1807
1808 if (chan->direction == DMA_DEV_TO_MEM)
1809 ser_offset = XILINX_MCDMA_RXINT_SER_OFFSET;
1810 else
1811 ser_offset = XILINX_MCDMA_TXINT_SER_OFFSET;
1812
1813 /* Read the channel id raising the interrupt*/
1814 chan_sermask = dma_ctrl_read(chan, ser_offset);
1815 chan_id = ffs(chan_sermask);
1816
1817 if (!chan_id)
1818 return IRQ_NONE;
1819
1820 if (chan->direction == DMA_DEV_TO_MEM)
1821 chan_offset = chan->xdev->dma_config->max_channels / 2;
1822
1823 chan_offset = chan_offset + (chan_id - 1);
1824 chan = chan->xdev->chan[chan_offset];
1825 /* Read the status and ack the interrupts. */
1826 status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest));
1827 if (!(status & XILINX_MCDMA_IRQ_ALL_MASK))
1828 return IRQ_NONE;
1829
1830 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest),
1831 status & XILINX_MCDMA_IRQ_ALL_MASK);
1832
1833 if (status & XILINX_MCDMA_IRQ_ERR_MASK) {
1834 dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n",
1835 chan,
1836 dma_ctrl_read(chan, XILINX_MCDMA_CH_ERR_OFFSET),
1837 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET
1838 (chan->tdest)),
1839 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET
1840 (chan->tdest)));
1841 chan->err = true;
1842 }
1843
1844 if (status & XILINX_MCDMA_IRQ_DELAY_MASK) {
1845 /*
1846 * Device takes too long to do the transfer when user requires
1847 * responsiveness.
1848 */
1849 dev_dbg(chan->dev, "Inter-packet latency too long\n");
1850 }
1851
1852 if (status & XILINX_MCDMA_IRQ_IOC_MASK) {
1853 spin_lock(&chan->lock);
1854 xilinx_dma_complete_descriptor(chan);
1855 chan->idle = true;
1856 chan->start_transfer(chan);
1857 spin_unlock(&chan->lock);
1858 }
1859
1860 tasklet_hi_schedule(&chan->tasklet);
1861 return IRQ_HANDLED;
1862}
1863
1864/**
1865 * xilinx_dma_irq_handler - DMA Interrupt handler
1866 * @irq: IRQ number
1867 * @data: Pointer to the Xilinx DMA channel structure
1868 *
1869 * Return: IRQ_HANDLED/IRQ_NONE
1870 */
1871static irqreturn_t xilinx_dma_irq_handler(int irq, void *data)
1872{
1873 struct xilinx_dma_chan *chan = data;
1874 u32 status;
1875
1876 /* Read the status and ack the interrupts. */
1877 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR);
1878 if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK))
1879 return IRQ_NONE;
1880
1881 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1882 status & XILINX_DMA_DMAXR_ALL_IRQ_MASK);
1883
1884 if (status & XILINX_DMA_DMASR_ERR_IRQ) {
1885 /*
1886 * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the
1887 * error is recoverable, ignore it. Otherwise flag the error.
1888 *
1889 * Only recoverable errors can be cleared in the DMASR register,
1890 * make sure not to write to other error bits to 1.
1891 */
1892 u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK;
1893
1894 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
1895 errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK);
1896
1897 if (!chan->flush_on_fsync ||
1898 (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) {
1899 dev_err(chan->dev,
1900 "Channel %p has errors %x, cdr %x tdr %x\n",
1901 chan, errors,
1902 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC),
1903 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC));
1904 chan->err = true;
1905 }
1906 }
1907
1908 if (status & (XILINX_DMA_DMASR_FRM_CNT_IRQ |
1909 XILINX_DMA_DMASR_DLY_CNT_IRQ)) {
1910 spin_lock(&chan->lock);
1911 xilinx_dma_complete_descriptor(chan);
1912 chan->idle = true;
1913 chan->start_transfer(chan);
1914 spin_unlock(&chan->lock);
1915 }
1916
1917 tasklet_schedule(&chan->tasklet);
1918 return IRQ_HANDLED;
1919}
1920
1921/**
1922 * append_desc_queue - Queuing descriptor
1923 * @chan: Driver specific dma channel
1924 * @desc: dma transaction descriptor
1925 */
1926static void append_desc_queue(struct xilinx_dma_chan *chan,
1927 struct xilinx_dma_tx_descriptor *desc)
1928{
1929 struct xilinx_vdma_tx_segment *tail_segment;
1930 struct xilinx_dma_tx_descriptor *tail_desc;
1931 struct xilinx_axidma_tx_segment *axidma_tail_segment;
1932 struct xilinx_aximcdma_tx_segment *aximcdma_tail_segment;
1933 struct xilinx_cdma_tx_segment *cdma_tail_segment;
1934
1935 if (list_empty(&chan->pending_list))
1936 goto append;
1937
1938 /*
1939 * Add the hardware descriptor to the chain of hardware descriptors
1940 * that already exists in memory.
1941 */
1942 tail_desc = list_last_entry(&chan->pending_list,
1943 struct xilinx_dma_tx_descriptor, node);
1944 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
1945 tail_segment = list_last_entry(&tail_desc->segments,
1946 struct xilinx_vdma_tx_segment,
1947 node);
1948 tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1949 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
1950 cdma_tail_segment = list_last_entry(&tail_desc->segments,
1951 struct xilinx_cdma_tx_segment,
1952 node);
1953 cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1954 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
1955 axidma_tail_segment = list_last_entry(&tail_desc->segments,
1956 struct xilinx_axidma_tx_segment,
1957 node);
1958 axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1959 } else {
1960 aximcdma_tail_segment =
1961 list_last_entry(&tail_desc->segments,
1962 struct xilinx_aximcdma_tx_segment,
1963 node);
1964 aximcdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
1965 }
1966
1967 /*
1968 * Add the software descriptor and all children to the list
1969 * of pending transactions
1970 */
1971append:
1972 list_add_tail(&desc->node, &chan->pending_list);
1973 chan->desc_pendingcount++;
1974
1975 if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA)
1976 && unlikely(chan->desc_pendingcount > chan->num_frms)) {
1977 dev_dbg(chan->dev, "desc pendingcount is too high\n");
1978 chan->desc_pendingcount = chan->num_frms;
1979 }
1980}
1981
1982/**
1983 * xilinx_dma_tx_submit - Submit DMA transaction
1984 * @tx: Async transaction descriptor
1985 *
1986 * Return: cookie value on success and failure value on error
1987 */
1988static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
1989{
1990 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
1991 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan);
1992 dma_cookie_t cookie;
1993 unsigned long flags;
1994 int err;
1995
1996 if (chan->cyclic) {
1997 xilinx_dma_free_tx_descriptor(chan, desc);
1998 return -EBUSY;
1999 }
2000
2001 if (chan->err) {
2002 /*
2003 * If reset fails, need to hard reset the system.
2004 * Channel is no longer functional
2005 */
2006 err = xilinx_dma_chan_reset(chan);
2007 if (err < 0)
2008 return err;
2009 }
2010
2011 spin_lock_irqsave(&chan->lock, flags);
2012
2013 cookie = dma_cookie_assign(tx);
2014
2015 /* Put this transaction onto the tail of the pending queue */
2016 append_desc_queue(chan, desc);
2017
2018 if (desc->cyclic)
2019 chan->cyclic = true;
2020
2021 chan->terminating = false;
2022
2023 spin_unlock_irqrestore(&chan->lock, flags);
2024
2025 return cookie;
2026}
2027
2028/**
2029 * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a
2030 * DMA_SLAVE transaction
2031 * @dchan: DMA channel
2032 * @xt: Interleaved template pointer
2033 * @flags: transfer ack flags
2034 *
2035 * Return: Async transaction descriptor on success and NULL on failure
2036 */
2037static struct dma_async_tx_descriptor *
2038xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
2039 struct dma_interleaved_template *xt,
2040 unsigned long flags)
2041{
2042 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2043 struct xilinx_dma_tx_descriptor *desc;
2044 struct xilinx_vdma_tx_segment *segment;
2045 struct xilinx_vdma_desc_hw *hw;
2046
2047 if (!is_slave_direction(xt->dir))
2048 return NULL;
2049
2050 if (!xt->numf || !xt->sgl[0].size)
2051 return NULL;
2052
2053 if (xt->frame_size != 1)
2054 return NULL;
2055
2056 /* Allocate a transaction descriptor. */
2057 desc = xilinx_dma_alloc_tx_descriptor(chan);
2058 if (!desc)
2059 return NULL;
2060
2061 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2062 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2063 async_tx_ack(&desc->async_tx);
2064
2065 /* Allocate the link descriptor from DMA pool */
2066 segment = xilinx_vdma_alloc_tx_segment(chan);
2067 if (!segment)
2068 goto error;
2069
2070 /* Fill in the hardware descriptor */
2071 hw = &segment->hw;
2072 hw->vsize = xt->numf;
2073 hw->hsize = xt->sgl[0].size;
2074 hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) <<
2075 XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT;
2076 hw->stride |= chan->config.frm_dly <<
2077 XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT;
2078
2079 if (xt->dir != DMA_MEM_TO_DEV) {
2080 if (chan->ext_addr) {
2081 hw->buf_addr = lower_32_bits(xt->dst_start);
2082 hw->buf_addr_msb = upper_32_bits(xt->dst_start);
2083 } else {
2084 hw->buf_addr = xt->dst_start;
2085 }
2086 } else {
2087 if (chan->ext_addr) {
2088 hw->buf_addr = lower_32_bits(xt->src_start);
2089 hw->buf_addr_msb = upper_32_bits(xt->src_start);
2090 } else {
2091 hw->buf_addr = xt->src_start;
2092 }
2093 }
2094
2095 /* Insert the segment into the descriptor segments list. */
2096 list_add_tail(&segment->node, &desc->segments);
2097
2098 /* Link the last hardware descriptor with the first. */
2099 segment = list_first_entry(&desc->segments,
2100 struct xilinx_vdma_tx_segment, node);
2101 desc->async_tx.phys = segment->phys;
2102
2103 return &desc->async_tx;
2104
2105error:
2106 xilinx_dma_free_tx_descriptor(chan, desc);
2107 return NULL;
2108}
2109
2110/**
2111 * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction
2112 * @dchan: DMA channel
2113 * @dma_dst: destination address
2114 * @dma_src: source address
2115 * @len: transfer length
2116 * @flags: transfer ack flags
2117 *
2118 * Return: Async transaction descriptor on success and NULL on failure
2119 */
2120static struct dma_async_tx_descriptor *
2121xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst,
2122 dma_addr_t dma_src, size_t len, unsigned long flags)
2123{
2124 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2125 struct xilinx_dma_tx_descriptor *desc;
2126 struct xilinx_cdma_tx_segment *segment;
2127 struct xilinx_cdma_desc_hw *hw;
2128
2129 if (!len || len > chan->xdev->max_buffer_len)
2130 return NULL;
2131
2132 desc = xilinx_dma_alloc_tx_descriptor(chan);
2133 if (!desc)
2134 return NULL;
2135
2136 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2137 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2138
2139 /* Allocate the link descriptor from DMA pool */
2140 segment = xilinx_cdma_alloc_tx_segment(chan);
2141 if (!segment)
2142 goto error;
2143
2144 hw = &segment->hw;
2145 hw->control = len;
2146 hw->src_addr = dma_src;
2147 hw->dest_addr = dma_dst;
2148 if (chan->ext_addr) {
2149 hw->src_addr_msb = upper_32_bits(dma_src);
2150 hw->dest_addr_msb = upper_32_bits(dma_dst);
2151 }
2152
2153 /* Insert the segment into the descriptor segments list. */
2154 list_add_tail(&segment->node, &desc->segments);
2155
2156 desc->async_tx.phys = segment->phys;
2157 hw->next_desc = segment->phys;
2158
2159 return &desc->async_tx;
2160
2161error:
2162 xilinx_dma_free_tx_descriptor(chan, desc);
2163 return NULL;
2164}
2165
2166/**
2167 * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
2168 * @dchan: DMA channel
2169 * @sgl: scatterlist to transfer to/from
2170 * @sg_len: number of entries in @scatterlist
2171 * @direction: DMA direction
2172 * @flags: transfer ack flags
2173 * @context: APP words of the descriptor
2174 *
2175 * Return: Async transaction descriptor on success and NULL on failure
2176 */
2177static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(
2178 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
2179 enum dma_transfer_direction direction, unsigned long flags,
2180 void *context)
2181{
2182 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2183 struct xilinx_dma_tx_descriptor *desc;
2184 struct xilinx_axidma_tx_segment *segment = NULL;
2185 u32 *app_w = (u32 *)context;
2186 struct scatterlist *sg;
2187 size_t copy;
2188 size_t sg_used;
2189 unsigned int i;
2190
2191 if (!is_slave_direction(direction))
2192 return NULL;
2193
2194 /* Allocate a transaction descriptor. */
2195 desc = xilinx_dma_alloc_tx_descriptor(chan);
2196 if (!desc)
2197 return NULL;
2198
2199 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2200 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2201
2202 /* Build transactions using information in the scatter gather list */
2203 for_each_sg(sgl, sg, sg_len, i) {
2204 sg_used = 0;
2205
2206 /* Loop until the entire scatterlist entry is used */
2207 while (sg_used < sg_dma_len(sg)) {
2208 struct xilinx_axidma_desc_hw *hw;
2209
2210 /* Get a free segment */
2211 segment = xilinx_axidma_alloc_tx_segment(chan);
2212 if (!segment)
2213 goto error;
2214
2215 /*
2216 * Calculate the maximum number of bytes to transfer,
2217 * making sure it is less than the hw limit
2218 */
2219 copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg),
2220 sg_used);
2221 hw = &segment->hw;
2222
2223 /* Fill in the descriptor */
2224 xilinx_axidma_buf(chan, hw, sg_dma_address(sg),
2225 sg_used, 0);
2226
2227 hw->control = copy;
2228
2229 if (chan->direction == DMA_MEM_TO_DEV) {
2230 if (app_w)
2231 memcpy(hw->app, app_w, sizeof(u32) *
2232 XILINX_DMA_NUM_APP_WORDS);
2233 }
2234
2235 sg_used += copy;
2236
2237 /*
2238 * Insert the segment into the descriptor segments
2239 * list.
2240 */
2241 list_add_tail(&segment->node, &desc->segments);
2242 }
2243 }
2244
2245 segment = list_first_entry(&desc->segments,
2246 struct xilinx_axidma_tx_segment, node);
2247 desc->async_tx.phys = segment->phys;
2248
2249 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2250 if (chan->direction == DMA_MEM_TO_DEV) {
2251 segment->hw.control |= XILINX_DMA_BD_SOP;
2252 segment = list_last_entry(&desc->segments,
2253 struct xilinx_axidma_tx_segment,
2254 node);
2255 segment->hw.control |= XILINX_DMA_BD_EOP;
2256 }
2257
2258 if (chan->xdev->has_axistream_connected)
2259 desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops;
2260
2261 return &desc->async_tx;
2262
2263error:
2264 xilinx_dma_free_tx_descriptor(chan, desc);
2265 return NULL;
2266}
2267
2268/**
2269 * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction
2270 * @dchan: DMA channel
2271 * @buf_addr: Physical address of the buffer
2272 * @buf_len: Total length of the cyclic buffers
2273 * @period_len: length of individual cyclic buffer
2274 * @direction: DMA direction
2275 * @flags: transfer ack flags
2276 *
2277 * Return: Async transaction descriptor on success and NULL on failure
2278 */
2279static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(
2280 struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len,
2281 size_t period_len, enum dma_transfer_direction direction,
2282 unsigned long flags)
2283{
2284 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2285 struct xilinx_dma_tx_descriptor *desc;
2286 struct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL;
2287 size_t copy, sg_used;
2288 unsigned int num_periods;
2289 int i;
2290 u32 reg;
2291
2292 if (!period_len)
2293 return NULL;
2294
2295 num_periods = buf_len / period_len;
2296
2297 if (!num_periods)
2298 return NULL;
2299
2300 if (!is_slave_direction(direction))
2301 return NULL;
2302
2303 /* Allocate a transaction descriptor. */
2304 desc = xilinx_dma_alloc_tx_descriptor(chan);
2305 if (!desc)
2306 return NULL;
2307
2308 chan->direction = direction;
2309 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2310 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2311
2312 for (i = 0; i < num_periods; ++i) {
2313 sg_used = 0;
2314
2315 while (sg_used < period_len) {
2316 struct xilinx_axidma_desc_hw *hw;
2317
2318 /* Get a free segment */
2319 segment = xilinx_axidma_alloc_tx_segment(chan);
2320 if (!segment)
2321 goto error;
2322
2323 /*
2324 * Calculate the maximum number of bytes to transfer,
2325 * making sure it is less than the hw limit
2326 */
2327 copy = xilinx_dma_calc_copysize(chan, period_len,
2328 sg_used);
2329 hw = &segment->hw;
2330 xilinx_axidma_buf(chan, hw, buf_addr, sg_used,
2331 period_len * i);
2332 hw->control = copy;
2333
2334 if (prev)
2335 prev->hw.next_desc = segment->phys;
2336
2337 prev = segment;
2338 sg_used += copy;
2339
2340 /*
2341 * Insert the segment into the descriptor segments
2342 * list.
2343 */
2344 list_add_tail(&segment->node, &desc->segments);
2345 }
2346 }
2347
2348 head_segment = list_first_entry(&desc->segments,
2349 struct xilinx_axidma_tx_segment, node);
2350 desc->async_tx.phys = head_segment->phys;
2351
2352 desc->cyclic = true;
2353 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2354 reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
2355 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
2356
2357 segment = list_last_entry(&desc->segments,
2358 struct xilinx_axidma_tx_segment,
2359 node);
2360 segment->hw.next_desc = (u32) head_segment->phys;
2361
2362 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2363 if (direction == DMA_MEM_TO_DEV) {
2364 head_segment->hw.control |= XILINX_DMA_BD_SOP;
2365 segment->hw.control |= XILINX_DMA_BD_EOP;
2366 }
2367
2368 return &desc->async_tx;
2369
2370error:
2371 xilinx_dma_free_tx_descriptor(chan, desc);
2372 return NULL;
2373}
2374
2375/**
2376 * xilinx_mcdma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
2377 * @dchan: DMA channel
2378 * @sgl: scatterlist to transfer to/from
2379 * @sg_len: number of entries in @scatterlist
2380 * @direction: DMA direction
2381 * @flags: transfer ack flags
2382 * @context: APP words of the descriptor
2383 *
2384 * Return: Async transaction descriptor on success and NULL on failure
2385 */
2386static struct dma_async_tx_descriptor *
2387xilinx_mcdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
2388 unsigned int sg_len,
2389 enum dma_transfer_direction direction,
2390 unsigned long flags, void *context)
2391{
2392 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2393 struct xilinx_dma_tx_descriptor *desc;
2394 struct xilinx_aximcdma_tx_segment *segment = NULL;
2395 u32 *app_w = (u32 *)context;
2396 struct scatterlist *sg;
2397 size_t copy;
2398 size_t sg_used;
2399 unsigned int i;
2400
2401 if (!is_slave_direction(direction))
2402 return NULL;
2403
2404 /* Allocate a transaction descriptor. */
2405 desc = xilinx_dma_alloc_tx_descriptor(chan);
2406 if (!desc)
2407 return NULL;
2408
2409 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
2410 desc->async_tx.tx_submit = xilinx_dma_tx_submit;
2411
2412 /* Build transactions using information in the scatter gather list */
2413 for_each_sg(sgl, sg, sg_len, i) {
2414 sg_used = 0;
2415
2416 /* Loop until the entire scatterlist entry is used */
2417 while (sg_used < sg_dma_len(sg)) {
2418 struct xilinx_aximcdma_desc_hw *hw;
2419
2420 /* Get a free segment */
2421 segment = xilinx_aximcdma_alloc_tx_segment(chan);
2422 if (!segment)
2423 goto error;
2424
2425 /*
2426 * Calculate the maximum number of bytes to transfer,
2427 * making sure it is less than the hw limit
2428 */
2429 copy = min_t(size_t, sg_dma_len(sg) - sg_used,
2430 chan->xdev->max_buffer_len);
2431 hw = &segment->hw;
2432
2433 /* Fill in the descriptor */
2434 xilinx_aximcdma_buf(chan, hw, sg_dma_address(sg),
2435 sg_used);
2436 hw->control = copy;
2437
2438 if (chan->direction == DMA_MEM_TO_DEV && app_w) {
2439 memcpy(hw->app, app_w, sizeof(u32) *
2440 XILINX_DMA_NUM_APP_WORDS);
2441 }
2442
2443 sg_used += copy;
2444 /*
2445 * Insert the segment into the descriptor segments
2446 * list.
2447 */
2448 list_add_tail(&segment->node, &desc->segments);
2449 }
2450 }
2451
2452 segment = list_first_entry(&desc->segments,
2453 struct xilinx_aximcdma_tx_segment, node);
2454 desc->async_tx.phys = segment->phys;
2455
2456 /* For the last DMA_MEM_TO_DEV transfer, set EOP */
2457 if (chan->direction == DMA_MEM_TO_DEV) {
2458 segment->hw.control |= XILINX_MCDMA_BD_SOP;
2459 segment = list_last_entry(&desc->segments,
2460 struct xilinx_aximcdma_tx_segment,
2461 node);
2462 segment->hw.control |= XILINX_MCDMA_BD_EOP;
2463 }
2464
2465 return &desc->async_tx;
2466
2467error:
2468 xilinx_dma_free_tx_descriptor(chan, desc);
2469
2470 return NULL;
2471}
2472
2473/**
2474 * xilinx_dma_terminate_all - Halt the channel and free descriptors
2475 * @dchan: Driver specific DMA Channel pointer
2476 *
2477 * Return: '0' always.
2478 */
2479static int xilinx_dma_terminate_all(struct dma_chan *dchan)
2480{
2481 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2482 u32 reg;
2483 int err;
2484
2485 if (!chan->cyclic) {
2486 err = chan->stop_transfer(chan);
2487 if (err) {
2488 dev_err(chan->dev, "Cannot stop channel %p: %x\n",
2489 chan, dma_ctrl_read(chan,
2490 XILINX_DMA_REG_DMASR));
2491 chan->err = true;
2492 }
2493 }
2494
2495 xilinx_dma_chan_reset(chan);
2496 /* Remove and free all of the descriptors in the lists */
2497 chan->terminating = true;
2498 xilinx_dma_free_descriptors(chan);
2499 chan->idle = true;
2500
2501 if (chan->cyclic) {
2502 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2503 reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK;
2504 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
2505 chan->cyclic = false;
2506 }
2507
2508 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
2509 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2510 XILINX_CDMA_CR_SGMODE);
2511
2512 return 0;
2513}
2514
2515static void xilinx_dma_synchronize(struct dma_chan *dchan)
2516{
2517 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2518
2519 tasklet_kill(&chan->tasklet);
2520}
2521
2522/**
2523 * xilinx_vdma_channel_set_config - Configure VDMA channel
2524 * Run-time configuration for Axi VDMA, supports:
2525 * . halt the channel
2526 * . configure interrupt coalescing and inter-packet delay threshold
2527 * . start/stop parking
2528 * . enable genlock
2529 *
2530 * @dchan: DMA channel
2531 * @cfg: VDMA device configuration pointer
2532 *
2533 * Return: '0' on success and failure value on error
2534 */
2535int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
2536 struct xilinx_vdma_config *cfg)
2537{
2538 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
2539 u32 dmacr;
2540
2541 if (cfg->reset)
2542 return xilinx_dma_chan_reset(chan);
2543
2544 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
2545
2546 chan->config.frm_dly = cfg->frm_dly;
2547 chan->config.park = cfg->park;
2548
2549 /* genlock settings */
2550 chan->config.gen_lock = cfg->gen_lock;
2551 chan->config.master = cfg->master;
2552
2553 dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN;
2554 if (cfg->gen_lock && chan->genlock) {
2555 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN;
2556 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK;
2557 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;
2558 }
2559
2560 chan->config.frm_cnt_en = cfg->frm_cnt_en;
2561 chan->config.vflip_en = cfg->vflip_en;
2562
2563 if (cfg->park)
2564 chan->config.park_frm = cfg->park_frm;
2565 else
2566 chan->config.park_frm = -1;
2567
2568 chan->config.coalesc = cfg->coalesc;
2569 chan->config.delay = cfg->delay;
2570
2571 if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {
2572 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK;
2573 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;
2574 chan->config.coalesc = cfg->coalesc;
2575 }
2576
2577 if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {
2578 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK;
2579 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;
2580 chan->config.delay = cfg->delay;
2581 }
2582
2583 /* FSync Source selection */
2584 dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK;
2585 dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT;
2586
2587 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);
2588
2589 return 0;
2590}
2591EXPORT_SYMBOL(xilinx_vdma_channel_set_config);
2592
2593/* -----------------------------------------------------------------------------
2594 * Probe and remove
2595 */
2596
2597/**
2598 * xilinx_dma_chan_remove - Per Channel remove function
2599 * @chan: Driver specific DMA channel
2600 */
2601static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan)
2602{
2603 /* Disable all interrupts */
2604 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
2605 XILINX_DMA_DMAXR_ALL_IRQ_MASK);
2606
2607 if (chan->irq > 0)
2608 free_irq(chan->irq, chan);
2609
2610 tasklet_kill(&chan->tasklet);
2611
2612 list_del(&chan->common.device_node);
2613}
2614
2615static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2616 struct clk **tx_clk, struct clk **rx_clk,
2617 struct clk **sg_clk, struct clk **tmp_clk)
2618{
2619 int err;
2620
2621 *tmp_clk = NULL;
2622
2623 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2624 if (IS_ERR(*axi_clk))
2625 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n");
2626
2627 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2628 if (IS_ERR(*tx_clk))
2629 *tx_clk = NULL;
2630
2631 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2632 if (IS_ERR(*rx_clk))
2633 *rx_clk = NULL;
2634
2635 *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk");
2636 if (IS_ERR(*sg_clk))
2637 *sg_clk = NULL;
2638
2639 err = clk_prepare_enable(*axi_clk);
2640 if (err) {
2641 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2642 return err;
2643 }
2644
2645 err = clk_prepare_enable(*tx_clk);
2646 if (err) {
2647 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2648 goto err_disable_axiclk;
2649 }
2650
2651 err = clk_prepare_enable(*rx_clk);
2652 if (err) {
2653 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2654 goto err_disable_txclk;
2655 }
2656
2657 err = clk_prepare_enable(*sg_clk);
2658 if (err) {
2659 dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n", err);
2660 goto err_disable_rxclk;
2661 }
2662
2663 return 0;
2664
2665err_disable_rxclk:
2666 clk_disable_unprepare(*rx_clk);
2667err_disable_txclk:
2668 clk_disable_unprepare(*tx_clk);
2669err_disable_axiclk:
2670 clk_disable_unprepare(*axi_clk);
2671
2672 return err;
2673}
2674
2675static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2676 struct clk **dev_clk, struct clk **tmp_clk,
2677 struct clk **tmp1_clk, struct clk **tmp2_clk)
2678{
2679 int err;
2680
2681 *tmp_clk = NULL;
2682 *tmp1_clk = NULL;
2683 *tmp2_clk = NULL;
2684
2685 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2686 if (IS_ERR(*axi_clk))
2687 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n");
2688
2689 *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk");
2690 if (IS_ERR(*dev_clk))
2691 return dev_err_probe(&pdev->dev, PTR_ERR(*dev_clk), "failed to get dev_clk\n");
2692
2693 err = clk_prepare_enable(*axi_clk);
2694 if (err) {
2695 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err);
2696 return err;
2697 }
2698
2699 err = clk_prepare_enable(*dev_clk);
2700 if (err) {
2701 dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n", err);
2702 goto err_disable_axiclk;
2703 }
2704
2705 return 0;
2706
2707err_disable_axiclk:
2708 clk_disable_unprepare(*axi_clk);
2709
2710 return err;
2711}
2712
2713static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk,
2714 struct clk **tx_clk, struct clk **txs_clk,
2715 struct clk **rx_clk, struct clk **rxs_clk)
2716{
2717 int err;
2718
2719 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk");
2720 if (IS_ERR(*axi_clk))
2721 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n");
2722
2723 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk");
2724 if (IS_ERR(*tx_clk))
2725 *tx_clk = NULL;
2726
2727 *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk");
2728 if (IS_ERR(*txs_clk))
2729 *txs_clk = NULL;
2730
2731 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk");
2732 if (IS_ERR(*rx_clk))
2733 *rx_clk = NULL;
2734
2735 *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk");
2736 if (IS_ERR(*rxs_clk))
2737 *rxs_clk = NULL;
2738
2739 err = clk_prepare_enable(*axi_clk);
2740 if (err) {
2741 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n",
2742 err);
2743 return err;
2744 }
2745
2746 err = clk_prepare_enable(*tx_clk);
2747 if (err) {
2748 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
2749 goto err_disable_axiclk;
2750 }
2751
2752 err = clk_prepare_enable(*txs_clk);
2753 if (err) {
2754 dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n", err);
2755 goto err_disable_txclk;
2756 }
2757
2758 err = clk_prepare_enable(*rx_clk);
2759 if (err) {
2760 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
2761 goto err_disable_txsclk;
2762 }
2763
2764 err = clk_prepare_enable(*rxs_clk);
2765 if (err) {
2766 dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n", err);
2767 goto err_disable_rxclk;
2768 }
2769
2770 return 0;
2771
2772err_disable_rxclk:
2773 clk_disable_unprepare(*rx_clk);
2774err_disable_txsclk:
2775 clk_disable_unprepare(*txs_clk);
2776err_disable_txclk:
2777 clk_disable_unprepare(*tx_clk);
2778err_disable_axiclk:
2779 clk_disable_unprepare(*axi_clk);
2780
2781 return err;
2782}
2783
2784static void xdma_disable_allclks(struct xilinx_dma_device *xdev)
2785{
2786 clk_disable_unprepare(xdev->rxs_clk);
2787 clk_disable_unprepare(xdev->rx_clk);
2788 clk_disable_unprepare(xdev->txs_clk);
2789 clk_disable_unprepare(xdev->tx_clk);
2790 clk_disable_unprepare(xdev->axi_clk);
2791}
2792
2793/**
2794 * xilinx_dma_chan_probe - Per Channel Probing
2795 * It get channel features from the device tree entry and
2796 * initialize special channel handling routines
2797 *
2798 * @xdev: Driver specific device structure
2799 * @node: Device node
2800 *
2801 * Return: '0' on success and failure value on error
2802 */
2803static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
2804 struct device_node *node)
2805{
2806 struct xilinx_dma_chan *chan;
2807 bool has_dre = false;
2808 u32 value, width;
2809 int err;
2810
2811 /* Allocate and initialize the channel structure */
2812 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
2813 if (!chan)
2814 return -ENOMEM;
2815
2816 chan->dev = xdev->dev;
2817 chan->xdev = xdev;
2818 chan->desc_pendingcount = 0x0;
2819 chan->ext_addr = xdev->ext_addr;
2820 /* This variable ensures that descriptors are not
2821 * Submitted when dma engine is in progress. This variable is
2822 * Added to avoid polling for a bit in the status register to
2823 * Know dma state in the driver hot path.
2824 */
2825 chan->idle = true;
2826
2827 spin_lock_init(&chan->lock);
2828 INIT_LIST_HEAD(&chan->pending_list);
2829 INIT_LIST_HEAD(&chan->done_list);
2830 INIT_LIST_HEAD(&chan->active_list);
2831 INIT_LIST_HEAD(&chan->free_seg_list);
2832
2833 /* Retrieve the channel properties from the device tree */
2834 has_dre = of_property_read_bool(node, "xlnx,include-dre");
2835
2836 of_property_read_u8(node, "xlnx,irq-delay", &chan->irq_delay);
2837
2838 chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode");
2839
2840 err = of_property_read_u32(node, "xlnx,datawidth", &value);
2841 if (err) {
2842 dev_err(xdev->dev, "missing xlnx,datawidth property\n");
2843 return err;
2844 }
2845 width = value >> 3; /* Convert bits to bytes */
2846
2847 /* If data width is greater than 8 bytes, DRE is not in hw */
2848 if (width > 8)
2849 has_dre = false;
2850
2851 if (!has_dre)
2852 xdev->common.copy_align = (enum dmaengine_alignment)fls(width - 1);
2853
2854 if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") ||
2855 of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") ||
2856 of_device_is_compatible(node, "xlnx,axi-cdma-channel")) {
2857 chan->direction = DMA_MEM_TO_DEV;
2858 chan->id = xdev->mm2s_chan_id++;
2859 chan->tdest = chan->id;
2860
2861 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
2862 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2863 chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET;
2864 chan->config.park = 1;
2865
2866 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2867 xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S)
2868 chan->flush_on_fsync = true;
2869 }
2870 } else if (of_device_is_compatible(node,
2871 "xlnx,axi-vdma-s2mm-channel") ||
2872 of_device_is_compatible(node,
2873 "xlnx,axi-dma-s2mm-channel")) {
2874 chan->direction = DMA_DEV_TO_MEM;
2875 chan->id = xdev->s2mm_chan_id++;
2876 chan->tdest = chan->id - xdev->dma_config->max_channels / 2;
2877 chan->has_vflip = of_property_read_bool(node,
2878 "xlnx,enable-vert-flip");
2879 if (chan->has_vflip) {
2880 chan->config.vflip_en = dma_read(chan,
2881 XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP) &
2882 XILINX_VDMA_ENABLE_VERTICAL_FLIP;
2883 }
2884
2885 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA)
2886 chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET;
2887 else
2888 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
2889
2890 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
2891 chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET;
2892 chan->config.park = 1;
2893
2894 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
2895 xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM)
2896 chan->flush_on_fsync = true;
2897 }
2898 } else {
2899 dev_err(xdev->dev, "Invalid channel compatible node\n");
2900 return -EINVAL;
2901 }
2902
2903 /* Request the interrupt */
2904 chan->irq = of_irq_get(node, chan->tdest);
2905 if (chan->irq < 0)
2906 return dev_err_probe(xdev->dev, chan->irq, "failed to get irq\n");
2907 err = request_irq(chan->irq, xdev->dma_config->irq_handler,
2908 IRQF_SHARED, "xilinx-dma-controller", chan);
2909 if (err) {
2910 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq);
2911 return err;
2912 }
2913
2914 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
2915 chan->start_transfer = xilinx_dma_start_transfer;
2916 chan->stop_transfer = xilinx_dma_stop_transfer;
2917 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
2918 chan->start_transfer = xilinx_mcdma_start_transfer;
2919 chan->stop_transfer = xilinx_dma_stop_transfer;
2920 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
2921 chan->start_transfer = xilinx_cdma_start_transfer;
2922 chan->stop_transfer = xilinx_cdma_stop_transfer;
2923 } else {
2924 chan->start_transfer = xilinx_vdma_start_transfer;
2925 chan->stop_transfer = xilinx_dma_stop_transfer;
2926 }
2927
2928 /* check if SG is enabled (only for AXIDMA, AXIMCDMA, and CDMA) */
2929 if (xdev->dma_config->dmatype != XDMA_TYPE_VDMA) {
2930 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA ||
2931 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) &
2932 XILINX_DMA_DMASR_SG_MASK)
2933 chan->has_sg = true;
2934 dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id,
2935 chan->has_sg ? "enabled" : "disabled");
2936 }
2937
2938 /* Initialize the tasklet */
2939 tasklet_setup(&chan->tasklet, xilinx_dma_do_tasklet);
2940
2941 /*
2942 * Initialize the DMA channel and add it to the DMA engine channels
2943 * list.
2944 */
2945 chan->common.device = &xdev->common;
2946
2947 list_add_tail(&chan->common.device_node, &xdev->common.channels);
2948 xdev->chan[chan->id] = chan;
2949
2950 /* Reset the channel */
2951 err = xilinx_dma_chan_reset(chan);
2952 if (err < 0) {
2953 dev_err(xdev->dev, "Reset channel failed\n");
2954 return err;
2955 }
2956
2957 return 0;
2958}
2959
2960/**
2961 * xilinx_dma_child_probe - Per child node probe
2962 * It get number of dma-channels per child node from
2963 * device-tree and initializes all the channels.
2964 *
2965 * @xdev: Driver specific device structure
2966 * @node: Device node
2967 *
2968 * Return: '0' on success and failure value on error.
2969 */
2970static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev,
2971 struct device_node *node)
2972{
2973 int ret, i;
2974 u32 nr_channels = 1;
2975
2976 ret = of_property_read_u32(node, "dma-channels", &nr_channels);
2977 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA && ret < 0)
2978 dev_warn(xdev->dev, "missing dma-channels property\n");
2979
2980 for (i = 0; i < nr_channels; i++) {
2981 ret = xilinx_dma_chan_probe(xdev, node);
2982 if (ret)
2983 return ret;
2984 }
2985
2986 return 0;
2987}
2988
2989/**
2990 * of_dma_xilinx_xlate - Translation function
2991 * @dma_spec: Pointer to DMA specifier as found in the device tree
2992 * @ofdma: Pointer to DMA controller data
2993 *
2994 * Return: DMA channel pointer on success and NULL on error
2995 */
2996static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
2997 struct of_dma *ofdma)
2998{
2999 struct xilinx_dma_device *xdev = ofdma->of_dma_data;
3000 int chan_id = dma_spec->args[0];
3001
3002 if (chan_id >= xdev->dma_config->max_channels || !xdev->chan[chan_id])
3003 return NULL;
3004
3005 return dma_get_slave_channel(&xdev->chan[chan_id]->common);
3006}
3007
3008static const struct xilinx_dma_config axidma_config = {
3009 .dmatype = XDMA_TYPE_AXIDMA,
3010 .clk_init = axidma_clk_init,
3011 .irq_handler = xilinx_dma_irq_handler,
3012 .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE,
3013};
3014
3015static const struct xilinx_dma_config aximcdma_config = {
3016 .dmatype = XDMA_TYPE_AXIMCDMA,
3017 .clk_init = axidma_clk_init,
3018 .irq_handler = xilinx_mcdma_irq_handler,
3019 .max_channels = XILINX_MCDMA_MAX_CHANS_PER_DEVICE,
3020};
3021static const struct xilinx_dma_config axicdma_config = {
3022 .dmatype = XDMA_TYPE_CDMA,
3023 .clk_init = axicdma_clk_init,
3024 .irq_handler = xilinx_dma_irq_handler,
3025 .max_channels = XILINX_CDMA_MAX_CHANS_PER_DEVICE,
3026};
3027
3028static const struct xilinx_dma_config axivdma_config = {
3029 .dmatype = XDMA_TYPE_VDMA,
3030 .clk_init = axivdma_clk_init,
3031 .irq_handler = xilinx_dma_irq_handler,
3032 .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE,
3033};
3034
3035static const struct of_device_id xilinx_dma_of_ids[] = {
3036 { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config },
3037 { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config },
3038 { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config },
3039 { .compatible = "xlnx,axi-mcdma-1.00.a", .data = &aximcdma_config },
3040 {}
3041};
3042MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids);
3043
3044/**
3045 * xilinx_dma_probe - Driver probe function
3046 * @pdev: Pointer to the platform_device structure
3047 *
3048 * Return: '0' on success and failure value on error
3049 */
3050static int xilinx_dma_probe(struct platform_device *pdev)
3051{
3052 int (*clk_init)(struct platform_device *, struct clk **, struct clk **,
3053 struct clk **, struct clk **, struct clk **)
3054 = axivdma_clk_init;
3055 struct device_node *node = pdev->dev.of_node;
3056 struct xilinx_dma_device *xdev;
3057 struct device_node *child, *np = pdev->dev.of_node;
3058 u32 num_frames, addr_width, len_width;
3059 int i, err;
3060
3061 /* Allocate and initialize the DMA engine structure */
3062 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
3063 if (!xdev)
3064 return -ENOMEM;
3065
3066 xdev->dev = &pdev->dev;
3067 if (np) {
3068 const struct of_device_id *match;
3069
3070 match = of_match_node(xilinx_dma_of_ids, np);
3071 if (match && match->data) {
3072 xdev->dma_config = match->data;
3073 clk_init = xdev->dma_config->clk_init;
3074 }
3075 }
3076
3077 err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk,
3078 &xdev->rx_clk, &xdev->rxs_clk);
3079 if (err)
3080 return err;
3081
3082 /* Request and map I/O memory */
3083 xdev->regs = devm_platform_ioremap_resource(pdev, 0);
3084 if (IS_ERR(xdev->regs)) {
3085 err = PTR_ERR(xdev->regs);
3086 goto disable_clks;
3087 }
3088 /* Retrieve the DMA engine properties from the device tree */
3089 xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0);
3090 xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2;
3091
3092 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA ||
3093 xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
3094 if (!of_property_read_u32(node, "xlnx,sg-length-width",
3095 &len_width)) {
3096 if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN ||
3097 len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) {
3098 dev_warn(xdev->dev,
3099 "invalid xlnx,sg-length-width property value. Using default width\n");
3100 } else {
3101 if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX)
3102 dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n");
3103 xdev->max_buffer_len =
3104 GENMASK(len_width - 1, 0);
3105 }
3106 }
3107 }
3108
3109 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
3110 xdev->has_axistream_connected =
3111 of_property_read_bool(node, "xlnx,axistream-connected");
3112 }
3113
3114 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
3115 err = of_property_read_u32(node, "xlnx,num-fstores",
3116 &num_frames);
3117 if (err < 0) {
3118 dev_err(xdev->dev,
3119 "missing xlnx,num-fstores property\n");
3120 goto disable_clks;
3121 }
3122
3123 err = of_property_read_u32(node, "xlnx,flush-fsync",
3124 &xdev->flush_on_fsync);
3125 if (err < 0)
3126 dev_warn(xdev->dev,
3127 "missing xlnx,flush-fsync property\n");
3128 }
3129
3130 err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width);
3131 if (err < 0)
3132 dev_warn(xdev->dev, "missing xlnx,addrwidth property\n");
3133
3134 if (addr_width > 32)
3135 xdev->ext_addr = true;
3136 else
3137 xdev->ext_addr = false;
3138
3139 /* Set metadata mode */
3140 if (xdev->has_axistream_connected)
3141 xdev->common.desc_metadata_modes = DESC_METADATA_ENGINE;
3142
3143 /* Set the dma mask bits */
3144 err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width));
3145 if (err < 0) {
3146 dev_err(xdev->dev, "DMA mask error %d\n", err);
3147 goto disable_clks;
3148 }
3149
3150 /* Initialize the DMA engine */
3151 xdev->common.dev = &pdev->dev;
3152
3153 INIT_LIST_HEAD(&xdev->common.channels);
3154 if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) {
3155 dma_cap_set(DMA_SLAVE, xdev->common.cap_mask);
3156 dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask);
3157 }
3158
3159 xdev->common.device_alloc_chan_resources =
3160 xilinx_dma_alloc_chan_resources;
3161 xdev->common.device_free_chan_resources =
3162 xilinx_dma_free_chan_resources;
3163 xdev->common.device_terminate_all = xilinx_dma_terminate_all;
3164 xdev->common.device_synchronize = xilinx_dma_synchronize;
3165 xdev->common.device_tx_status = xilinx_dma_tx_status;
3166 xdev->common.device_issue_pending = xilinx_dma_issue_pending;
3167 xdev->common.device_config = xilinx_dma_device_config;
3168 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
3169 dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask);
3170 xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg;
3171 xdev->common.device_prep_dma_cyclic =
3172 xilinx_dma_prep_dma_cyclic;
3173 /* Residue calculation is supported by only AXI DMA and CDMA */
3174 xdev->common.residue_granularity =
3175 DMA_RESIDUE_GRANULARITY_SEGMENT;
3176 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) {
3177 dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask);
3178 xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy;
3179 /* Residue calculation is supported by only AXI DMA and CDMA */
3180 xdev->common.residue_granularity =
3181 DMA_RESIDUE_GRANULARITY_SEGMENT;
3182 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
3183 xdev->common.device_prep_slave_sg = xilinx_mcdma_prep_slave_sg;
3184 } else {
3185 xdev->common.device_prep_interleaved_dma =
3186 xilinx_vdma_dma_prep_interleaved;
3187 }
3188
3189 platform_set_drvdata(pdev, xdev);
3190
3191 /* Initialize the channels */
3192 for_each_child_of_node(node, child) {
3193 err = xilinx_dma_child_probe(xdev, child);
3194 if (err < 0) {
3195 of_node_put(child);
3196 goto error;
3197 }
3198 }
3199
3200 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
3201 for (i = 0; i < xdev->dma_config->max_channels; i++)
3202 if (xdev->chan[i])
3203 xdev->chan[i]->num_frms = num_frames;
3204 }
3205
3206 /* Register the DMA engine with the core */
3207 err = dma_async_device_register(&xdev->common);
3208 if (err) {
3209 dev_err(xdev->dev, "failed to register the dma device\n");
3210 goto error;
3211 }
3212
3213 err = of_dma_controller_register(node, of_dma_xilinx_xlate,
3214 xdev);
3215 if (err < 0) {
3216 dev_err(&pdev->dev, "Unable to register DMA to DT\n");
3217 dma_async_device_unregister(&xdev->common);
3218 goto error;
3219 }
3220
3221 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
3222 dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n");
3223 else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA)
3224 dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n");
3225 else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA)
3226 dev_info(&pdev->dev, "Xilinx AXI MCDMA Engine Driver Probed!!\n");
3227 else
3228 dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n");
3229
3230 return 0;
3231
3232error:
3233 for (i = 0; i < xdev->dma_config->max_channels; i++)
3234 if (xdev->chan[i])
3235 xilinx_dma_chan_remove(xdev->chan[i]);
3236disable_clks:
3237 xdma_disable_allclks(xdev);
3238
3239 return err;
3240}
3241
3242/**
3243 * xilinx_dma_remove - Driver remove function
3244 * @pdev: Pointer to the platform_device structure
3245 */
3246static void xilinx_dma_remove(struct platform_device *pdev)
3247{
3248 struct xilinx_dma_device *xdev = platform_get_drvdata(pdev);
3249 int i;
3250
3251 of_dma_controller_free(pdev->dev.of_node);
3252
3253 dma_async_device_unregister(&xdev->common);
3254
3255 for (i = 0; i < xdev->dma_config->max_channels; i++)
3256 if (xdev->chan[i])
3257 xilinx_dma_chan_remove(xdev->chan[i]);
3258
3259 xdma_disable_allclks(xdev);
3260}
3261
3262static struct platform_driver xilinx_vdma_driver = {
3263 .driver = {
3264 .name = "xilinx-vdma",
3265 .of_match_table = xilinx_dma_of_ids,
3266 },
3267 .probe = xilinx_dma_probe,
3268 .remove_new = xilinx_dma_remove,
3269};
3270
3271module_platform_driver(xilinx_vdma_driver);
3272
3273MODULE_AUTHOR("Xilinx, Inc.");
3274MODULE_DESCRIPTION("Xilinx VDMA driver");
3275MODULE_LICENSE("GPL v2");