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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * General MIPS MT support routines, usable in AP/SP and SMVP.
4 * Copyright (C) 2005 Mips Technologies, Inc
5 */
6
7#include <linux/device.h>
8#include <linux/kernel.h>
9#include <linux/sched.h>
10#include <linux/export.h>
11#include <linux/interrupt.h>
12#include <linux/security.h>
13
14#include <asm/cpu.h>
15#include <asm/processor.h>
16#include <linux/atomic.h>
17#include <asm/hardirq.h>
18#include <asm/mmu_context.h>
19#include <asm/mipsmtregs.h>
20#include <asm/r4kcache.h>
21#include <asm/cacheflush.h>
22
23int vpelimit;
24
25static int __init maxvpes(char *str)
26{
27 get_option(&str, &vpelimit);
28
29 return 1;
30}
31
32__setup("maxvpes=", maxvpes);
33
34int tclimit;
35
36static int __init maxtcs(char *str)
37{
38 get_option(&str, &tclimit);
39
40 return 1;
41}
42
43__setup("maxtcs=", maxtcs);
44
45/*
46 * Dump new MIPS MT state for the core. Does not leave TCs halted.
47 * Takes an argument which taken to be a pre-call MVPControl value.
48 */
49
50void mips_mt_regdump(unsigned long mvpctl)
51{
52 unsigned long flags;
53 unsigned long vpflags;
54 unsigned long mvpconf0;
55 int nvpe;
56 int ntc;
57 int i;
58 int tc;
59 unsigned long haltval;
60 unsigned long tcstatval;
61
62 local_irq_save(flags);
63 vpflags = dvpe();
64 printk("=== MIPS MT State Dump ===\n");
65 printk("-- Global State --\n");
66 printk(" MVPControl Passed: %08lx\n", mvpctl);
67 printk(" MVPControl Read: %08lx\n", vpflags);
68 printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
69 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
70 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
71 printk("-- per-VPE State --\n");
72 for (i = 0; i < nvpe; i++) {
73 for (tc = 0; tc < ntc; tc++) {
74 settc(tc);
75 if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
76 printk(" VPE %d\n", i);
77 printk(" VPEControl : %08lx\n",
78 read_vpe_c0_vpecontrol());
79 printk(" VPEConf0 : %08lx\n",
80 read_vpe_c0_vpeconf0());
81 printk(" VPE%d.Status : %08lx\n",
82 i, read_vpe_c0_status());
83 printk(" VPE%d.EPC : %08lx %pS\n",
84 i, read_vpe_c0_epc(),
85 (void *) read_vpe_c0_epc());
86 printk(" VPE%d.Cause : %08lx\n",
87 i, read_vpe_c0_cause());
88 printk(" VPE%d.Config7 : %08lx\n",
89 i, read_vpe_c0_config7());
90 break; /* Next VPE */
91 }
92 }
93 }
94 printk("-- per-TC State --\n");
95 for (tc = 0; tc < ntc; tc++) {
96 settc(tc);
97 if (read_tc_c0_tcbind() == read_c0_tcbind()) {
98 /* Are we dumping ourself? */
99 haltval = 0; /* Then we're not halted, and mustn't be */
100 tcstatval = flags; /* And pre-dump TCStatus is flags */
101 printk(" TC %d (current TC with VPE EPC above)\n", tc);
102 } else {
103 haltval = read_tc_c0_tchalt();
104 write_tc_c0_tchalt(1);
105 tcstatval = read_tc_c0_tcstatus();
106 printk(" TC %d\n", tc);
107 }
108 printk(" TCStatus : %08lx\n", tcstatval);
109 printk(" TCBind : %08lx\n", read_tc_c0_tcbind());
110 printk(" TCRestart : %08lx %pS\n",
111 read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart());
112 printk(" TCHalt : %08lx\n", haltval);
113 printk(" TCContext : %08lx\n", read_tc_c0_tccontext());
114 if (!haltval)
115 write_tc_c0_tchalt(0);
116 }
117 printk("===========================\n");
118 evpe(vpflags);
119 local_irq_restore(flags);
120}
121
122static int mt_opt_rpsctl = -1;
123static int mt_opt_nblsu = -1;
124static int mt_opt_forceconfig7;
125static int mt_opt_config7 = -1;
126
127static int __init rpsctl_set(char *str)
128{
129 get_option(&str, &mt_opt_rpsctl);
130 return 1;
131}
132__setup("rpsctl=", rpsctl_set);
133
134static int __init nblsu_set(char *str)
135{
136 get_option(&str, &mt_opt_nblsu);
137 return 1;
138}
139__setup("nblsu=", nblsu_set);
140
141static int __init config7_set(char *str)
142{
143 get_option(&str, &mt_opt_config7);
144 mt_opt_forceconfig7 = 1;
145 return 1;
146}
147__setup("config7=", config7_set);
148
149static unsigned int itc_base;
150
151static int __init set_itc_base(char *str)
152{
153 get_option(&str, &itc_base);
154 return 1;
155}
156
157__setup("itcbase=", set_itc_base);
158
159void mips_mt_set_cpuoptions(void)
160{
161 unsigned int oconfig7 = read_c0_config7();
162 unsigned int nconfig7 = oconfig7;
163
164 if (mt_opt_rpsctl >= 0) {
165 printk("34K return prediction stack override set to %d.\n",
166 mt_opt_rpsctl);
167 if (mt_opt_rpsctl)
168 nconfig7 |= (1 << 2);
169 else
170 nconfig7 &= ~(1 << 2);
171 }
172 if (mt_opt_nblsu >= 0) {
173 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
174 if (mt_opt_nblsu)
175 nconfig7 |= (1 << 5);
176 else
177 nconfig7 &= ~(1 << 5);
178 }
179 if (mt_opt_forceconfig7) {
180 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
181 nconfig7 = mt_opt_config7;
182 }
183 if (oconfig7 != nconfig7) {
184 __asm__ __volatile("sync");
185 write_c0_config7(nconfig7);
186 ehb();
187 printk("Config7: 0x%08x\n", read_c0_config7());
188 }
189
190 if (itc_base != 0) {
191 /*
192 * Configure ITC mapping. This code is very
193 * specific to the 34K core family, which uses
194 * a special mode bit ("ITC") in the ErrCtl
195 * register to enable access to ITC control
196 * registers via cache "tag" operations.
197 */
198 unsigned long ectlval;
199 unsigned long itcblkgrn;
200
201 /* ErrCtl register is known as "ecc" to Linux */
202 ectlval = read_c0_ecc();
203 write_c0_ecc(ectlval | (0x1 << 26));
204 ehb();
205#define INDEX_0 (0x80000000)
206#define INDEX_8 (0x80000008)
207 /* Read "cache tag" for Dcache pseudo-index 8 */
208 cache_op(Index_Load_Tag_D, INDEX_8);
209 ehb();
210 itcblkgrn = read_c0_dtaglo();
211 itcblkgrn &= 0xfffe0000;
212 /* Set for 128 byte pitch of ITC cells */
213 itcblkgrn |= 0x00000c00;
214 /* Stage in Tag register */
215 write_c0_dtaglo(itcblkgrn);
216 ehb();
217 /* Write out to ITU with CACHE op */
218 cache_op(Index_Store_Tag_D, INDEX_8);
219 /* Now set base address, and turn ITC on with 0x1 bit */
220 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
221 ehb();
222 /* Write out to ITU with CACHE op */
223 cache_op(Index_Store_Tag_D, INDEX_0);
224 write_c0_ecc(ectlval);
225 ehb();
226 printk("Mapped %ld ITC cells starting at 0x%08x\n",
227 ((itcblkgrn & 0x7fe00000) >> 20), itc_base);
228 }
229}
230
231struct class *mt_class;
232
233static int __init mips_mt_init(void)
234{
235 struct class *mtc;
236
237 mtc = class_create(THIS_MODULE, "mt");
238 if (IS_ERR(mtc))
239 return PTR_ERR(mtc);
240
241 mt_class = mtc;
242
243 return 0;
244}
245
246subsys_initcall(mips_mt_init);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * General MIPS MT support routines, usable in AP/SP and SMVP.
4 * Copyright (C) 2005 Mips Technologies, Inc
5 */
6
7#include <linux/device.h>
8#include <linux/kernel.h>
9#include <linux/sched.h>
10#include <linux/export.h>
11#include <linux/interrupt.h>
12#include <linux/security.h>
13
14#include <asm/cpu.h>
15#include <asm/processor.h>
16#include <linux/atomic.h>
17#include <asm/hardirq.h>
18#include <asm/mmu_context.h>
19#include <asm/mipsmtregs.h>
20#include <asm/r4kcache.h>
21#include <asm/cacheflush.h>
22#include <asm/mips_mt.h>
23
24int vpelimit;
25
26static int __init maxvpes(char *str)
27{
28 get_option(&str, &vpelimit);
29
30 return 1;
31}
32
33__setup("maxvpes=", maxvpes);
34
35int tclimit;
36
37static int __init maxtcs(char *str)
38{
39 get_option(&str, &tclimit);
40
41 return 1;
42}
43
44__setup("maxtcs=", maxtcs);
45
46/*
47 * Dump new MIPS MT state for the core. Does not leave TCs halted.
48 * Takes an argument which taken to be a pre-call MVPControl value.
49 */
50
51void mips_mt_regdump(unsigned long mvpctl)
52{
53 unsigned long flags;
54 unsigned long vpflags;
55 unsigned long mvpconf0;
56 int nvpe;
57 int ntc;
58 int i;
59 int tc;
60 unsigned long haltval;
61 unsigned long tcstatval;
62
63 local_irq_save(flags);
64 vpflags = dvpe();
65 printk("=== MIPS MT State Dump ===\n");
66 printk("-- Global State --\n");
67 printk(" MVPControl Passed: %08lx\n", mvpctl);
68 printk(" MVPControl Read: %08lx\n", vpflags);
69 printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
70 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
71 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
72 printk("-- per-VPE State --\n");
73 for (i = 0; i < nvpe; i++) {
74 for (tc = 0; tc < ntc; tc++) {
75 settc(tc);
76 if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
77 printk(" VPE %d\n", i);
78 printk(" VPEControl : %08lx\n",
79 read_vpe_c0_vpecontrol());
80 printk(" VPEConf0 : %08lx\n",
81 read_vpe_c0_vpeconf0());
82 printk(" VPE%d.Status : %08lx\n",
83 i, read_vpe_c0_status());
84 printk(" VPE%d.EPC : %08lx %pS\n",
85 i, read_vpe_c0_epc(),
86 (void *) read_vpe_c0_epc());
87 printk(" VPE%d.Cause : %08lx\n",
88 i, read_vpe_c0_cause());
89 printk(" VPE%d.Config7 : %08lx\n",
90 i, read_vpe_c0_config7());
91 break; /* Next VPE */
92 }
93 }
94 }
95 printk("-- per-TC State --\n");
96 for (tc = 0; tc < ntc; tc++) {
97 settc(tc);
98 if (read_tc_c0_tcbind() == read_c0_tcbind()) {
99 /* Are we dumping ourself? */
100 haltval = 0; /* Then we're not halted, and mustn't be */
101 tcstatval = flags; /* And pre-dump TCStatus is flags */
102 printk(" TC %d (current TC with VPE EPC above)\n", tc);
103 } else {
104 haltval = read_tc_c0_tchalt();
105 write_tc_c0_tchalt(1);
106 tcstatval = read_tc_c0_tcstatus();
107 printk(" TC %d\n", tc);
108 }
109 printk(" TCStatus : %08lx\n", tcstatval);
110 printk(" TCBind : %08lx\n", read_tc_c0_tcbind());
111 printk(" TCRestart : %08lx %pS\n",
112 read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart());
113 printk(" TCHalt : %08lx\n", haltval);
114 printk(" TCContext : %08lx\n", read_tc_c0_tccontext());
115 if (!haltval)
116 write_tc_c0_tchalt(0);
117 }
118 printk("===========================\n");
119 evpe(vpflags);
120 local_irq_restore(flags);
121}
122
123static int mt_opt_rpsctl = -1;
124static int mt_opt_nblsu = -1;
125static int mt_opt_forceconfig7;
126static int mt_opt_config7 = -1;
127
128static int __init rpsctl_set(char *str)
129{
130 get_option(&str, &mt_opt_rpsctl);
131 return 1;
132}
133__setup("rpsctl=", rpsctl_set);
134
135static int __init nblsu_set(char *str)
136{
137 get_option(&str, &mt_opt_nblsu);
138 return 1;
139}
140__setup("nblsu=", nblsu_set);
141
142static int __init config7_set(char *str)
143{
144 get_option(&str, &mt_opt_config7);
145 mt_opt_forceconfig7 = 1;
146 return 1;
147}
148__setup("config7=", config7_set);
149
150static unsigned int itc_base;
151
152static int __init set_itc_base(char *str)
153{
154 get_option(&str, &itc_base);
155 return 1;
156}
157
158__setup("itcbase=", set_itc_base);
159
160void mips_mt_set_cpuoptions(void)
161{
162 unsigned int oconfig7 = read_c0_config7();
163 unsigned int nconfig7 = oconfig7;
164
165 if (mt_opt_rpsctl >= 0) {
166 printk("34K return prediction stack override set to %d.\n",
167 mt_opt_rpsctl);
168 if (mt_opt_rpsctl)
169 nconfig7 |= (1 << 2);
170 else
171 nconfig7 &= ~(1 << 2);
172 }
173 if (mt_opt_nblsu >= 0) {
174 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
175 if (mt_opt_nblsu)
176 nconfig7 |= (1 << 5);
177 else
178 nconfig7 &= ~(1 << 5);
179 }
180 if (mt_opt_forceconfig7) {
181 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
182 nconfig7 = mt_opt_config7;
183 }
184 if (oconfig7 != nconfig7) {
185 __asm__ __volatile("sync");
186 write_c0_config7(nconfig7);
187 ehb();
188 printk("Config7: 0x%08x\n", read_c0_config7());
189 }
190
191 if (itc_base != 0) {
192 /*
193 * Configure ITC mapping. This code is very
194 * specific to the 34K core family, which uses
195 * a special mode bit ("ITC") in the ErrCtl
196 * register to enable access to ITC control
197 * registers via cache "tag" operations.
198 */
199 unsigned long ectlval;
200 unsigned long itcblkgrn;
201
202 /* ErrCtl register is known as "ecc" to Linux */
203 ectlval = read_c0_ecc();
204 write_c0_ecc(ectlval | (0x1 << 26));
205 ehb();
206#define INDEX_0 (0x80000000)
207#define INDEX_8 (0x80000008)
208 /* Read "cache tag" for Dcache pseudo-index 8 */
209 cache_op(Index_Load_Tag_D, INDEX_8);
210 ehb();
211 itcblkgrn = read_c0_dtaglo();
212 itcblkgrn &= 0xfffe0000;
213 /* Set for 128 byte pitch of ITC cells */
214 itcblkgrn |= 0x00000c00;
215 /* Stage in Tag register */
216 write_c0_dtaglo(itcblkgrn);
217 ehb();
218 /* Write out to ITU with CACHE op */
219 cache_op(Index_Store_Tag_D, INDEX_8);
220 /* Now set base address, and turn ITC on with 0x1 bit */
221 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
222 ehb();
223 /* Write out to ITU with CACHE op */
224 cache_op(Index_Store_Tag_D, INDEX_0);
225 write_c0_ecc(ectlval);
226 ehb();
227 printk("Mapped %ld ITC cells starting at 0x%08x\n",
228 ((itcblkgrn & 0x7fe00000) >> 20), itc_base);
229 }
230}
231
232struct class *mt_class;
233
234static int __init mips_mt_init(void)
235{
236 struct class *mtc;
237
238 mtc = class_create("mt");
239 if (IS_ERR(mtc))
240 return PTR_ERR(mtc);
241
242 mt_class = mtc;
243
244 return 0;
245}
246
247subsys_initcall(mips_mt_init);