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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
4 *
5 * Derived from MIPS:
6 * Copyright (C) 1996, 99 Ralf Baechle
7 * Copyright (C) 2000, 2002 Maciej W. Rozycki
8 * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
9 */
10#ifndef _ASM_ADDRSPACE_H
11#define _ASM_ADDRSPACE_H
12
13#include <linux/const.h>
14
15#include <asm/loongarch.h>
16
17/*
18 * This gives the physical RAM offset.
19 */
20#ifndef __ASSEMBLY__
21#ifndef PHYS_OFFSET
22#define PHYS_OFFSET _AC(0, UL)
23#endif
24extern unsigned long vm_map_base;
25#endif /* __ASSEMBLY__ */
26
27#ifndef IO_BASE
28#define IO_BASE CSR_DMW0_BASE
29#endif
30
31#ifndef CACHE_BASE
32#define CACHE_BASE CSR_DMW1_BASE
33#endif
34
35#ifndef UNCACHE_BASE
36#define UNCACHE_BASE CSR_DMW0_BASE
37#endif
38
39#define DMW_PABITS 48
40#define TO_PHYS_MASK ((1ULL << DMW_PABITS) - 1)
41
42/*
43 * Memory above this physical address will be considered highmem.
44 */
45#ifndef HIGHMEM_START
46#define HIGHMEM_START (_AC(1, UL) << _AC(DMW_PABITS, UL))
47#endif
48
49#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
50#define TO_CACHE(x) (CACHE_BASE | ((x) & TO_PHYS_MASK))
51#define TO_UNCACHE(x) (UNCACHE_BASE | ((x) & TO_PHYS_MASK))
52
53/*
54 * This handles the memory map.
55 */
56#ifndef PAGE_OFFSET
57#define PAGE_OFFSET (CACHE_BASE + PHYS_OFFSET)
58#endif
59
60#ifndef FIXADDR_TOP
61#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
62#endif
63
64#ifdef __ASSEMBLY__
65#define _ATYPE_
66#define _ATYPE32_
67#define _ATYPE64_
68#define _CONST64_(x) x
69#else
70#define _ATYPE_ __PTRDIFF_TYPE__
71#define _ATYPE32_ int
72#define _ATYPE64_ __s64
73#ifdef CONFIG_64BIT
74#define _CONST64_(x) x ## L
75#else
76#define _CONST64_(x) x ## LL
77#endif
78#endif
79
80/*
81 * 32/64-bit LoongArch address spaces
82 */
83#ifdef __ASSEMBLY__
84#define _ACAST32_
85#define _ACAST64_
86#else
87#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
88#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
89#endif
90
91#ifdef CONFIG_32BIT
92
93#define UVRANGE 0x00000000
94#define KPRANGE0 0x80000000
95#define KPRANGE1 0xa0000000
96#define KVRANGE 0xc0000000
97
98#else
99
100#define XUVRANGE _CONST64_(0x0000000000000000)
101#define XSPRANGE _CONST64_(0x4000000000000000)
102#define XKPRANGE _CONST64_(0x8000000000000000)
103#define XKVRANGE _CONST64_(0xc000000000000000)
104
105#endif
106
107/*
108 * Returns the physical address of a KPRANGEx / XKPRANGE address
109 */
110#define PHYSADDR(a) ((_ACAST64_(a)) & TO_PHYS_MASK)
111
112/*
113 * On LoongArch, I/O ports mappring is following:
114 *
115 * | .... |
116 * |-----------------------|
117 * | pci io ports(16K~32M) |
118 * |-----------------------|
119 * | isa io ports(0 ~16K) |
120 * PCI_IOBASE ->|-----------------------|
121 * | .... |
122 */
123#define PCI_IOBASE ((void __iomem *)(vm_map_base + (2 * PAGE_SIZE)))
124#define PCI_IOSIZE SZ_32M
125#define ISA_IOSIZE SZ_16K
126#define IO_SPACE_LIMIT (PCI_IOSIZE - 1)
127
128#endif /* _ASM_ADDRSPACE_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
4 *
5 * Derived from MIPS:
6 * Copyright (C) 1996, 99 Ralf Baechle
7 * Copyright (C) 2000, 2002 Maciej W. Rozycki
8 * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
9 */
10#ifndef _ASM_ADDRSPACE_H
11#define _ASM_ADDRSPACE_H
12
13#include <linux/const.h>
14
15#include <asm/loongarch.h>
16
17/*
18 * This gives the physical RAM offset.
19 */
20#ifndef __ASSEMBLY__
21#ifndef PHYS_OFFSET
22#define PHYS_OFFSET _UL(0)
23#endif
24extern unsigned long vm_map_base;
25#endif /* __ASSEMBLY__ */
26
27#ifndef IO_BASE
28#define IO_BASE CSR_DMW0_BASE
29#endif
30
31#ifndef CACHE_BASE
32#define CACHE_BASE CSR_DMW1_BASE
33#endif
34
35#ifndef UNCACHE_BASE
36#define UNCACHE_BASE CSR_DMW0_BASE
37#endif
38
39#define DMW_PABITS 48
40#define TO_PHYS_MASK ((1ULL << DMW_PABITS) - 1)
41
42/*
43 * Memory above this physical address will be considered highmem.
44 */
45#ifndef HIGHMEM_START
46#define HIGHMEM_START (_UL(1) << _UL(DMW_PABITS))
47#endif
48
49#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
50#define TO_CACHE(x) (CACHE_BASE | ((x) & TO_PHYS_MASK))
51#define TO_UNCACHE(x) (UNCACHE_BASE | ((x) & TO_PHYS_MASK))
52
53/*
54 * This handles the memory map.
55 */
56#ifndef PAGE_OFFSET
57#define PAGE_OFFSET (CACHE_BASE + PHYS_OFFSET)
58#endif
59
60#ifndef FIXADDR_TOP
61#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
62#endif
63
64#ifdef __ASSEMBLY__
65#define _ATYPE_
66#define _ATYPE32_
67#define _ATYPE64_
68#else
69#define _ATYPE_ __PTRDIFF_TYPE__
70#define _ATYPE32_ int
71#define _ATYPE64_ __s64
72#endif
73
74#ifdef CONFIG_64BIT
75#define _CONST64_(x) _UL(x)
76#else
77#define _CONST64_(x) _ULL(x)
78#endif
79
80/*
81 * 32/64-bit LoongArch address spaces
82 */
83#ifdef __ASSEMBLY__
84#define _ACAST32_
85#define _ACAST64_
86#else
87#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
88#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
89#endif
90
91#ifdef CONFIG_32BIT
92
93#define UVRANGE 0x00000000
94#define KPRANGE0 0x80000000
95#define KPRANGE1 0xa0000000
96#define KVRANGE 0xc0000000
97
98#else
99
100#define XUVRANGE _CONST64_(0x0000000000000000)
101#define XSPRANGE _CONST64_(0x4000000000000000)
102#define XKPRANGE _CONST64_(0x8000000000000000)
103#define XKVRANGE _CONST64_(0xc000000000000000)
104
105#endif
106
107/*
108 * Returns the physical address of a KPRANGEx / XKPRANGE address
109 */
110#define PHYSADDR(a) ((_ACAST64_(a)) & TO_PHYS_MASK)
111
112/*
113 * On LoongArch, I/O ports mappring is following:
114 *
115 * | .... |
116 * |-----------------------|
117 * | pci io ports(16K~32M) |
118 * |-----------------------|
119 * | isa io ports(0 ~16K) |
120 * PCI_IOBASE ->|-----------------------|
121 * | .... |
122 */
123#define PCI_IOBASE ((void __iomem *)(vm_map_base + (2 * PAGE_SIZE)))
124#define PCI_IOSIZE SZ_32M
125#define ISA_IOSIZE SZ_16K
126#define IO_SPACE_LIMIT (PCI_IOSIZE - 1)
127
128#define PHYS_LINK_KADDR PHYSADDR(VMLINUX_LOAD_ADDRESS)
129
130#endif /* _ASM_ADDRSPACE_H */