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1// SPDX-License-Identifier: GPL-2.0
2
3#include <dt-bindings/input/gpio-keys.h>
4#include <dt-bindings/input/input.h>
5#include <dt-bindings/thermal/thermal.h>
6
7#include "tegra30.dtsi"
8#include "tegra30-cpu-opp.dtsi"
9#include "tegra30-cpu-opp-microvolt.dtsi"
10
11/ {
12 chassis-type = "convertible";
13
14 aliases {
15 mmc0 = "/mmc@78000600"; /* eMMC */
16 mmc1 = "/mmc@78000000"; /* uSD slot */
17 mmc2 = "/mmc@78000400"; /* WiFi */
18
19 rtc0 = &pmic;
20 rtc1 = "/rtc@7000e000";
21
22 display0 = &lcd;
23 display1 = &hdmi;
24
25 serial1 = &uartc; /* Bluetooth */
26 serial2 = &uartb; /* GPS */
27 };
28
29 /*
30 * The decompressor and also some bootloaders rely on a
31 * pre-existing /chosen node to be available to insert the
32 * command line and merge other ATAGS info.
33 */
34 chosen {};
35
36 memory@80000000 {
37 reg = <0x80000000 0x40000000>;
38 };
39
40 reserved-memory {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 ranges;
44
45 linux,cma@80000000 {
46 compatible = "shared-dma-pool";
47 alloc-ranges = <0x80000000 0x30000000>;
48 size = <0x10000000>; /* 256MiB */
49 linux,cma-default;
50 reusable;
51 };
52
53 ramoops@beb00000 {
54 compatible = "ramoops";
55 reg = <0xbeb00000 0x10000>; /* 64kB */
56 console-size = <0x8000>; /* 32kB */
57 record-size = <0x400>; /* 1kB */
58 ecc-size = <16>;
59 };
60
61 trustzone@bfe00000 {
62 reg = <0xbfe00000 0x200000>; /* 2MB */
63 no-map;
64 };
65 };
66
67 host1x@50000000 {
68 hdmi: hdmi@54280000 {
69 status = "okay";
70
71 hdmi-supply = <&hdmi_5v0_sys>;
72 pll-supply = <&vdd_1v8_vio>;
73 vdd-supply = <&vdd_3v3_sys>;
74
75 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
76 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
77 };
78 };
79
80 gpio@6000d000 {
81 init-lpm-in-hog {
82 gpio-hog;
83 gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>,
84 <TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
85 input;
86 };
87
88 init-lpm-out-hog {
89 gpio-hog;
90 gpios = <TEGRA_GPIO(K, 7) GPIO_ACTIVE_HIGH>,
91 <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
92 output-low;
93 };
94
95 usb-charge-limit-hog {
96 gpio-hog;
97 gpios = <TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
98 output-high;
99 };
100 };
101
102 vde@6001a000 {
103 assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
104 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
105 assigned-clock-rates = <408000000>;
106 };
107
108 pinmux@70000868 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&state_default>;
111
112 state_default: pinmux {
113 /* SDMMC1 pinmux */
114 sdmmc1_clk {
115 nvidia,pins = "sdmmc1_clk_pz0";
116 nvidia,function = "sdmmc1";
117 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
118 nvidia,tristate = <TEGRA_PIN_DISABLE>;
119 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
120 };
121
122 sdmmc1_cmd {
123 nvidia,pins = "sdmmc1_dat3_py4",
124 "sdmmc1_dat2_py5",
125 "sdmmc1_dat1_py6",
126 "sdmmc1_dat0_py7",
127 "sdmmc1_cmd_pz1";
128 nvidia,function = "sdmmc1";
129 nvidia,pull = <TEGRA_PIN_PULL_UP>;
130 nvidia,tristate = <TEGRA_PIN_DISABLE>;
131 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
132 };
133
134 sdmmc1_cd {
135 nvidia,pins = "gmi_iordy_pi5";
136 nvidia,function = "rsvd1";
137 nvidia,pull = <TEGRA_PIN_PULL_UP>;
138 nvidia,tristate = <TEGRA_PIN_DISABLE>;
139 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
140 };
141
142 sdmmc1_wp {
143 nvidia,pins = "vi_d11_pt3";
144 nvidia,function = "rsvd2";
145 nvidia,pull = <TEGRA_PIN_PULL_UP>;
146 nvidia,tristate = <TEGRA_PIN_DISABLE>;
147 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
148 };
149
150 /* SDMMC2 pinmux */
151 vi_d1_pd5 {
152 nvidia,pins = "vi_d1_pd5",
153 "vi_d2_pl0",
154 "vi_d3_pl1",
155 "vi_d5_pl3",
156 "vi_d7_pl5";
157 nvidia,function = "sdmmc2";
158 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
159 nvidia,tristate = <TEGRA_PIN_DISABLE>;
160 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
161 };
162
163 vi_d8_pl6 {
164 nvidia,pins = "vi_d8_pl6",
165 "vi_d9_pl7";
166 nvidia,function = "sdmmc2";
167 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
168 nvidia,tristate = <TEGRA_PIN_DISABLE>;
169 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
170 nvidia,lock = <0>;
171 nvidia,io-reset = <0>;
172 };
173
174 /* SDMMC3 pinmux */
175 sdmmc3_clk {
176 nvidia,pins = "sdmmc3_clk_pa6";
177 nvidia,function = "sdmmc3";
178 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
179 nvidia,tristate = <TEGRA_PIN_DISABLE>;
180 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
181 };
182
183 sdmmc3_cmd {
184 nvidia,pins = "sdmmc3_cmd_pa7",
185 "sdmmc3_dat0_pb7",
186 "sdmmc3_dat1_pb6",
187 "sdmmc3_dat2_pb5",
188 "sdmmc3_dat3_pb4",
189 "sdmmc3_dat4_pd1",
190 "sdmmc3_dat5_pd0",
191 "sdmmc3_dat6_pd3",
192 "sdmmc3_dat7_pd4";
193 nvidia,function = "sdmmc3";
194 nvidia,pull = <TEGRA_PIN_PULL_UP>;
195 nvidia,tristate = <TEGRA_PIN_DISABLE>;
196 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
197 };
198
199 /* SDMMC4 pinmux */
200 sdmmc4_clk {
201 nvidia,pins = "sdmmc4_clk_pcc4";
202 nvidia,function = "sdmmc4";
203 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
204 nvidia,tristate = <TEGRA_PIN_DISABLE>;
205 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
206 };
207
208 sdmmc4_cmd {
209 nvidia,pins = "sdmmc4_cmd_pt7",
210 "sdmmc4_dat0_paa0",
211 "sdmmc4_dat1_paa1",
212 "sdmmc4_dat2_paa2",
213 "sdmmc4_dat3_paa3",
214 "sdmmc4_dat4_paa4",
215 "sdmmc4_dat5_paa5",
216 "sdmmc4_dat6_paa6",
217 "sdmmc4_dat7_paa7";
218 nvidia,function = "sdmmc4";
219 nvidia,pull = <TEGRA_PIN_PULL_UP>;
220 nvidia,tristate = <TEGRA_PIN_DISABLE>;
221 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
222 };
223
224 sdmmc4_rst_n {
225 nvidia,pins = "sdmmc4_rst_n_pcc3";
226 nvidia,function = "rsvd2";
227 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
228 nvidia,tristate = <TEGRA_PIN_DISABLE>;
229 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
230 };
231
232 cam_mclk {
233 nvidia,pins = "cam_mclk_pcc0";
234 nvidia,function = "vi_alt3";
235 nvidia,pull = <TEGRA_PIN_PULL_UP>;
236 nvidia,tristate = <TEGRA_PIN_DISABLE>;
237 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
238 };
239
240 drive_sdmmc4 {
241 nvidia,pins = "drive_gma",
242 "drive_gmb",
243 "drive_gmc",
244 "drive_gmd";
245 nvidia,pull-down-strength = <9>;
246 nvidia,pull-up-strength = <9>;
247 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
248 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
249 };
250
251 /* I2C pinmux */
252 gen1_i2c {
253 nvidia,pins = "gen1_i2c_scl_pc4",
254 "gen1_i2c_sda_pc5";
255 nvidia,function = "i2c1";
256 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
257 nvidia,tristate = <TEGRA_PIN_DISABLE>;
258 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
259 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
260 nvidia,lock = <0>;
261 };
262
263 gen2_i2c {
264 nvidia,pins = "gen2_i2c_scl_pt5",
265 "gen2_i2c_sda_pt6";
266 nvidia,function = "i2c2";
267 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
268 nvidia,tristate = <TEGRA_PIN_DISABLE>;
269 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
270 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
271 nvidia,lock = <0>;
272 };
273
274 cam_i2c {
275 nvidia,pins = "cam_i2c_scl_pbb1",
276 "cam_i2c_sda_pbb2";
277 nvidia,function = "i2c3";
278 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
279 nvidia,tristate = <TEGRA_PIN_DISABLE>;
280 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
281 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
282 nvidia,lock = <0>;
283 };
284
285 ddc_i2c {
286 nvidia,pins = "ddc_scl_pv4",
287 "ddc_sda_pv5";
288 nvidia,function = "i2c4";
289 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
290 nvidia,tristate = <TEGRA_PIN_DISABLE>;
291 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
292 nvidia,lock = <0>;
293 };
294
295 pwr_i2c {
296 nvidia,pins = "pwr_i2c_scl_pz6",
297 "pwr_i2c_sda_pz7";
298 nvidia,function = "i2cpwr";
299 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
300 nvidia,tristate = <TEGRA_PIN_DISABLE>;
301 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
302 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
303 nvidia,lock = <0>;
304 };
305
306 hotplug_i2c {
307 nvidia,pins = "pu4";
308 nvidia,function = "rsvd4";
309 nvidia,pull = <TEGRA_PIN_PULL_UP>;
310 nvidia,tristate = <TEGRA_PIN_DISABLE>;
311 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
312 };
313
314 /* HDMI pinmux */
315 hdmi_cec {
316 nvidia,pins = "hdmi_cec_pee3";
317 nvidia,function = "cec";
318 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
319 nvidia,tristate = <TEGRA_PIN_DISABLE>;
320 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
321 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
322 nvidia,lock = <0>;
323 };
324
325 hdmi_hpd {
326 nvidia,pins = "hdmi_int_pn7";
327 nvidia,function = "hdmi";
328 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
329 nvidia,tristate = <TEGRA_PIN_ENABLE>;
330 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
331 };
332
333 /* UART-A */
334 ulpi_data0_po1 {
335 nvidia,pins = "ulpi_data0_po1";
336 nvidia,function = "uarta";
337 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
338 nvidia,tristate = <TEGRA_PIN_DISABLE>;
339 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
340 };
341
342 ulpi_data1_po2 {
343 nvidia,pins = "ulpi_data1_po2";
344 nvidia,function = "uarta";
345 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
346 nvidia,tristate = <TEGRA_PIN_ENABLE>;
347 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
348 };
349
350 ulpi_data5_po6 {
351 nvidia,pins = "ulpi_data5_po6";
352 nvidia,function = "uarta";
353 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
354 nvidia,tristate = <TEGRA_PIN_ENABLE>;
355 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
356 };
357
358 ulpi_data7_po0 {
359 nvidia,pins = "ulpi_data7_po0",
360 "ulpi_data2_po3",
361 "ulpi_data3_po4",
362 "ulpi_data4_po5",
363 "ulpi_data6_po7";
364 nvidia,function = "uarta";
365 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
366 nvidia,tristate = <TEGRA_PIN_DISABLE>;
367 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
368 };
369
370 /* UART-B */
371 uartb_txd_rts {
372 nvidia,pins = "uart2_txd_pc2",
373 "uart2_rts_n_pj6";
374 nvidia,function = "uartb";
375 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
376 nvidia,tristate = <TEGRA_PIN_DISABLE>;
377 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
378 };
379
380 uartb_rxd_cts {
381 nvidia,pins = "uart2_rxd_pc3",
382 "uart2_cts_n_pj5";
383 nvidia,function = "uartb";
384 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
385 nvidia,tristate = <TEGRA_PIN_DISABLE>;
386 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
387 };
388
389 /* UART-C */
390 uartc_rxd_cts {
391 nvidia,pins = "uart3_cts_n_pa1",
392 "uart3_rxd_pw7";
393 nvidia,function = "uartc";
394 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
395 nvidia,tristate = <TEGRA_PIN_DISABLE>;
396 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
397 };
398
399 uartc_txd_rts {
400 nvidia,pins = "uart3_rts_n_pc0",
401 "uart3_txd_pw6";
402 nvidia,function = "uartc";
403 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
404 nvidia,tristate = <TEGRA_PIN_DISABLE>;
405 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
406 };
407
408 /* UART-D */
409 ulpi_nxt_py2 {
410 nvidia,pins = "ulpi_nxt_py2";
411 nvidia,function = "uartd";
412 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
413 nvidia,tristate = <TEGRA_PIN_ENABLE>;
414 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
415 };
416
417 ulpi_clk_py0 {
418 nvidia,pins = "ulpi_clk_py0",
419 "ulpi_dir_py1",
420 "ulpi_stp_py3";
421 nvidia,function = "uartd";
422 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
423 nvidia,tristate = <TEGRA_PIN_ENABLE>;
424 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
425 };
426
427 /* I2S pinmux */
428 dap_i2s0 {
429 nvidia,pins = "dap1_fs_pn0",
430 "dap1_din_pn1",
431 "dap1_dout_pn2",
432 "dap1_sclk_pn3";
433 nvidia,function = "i2s0";
434 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
435 nvidia,tristate = <TEGRA_PIN_ENABLE>;
436 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
437 };
438
439 dap_i2s1 {
440 nvidia,pins = "dap2_fs_pa2",
441 "dap2_sclk_pa3",
442 "dap2_din_pa4",
443 "dap2_dout_pa5";
444 nvidia,function = "i2s1";
445 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
446 nvidia,tristate = <TEGRA_PIN_DISABLE>;
447 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
448 };
449
450 dap3_fs {
451 nvidia,pins = "dap3_fs_pp0",
452 "dap3_din_pp1";
453 nvidia,function = "i2s2";
454 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
455 nvidia,tristate = <TEGRA_PIN_ENABLE>;
456 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
457 };
458
459 dap3_dout {
460 nvidia,pins = "dap3_dout_pp2",
461 "dap3_sclk_pp3";
462 nvidia,function = "i2s2";
463 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
464 nvidia,tristate = <TEGRA_PIN_DISABLE>;
465 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
466 };
467
468 dap_i2s3 {
469 nvidia,pins = "dap4_fs_pp4",
470 "dap4_din_pp5",
471 "dap4_dout_pp6",
472 "dap4_sclk_pp7";
473 nvidia,function = "i2s3";
474 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
475 nvidia,tristate = <TEGRA_PIN_DISABLE>;
476 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
477 };
478
479 /* Sensors pinmux */
480 nct_irq {
481 nvidia,pins = "pcc2";
482 nvidia,function = "i2s4";
483 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
484 nvidia,tristate = <TEGRA_PIN_DISABLE>;
485 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
486 };
487
488 /* Asus EC pinmux */
489 ec_irqs {
490 nvidia,pins = "kb_row10_ps2",
491 "kb_row15_ps7";
492 nvidia,function = "kbc";
493 nvidia,pull = <TEGRA_PIN_PULL_UP>;
494 nvidia,tristate = <TEGRA_PIN_DISABLE>;
495 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
496 };
497
498 ec_reqs {
499 nvidia,pins = "kb_col1_pq1";
500 nvidia,function = "kbc";
501 nvidia,pull = <TEGRA_PIN_PULL_UP>;
502 nvidia,tristate = <TEGRA_PIN_DISABLE>;
503 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
504 };
505
506 /* Memory type bootstrap */
507 mem_boostraps {
508 nvidia,pins = "gmi_ad4_pg4",
509 "gmi_ad5_pg5";
510 nvidia,function = "nand";
511 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
512 nvidia,tristate = <TEGRA_PIN_DISABLE>;
513 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
514 };
515
516 /* PCI-e pinmux */
517 pex_l2_rst_n {
518 nvidia,pins = "pex_l2_rst_n_pcc6",
519 "pex_l0_rst_n_pdd1",
520 "pex_l1_rst_n_pdd5";
521 nvidia,function = "pcie";
522 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
523 nvidia,tristate = <TEGRA_PIN_DISABLE>;
524 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
525 };
526
527 pex_l2_clkreq_n {
528 nvidia,pins = "pex_l2_clkreq_n_pcc7",
529 "pex_l0_prsnt_n_pdd0",
530 "pex_l0_clkreq_n_pdd2",
531 "pex_wake_n_pdd3",
532 "pex_l1_prsnt_n_pdd4",
533 "pex_l1_clkreq_n_pdd6",
534 "pex_l2_prsnt_n_pdd7";
535 nvidia,function = "pcie";
536 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
537 nvidia,tristate = <TEGRA_PIN_DISABLE>;
538 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
539 };
540
541 /* SPI pinmux */
542 spi1_mosi_px4 {
543 nvidia,pins = "spi1_mosi_px4",
544 "spi1_sck_px5",
545 "spi1_cs0_n_px6",
546 "spi1_miso_px7";
547 nvidia,function = "spi1";
548 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
549 nvidia,tristate = <TEGRA_PIN_ENABLE>;
550 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
551 };
552
553 spi2_cs1_n_pw2 {
554 nvidia,pins = "spi2_cs1_n_pw2";
555 nvidia,function = "spi2";
556 nvidia,pull = <TEGRA_PIN_PULL_UP>;
557 nvidia,tristate = <TEGRA_PIN_DISABLE>;
558 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
559 };
560
561 spi2_sck_px2 {
562 nvidia,pins = "spi2_sck_px2";
563 nvidia,function = "spi2";
564 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
565 nvidia,tristate = <TEGRA_PIN_DISABLE>;
566 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
567 };
568
569 gmi_a17_pb0 {
570 nvidia,pins = "gmi_a17_pb0",
571 "gmi_a16_pj7";
572 nvidia,function = "spi4";
573 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
574 nvidia,tristate = <TEGRA_PIN_ENABLE>;
575 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
576 };
577
578 gmi_a18_pb1 {
579 nvidia,pins = "gmi_a18_pb1";
580 nvidia,function = "spi4";
581 nvidia,pull = <TEGRA_PIN_PULL_UP>;
582 nvidia,tristate = <TEGRA_PIN_DISABLE>;
583 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
584 };
585
586 gmi_a19_pk7 {
587 nvidia,pins = "gmi_a19_pk7";
588 nvidia,function = "spi4";
589 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
590 nvidia,tristate = <TEGRA_PIN_DISABLE>;
591 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
592 };
593
594 /* Display A pinmux */
595 lcd_pwr0_pb2 {
596 nvidia,pins = "lcd_pwr0_pb2",
597 "lcd_pclk_pb3",
598 "lcd_pwr1_pc1",
599 "lcd_d0_pe0",
600 "lcd_d1_pe1",
601 "lcd_d2_pe2",
602 "lcd_d3_pe3",
603 "lcd_d4_pe4",
604 "lcd_d5_pe5",
605 "lcd_d6_pe6",
606 "lcd_d7_pe7",
607 "lcd_d8_pf0",
608 "lcd_d9_pf1",
609 "lcd_d10_pf2",
610 "lcd_d11_pf3",
611 "lcd_d12_pf4",
612 "lcd_d13_pf5",
613 "lcd_d14_pf6",
614 "lcd_d15_pf7",
615 "lcd_de_pj1",
616 "lcd_hsync_pj3",
617 "lcd_vsync_pj4",
618 "lcd_d16_pm0",
619 "lcd_d17_pm1",
620 "lcd_d18_pm2",
621 "lcd_d19_pm3",
622 "lcd_d20_pm4",
623 "lcd_d21_pm5",
624 "lcd_d22_pm6",
625 "lcd_d23_pm7",
626 "lcd_dc0_pn6",
627 "lcd_sdin_pz2";
628 nvidia,function = "displaya";
629 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
630 nvidia,tristate = <TEGRA_PIN_DISABLE>;
631 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
632 };
633
634 lcd_cs0_n_pn4 {
635 nvidia,pins = "lcd_cs0_n_pn4",
636 "lcd_sdout_pn5",
637 "lcd_wr_n_pz3";
638 nvidia,function = "displaya";
639 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
640 nvidia,tristate = <TEGRA_PIN_ENABLE>;
641 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
642 };
643
644 blink {
645 nvidia,pins = "clk_32k_out_pa0";
646 nvidia,function = "blink";
647 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
648 nvidia,tristate = <TEGRA_PIN_DISABLE>;
649 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
650 };
651
652 /* KBC keys */
653 kb_col0_pq0 {
654 nvidia,pins = "kb_col0_pq0";
655 nvidia,function = "kbc";
656 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
657 nvidia,tristate = <TEGRA_PIN_ENABLE>;
658 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
659 };
660
661 kb_col1_pq1 {
662 nvidia,pins = "kb_row1_pr1",
663 "kb_row3_pr3",
664 "kb_row8_ps0",
665 "kb_row14_ps6";
666 nvidia,function = "kbc";
667 nvidia,pull = <TEGRA_PIN_PULL_UP>;
668 nvidia,tristate = <TEGRA_PIN_DISABLE>;
669 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
670 };
671
672 kb_col4_pq4 {
673 nvidia,pins = "kb_col4_pq4",
674 "kb_col5_pq5",
675 "kb_col7_pq7",
676 "kb_row2_pr2",
677 "kb_row4_pr4",
678 "kb_row5_pr5",
679 "kb_row12_ps4",
680 "kb_row13_ps5";
681 nvidia,function = "kbc";
682 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
683 nvidia,tristate = <TEGRA_PIN_ENABLE>;
684 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
685 };
686
687 gmi_wp_n_pc7 {
688 nvidia,pins = "gmi_wp_n_pc7",
689 "gmi_wait_pi7",
690 "gmi_cs3_n_pk4";
691 nvidia,function = "rsvd1";
692 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
693 nvidia,tristate = <TEGRA_PIN_ENABLE>;
694 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
695 };
696
697 gmi_cs0_n_pj0 {
698 nvidia,pins = "gmi_cs0_n_pj0",
699 "gmi_cs1_n_pj2",
700 "gmi_cs2_n_pk3";
701 nvidia,function = "rsvd1";
702 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
703 nvidia,tristate = <TEGRA_PIN_ENABLE>;
704 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
705 };
706
707 vi_pclk_pt0 {
708 nvidia,pins = "vi_pclk_pt0";
709 nvidia,function = "rsvd1";
710 nvidia,pull = <TEGRA_PIN_PULL_UP>;
711 nvidia,tristate = <TEGRA_PIN_ENABLE>;
712 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
713 nvidia,lock = <0>;
714 nvidia,io-reset = <0>;
715 };
716
717 /* GPIO keys pinmux */
718 power_key {
719 nvidia,pins = "pv0";
720 nvidia,function = "rsvd1";
721 nvidia,pull = <TEGRA_PIN_PULL_UP>;
722 nvidia,tristate = <TEGRA_PIN_ENABLE>;
723 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
724 };
725
726 vol_keys {
727 nvidia,pins = "kb_col2_pq2",
728 "kb_col3_pq3";
729 nvidia,function = "rsvd4";
730 nvidia,pull = <TEGRA_PIN_PULL_UP>;
731 nvidia,tristate = <TEGRA_PIN_ENABLE>;
732 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
733 };
734
735 /* Bluetooth */
736 bt_shutdown {
737 nvidia,pins = "pu0";
738 nvidia,function = "rsvd4";
739 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
740 nvidia,tristate = <TEGRA_PIN_DISABLE>;
741 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
742 };
743
744 bt_dev_wake {
745 nvidia,pins = "pu1";
746 nvidia,function = "rsvd1";
747 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
748 nvidia,tristate = <TEGRA_PIN_DISABLE>;
749 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
750 };
751
752 bt_host_wake {
753 nvidia,pins = "pu6";
754 nvidia,function = "rsvd4";
755 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
756 nvidia,tristate = <TEGRA_PIN_DISABLE>;
757 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
758 };
759
760 pu2 {
761 nvidia,pins = "pu2";
762 nvidia,function = "rsvd1";
763 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
764 nvidia,tristate = <TEGRA_PIN_DISABLE>;
765 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
766 };
767
768 pu3 {
769 nvidia,pins = "pu3";
770 nvidia,function = "rsvd4";
771 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
772 nvidia,tristate = <TEGRA_PIN_DISABLE>;
773 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
774 };
775
776 pcc1 {
777 nvidia,pins = "pcc1";
778 nvidia,function = "rsvd2";
779 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
780 nvidia,tristate = <TEGRA_PIN_ENABLE>;
781 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
782 };
783
784 pv2 {
785 nvidia,pins = "pv2";
786 nvidia,function = "rsvd2";
787 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
788 nvidia,tristate = <TEGRA_PIN_DISABLE>;
789 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
790 };
791
792 pv3 {
793 nvidia,pins = "pv3";
794 nvidia,function = "rsvd2";
795 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
796 nvidia,tristate = <TEGRA_PIN_ENABLE>;
797 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
798 };
799
800 vi_vsync_pd6 {
801 nvidia,pins = "vi_vsync_pd6",
802 "vi_hsync_pd7";
803 nvidia,function = "rsvd2";
804 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
805 nvidia,tristate = <TEGRA_PIN_DISABLE>;
806 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
807 nvidia,lock = <0>;
808 nvidia,io-reset = <0>;
809 };
810
811 vi_d10_pt2 {
812 nvidia,pins = "vi_d10_pt2",
813 "vi_d0_pt4", "pbb0";
814 nvidia,function = "rsvd2";
815 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
816 nvidia,tristate = <TEGRA_PIN_DISABLE>;
817 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
818 };
819
820 kb_row0_pr0 {
821 nvidia,pins = "kb_row0_pr0";
822 nvidia,function = "rsvd4";
823 nvidia,pull = <TEGRA_PIN_PULL_UP>;
824 nvidia,tristate = <TEGRA_PIN_DISABLE>;
825 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
826 };
827
828 gmi_ad0_pg0 {
829 nvidia,pins = "gmi_ad0_pg0",
830 "gmi_ad1_pg1",
831 "gmi_ad2_pg2",
832 "gmi_ad3_pg3",
833 "gmi_ad6_pg6",
834 "gmi_ad7_pg7",
835 "gmi_wr_n_pi0",
836 "gmi_oe_n_pi1",
837 "gmi_dqs_pi2",
838 "gmi_adv_n_pk0",
839 "gmi_clk_pk1";
840 nvidia,function = "nand";
841 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
842 nvidia,tristate = <TEGRA_PIN_ENABLE>;
843 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
844 };
845
846 gmi_ad13_ph5 {
847 nvidia,pins = "gmi_ad13_ph5";
848 nvidia,function = "nand";
849 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
850 nvidia,tristate = <TEGRA_PIN_DISABLE>;
851 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
852 };
853
854 gmi_ad10_ph2 {
855 nvidia,pins = "gmi_ad10_ph2",
856 "gmi_ad11_ph3",
857 "gmi_ad14_ph6";
858 nvidia,function = "nand";
859 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
860 nvidia,tristate = <TEGRA_PIN_DISABLE>;
861 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
862 };
863
864 gmi_ad12_ph4 {
865 nvidia,pins = "gmi_ad12_ph4",
866 "gmi_rst_n_pi4",
867 "gmi_cs7_n_pi6";
868 nvidia,function = "nand";
869 nvidia,pull = <TEGRA_PIN_PULL_UP>;
870 nvidia,tristate = <TEGRA_PIN_DISABLE>;
871 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
872 };
873
874 /* Vibrator control */
875 vibrator {
876 nvidia,pins = "gmi_ad15_ph7";
877 nvidia,function = "nand";
878 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
879 nvidia,tristate = <TEGRA_PIN_DISABLE>;
880 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
881 };
882
883 /* PWM pimnmux */
884 pwm_0 {
885 nvidia,pins = "gmi_ad8_ph0";
886 nvidia,function = "pwm0";
887 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
888 nvidia,tristate = <TEGRA_PIN_DISABLE>;
889 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
890 };
891
892 pwm_2 {
893 nvidia,pins = "pu5";
894 nvidia,function = "pwm2";
895 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
896 nvidia,tristate = <TEGRA_PIN_DISABLE>;
897 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
898 };
899
900 gmi_cs6_n_pi3 {
901 nvidia,pins = "gmi_cs6_n_pi3";
902 nvidia,function = "gmi";
903 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
904 nvidia,tristate = <TEGRA_PIN_ENABLE>;
905 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
906 };
907
908 /* Spdif pinmux */
909 spdif_out {
910 nvidia,pins = "spdif_out_pk5";
911 nvidia,function = "spdif";
912 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
913 nvidia,tristate = <TEGRA_PIN_ENABLE>;
914 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
915 };
916
917 spdif_in {
918 nvidia,pins = "spdif_in_pk6";
919 nvidia,function = "spdif";
920 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
921 nvidia,tristate = <TEGRA_PIN_ENABLE>;
922 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
923 };
924
925 vi_d4_pl2 {
926 nvidia,pins = "vi_d4_pl2";
927 nvidia,function = "vi";
928 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
929 nvidia,tristate = <TEGRA_PIN_DISABLE>;
930 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
931 };
932
933 vi_d6_pl4 {
934 nvidia,pins = "vi_d6_pl4";
935 nvidia,function = "vi";
936 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
937 nvidia,tristate = <TEGRA_PIN_DISABLE>;
938 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
939 nvidia,lock = <0>;
940 nvidia,io-reset = <0>;
941 };
942
943 vi_mclk_pt1 {
944 nvidia,pins = "vi_mclk_pt1";
945 nvidia,function = "vi";
946 nvidia,pull = <TEGRA_PIN_PULL_UP>;
947 nvidia,tristate = <TEGRA_PIN_DISABLE>;
948 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
949 };
950
951 jtag_rtck {
952 nvidia,pins = "jtag_rtck_pu7";
953 nvidia,function = "rtck";
954 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
955 nvidia,tristate = <TEGRA_PIN_DISABLE>;
956 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
957 };
958
959 crt_hsync_pv6 {
960 nvidia,pins = "crt_hsync_pv6",
961 "crt_vsync_pv7";
962 nvidia,function = "crt";
963 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
964 nvidia,tristate = <TEGRA_PIN_ENABLE>;
965 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
966 };
967
968 clk1_out {
969 nvidia,pins = "clk1_out_pw4";
970 nvidia,function = "extperiph1";
971 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
972 nvidia,tristate = <TEGRA_PIN_DISABLE>;
973 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
974 };
975
976 clk2_out {
977 nvidia,pins = "clk2_out_pw5";
978 nvidia,function = "extperiph2";
979 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
980 nvidia,tristate = <TEGRA_PIN_DISABLE>;
981 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
982 };
983
984 clk3_out {
985 nvidia,pins = "clk3_out_pee0";
986 nvidia,function = "extperiph3";
987 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
988 nvidia,tristate = <TEGRA_PIN_ENABLE>;
989 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
990 };
991
992 sys_clk_req {
993 nvidia,pins = "sys_clk_req_pz5";
994 nvidia,function = "sysclk";
995 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
996 nvidia,tristate = <TEGRA_PIN_DISABLE>;
997 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
998 };
999
1000 pbb4 {
1001 nvidia,pins = "pbb4";
1002 nvidia,function = "vgp4";
1003 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1004 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1005 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1006 };
1007
1008 pbb5 {
1009 nvidia,pins = "pbb5";
1010 nvidia,function = "vgp5";
1011 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1012 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1013 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1014 };
1015
1016 pbb6 {
1017 nvidia,pins = "pbb6";
1018 nvidia,function = "vgp6";
1019 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1020 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1021 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1022 };
1023
1024 clk2_req_pcc5 {
1025 nvidia,pins = "clk2_req_pcc5",
1026 "clk1_req_pee2";
1027 nvidia,function = "dap";
1028 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1029 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1030 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1031 };
1032
1033 clk3_req_pee1 {
1034 nvidia,pins = "clk3_req_pee1";
1035 nvidia,function = "dev3";
1036 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1037 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1038 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1039 };
1040
1041 owr {
1042 nvidia,pins = "owr";
1043 nvidia,function = "owr";
1044 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1045 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1046 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1047 };
1048
1049 /* GPIO power/drive control */
1050 drive_dap1 {
1051 nvidia,pins = "drive_dap1",
1052 "drive_dap2",
1053 "drive_dbg",
1054 "drive_at5",
1055 "drive_gme",
1056 "drive_ddc",
1057 "drive_ao1",
1058 "drive_uart3";
1059 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
1060 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
1061 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
1062 nvidia,pull-down-strength = <31>;
1063 nvidia,pull-up-strength = <31>;
1064 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
1065 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
1066 };
1067
1068 drive_sdio1 {
1069 nvidia,pins = "drive_sdio1",
1070 "drive_sdio3";
1071 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
1072 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
1073 nvidia,pull-down-strength = <46>;
1074 nvidia,pull-up-strength = <42>;
1075 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
1076 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
1077 };
1078 };
1079 };
1080
1081 serial@70006040 {
1082 compatible = "nvidia,tegra30-hsuart";
1083 /delete-property/ reg-shift;
1084 status = "okay";
1085
1086 /* Broadcom GPS BCM47511 */
1087 };
1088
1089 serial@70006200 {
1090 compatible = "nvidia,tegra30-hsuart";
1091 /delete-property/ reg-shift;
1092 status = "okay";
1093
1094 nvidia,adjust-baud-rates = <0 9600 100>,
1095 <9600 115200 200>,
1096 <1000000 4000000 136>;
1097
1098 bluetooth {
1099 max-speed = <4000000>;
1100
1101 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
1102 clock-names = "txco";
1103
1104 interrupt-parent = <&gpio>;
1105 interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
1106 interrupt-names = "host-wakeup";
1107
1108 device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
1109 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
1110
1111 vbat-supply = <&vdd_3v3_com>;
1112 vddio-supply = <&vdd_1v8_vio>;
1113 };
1114 };
1115
1116 pwm@7000a000 {
1117 status = "okay";
1118 };
1119
1120 lcd_ddc: i2c@7000c000 {
1121 status = "okay";
1122 clock-frequency = <100000>;
1123 };
1124
1125 i2c@7000c400 {
1126 status = "okay";
1127 clock-frequency = <400000>;
1128 };
1129
1130 i2c@7000c500 {
1131 status = "okay";
1132
1133 /* Aichi AMI306 digital compass */
1134 magnetometer@e {
1135 compatible = "asahi-kasei,ak8974";
1136 reg = <0x0e>;
1137
1138 avdd-supply = <&vdd_3v3_sys>;
1139 dvdd-supply = <&vdd_1v8_vio>;
1140 };
1141
1142 /* Dynaimage ambient light sensor */
1143 light-sensor@1c {
1144 compatible = "dynaimage,al3010";
1145 reg = <0x1c>;
1146
1147 interrupt-parent = <&gpio>;
1148 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
1149
1150 vdd-supply = <&vdd_3v3_sys>;
1151 };
1152
1153 gyroscope@68 {
1154 compatible = "invensense,mpu3050";
1155 reg = <0x68>;
1156
1157 interrupt-parent = <&gpio>;
1158 interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>;
1159
1160 vdd-supply = <&vdd_3v3_sys>;
1161 vlogic-supply = <&vdd_1v8_vio>;
1162
1163 i2c-gate {
1164 #address-cells = <1>;
1165 #size-cells = <0>;
1166
1167 accelerometer@f {
1168 compatible = "kionix,kxtf9";
1169 reg = <0x0f>;
1170
1171 interrupt-parent = <&gpio>;
1172 interrupts = <TEGRA_GPIO(O, 5) IRQ_TYPE_EDGE_RISING>;
1173
1174 vdd-supply = <&vdd_1v8_vio>;
1175 vddio-supply = <&vdd_1v8_vio>;
1176 };
1177 };
1178 };
1179 };
1180
1181 hdmi_ddc: i2c@7000c700 {
1182 status = "okay";
1183 clock-frequency = <93750>;
1184 };
1185
1186 i2c@7000d000 {
1187 status = "okay";
1188 clock-frequency = <400000>;
1189
1190 nct72: temperature-sensor@4c {
1191 compatible = "onnn,nct1008";
1192 reg = <0x4c>;
1193
1194 interrupt-parent = <&gpio>;
1195 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
1196
1197 vcc-supply = <&vdd_3v3_sys>;
1198 #thermal-sensor-cells = <1>;
1199 };
1200
1201 /* Texas Instruments TPS659110 PMIC */
1202 pmic: pmic@2d {
1203 compatible = "ti,tps65911";
1204 reg = <0x2d>;
1205
1206 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1207 #interrupt-cells = <2>;
1208 interrupt-controller;
1209 wakeup-source;
1210
1211 ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
1212 ti,system-power-controller;
1213 ti,sleep-keep-ck32k;
1214 ti,sleep-enable;
1215
1216 #gpio-cells = <2>;
1217 gpio-controller;
1218
1219 vcc1-supply = <&vdd_5v0_bat>;
1220 vcc2-supply = <&vdd_5v0_bat>;
1221 vcc3-supply = <&vdd_1v8_vio>;
1222 vcc4-supply = <&vdd_5v0_sys>;
1223 vcc5-supply = <&vdd_5v0_bat>;
1224 vcc6-supply = <&vdd_3v3_sys>;
1225 vcc7-supply = <&vdd_5v0_bat>;
1226 vccio-supply = <&vdd_5v0_bat>;
1227
1228 pmic-sleep-hog {
1229 gpio-hog;
1230 gpios = <2 GPIO_ACTIVE_HIGH>;
1231 output-high;
1232 };
1233
1234 regulators {
1235 /* VDD1 is not used by Transformers */
1236
1237 vddio_ddr: vdd2 {
1238 regulator-name = "vddio_ddr";
1239 regulator-min-microvolt = <1200000>;
1240 regulator-max-microvolt = <1200000>;
1241 regulator-always-on;
1242 regulator-boot-on;
1243 };
1244
1245 vdd_cpu: vddctrl {
1246 regulator-name = "vdd_cpu,vdd_sys";
1247 regulator-min-microvolt = <600000>;
1248 regulator-max-microvolt = <1400000>;
1249 regulator-coupled-with = <&vdd_core>;
1250 regulator-coupled-max-spread = <300000>;
1251 regulator-max-step-microvolt = <100000>;
1252 regulator-always-on;
1253 regulator-boot-on;
1254 ti,regulator-ext-sleep-control = <1>;
1255
1256 nvidia,tegra-cpu-regulator;
1257 };
1258
1259 vdd_1v8_vio: vio {
1260 regulator-name = "vdd_1v8_gen";
1261 /* FIXME: eMMC won't work, if set to 1.8 V */
1262 regulator-min-microvolt = <1500000>;
1263 regulator-max-microvolt = <3300000>;
1264 regulator-always-on;
1265 regulator-boot-on;
1266 };
1267
1268 /* eMMC VDD */
1269 vcore_emmc: ldo1 {
1270 regulator-name = "vdd_emmc_core";
1271 regulator-min-microvolt = <3300000>;
1272 regulator-max-microvolt = <3300000>;
1273 regulator-always-on;
1274 };
1275
1276 /* uSD slot VDD */
1277 vdd_usd: ldo2 {
1278 regulator-name = "vdd_usd";
1279 regulator-min-microvolt = <3100000>;
1280 regulator-max-microvolt = <3100000>;
1281 /* FIXME: Without this, voltage switching fails */
1282 regulator-always-on;
1283 };
1284
1285 /* uSD slot VDDIO */
1286 vddio_usd: ldo3 {
1287 regulator-name = "vddio_usd";
1288 regulator-min-microvolt = <1800000>;
1289 regulator-max-microvolt = <3100000>;
1290 };
1291
1292 ldo4 {
1293 regulator-name = "vdd_rtc";
1294 regulator-min-microvolt = <1200000>;
1295 regulator-max-microvolt = <1200000>;
1296 regulator-always-on;
1297 };
1298
1299 /* LDO5 is not used by Transformers */
1300
1301 ldo6 {
1302 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
1303 regulator-min-microvolt = <1200000>;
1304 regulator-max-microvolt = <1200000>;
1305 };
1306
1307 ldo7 {
1308 regulator-name = "vdd_pllm,x,u,a_p_c_s";
1309 regulator-min-microvolt = <1200000>;
1310 regulator-max-microvolt = <1200000>;
1311 regulator-always-on;
1312 regulator-boot-on;
1313 ti,regulator-ext-sleep-control = <8>;
1314 };
1315
1316 ldo8 {
1317 regulator-name = "vdd_ddr_hs";
1318 regulator-min-microvolt = <1000000>;
1319 regulator-max-microvolt = <1000000>;
1320 regulator-always-on;
1321 ti,regulator-ext-sleep-control = <8>;
1322 };
1323 };
1324 };
1325
1326 vdd_core: core-regulator@60 {
1327 compatible = "ti,tps62361";
1328 reg = <0x60>;
1329
1330 regulator-name = "tps62361-vout";
1331 regulator-min-microvolt = <500000>;
1332 regulator-max-microvolt = <1770000>;
1333 regulator-coupled-with = <&vdd_cpu>;
1334 regulator-coupled-max-spread = <300000>;
1335 regulator-max-step-microvolt = <100000>;
1336 regulator-boot-on;
1337 regulator-always-on;
1338 ti,enable-vout-discharge;
1339 ti,vsel0-state-high;
1340 ti,vsel1-state-high;
1341
1342 nvidia,tegra-core-regulator;
1343 };
1344 };
1345
1346 pmc@7000e400 {
1347 status = "okay";
1348 nvidia,invert-interrupt;
1349 /* FIXME: LP1 doesn't work at the moment */
1350 nvidia,suspend-mode = <2>;
1351 nvidia,cpu-pwr-good-time = <2000>;
1352 nvidia,cpu-pwr-off-time = <200>;
1353 nvidia,core-pwr-good-time = <3845 3845>;
1354 nvidia,core-pwr-off-time = <0>;
1355 nvidia,core-power-req-active-high;
1356 nvidia,sys-clock-req-active-high;
1357 core-supply = <&vdd_core>;
1358
1359 /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */
1360 i2c-thermtrip {
1361 nvidia,i2c-controller-id = <4>;
1362 nvidia,bus-addr = <0x2d>;
1363 nvidia,reg-addr = <0x3f>;
1364 nvidia,reg-data = <0x81>;
1365 };
1366 };
1367
1368 hda@70030000 {
1369 status = "okay";
1370 };
1371
1372 ahub@70080000 {
1373 i2s@70080400 { /* i2s1 */
1374 status = "okay";
1375 };
1376
1377 /* BT SCO */
1378 i2s@70080600 { /* i2s3 */
1379 status = "okay";
1380 };
1381 };
1382
1383 mmc@78000000 {
1384 status = "okay";
1385
1386 /* FIXME: Full 208Mhz clock rate doesn't work reliably */
1387 max-frequency = <104000000>;
1388
1389 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
1390 bus-width = <4>;
1391
1392 vmmc-supply = <&vdd_usd>; /* ldo2 */
1393 vqmmc-supply = <&vddio_usd>; /* ldo3 */
1394 };
1395
1396 mmc@78000400 {
1397 status = "okay";
1398
1399 #address-cells = <1>;
1400 #size-cells = <0>;
1401
1402 assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
1403 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
1404 assigned-clock-rates = <50000000>;
1405
1406 max-frequency = <50000000>;
1407 keep-power-in-suspend;
1408 bus-width = <4>;
1409 non-removable;
1410
1411 mmc-pwrseq = <&brcm_wifi_pwrseq>;
1412 vmmc-supply = <&vdd_3v3_com>;
1413 vqmmc-supply = <&vdd_1v8_vio>;
1414
1415 /* Azurewave AW-NH615 BCM4329B1 or AW-NH665 BCM4330B1 */
1416 wifi@1 {
1417 compatible = "brcm,bcm4329-fmac";
1418 reg = <1>;
1419
1420 interrupt-parent = <&gpio>;
1421 interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
1422 interrupt-names = "host-wake";
1423 };
1424 };
1425
1426 mmc@78000600 {
1427 status = "okay";
1428 bus-width = <8>;
1429 vmmc-supply = <&vcore_emmc>;
1430 vqmmc-supply = <&vdd_1v8_vio>;
1431 mmc-ddr-3_3v;
1432 non-removable;
1433 };
1434
1435 /* USB via ASUS connector */
1436 usb@7d000000 {
1437 compatible = "nvidia,tegra30-udc";
1438 status = "okay";
1439 dr_mode = "peripheral";
1440 };
1441
1442 usb-phy@7d000000 {
1443 status = "okay";
1444 dr_mode = "peripheral";
1445 nvidia,hssync-start-delay = <0>;
1446 nvidia,xcvr-lsfslew = <2>;
1447 nvidia,xcvr-lsrslew = <2>;
1448 vbus-supply = <&vdd_5v0_sys>;
1449 };
1450
1451 /* Dock's USB port */
1452 usb@7d008000 {
1453 status = "okay";
1454 };
1455
1456 usb-phy@7d008000 {
1457 status = "okay";
1458 vbus-supply = <&vdd_5v0_bat>;
1459 };
1460
1461 mains: ac-adapter-detect {
1462 compatible = "gpio-charger";
1463 charger-type = "mains";
1464 gpios = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
1465 };
1466
1467 backlight: backlight {
1468 compatible = "pwm-backlight";
1469
1470 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1471 power-supply = <&vdd_5v0_bl>;
1472 pwms = <&pwm 0 4000000>;
1473
1474 brightness-levels = <1 255>;
1475 num-interpolated-steps = <254>;
1476 default-brightness-level = <40>;
1477 };
1478
1479 /* PMIC has a built-in 32KHz oscillator which is used by PMC */
1480 clk32k_in: clock-32k {
1481 compatible = "fixed-clock";
1482 #clock-cells = <0>;
1483 clock-frequency = <32768>;
1484 clock-output-names = "pmic-oscillator";
1485 };
1486
1487 cpus {
1488 cpu0: cpu@0 {
1489 cpu-supply = <&vdd_cpu>;
1490 operating-points-v2 = <&cpu0_opp_table>;
1491 #cooling-cells = <2>;
1492 };
1493 cpu1: cpu@1 {
1494 cpu-supply = <&vdd_cpu>;
1495 operating-points-v2 = <&cpu0_opp_table>;
1496 #cooling-cells = <2>;
1497 };
1498 cpu2: cpu@2 {
1499 cpu-supply = <&vdd_cpu>;
1500 operating-points-v2 = <&cpu0_opp_table>;
1501 #cooling-cells = <2>;
1502 };
1503 cpu3: cpu@3 {
1504 cpu-supply = <&vdd_cpu>;
1505 operating-points-v2 = <&cpu0_opp_table>;
1506 #cooling-cells = <2>;
1507 };
1508 };
1509
1510 extcon-keys {
1511 compatible = "gpio-keys";
1512
1513 switch-dock-hall-sensor {
1514 label = "Lid sensor";
1515 gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>;
1516 linux,input-type = <EV_SW>;
1517 linux,code = <SW_LID>;
1518 debounce-interval = <500>;
1519 wakeup-event-action = <EV_ACT_ASSERTED>;
1520 wakeup-source;
1521 };
1522
1523 switch-lineout-detect {
1524 label = "Audio dock line-out detect";
1525 gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>;
1526 linux,input-type = <EV_SW>;
1527 linux,code = <SW_LINEOUT_INSERT>;
1528 debounce-interval = <10>;
1529 wakeup-event-action = <EV_ACT_ASSERTED>;
1530 wakeup-source;
1531 };
1532 };
1533
1534 firmware {
1535 trusted-foundations {
1536 compatible = "tlm,trusted-foundations";
1537 tlm,version-major = <2>;
1538 tlm,version-minor = <8>;
1539 };
1540 };
1541
1542 gpio-keys {
1543 compatible = "gpio-keys";
1544
1545 key-power {
1546 label = "Power";
1547 gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
1548 linux,code = <KEY_POWER>;
1549 debounce-interval = <10>;
1550 wakeup-event-action = <EV_ACT_ASSERTED>;
1551 wakeup-source;
1552 };
1553
1554 key-volume-up {
1555 label = "Volume Up";
1556 gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
1557 linux,code = <KEY_VOLUMEUP>;
1558 debounce-interval = <10>;
1559 wakeup-event-action = <EV_ACT_ASSERTED>;
1560 wakeup-source;
1561 };
1562
1563 key-volume-down {
1564 label = "Volume Down";
1565 gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
1566 linux,code = <KEY_VOLUMEDOWN>;
1567 debounce-interval = <10>;
1568 wakeup-event-action = <EV_ACT_ASSERTED>;
1569 wakeup-source;
1570 };
1571 };
1572
1573 vdd_5v0_bat: regulator-bat {
1574 compatible = "regulator-fixed";
1575 regulator-name = "vdd_ac_bat";
1576 regulator-min-microvolt = <5000000>;
1577 regulator-max-microvolt = <5000000>;
1578 regulator-always-on;
1579 regulator-boot-on;
1580 };
1581
1582 vdd_5v0_cp: regulator-sby {
1583 compatible = "regulator-fixed";
1584 regulator-name = "vdd_5v0_sby";
1585 regulator-min-microvolt = <5000000>;
1586 regulator-max-microvolt = <5000000>;
1587 regulator-always-on;
1588 regulator-boot-on;
1589 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
1590 enable-active-high;
1591 vin-supply = <&vdd_5v0_bat>;
1592 };
1593
1594 vdd_5v0_sys: regulator-5v {
1595 compatible = "regulator-fixed";
1596 regulator-name = "vdd_5v0_sys";
1597 regulator-min-microvolt = <5000000>;
1598 regulator-max-microvolt = <5000000>;
1599 regulator-always-on;
1600 regulator-boot-on;
1601 gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
1602 enable-active-high;
1603 vin-supply = <&vdd_5v0_bat>;
1604 };
1605
1606 vdd_1v5_ddr: regulator-ddr {
1607 compatible = "regulator-fixed";
1608 regulator-name = "vdd_ddr";
1609 regulator-min-microvolt = <1500000>;
1610 regulator-max-microvolt = <1500000>;
1611 regulator-always-on;
1612 regulator-boot-on;
1613 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
1614 enable-active-high;
1615 vin-supply = <&vdd_5v0_bat>;
1616 };
1617
1618 vdd_3v3_sys: regulator-3v {
1619 compatible = "regulator-fixed";
1620 regulator-name = "vdd_3v3_sys";
1621 regulator-min-microvolt = <3300000>;
1622 regulator-max-microvolt = <3300000>;
1623 regulator-always-on;
1624 regulator-boot-on;
1625 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1626 enable-active-high;
1627 vin-supply = <&vdd_5v0_bat>;
1628 };
1629
1630 vdd_pnl: regulator-panel {
1631 compatible = "regulator-fixed";
1632 regulator-name = "vdd_panel";
1633 regulator-min-microvolt = <3300000>;
1634 regulator-max-microvolt = <3300000>;
1635 regulator-enable-ramp-delay = <20000>;
1636 gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
1637 enable-active-high;
1638 vin-supply = <&vdd_3v3_sys>;
1639 };
1640
1641 vdd_3v3_com: regulator-com {
1642 compatible = "regulator-fixed";
1643 regulator-name = "vdd_3v3_com";
1644 regulator-min-microvolt = <3300000>;
1645 regulator-max-microvolt = <3300000>;
1646 regulator-always-on;
1647 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
1648 enable-active-high;
1649 vin-supply = <&vdd_3v3_sys>;
1650 };
1651
1652 vdd_5v0_bl: regulator-bl {
1653 compatible = "regulator-fixed";
1654 regulator-name = "vdd_5v0_bl";
1655 regulator-min-microvolt = <5000000>;
1656 regulator-max-microvolt = <5000000>;
1657 regulator-boot-on;
1658 gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
1659 enable-active-high;
1660 vin-supply = <&vdd_5v0_bat>;
1661 };
1662
1663 hdmi_5v0_sys: regulator-hdmi {
1664 compatible = "regulator-fixed";
1665 regulator-name = "hdmi_5v0_sys";
1666 regulator-min-microvolt = <5000000>;
1667 regulator-max-microvolt = <5000000>;
1668 gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
1669 enable-active-high;
1670 vin-supply = <&vdd_5v0_sys>;
1671 };
1672
1673 sound {
1674 nvidia,i2s-controller = <&tegra_i2s1>;
1675
1676 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
1677 nvidia,hp-mute-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>;
1678
1679 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1680 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1681 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1682 clock-names = "pll_a", "pll_a_out0", "mclk";
1683
1684 assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1685 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1686
1687 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1688 <&tegra_car TEGRA30_CLK_EXTERN1>;
1689 };
1690
1691 thermal-zones {
1692 /*
1693 * NCT72 has two sensors:
1694 *
1695 * 0: internal that monitors ambient/skin temperature
1696 * 1: external that is connected to the CPU's diode
1697 *
1698 * Ideally we should use userspace thermal governor,
1699 * but it's a much more complex solution. The "skin"
1700 * zone exists as a simpler solution which prevents
1701 * Transformers from getting too hot from a user's
1702 * tactile perspective. The CPU zone is intended to
1703 * protect silicon from damage.
1704 */
1705
1706 skin-thermal {
1707 polling-delay-passive = <1000>; /* milliseconds */
1708 polling-delay = <5000>; /* milliseconds */
1709
1710 thermal-sensors = <&nct72 0>;
1711
1712 trips {
1713 trip0: skin-alert {
1714 /* throttle at 57C until temperature drops to 56.8C */
1715 temperature = <57000>;
1716 hysteresis = <200>;
1717 type = "passive";
1718 };
1719
1720 trip1: skin-crit {
1721 /* shut down at 65C */
1722 temperature = <65000>;
1723 hysteresis = <2000>;
1724 type = "critical";
1725 };
1726 };
1727
1728 cooling-maps {
1729 map0 {
1730 trip = <&trip0>;
1731 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1732 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1733 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1734 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1735 <&actmon THERMAL_NO_LIMIT
1736 THERMAL_NO_LIMIT>;
1737 };
1738 };
1739 };
1740
1741 cpu-thermal {
1742 polling-delay-passive = <1000>; /* milliseconds */
1743 polling-delay = <5000>; /* milliseconds */
1744
1745 thermal-sensors = <&nct72 1>;
1746
1747 trips {
1748 trip2: cpu-alert {
1749 /* throttle at 75C until temperature drops to 74.8C */
1750 temperature = <75000>;
1751 hysteresis = <200>;
1752 type = "passive";
1753 };
1754
1755 trip3: cpu-crit {
1756 /* shut down at 90C */
1757 temperature = <90000>;
1758 hysteresis = <2000>;
1759 type = "critical";
1760 };
1761 };
1762
1763 cooling-maps {
1764 map1 {
1765 trip = <&trip2>;
1766 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1767 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1768 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1769 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1770 <&actmon THERMAL_NO_LIMIT
1771 THERMAL_NO_LIMIT>;
1772 };
1773 };
1774 };
1775 };
1776
1777 brcm_wifi_pwrseq: wifi-pwrseq {
1778 compatible = "mmc-pwrseq-simple";
1779
1780 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
1781 clock-names = "ext_clock";
1782
1783 reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>;
1784 post-power-on-delay-ms = <300>;
1785 power-off-delay-us = <300>;
1786 };
1787};