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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp13-clks.h>
8#include <dt-bindings/reset/stm32mp13-resets.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a7";
20 device_type = "cpu";
21 reg = <0>;
22 };
23 };
24
25 arm-pmu {
26 compatible = "arm,cortex-a7-pmu";
27 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
28 interrupt-affinity = <&cpu0>;
29 interrupt-parent = <&intc>;
30 };
31
32 firmware {
33 optee {
34 method = "smc";
35 compatible = "linaro,optee-tz";
36 };
37
38 scmi: scmi {
39 compatible = "linaro,scmi-optee";
40 #address-cells = <1>;
41 #size-cells = <0>;
42 linaro,optee-channel-id = <0>;
43 shmem = <&scmi_shm>;
44
45 scmi_clk: protocol@14 {
46 reg = <0x14>;
47 #clock-cells = <1>;
48 };
49
50 scmi_reset: protocol@16 {
51 reg = <0x16>;
52 #reset-cells = <1>;
53 };
54 };
55 };
56
57 intc: interrupt-controller@a0021000 {
58 compatible = "arm,cortex-a7-gic";
59 #interrupt-cells = <3>;
60 interrupt-controller;
61 reg = <0xa0021000 0x1000>,
62 <0xa0022000 0x2000>;
63 };
64
65 psci {
66 compatible = "arm,psci-1.0";
67 method = "smc";
68 };
69
70 timer {
71 compatible = "arm,armv7-timer";
72 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
73 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
74 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
76 interrupt-parent = <&intc>;
77 always-on;
78 };
79
80 /* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */
81 reg11: reg11 {
82 compatible = "regulator-fixed";
83 regulator-name = "reg11";
84 regulator-min-microvolt = <1100000>;
85 regulator-max-microvolt = <1100000>;
86 };
87
88 reg18: reg18 {
89 compatible = "regulator-fixed";
90 regulator-name = "reg18";
91 regulator-min-microvolt = <1800000>;
92 regulator-max-microvolt = <1800000>;
93 };
94
95 usb33: usb33 {
96 compatible = "regulator-fixed";
97 regulator-name = "usb33";
98 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <3300000>;
100 };
101
102 soc {
103 compatible = "simple-bus";
104 #address-cells = <1>;
105 #size-cells = <1>;
106 interrupt-parent = <&intc>;
107 ranges;
108
109 scmi_sram: sram@2ffff000 {
110 compatible = "mmio-sram";
111 reg = <0x2ffff000 0x1000>;
112 #address-cells = <1>;
113 #size-cells = <1>;
114 ranges = <0 0x2ffff000 0x1000>;
115
116 scmi_shm: scmi-sram@0 {
117 compatible = "arm,scmi-shmem";
118 reg = <0 0x80>;
119 };
120 };
121
122 spi2: spi@4000b000 {
123 compatible = "st,stm32h7-spi";
124 reg = <0x4000b000 0x400>;
125 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
126 clocks = <&rcc SPI2_K>;
127 resets = <&rcc SPI2_R>;
128 #address-cells = <1>;
129 #size-cells = <0>;
130 dmas = <&dmamux1 39 0x400 0x01>,
131 <&dmamux1 40 0x400 0x01>;
132 dma-names = "rx", "tx";
133 status = "disabled";
134 };
135
136 spi3: spi@4000c000 {
137 compatible = "st,stm32h7-spi";
138 reg = <0x4000c000 0x400>;
139 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&rcc SPI3_K>;
141 resets = <&rcc SPI3_R>;
142 #address-cells = <1>;
143 #size-cells = <0>;
144 dmas = <&dmamux1 61 0x400 0x01>,
145 <&dmamux1 62 0x400 0x01>;
146 dma-names = "rx", "tx";
147 status = "disabled";
148 };
149
150 uart4: serial@40010000 {
151 compatible = "st,stm32h7-uart";
152 reg = <0x40010000 0x400>;
153 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&rcc UART4_K>;
155 resets = <&rcc UART4_R>;
156 status = "disabled";
157 };
158
159 i2c1: i2c@40012000 {
160 compatible = "st,stm32mp13-i2c";
161 reg = <0x40012000 0x400>;
162 interrupt-names = "event", "error";
163 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&rcc I2C1_K>;
166 resets = <&rcc I2C1_R>;
167 #address-cells = <1>;
168 #size-cells = <0>;
169 dmas = <&dmamux1 33 0x400 0x1>,
170 <&dmamux1 34 0x400 0x1>;
171 dma-names = "rx", "tx";
172 st,syscfg-fmp = <&syscfg 0x4 0x1>;
173 i2c-analog-filter;
174 status = "disabled";
175 };
176
177 i2c2: i2c@40013000 {
178 compatible = "st,stm32mp13-i2c";
179 reg = <0x40013000 0x400>;
180 interrupt-names = "event", "error";
181 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&rcc I2C2_K>;
184 resets = <&rcc I2C2_R>;
185 #address-cells = <1>;
186 #size-cells = <0>;
187 dmas = <&dmamux1 35 0x400 0x1>,
188 <&dmamux1 36 0x400 0x1>;
189 dma-names = "rx", "tx";
190 st,syscfg-fmp = <&syscfg 0x4 0x2>;
191 i2c-analog-filter;
192 status = "disabled";
193 };
194
195 spi1: spi@44004000 {
196 compatible = "st,stm32h7-spi";
197 reg = <0x44004000 0x400>;
198 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&rcc SPI1_K>;
200 resets = <&rcc SPI1_R>;
201 #address-cells = <1>;
202 #size-cells = <0>;
203 dmas = <&dmamux1 37 0x400 0x01>,
204 <&dmamux1 38 0x400 0x01>;
205 dma-names = "rx", "tx";
206 status = "disabled";
207 };
208
209 dma1: dma-controller@48000000 {
210 compatible = "st,stm32-dma";
211 reg = <0x48000000 0x400>;
212 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&rcc DMA1>;
221 resets = <&rcc DMA1_R>;
222 #dma-cells = <4>;
223 st,mem2mem;
224 dma-requests = <8>;
225 };
226
227 dma2: dma-controller@48001000 {
228 compatible = "st,stm32-dma";
229 reg = <0x48001000 0x400>;
230 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&rcc DMA2>;
239 resets = <&rcc DMA2_R>;
240 #dma-cells = <4>;
241 st,mem2mem;
242 dma-requests = <8>;
243 };
244
245 dmamux1: dma-router@48002000 {
246 compatible = "st,stm32h7-dmamux";
247 reg = <0x48002000 0x40>;
248 clocks = <&rcc DMAMUX1>;
249 resets = <&rcc DMAMUX1_R>;
250 #dma-cells = <3>;
251 dma-masters = <&dma1 &dma2>;
252 dma-requests = <128>;
253 dma-channels = <16>;
254 };
255
256 adc_2: adc@48004000 {
257 compatible = "st,stm32mp13-adc-core";
258 reg = <0x48004000 0x400>;
259 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&rcc ADC2>, <&rcc ADC2_K>;
261 clock-names = "bus", "adc";
262 interrupt-controller;
263 #interrupt-cells = <1>;
264 #address-cells = <1>;
265 #size-cells = <0>;
266 status = "disabled";
267
268 adc2: adc@0 {
269 compatible = "st,stm32mp13-adc";
270 #io-channel-cells = <1>;
271 #address-cells = <1>;
272 #size-cells = <0>;
273 reg = <0x0>;
274 interrupt-parent = <&adc_2>;
275 interrupts = <0>;
276 dmas = <&dmamux1 10 0x400 0x80000001>;
277 dma-names = "rx";
278 status = "disabled";
279
280 channel@13 {
281 reg = <13>;
282 label = "vrefint";
283 };
284 channel@14 {
285 reg = <14>;
286 label = "vddcore";
287 };
288 channel@16 {
289 reg = <16>;
290 label = "vddcpu";
291 };
292 channel@17 {
293 reg = <17>;
294 label = "vddq_ddr";
295 };
296 };
297 };
298
299 usbotg_hs: usb@49000000 {
300 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
301 reg = <0x49000000 0x40000>;
302 clocks = <&rcc USBO_K>;
303 clock-names = "otg";
304 resets = <&rcc USBO_R>;
305 reset-names = "dwc2";
306 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
307 g-rx-fifo-size = <512>;
308 g-np-tx-fifo-size = <32>;
309 g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
310 dr_mode = "otg";
311 otg-rev = <0x200>;
312 usb33d-supply = <&usb33>;
313 status = "disabled";
314 };
315
316 spi4: spi@4c002000 {
317 compatible = "st,stm32h7-spi";
318 reg = <0x4c002000 0x400>;
319 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&rcc SPI4_K>;
321 resets = <&rcc SPI4_R>;
322 #address-cells = <1>;
323 #size-cells = <0>;
324 dmas = <&dmamux1 83 0x400 0x01>,
325 <&dmamux1 84 0x400 0x01>;
326 dma-names = "rx", "tx";
327 status = "disabled";
328 };
329
330 spi5: spi@4c003000 {
331 compatible = "st,stm32h7-spi";
332 reg = <0x4c003000 0x400>;
333 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&rcc SPI5_K>;
335 resets = <&rcc SPI5_R>;
336 #address-cells = <1>;
337 #size-cells = <0>;
338 dmas = <&dmamux1 85 0x400 0x01>,
339 <&dmamux1 86 0x400 0x01>;
340 dma-names = "rx", "tx";
341 status = "disabled";
342 };
343
344 i2c3: i2c@4c004000 {
345 compatible = "st,stm32mp13-i2c";
346 reg = <0x4c004000 0x400>;
347 interrupt-names = "event", "error";
348 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&rcc I2C3_K>;
351 resets = <&rcc I2C3_R>;
352 #address-cells = <1>;
353 #size-cells = <0>;
354 dmas = <&dmamux1 73 0x400 0x1>,
355 <&dmamux1 74 0x400 0x1>;
356 dma-names = "rx", "tx";
357 st,syscfg-fmp = <&syscfg 0x4 0x4>;
358 i2c-analog-filter;
359 status = "disabled";
360 };
361
362 i2c4: i2c@4c005000 {
363 compatible = "st,stm32mp13-i2c";
364 reg = <0x4c005000 0x400>;
365 interrupt-names = "event", "error";
366 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&rcc I2C4_K>;
369 resets = <&rcc I2C4_R>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372 dmas = <&dmamux1 75 0x400 0x1>,
373 <&dmamux1 76 0x400 0x1>;
374 dma-names = "rx", "tx";
375 st,syscfg-fmp = <&syscfg 0x4 0x8>;
376 i2c-analog-filter;
377 status = "disabled";
378 };
379
380 i2c5: i2c@4c006000 {
381 compatible = "st,stm32mp13-i2c";
382 reg = <0x4c006000 0x400>;
383 interrupt-names = "event", "error";
384 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&rcc I2C5_K>;
387 resets = <&rcc I2C5_R>;
388 #address-cells = <1>;
389 #size-cells = <0>;
390 dmas = <&dmamux1 115 0x400 0x1>,
391 <&dmamux1 116 0x400 0x1>;
392 dma-names = "rx", "tx";
393 st,syscfg-fmp = <&syscfg 0x4 0x10>;
394 i2c-analog-filter;
395 status = "disabled";
396 };
397
398 rcc: rcc@50000000 {
399 compatible = "st,stm32mp13-rcc", "syscon";
400 reg = <0x50000000 0x1000>;
401 #clock-cells = <1>;
402 #reset-cells = <1>;
403 clock-names = "hse", "hsi", "csi", "lse", "lsi";
404 clocks = <&scmi_clk CK_SCMI_HSE>,
405 <&scmi_clk CK_SCMI_HSI>,
406 <&scmi_clk CK_SCMI_CSI>,
407 <&scmi_clk CK_SCMI_LSE>,
408 <&scmi_clk CK_SCMI_LSI>;
409 };
410
411 exti: interrupt-controller@5000d000 {
412 compatible = "st,stm32mp13-exti", "syscon";
413 interrupt-controller;
414 #interrupt-cells = <2>;
415 reg = <0x5000d000 0x400>;
416 };
417
418 syscfg: syscon@50020000 {
419 compatible = "st,stm32mp157-syscfg", "syscon";
420 reg = <0x50020000 0x400>;
421 clocks = <&rcc SYSCFG>;
422 };
423
424 mdma: dma-controller@58000000 {
425 compatible = "st,stm32h7-mdma";
426 reg = <0x58000000 0x1000>;
427 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&rcc MDMA>;
429 #dma-cells = <5>;
430 dma-channels = <32>;
431 dma-requests = <48>;
432 };
433
434 sdmmc1: mmc@58005000 {
435 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
436 arm,primecell-periphid = <0x20253180>;
437 reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
438 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&rcc SDMMC1_K>;
440 clock-names = "apb_pclk";
441 resets = <&rcc SDMMC1_R>;
442 cap-sd-highspeed;
443 cap-mmc-highspeed;
444 max-frequency = <130000000>;
445 status = "disabled";
446 };
447
448 sdmmc2: mmc@58007000 {
449 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
450 arm,primecell-periphid = <0x20253180>;
451 reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
452 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&rcc SDMMC2_K>;
454 clock-names = "apb_pclk";
455 resets = <&rcc SDMMC2_R>;
456 cap-sd-highspeed;
457 cap-mmc-highspeed;
458 max-frequency = <130000000>;
459 status = "disabled";
460 };
461
462 usbh_ohci: usb@5800c000 {
463 compatible = "generic-ohci";
464 reg = <0x5800c000 0x1000>;
465 clocks = <&usbphyc>, <&rcc USBH>;
466 resets = <&rcc USBH_R>;
467 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
468 status = "disabled";
469 };
470
471 usbh_ehci: usb@5800d000 {
472 compatible = "generic-ehci";
473 reg = <0x5800d000 0x1000>;
474 clocks = <&usbphyc>, <&rcc USBH>;
475 resets = <&rcc USBH_R>;
476 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
477 companion = <&usbh_ohci>;
478 status = "disabled";
479 };
480
481 iwdg2: watchdog@5a002000 {
482 compatible = "st,stm32mp1-iwdg";
483 reg = <0x5a002000 0x400>;
484 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
485 clock-names = "pclk", "lsi";
486 status = "disabled";
487 };
488
489 usbphyc: usbphyc@5a006000 {
490 #address-cells = <1>;
491 #size-cells = <0>;
492 #clock-cells = <0>;
493 compatible = "st,stm32mp1-usbphyc";
494 reg = <0x5a006000 0x1000>;
495 clocks = <&rcc USBPHY_K>;
496 resets = <&rcc USBPHY_R>;
497 vdda1v1-supply = <®11>;
498 vdda1v8-supply = <®18>;
499 status = "disabled";
500
501 usbphyc_port0: usb-phy@0 {
502 #phy-cells = <0>;
503 reg = <0>;
504 };
505
506 usbphyc_port1: usb-phy@1 {
507 #phy-cells = <1>;
508 reg = <1>;
509 };
510 };
511
512 rtc: rtc@5c004000 {
513 compatible = "st,stm32mp1-rtc";
514 reg = <0x5c004000 0x400>;
515 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&scmi_clk CK_SCMI_RTCAPB>,
517 <&scmi_clk CK_SCMI_RTC>;
518 clock-names = "pclk", "rtc_ck";
519 status = "disabled";
520 };
521
522 bsec: efuse@5c005000 {
523 compatible = "st,stm32mp15-bsec";
524 reg = <0x5c005000 0x400>;
525 #address-cells = <1>;
526 #size-cells = <1>;
527
528 part_number_otp: part_number_otp@4 {
529 reg = <0x4 0x2>;
530 };
531 ts_cal1: calib@5c {
532 reg = <0x5c 0x2>;
533 };
534 ts_cal2: calib@5e {
535 reg = <0x5e 0x2>;
536 };
537 };
538
539 /*
540 * Break node order to solve dependency probe issue between
541 * pinctrl and exti.
542 */
543 pinctrl: pinctrl@50002000 {
544 #address-cells = <1>;
545 #size-cells = <1>;
546 compatible = "st,stm32mp135-pinctrl";
547 ranges = <0 0x50002000 0x8400>;
548 interrupt-parent = <&exti>;
549 st,syscfg = <&exti 0x60 0xff>;
550 pins-are-numbered;
551
552 gpioa: gpio@50002000 {
553 gpio-controller;
554 #gpio-cells = <2>;
555 interrupt-controller;
556 #interrupt-cells = <2>;
557 reg = <0x0 0x400>;
558 clocks = <&rcc GPIOA>;
559 st,bank-name = "GPIOA";
560 ngpios = <16>;
561 gpio-ranges = <&pinctrl 0 0 16>;
562 };
563
564 gpiob: gpio@50003000 {
565 gpio-controller;
566 #gpio-cells = <2>;
567 interrupt-controller;
568 #interrupt-cells = <2>;
569 reg = <0x1000 0x400>;
570 clocks = <&rcc GPIOB>;
571 st,bank-name = "GPIOB";
572 ngpios = <16>;
573 gpio-ranges = <&pinctrl 0 16 16>;
574 };
575
576 gpioc: gpio@50004000 {
577 gpio-controller;
578 #gpio-cells = <2>;
579 interrupt-controller;
580 #interrupt-cells = <2>;
581 reg = <0x2000 0x400>;
582 clocks = <&rcc GPIOC>;
583 st,bank-name = "GPIOC";
584 ngpios = <16>;
585 gpio-ranges = <&pinctrl 0 32 16>;
586 };
587
588 gpiod: gpio@50005000 {
589 gpio-controller;
590 #gpio-cells = <2>;
591 interrupt-controller;
592 #interrupt-cells = <2>;
593 reg = <0x3000 0x400>;
594 clocks = <&rcc GPIOD>;
595 st,bank-name = "GPIOD";
596 ngpios = <16>;
597 gpio-ranges = <&pinctrl 0 48 16>;
598 };
599
600 gpioe: gpio@50006000 {
601 gpio-controller;
602 #gpio-cells = <2>;
603 interrupt-controller;
604 #interrupt-cells = <2>;
605 reg = <0x4000 0x400>;
606 clocks = <&rcc GPIOE>;
607 st,bank-name = "GPIOE";
608 ngpios = <16>;
609 gpio-ranges = <&pinctrl 0 64 16>;
610 };
611
612 gpiof: gpio@50007000 {
613 gpio-controller;
614 #gpio-cells = <2>;
615 interrupt-controller;
616 #interrupt-cells = <2>;
617 reg = <0x5000 0x400>;
618 clocks = <&rcc GPIOF>;
619 st,bank-name = "GPIOF";
620 ngpios = <16>;
621 gpio-ranges = <&pinctrl 0 80 16>;
622 };
623
624 gpiog: gpio@50008000 {
625 gpio-controller;
626 #gpio-cells = <2>;
627 interrupt-controller;
628 #interrupt-cells = <2>;
629 reg = <0x6000 0x400>;
630 clocks = <&rcc GPIOG>;
631 st,bank-name = "GPIOG";
632 ngpios = <16>;
633 gpio-ranges = <&pinctrl 0 96 16>;
634 };
635
636 gpioh: gpio@50009000 {
637 gpio-controller;
638 #gpio-cells = <2>;
639 interrupt-controller;
640 #interrupt-cells = <2>;
641 reg = <0x7000 0x400>;
642 clocks = <&rcc GPIOH>;
643 st,bank-name = "GPIOH";
644 ngpios = <15>;
645 gpio-ranges = <&pinctrl 0 112 15>;
646 };
647
648 gpioi: gpio@5000a000 {
649 gpio-controller;
650 #gpio-cells = <2>;
651 interrupt-controller;
652 #interrupt-cells = <2>;
653 reg = <0x8000 0x400>;
654 clocks = <&rcc GPIOI>;
655 st,bank-name = "GPIOI";
656 ngpios = <8>;
657 gpio-ranges = <&pinctrl 0 128 8>;
658 };
659 };
660 };
661};