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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mfd/qcom-rpm.h>
6#include <dt-bindings/clock/qcom,rpmcc.h>
7#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11#include <dt-bindings/soc/qcom,gsbi.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14/ {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 model = "Qualcomm IPQ8064";
18 compatible = "qcom,ipq8064";
19 interrupt-parent = <&intc>;
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu0: cpu@0 {
26 compatible = "qcom,krait";
27 enable-method = "qcom,kpss-acc-v1";
28 device_type = "cpu";
29 reg = <0>;
30 next-level-cache = <&L2>;
31 qcom,acc = <&acc0>;
32 qcom,saw = <&saw0>;
33 };
34
35 cpu1: cpu@1 {
36 compatible = "qcom,krait";
37 enable-method = "qcom,kpss-acc-v1";
38 device_type = "cpu";
39 reg = <1>;
40 next-level-cache = <&L2>;
41 qcom,acc = <&acc1>;
42 qcom,saw = <&saw1>;
43 };
44
45 L2: l2-cache {
46 compatible = "cache";
47 cache-level = <2>;
48 cache-unified;
49 };
50 };
51
52 thermal-zones {
53 sensor0-thermal {
54 polling-delay-passive = <0>;
55 polling-delay = <0>;
56 thermal-sensors = <&tsens 0>;
57
58 trips {
59 cpu-critical {
60 temperature = <105000>;
61 hysteresis = <2000>;
62 type = "critical";
63 };
64
65 cpu-hot {
66 temperature = <95000>;
67 hysteresis = <2000>;
68 type = "hot";
69 };
70 };
71 };
72
73 sensor1-thermal {
74 polling-delay-passive = <0>;
75 polling-delay = <0>;
76 thermal-sensors = <&tsens 1>;
77
78 trips {
79 cpu-critical {
80 temperature = <105000>;
81 hysteresis = <2000>;
82 type = "critical";
83 };
84
85 cpu-hot {
86 temperature = <95000>;
87 hysteresis = <2000>;
88 type = "hot";
89 };
90 };
91 };
92
93 sensor2-thermal {
94 polling-delay-passive = <0>;
95 polling-delay = <0>;
96 thermal-sensors = <&tsens 2>;
97
98 trips {
99 cpu-critical {
100 temperature = <105000>;
101 hysteresis = <2000>;
102 type = "critical";
103 };
104
105 cpu-hot {
106 temperature = <95000>;
107 hysteresis = <2000>;
108 type = "hot";
109 };
110 };
111 };
112
113 sensor3-thermal {
114 polling-delay-passive = <0>;
115 polling-delay = <0>;
116 thermal-sensors = <&tsens 3>;
117
118 trips {
119 cpu-critical {
120 temperature = <105000>;
121 hysteresis = <2000>;
122 type = "critical";
123 };
124
125 cpu-hot {
126 temperature = <95000>;
127 hysteresis = <2000>;
128 type = "hot";
129 };
130 };
131 };
132
133 sensor4-thermal {
134 polling-delay-passive = <0>;
135 polling-delay = <0>;
136 thermal-sensors = <&tsens 4>;
137
138 trips {
139 cpu-critical {
140 temperature = <105000>;
141 hysteresis = <2000>;
142 type = "critical";
143 };
144
145 cpu-hot {
146 temperature = <95000>;
147 hysteresis = <2000>;
148 type = "hot";
149 };
150 };
151 };
152
153 sensor5-thermal {
154 polling-delay-passive = <0>;
155 polling-delay = <0>;
156 thermal-sensors = <&tsens 5>;
157
158 trips {
159 cpu-critical {
160 temperature = <105000>;
161 hysteresis = <2000>;
162 type = "critical";
163 };
164
165 cpu-hot {
166 temperature = <95000>;
167 hysteresis = <2000>;
168 type = "hot";
169 };
170 };
171 };
172
173 sensor6-thermal {
174 polling-delay-passive = <0>;
175 polling-delay = <0>;
176 thermal-sensors = <&tsens 6>;
177
178 trips {
179 cpu-critical {
180 temperature = <105000>;
181 hysteresis = <2000>;
182 type = "critical";
183 };
184
185 cpu-hot {
186 temperature = <95000>;
187 hysteresis = <2000>;
188 type = "hot";
189 };
190 };
191 };
192
193 sensor7-thermal {
194 polling-delay-passive = <0>;
195 polling-delay = <0>;
196 thermal-sensors = <&tsens 7>;
197
198 trips {
199 cpu-critical {
200 temperature = <105000>;
201 hysteresis = <2000>;
202 type = "critical";
203 };
204
205 cpu-hot {
206 temperature = <95000>;
207 hysteresis = <2000>;
208 type = "hot";
209 };
210 };
211 };
212
213 sensor8-thermal {
214 polling-delay-passive = <0>;
215 polling-delay = <0>;
216 thermal-sensors = <&tsens 8>;
217
218 trips {
219 cpu-critical {
220 temperature = <105000>;
221 hysteresis = <2000>;
222 type = "critical";
223 };
224
225 cpu-hot {
226 temperature = <95000>;
227 hysteresis = <2000>;
228 type = "hot";
229 };
230 };
231 };
232
233 sensor9-thermal {
234 polling-delay-passive = <0>;
235 polling-delay = <0>;
236 thermal-sensors = <&tsens 9>;
237
238 trips {
239 cpu-critical {
240 temperature = <105000>;
241 hysteresis = <2000>;
242 type = "critical";
243 };
244
245 cpu-hot {
246 temperature = <95000>;
247 hysteresis = <2000>;
248 type = "hot";
249 };
250 };
251 };
252
253 sensor10-thermal {
254 polling-delay-passive = <0>;
255 polling-delay = <0>;
256 thermal-sensors = <&tsens 10>;
257
258 trips {
259 cpu-critical {
260 temperature = <105000>;
261 hysteresis = <2000>;
262 type = "critical";
263 };
264
265 cpu-hot {
266 temperature = <95000>;
267 hysteresis = <2000>;
268 type = "hot";
269 };
270 };
271 };
272 };
273
274 memory {
275 device_type = "memory";
276 reg = <0x0 0x0>;
277 };
278
279 cpu-pmu {
280 compatible = "qcom,krait-pmu";
281 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
282 IRQ_TYPE_LEVEL_HIGH)>;
283 };
284
285 reserved-memory {
286 #address-cells = <1>;
287 #size-cells = <1>;
288 ranges;
289
290 nss@40000000 {
291 reg = <0x40000000 0x1000000>;
292 no-map;
293 };
294
295 smem: smem@41000000 {
296 compatible = "qcom,smem";
297 reg = <0x41000000 0x200000>;
298 no-map;
299
300 hwlocks = <&sfpb_mutex 3>;
301 };
302 };
303
304 clocks {
305 cxo_board: cxo_board {
306 compatible = "fixed-clock";
307 #clock-cells = <0>;
308 clock-frequency = <25000000>;
309 };
310
311 pxo_board: pxo_board {
312 compatible = "fixed-clock";
313 #clock-cells = <0>;
314 clock-frequency = <25000000>;
315 };
316
317 sleep_clk: sleep_clk {
318 compatible = "fixed-clock";
319 clock-frequency = <32768>;
320 #clock-cells = <0>;
321 };
322 };
323
324 firmware {
325 scm {
326 compatible = "qcom,scm-ipq806x", "qcom,scm";
327 };
328 };
329
330 stmmac_axi_setup: stmmac-axi-config {
331 snps,wr_osr_lmt = <7>;
332 snps,rd_osr_lmt = <7>;
333 snps,blen = <16 0 0 0 0 0 0>;
334 };
335
336 vsdcc_fixed: vsdcc-regulator {
337 compatible = "regulator-fixed";
338 regulator-name = "SDCC Power";
339 regulator-min-microvolt = <3300000>;
340 regulator-max-microvolt = <3300000>;
341 regulator-always-on;
342 };
343
344 soc: soc {
345 #address-cells = <1>;
346 #size-cells = <1>;
347 ranges;
348 compatible = "simple-bus";
349
350 rpm: rpm@108000 {
351 compatible = "qcom,rpm-ipq8064";
352 reg = <0x00108000 0x1000>;
353 qcom,ipc = <&l2cc 0x8 2>;
354
355 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
358 interrupt-names = "ack", "err", "wakeup";
359
360 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
361 clock-names = "ram";
362
363 rpmcc: clock-controller {
364 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
365 #clock-cells = <1>;
366 };
367 };
368
369 ssbi@500000 {
370 compatible = "qcom,ssbi";
371 reg = <0x00500000 0x1000>;
372 qcom,controller-type = "pmic-arbiter";
373 };
374
375 qfprom: qfprom@700000 {
376 compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
377 reg = <0x00700000 0x1000>;
378 #address-cells = <1>;
379 #size-cells = <1>;
380 speedbin_efuse: speedbin@c0 {
381 reg = <0xc0 0x4>;
382 };
383 tsens_calib: calib@400 {
384 reg = <0x400 0xb>;
385 };
386 tsens_calib_backup: calib_backup@410 {
387 reg = <0x410 0xb>;
388 };
389 };
390
391 qcom_pinmux: pinmux@800000 {
392 compatible = "qcom,ipq8064-pinctrl";
393 reg = <0x00800000 0x4000>;
394
395 gpio-controller;
396 gpio-ranges = <&qcom_pinmux 0 0 69>;
397 #gpio-cells = <2>;
398 interrupt-controller;
399 #interrupt-cells = <2>;
400 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
401
402 pcie0_pins: pcie0_pinmux {
403 mux {
404 pins = "gpio3";
405 function = "pcie1_rst";
406 drive-strength = <12>;
407 bias-disable;
408 };
409 };
410
411 pcie1_pins: pcie1_pinmux {
412 mux {
413 pins = "gpio48";
414 function = "pcie2_rst";
415 drive-strength = <12>;
416 bias-disable;
417 };
418 };
419
420 pcie2_pins: pcie2_pinmux {
421 mux {
422 pins = "gpio63";
423 function = "pcie3_rst";
424 drive-strength = <12>;
425 bias-disable;
426 };
427 };
428
429 i2c4_pins: i2c4-default {
430 pins = "gpio12", "gpio13";
431 function = "gsbi4";
432 drive-strength = <12>;
433 bias-disable;
434 };
435
436 spi_pins: spi_pins {
437 mux {
438 pins = "gpio18", "gpio19", "gpio21";
439 function = "gsbi5";
440 drive-strength = <10>;
441 bias-none;
442 };
443 };
444
445 leds_pins: leds_pins {
446 mux {
447 pins = "gpio7", "gpio8", "gpio9",
448 "gpio26", "gpio53";
449 function = "gpio";
450 drive-strength = <2>;
451 bias-pull-down;
452 output-low;
453 };
454 };
455
456 buttons_pins: buttons_pins {
457 mux {
458 pins = "gpio54";
459 drive-strength = <2>;
460 bias-pull-up;
461 };
462 };
463
464 nand_pins: nand_pins {
465 mux {
466 pins = "gpio34", "gpio35", "gpio36",
467 "gpio37", "gpio38", "gpio39",
468 "gpio40", "gpio41", "gpio42",
469 "gpio43", "gpio44", "gpio45",
470 "gpio46", "gpio47";
471 function = "nand";
472 drive-strength = <10>;
473 bias-disable;
474 };
475
476 pullups {
477 pins = "gpio39";
478 function = "nand";
479 drive-strength = <10>;
480 bias-pull-up;
481 };
482
483 hold {
484 pins = "gpio40", "gpio41", "gpio42",
485 "gpio43", "gpio44", "gpio45",
486 "gpio46", "gpio47";
487 function = "nand";
488 drive-strength = <10>;
489 bias-bus-hold;
490 };
491 };
492
493 mdio0_pins: mdio0-pins {
494 mux {
495 pins = "gpio0", "gpio1";
496 function = "mdio";
497 drive-strength = <8>;
498 bias-disable;
499 };
500 };
501
502 rgmii2_pins: rgmii2-pins {
503 mux {
504 pins = "gpio27", "gpio28", "gpio29",
505 "gpio30", "gpio31", "gpio32",
506 "gpio51", "gpio52", "gpio59",
507 "gpio60", "gpio61", "gpio62";
508 function = "rgmii2";
509 drive-strength = <8>;
510 bias-disable;
511 };
512 };
513 };
514
515 gcc: clock-controller@900000 {
516 compatible = "qcom,gcc-ipq8064", "syscon";
517 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
518 clock-names = "pxo", "cxo", "pll4";
519 reg = <0x00900000 0x4000>;
520 #clock-cells = <1>;
521 #reset-cells = <1>;
522 #power-domain-cells = <1>;
523
524 tsens: thermal-sensor {
525 compatible = "qcom,ipq8064-tsens";
526
527 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
528 nvmem-cell-names = "calib", "calib_backup";
529 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
530 interrupt-names = "uplow";
531
532 #qcom,sensors = <11>;
533 #thermal-sensor-cells = <1>;
534 };
535 };
536
537 sfpb_mutex: hwlock@1200600 {
538 compatible = "qcom,sfpb-mutex";
539 reg = <0x01200600 0x100>;
540
541 #hwlock-cells = <1>;
542 };
543
544 intc: interrupt-controller@2000000 {
545 compatible = "qcom,msm-qgic2";
546 interrupt-controller;
547 #interrupt-cells = <3>;
548 reg = <0x02000000 0x1000>,
549 <0x02002000 0x1000>;
550 };
551
552 timer@200a000 {
553 compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer",
554 "qcom,msm-timer";
555 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
556 IRQ_TYPE_EDGE_RISING)>,
557 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
558 IRQ_TYPE_EDGE_RISING)>,
559 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
560 IRQ_TYPE_EDGE_RISING)>,
561 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
562 IRQ_TYPE_EDGE_RISING)>,
563 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
564 IRQ_TYPE_EDGE_RISING)>;
565 reg = <0x0200a000 0x100>;
566 clock-frequency = <25000000>;
567 clocks = <&sleep_clk>;
568 clock-names = "sleep";
569 cpu-offset = <0x80000>;
570 };
571
572 l2cc: clock-controller@2011000 {
573 compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon";
574 reg = <0x02011000 0x1000>;
575 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
576 clock-names = "pll8_vote", "pxo";
577 #clock-cells = <0>;
578 };
579
580 acc0: clock-controller@2088000 {
581 compatible = "qcom,kpss-acc-v1";
582 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
583 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
584 clock-names = "pll8_vote", "pxo";
585 clock-output-names = "acpu0_aux";
586 #clock-cells = <0>;
587 };
588
589 saw0: regulator@2089000 {
590 compatible = "qcom,saw2";
591 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
592 regulator;
593 };
594
595 acc1: clock-controller@2098000 {
596 compatible = "qcom,kpss-acc-v1";
597 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
598 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
599 clock-names = "pll8_vote", "pxo";
600 clock-output-names = "acpu1_aux";
601 #clock-cells = <0>;
602 };
603
604 saw1: regulator@2099000 {
605 compatible = "qcom,saw2";
606 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
607 regulator;
608 };
609
610 nss_common: syscon@3000000 {
611 compatible = "syscon";
612 reg = <0x03000000 0x0000FFFF>;
613 };
614
615 usb3_0: usb@100f8800 {
616 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
617 #address-cells = <1>;
618 #size-cells = <1>;
619 reg = <0x100f8800 0x8000>;
620 clocks = <&gcc USB30_0_MASTER_CLK>;
621 clock-names = "core";
622
623 ranges;
624
625 resets = <&gcc USB30_0_MASTER_RESET>;
626 reset-names = "master";
627
628 status = "disabled";
629
630 dwc3_0: usb@10000000 {
631 compatible = "snps,dwc3";
632 reg = <0x10000000 0xcd00>;
633 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
634 phys = <&hs_phy_0>, <&ss_phy_0>;
635 phy-names = "usb2-phy", "usb3-phy";
636 dr_mode = "host";
637 snps,dis_u3_susphy_quirk;
638 };
639 };
640
641 hs_phy_0: phy@100f8800 {
642 compatible = "qcom,ipq806x-usb-phy-hs";
643 reg = <0x100f8800 0x30>;
644 clocks = <&gcc USB30_0_UTMI_CLK>;
645 clock-names = "ref";
646 #phy-cells = <0>;
647
648 status = "disabled";
649 };
650
651 ss_phy_0: phy@100f8830 {
652 compatible = "qcom,ipq806x-usb-phy-ss";
653 reg = <0x100f8830 0x30>;
654 clocks = <&gcc USB30_0_MASTER_CLK>;
655 clock-names = "ref";
656 #phy-cells = <0>;
657
658 status = "disabled";
659 };
660
661 usb3_1: usb@110f8800 {
662 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
663 #address-cells = <1>;
664 #size-cells = <1>;
665 reg = <0x110f8800 0x8000>;
666 clocks = <&gcc USB30_1_MASTER_CLK>;
667 clock-names = "core";
668
669 ranges;
670
671 resets = <&gcc USB30_1_MASTER_RESET>;
672 reset-names = "master";
673
674 status = "disabled";
675
676 dwc3_1: usb@11000000 {
677 compatible = "snps,dwc3";
678 reg = <0x11000000 0xcd00>;
679 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
680 phys = <&hs_phy_1>, <&ss_phy_1>;
681 phy-names = "usb2-phy", "usb3-phy";
682 dr_mode = "host";
683 snps,dis_u3_susphy_quirk;
684 };
685 };
686
687 hs_phy_1: phy@110f8800 {
688 compatible = "qcom,ipq806x-usb-phy-hs";
689 reg = <0x110f8800 0x30>;
690 clocks = <&gcc USB30_1_UTMI_CLK>;
691 clock-names = "ref";
692 #phy-cells = <0>;
693
694 status = "disabled";
695 };
696
697 ss_phy_1: phy@110f8830 {
698 compatible = "qcom,ipq806x-usb-phy-ss";
699 reg = <0x110f8830 0x30>;
700 clocks = <&gcc USB30_1_MASTER_CLK>;
701 clock-names = "ref";
702 #phy-cells = <0>;
703
704 status = "disabled";
705 };
706
707 sdcc3bam: dma-controller@12182000 {
708 compatible = "qcom,bam-v1.3.0";
709 reg = <0x12182000 0x8000>;
710 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&gcc SDC3_H_CLK>;
712 clock-names = "bam_clk";
713 #dma-cells = <1>;
714 qcom,ee = <0>;
715 };
716
717 sdcc1bam: dma-controller@12402000 {
718 compatible = "qcom,bam-v1.3.0";
719 reg = <0x12402000 0x8000>;
720 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&gcc SDC1_H_CLK>;
722 clock-names = "bam_clk";
723 #dma-cells = <1>;
724 qcom,ee = <0>;
725 };
726
727 amba: amba {
728 compatible = "simple-bus";
729 #address-cells = <1>;
730 #size-cells = <1>;
731 ranges;
732
733 sdcc3: mmc@12180000 {
734 compatible = "arm,pl18x", "arm,primecell";
735 arm,primecell-periphid = <0x00051180>;
736 status = "disabled";
737 reg = <0x12180000 0x2000>;
738 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
740 clock-names = "mclk", "apb_pclk";
741 bus-width = <8>;
742 cap-sd-highspeed;
743 cap-mmc-highspeed;
744 max-frequency = <192000000>;
745 sd-uhs-sdr104;
746 sd-uhs-ddr50;
747 vqmmc-supply = <&vsdcc_fixed>;
748 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
749 dma-names = "tx", "rx";
750 };
751
752 sdcc1: mmc@12400000 {
753 status = "disabled";
754 compatible = "arm,pl18x", "arm,primecell";
755 arm,primecell-periphid = <0x00051180>;
756 reg = <0x12400000 0x2000>;
757 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
759 clock-names = "mclk", "apb_pclk";
760 bus-width = <8>;
761 max-frequency = <96000000>;
762 non-removable;
763 cap-sd-highspeed;
764 cap-mmc-highspeed;
765 vmmc-supply = <&vsdcc_fixed>;
766 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
767 dma-names = "tx", "rx";
768 };
769 };
770
771 gsbi1: gsbi@12440000 {
772 compatible = "qcom,gsbi-v1.0.0";
773 reg = <0x12440000 0x100>;
774 cell-index = <1>;
775 clocks = <&gcc GSBI1_H_CLK>;
776 clock-names = "iface";
777 #address-cells = <1>;
778 #size-cells = <1>;
779 ranges;
780
781 syscon-tcsr = <&tcsr>;
782
783 status = "disabled";
784
785 gsbi1_serial: serial@12450000 {
786 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
787 reg = <0x12450000 0x100>,
788 <0x12400000 0x03>;
789 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
791 clock-names = "core", "iface";
792
793 status = "disabled";
794 };
795
796 gsbi1_i2c: i2c@12460000 {
797 compatible = "qcom,i2c-qup-v1.1.1";
798 reg = <0x12460000 0x1000>;
799 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
801 clock-names = "core", "iface";
802 #address-cells = <1>;
803 #size-cells = <0>;
804
805 status = "disabled";
806 };
807 };
808
809 gsbi2: gsbi@12480000 {
810 compatible = "qcom,gsbi-v1.0.0";
811 cell-index = <2>;
812 reg = <0x12480000 0x100>;
813 clocks = <&gcc GSBI2_H_CLK>;
814 clock-names = "iface";
815 #address-cells = <1>;
816 #size-cells = <1>;
817 ranges;
818 status = "disabled";
819
820 syscon-tcsr = <&tcsr>;
821
822 gsbi2_serial: serial@12490000 {
823 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
824 reg = <0x12490000 0x1000>,
825 <0x12480000 0x1000>;
826 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
827 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
828 clock-names = "core", "iface";
829 status = "disabled";
830 };
831
832 gsbi2_i2c: i2c@124a0000 {
833 compatible = "qcom,i2c-qup-v1.1.1";
834 reg = <0x124a0000 0x1000>;
835 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
836
837 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
838 clock-names = "core", "iface";
839 status = "disabled";
840
841 #address-cells = <1>;
842 #size-cells = <0>;
843 };
844 };
845
846 gsbi4: gsbi@16300000 {
847 compatible = "qcom,gsbi-v1.0.0";
848 cell-index = <4>;
849 reg = <0x16300000 0x100>;
850 clocks = <&gcc GSBI4_H_CLK>;
851 clock-names = "iface";
852 #address-cells = <1>;
853 #size-cells = <1>;
854 ranges;
855 status = "disabled";
856
857 syscon-tcsr = <&tcsr>;
858
859 gsbi4_serial: serial@16340000 {
860 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
861 reg = <0x16340000 0x1000>,
862 <0x16300000 0x1000>;
863 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
864 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
865 clock-names = "core", "iface";
866 status = "disabled";
867 };
868
869 i2c@16380000 {
870 compatible = "qcom,i2c-qup-v1.1.1";
871 reg = <0x16380000 0x1000>;
872 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
873
874 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
875 clock-names = "core", "iface";
876 status = "disabled";
877
878 #address-cells = <1>;
879 #size-cells = <0>;
880 };
881 };
882
883 gsbi6: gsbi@16500000 {
884 compatible = "qcom,gsbi-v1.0.0";
885 reg = <0x16500000 0x100>;
886 cell-index = <6>;
887 clocks = <&gcc GSBI6_H_CLK>;
888 clock-names = "iface";
889 #address-cells = <1>;
890 #size-cells = <1>;
891 ranges;
892
893 syscon-tcsr = <&tcsr>;
894
895 status = "disabled";
896
897 gsbi6_i2c: i2c@16580000 {
898 compatible = "qcom,i2c-qup-v1.1.1";
899 reg = <0x16580000 0x1000>;
900 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
901
902 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
903 clock-names = "core", "iface";
904
905 #address-cells = <1>;
906 #size-cells = <0>;
907
908 status = "disabled";
909 };
910
911 gsbi6_spi: spi@16580000 {
912 compatible = "qcom,spi-qup-v1.1.1";
913 reg = <0x16580000 0x1000>;
914 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
915
916 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
917 clock-names = "core", "iface";
918
919 #address-cells = <1>;
920 #size-cells = <0>;
921
922 status = "disabled";
923 };
924 };
925
926 gsbi7: gsbi@16600000 {
927 status = "disabled";
928 compatible = "qcom,gsbi-v1.0.0";
929 cell-index = <7>;
930 reg = <0x16600000 0x100>;
931 clocks = <&gcc GSBI7_H_CLK>;
932 clock-names = "iface";
933 #address-cells = <1>;
934 #size-cells = <1>;
935 ranges;
936 syscon-tcsr = <&tcsr>;
937
938 gsbi7_serial: serial@16640000 {
939 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
940 reg = <0x16640000 0x1000>,
941 <0x16600000 0x1000>;
942 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
944 clock-names = "core", "iface";
945 status = "disabled";
946 };
947
948 gsbi7_i2c: i2c@16680000 {
949 compatible = "qcom,i2c-qup-v1.1.1";
950 reg = <0x16680000 0x1000>;
951 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
952
953 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
954 clock-names = "core", "iface";
955
956 #address-cells = <1>;
957 #size-cells = <0>;
958
959 status = "disabled";
960 };
961 };
962
963 adm_dma: dma-controller@18300000 {
964 compatible = "qcom,adm";
965 reg = <0x18300000 0x100000>;
966 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
967 #dma-cells = <1>;
968
969 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
970 clock-names = "core", "iface";
971
972 resets = <&gcc ADM0_RESET>,
973 <&gcc ADM0_PBUS_RESET>,
974 <&gcc ADM0_C0_RESET>,
975 <&gcc ADM0_C1_RESET>,
976 <&gcc ADM0_C2_RESET>;
977 reset-names = "clk", "pbus", "c0", "c1", "c2";
978 qcom,ee = <0>;
979
980 status = "disabled";
981 };
982
983 gsbi5: gsbi@1a200000 {
984 compatible = "qcom,gsbi-v1.0.0";
985 cell-index = <5>;
986 reg = <0x1a200000 0x100>;
987 clocks = <&gcc GSBI5_H_CLK>;
988 clock-names = "iface";
989 #address-cells = <1>;
990
991 #size-cells = <1>;
992 ranges;
993 status = "disabled";
994
995 syscon-tcsr = <&tcsr>;
996
997 gsbi5_serial: serial@1a240000 {
998 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
999 reg = <0x1a240000 0x1000>,
1000 <0x1a200000 0x1000>;
1001 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
1003 clock-names = "core", "iface";
1004 status = "disabled";
1005 };
1006
1007 i2c@1a280000 {
1008 compatible = "qcom,i2c-qup-v1.1.1";
1009 reg = <0x1a280000 0x1000>;
1010 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1011
1012 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1013 clock-names = "core", "iface";
1014 status = "disabled";
1015
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1018 };
1019
1020 spi@1a280000 {
1021 compatible = "qcom,spi-qup-v1.1.1";
1022 reg = <0x1a280000 0x1000>;
1023 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1024
1025 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1026 clock-names = "core", "iface";
1027 status = "disabled";
1028
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1031 };
1032 };
1033
1034 tcsr: syscon@1a400000 {
1035 compatible = "qcom,tcsr-ipq8064", "syscon";
1036 reg = <0x1a400000 0x100>;
1037 };
1038
1039 rng@1a500000 {
1040 compatible = "qcom,prng";
1041 reg = <0x1a500000 0x200>;
1042 clocks = <&gcc PRNG_CLK>;
1043 clock-names = "core";
1044 };
1045
1046 nand: nand-controller@1ac00000 {
1047 compatible = "qcom,ipq806x-nand";
1048 reg = <0x1ac00000 0x800>;
1049
1050 pinctrl-0 = <&nand_pins>;
1051 pinctrl-names = "default";
1052
1053 clocks = <&gcc EBI2_CLK>,
1054 <&gcc EBI2_AON_CLK>;
1055 clock-names = "core", "aon";
1056
1057 dmas = <&adm_dma 3>;
1058 dma-names = "rxtx";
1059 qcom,cmd-crci = <15>;
1060 qcom,data-crci = <3>;
1061
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1064
1065 status = "disabled";
1066 };
1067
1068 sata_phy: sata-phy@1b400000 {
1069 compatible = "qcom,ipq806x-sata-phy";
1070 reg = <0x1b400000 0x200>;
1071
1072 clocks = <&gcc SATA_PHY_CFG_CLK>;
1073 clock-names = "cfg";
1074
1075 #phy-cells = <0>;
1076 status = "disabled";
1077 };
1078
1079 pcie0: pcie@1b500000 {
1080 compatible = "qcom,pcie-ipq8064";
1081 reg = <0x1b500000 0x1000
1082 0x1b502000 0x80
1083 0x1b600000 0x100
1084 0x0ff00000 0x100000>;
1085 reg-names = "dbi", "elbi", "parf", "config";
1086 device_type = "pci";
1087 linux,pci-domain = <0>;
1088 bus-range = <0x00 0xff>;
1089 num-lanes = <1>;
1090 #address-cells = <3>;
1091 #size-cells = <2>;
1092
1093 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */
1094 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */
1095
1096 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1097 interrupt-names = "msi";
1098 #interrupt-cells = <1>;
1099 interrupt-map-mask = <0 0 0 0x7>;
1100 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1101 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1102 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1103 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1104
1105 clocks = <&gcc PCIE_A_CLK>,
1106 <&gcc PCIE_H_CLK>,
1107 <&gcc PCIE_PHY_CLK>,
1108 <&gcc PCIE_AUX_CLK>,
1109 <&gcc PCIE_ALT_REF_CLK>;
1110 clock-names = "core", "iface", "phy", "aux", "ref";
1111
1112 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1113 assigned-clock-rates = <100000000>;
1114
1115 resets = <&gcc PCIE_ACLK_RESET>,
1116 <&gcc PCIE_HCLK_RESET>,
1117 <&gcc PCIE_POR_RESET>,
1118 <&gcc PCIE_PCI_RESET>,
1119 <&gcc PCIE_PHY_RESET>,
1120 <&gcc PCIE_EXT_RESET>;
1121 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1122
1123 pinctrl-0 = <&pcie0_pins>;
1124 pinctrl-names = "default";
1125
1126 status = "disabled";
1127 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1128 };
1129
1130 pcie1: pcie@1b700000 {
1131 compatible = "qcom,pcie-ipq8064";
1132 reg = <0x1b700000 0x1000
1133 0x1b702000 0x80
1134 0x1b800000 0x100
1135 0x31f00000 0x100000>;
1136 reg-names = "dbi", "elbi", "parf", "config";
1137 device_type = "pci";
1138 linux,pci-domain = <1>;
1139 bus-range = <0x00 0xff>;
1140 num-lanes = <1>;
1141 #address-cells = <3>;
1142 #size-cells = <2>;
1143
1144 ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */
1145 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */
1146
1147 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1148 interrupt-names = "msi";
1149 #interrupt-cells = <1>;
1150 interrupt-map-mask = <0 0 0 0x7>;
1151 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1152 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1153 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1154 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1155
1156 clocks = <&gcc PCIE_1_A_CLK>,
1157 <&gcc PCIE_1_H_CLK>,
1158 <&gcc PCIE_1_PHY_CLK>,
1159 <&gcc PCIE_1_AUX_CLK>,
1160 <&gcc PCIE_1_ALT_REF_CLK>;
1161 clock-names = "core", "iface", "phy", "aux", "ref";
1162
1163 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1164 assigned-clock-rates = <100000000>;
1165
1166 resets = <&gcc PCIE_1_ACLK_RESET>,
1167 <&gcc PCIE_1_HCLK_RESET>,
1168 <&gcc PCIE_1_POR_RESET>,
1169 <&gcc PCIE_1_PCI_RESET>,
1170 <&gcc PCIE_1_PHY_RESET>,
1171 <&gcc PCIE_1_EXT_RESET>;
1172 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1173
1174 pinctrl-0 = <&pcie1_pins>;
1175 pinctrl-names = "default";
1176
1177 status = "disabled";
1178 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1179 };
1180
1181 pcie2: pcie@1b900000 {
1182 compatible = "qcom,pcie-ipq8064";
1183 reg = <0x1b900000 0x1000
1184 0x1b902000 0x80
1185 0x1ba00000 0x100
1186 0x35f00000 0x100000>;
1187 reg-names = "dbi", "elbi", "parf", "config";
1188 device_type = "pci";
1189 linux,pci-domain = <2>;
1190 bus-range = <0x00 0xff>;
1191 num-lanes = <1>;
1192 #address-cells = <3>;
1193 #size-cells = <2>;
1194
1195 ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */
1196 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */
1197
1198 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1199 interrupt-names = "msi";
1200 #interrupt-cells = <1>;
1201 interrupt-map-mask = <0 0 0 0x7>;
1202 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1203 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1204 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1205 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1206
1207 clocks = <&gcc PCIE_2_A_CLK>,
1208 <&gcc PCIE_2_H_CLK>,
1209 <&gcc PCIE_2_PHY_CLK>,
1210 <&gcc PCIE_2_AUX_CLK>,
1211 <&gcc PCIE_2_ALT_REF_CLK>;
1212 clock-names = "core", "iface", "phy", "aux", "ref";
1213
1214 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1215 assigned-clock-rates = <100000000>;
1216
1217 resets = <&gcc PCIE_2_ACLK_RESET>,
1218 <&gcc PCIE_2_HCLK_RESET>,
1219 <&gcc PCIE_2_POR_RESET>,
1220 <&gcc PCIE_2_PCI_RESET>,
1221 <&gcc PCIE_2_PHY_RESET>,
1222 <&gcc PCIE_2_EXT_RESET>;
1223 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1224
1225 pinctrl-0 = <&pcie2_pins>;
1226 pinctrl-names = "default";
1227
1228 status = "disabled";
1229 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1230 };
1231
1232 qsgmii_csr: syscon@1bb00000 {
1233 compatible = "syscon";
1234 reg = <0x1bb00000 0x000001FF>;
1235 };
1236
1237 lcc: clock-controller@28000000 {
1238 compatible = "qcom,lcc-ipq8064";
1239 reg = <0x28000000 0x1000>;
1240 #clock-cells = <1>;
1241 #reset-cells = <1>;
1242 };
1243
1244 lpass@28100000 {
1245 compatible = "qcom,lpass-cpu";
1246 status = "disabled";
1247 clocks = <&lcc AHBIX_CLK>,
1248 <&lcc MI2S_OSR_CLK>,
1249 <&lcc MI2S_BIT_CLK>;
1250 clock-names = "ahbix-clk",
1251 "mi2s-osr-clk",
1252 "mi2s-bit-clk";
1253 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1254 interrupt-names = "lpass-irq-lpaif";
1255 reg = <0x28100000 0x10000>;
1256 reg-names = "lpass-lpaif";
1257 };
1258
1259 sata: sata@29000000 {
1260 compatible = "qcom,ipq806x-ahci", "generic-ahci";
1261 reg = <0x29000000 0x180>;
1262
1263 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1264
1265 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1266 <&gcc SATA_H_CLK>,
1267 <&gcc SATA_A_CLK>,
1268 <&gcc SATA_RXOOB_CLK>,
1269 <&gcc SATA_PMALIVE_CLK>;
1270 clock-names = "slave_face", "iface", "core",
1271 "rxoob", "pmalive";
1272
1273 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
1274 assigned-clock-rates = <100000000>, <100000000>;
1275
1276 phys = <&sata_phy>;
1277 phy-names = "sata-phy";
1278 status = "disabled";
1279 };
1280
1281 gmac0: ethernet@37000000 {
1282 device_type = "network";
1283 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1284 reg = <0x37000000 0x200000>;
1285 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1286 interrupt-names = "macirq";
1287
1288 snps,axi-config = <&stmmac_axi_setup>;
1289 snps,pbl = <32>;
1290 snps,aal;
1291
1292 qcom,nss-common = <&nss_common>;
1293 qcom,qsgmii-csr = <&qsgmii_csr>;
1294
1295 clocks = <&gcc GMAC_CORE1_CLK>;
1296 clock-names = "stmmaceth";
1297
1298 resets = <&gcc GMAC_CORE1_RESET>,
1299 <&gcc GMAC_AHB_RESET>;
1300 reset-names = "stmmaceth", "ahb";
1301
1302 status = "disabled";
1303 };
1304
1305 gmac1: ethernet@37200000 {
1306 device_type = "network";
1307 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1308 reg = <0x37200000 0x200000>;
1309 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1310 interrupt-names = "macirq";
1311
1312 snps,axi-config = <&stmmac_axi_setup>;
1313 snps,pbl = <32>;
1314 snps,aal;
1315
1316 qcom,nss-common = <&nss_common>;
1317 qcom,qsgmii-csr = <&qsgmii_csr>;
1318
1319 clocks = <&gcc GMAC_CORE2_CLK>;
1320 clock-names = "stmmaceth";
1321
1322 resets = <&gcc GMAC_CORE2_RESET>,
1323 <&gcc GMAC_AHB_RESET>;
1324 reset-names = "stmmaceth", "ahb";
1325
1326 status = "disabled";
1327 };
1328
1329 gmac2: ethernet@37400000 {
1330 device_type = "network";
1331 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1332 reg = <0x37400000 0x200000>;
1333 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1334 interrupt-names = "macirq";
1335
1336 snps,axi-config = <&stmmac_axi_setup>;
1337 snps,pbl = <32>;
1338 snps,aal;
1339
1340 qcom,nss-common = <&nss_common>;
1341 qcom,qsgmii-csr = <&qsgmii_csr>;
1342
1343 clocks = <&gcc GMAC_CORE3_CLK>;
1344 clock-names = "stmmaceth";
1345
1346 resets = <&gcc GMAC_CORE3_RESET>,
1347 <&gcc GMAC_AHB_RESET>;
1348 reset-names = "stmmaceth", "ahb";
1349
1350 status = "disabled";
1351 };
1352
1353 gmac3: ethernet@37600000 {
1354 device_type = "network";
1355 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1356 reg = <0x37600000 0x200000>;
1357 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1358 interrupt-names = "macirq";
1359
1360 snps,axi-config = <&stmmac_axi_setup>;
1361 snps,pbl = <32>;
1362 snps,aal;
1363
1364 qcom,nss-common = <&nss_common>;
1365 qcom,qsgmii-csr = <&qsgmii_csr>;
1366
1367 clocks = <&gcc GMAC_CORE4_CLK>;
1368 clock-names = "stmmaceth";
1369
1370 resets = <&gcc GMAC_CORE4_RESET>,
1371 <&gcc GMAC_AHB_RESET>;
1372 reset-names = "stmmaceth", "ahb";
1373
1374 status = "disabled";
1375 };
1376 };
1377};